Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device according to one aspect includes: a pad portion; an insulating layer that supports the pad portion; a first wiring layer formed in the lower layer of the pad portion and extending in a first direction below the pad portion; and a conductive member joined to the surface of the pad portion and extending in a direction for forming an angle of -30° to 30° with respect to the first direction. A semiconductor device according to another aspect includes: a pad portion; an insulating layer that supports the pad portion; a first wiring layer formed in the lower layer of the pad portion and extending in the first direction below the pad portion; and a conductive member joined to the surface of the pad portion and having a joint portion that is elongated in one direction in a plan view, wherein the angle of the joint portion in the longitudinal direction with respect to the first direction is -30° to 30°.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor device having a die pad, a SiC chip mounted on the die pad, a porous first sintered Ag layer that bonds the die pad and the SiC chip, a reinforcing resin portion that covers the surface of the first sintered Ag layer and is formed in a fillet shape, a source lead that is electrically connected to the source electrode of the SiC chip, a gate lead that is electrically connected to the gate electrode, a drain lead that is electrically connected to the drain electrode, and a sealing body that covers the SiC chip, the first sintered Ag layer, and a portion of the die pad. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-179541 Summary of the Invention [Means for solving the problem]

[0004] A semiconductor device according to one embodiment of the present invention includes a pad portion, an insulating layer supporting the pad portion, a first wiring layer formed below the pad portion and extending in a first direction below the pad portion, and a conductive member joined to the surface of the pad portion and extending in a direction forming an angle of -30° to 30° with respect to the first direction. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a front view of a semiconductor device according to one embodiment of the present invention. [Figure 3]FIG. 3 is a side view of a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 4 is a plan view of FIG. 1 in which the sealing resin is omitted. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7A] FIG. 7A is an exploded perspective view for explaining the first semiconductor element. [Figure 7B] FIG. 7B is an enlarged plan view of a main part of the first via portion in FIG. 7A. [Figure 7C] FIG. 7C is an enlarged plan view of a main part of the second via portion in FIG. 7A. [Figure 8] FIG. 8 is an enlarged view of a main part of FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] 12A to 12C are diagrams showing a part of the manufacturing process of the semiconductor device. [Figure 13] FIG. 13 is a diagram for explaining the direction in which ultrasonic waves are applied. [Figure 14] FIG. 14 is a diagram for explaining the direction in which ultrasonic waves are applied. [Figure 15] FIG. 15 is a diagram showing an evaluation of the crack occurrence rate when the direction of application of ultrasonic waves is 0° (parallel direction) with respect to the longitudinal direction of the second plate-shaped member. [Figure 16] FIG. 16 is a diagram showing an evaluation of the crack occurrence rate when the direction of application of ultrasonic waves is 90° (perpendicular direction) to the longitudinal direction of the second plate-shaped member. [Figure 17] FIG. 17 is a diagram for explaining variations in the material of the pad portion. [Figure 18] FIG. 18 is a diagram for explaining variations in the material of the pad portion. [Figure 19] FIG. 19 is a diagram illustrating variations in the shape of the second plate-shaped member. [Figure 20] FIG. 20 is a diagram illustrating variations in the shape of the second plate-shaped member. DETAILED DESCRIPTION OF THE INVENTION

[0006] <Embodiments of the present invention> First, embodiments of the present invention will be listed and described.

[0007] A semiconductor device according to one embodiment of the present invention includes a pad portion, an insulating layer supporting the pad portion, a first wiring layer formed below the pad portion and extending in a first direction below the pad portion, and a conductive member joined to the surface of the pad portion and extending in a direction forming an angle of -30° to 30° with respect to the first direction.

[0008] A semiconductor device according to one embodiment of the present invention includes a pad portion, an insulating layer supporting the pad portion, a first wiring layer formed below the pad portion and extending in a first direction below the pad portion, and a conductive member bonded to a surface of the pad portion and having a bonding portion that is long in one direction in a planar view, and the angle of the longitudinal direction of the bonding portion with respect to the first direction may be between -30° and 30°.

[0009] A semiconductor device according to one embodiment of the present invention can be manufactured by a method for manufacturing a semiconductor device according to one embodiment of the present invention, which includes, for example, a step of preparing a semiconductor substrate including a pad portion, an insulating layer supporting the pad portion, and a first wiring layer formed below the pad portion and extending in a first direction below the pad portion, and a step of bonding a conductive member to a surface of the pad portion by ultrasonic vibration applied along a direction forming an angle of -30° to 30° with respect to the first direction.

[0010] According to this method, the vibration direction of the ultrasonic waves is a direction that forms an angle of -30° to 30° with respect to the first direction. This makes it possible to suppress the occurrence of cracks in the insulating layer. Note that the first wiring layer extending in the first direction below the pad portion may include, for example, a first wiring layer extending in the first direction so as to overlap the pad portion in a plan view. Furthermore, one first wiring layer may extend in the first direction in the region below the pad portion, or multiple first wiring layers that are spaced apart from each other may extend in the first direction in the region below the pad portion.

[0011] In the semiconductor device according to one embodiment of the present invention, the bonding portion of the conductive member to the pad portion may include a bonding portion that is long in one direction in a plan view.

[0012] In the semiconductor device according to one embodiment of the present invention, the pad portion may contain a material containing aluminum as a main component.

[0013] In the semiconductor device according to one embodiment of the present invention, the conductive member may contain a material containing either aluminum or copper as a main component.

[0014] In the semiconductor device according to one embodiment of the present invention, the conductive member may have two or more bonding portions.

[0015] In the semiconductor device according to one embodiment of the present invention, the conductive member may include a linear member having a thickness of 100 μm to 600 μm.

[0016] According to this configuration, the linear conductive members have a thickness of 100 μm to 600 μm, so that a relatively large current can be passed through the linear members.

[0017] In the semiconductor device according to one embodiment of the present invention, the pad portion may have a thickness of 1.6 μm to 6.0 μm.

[0018] With this configuration, since the thickness of the pad portion is 1.6 μm to 6.0 μm, the force applied to the pad portion when joining the conductive member is less likely to be transmitted to the insulating layer, thereby suppressing the occurrence of cracks in the insulating layer.

[0019] A semiconductor device according to one embodiment of the present invention may include a semiconductor substrate having a substrate main surface, a first element electrode formed on the substrate main surface and conducting to the first wiring layer, a second element electrode formed on the substrate main surface at a distance from the first element electrode and through which a channel current flows between the first element electrode and the second element electrode via the semiconductor substrate, and a second wiring layer formed on the same layer as the first wiring layer at a distance from the first wiring layer and conducting to the second element electrode.

[0020] When an element structure in which a channel current flows laterally along the substrate main surface is formed on a semiconductor substrate, a second wiring layer may be formed around a first wiring layer due to space constraints on the semiconductor substrate. In such a case, if cracks in the insulating layer can be suppressed as described above, short circuits between the first wiring layer and the second wiring layer can be suppressed. As a result, a highly reliable semiconductor device can be provided.

[0021] A semiconductor device according to one embodiment of the present invention includes a third wiring layer formed below the first wiring layer and extending in a second direction below the first wiring layer, and the second direction may be parallel or perpendicular to the first direction.

[0022] In a semiconductor device according to one embodiment of the present invention, the pad portion includes a surface to which the conductive member is bonded, and the surface of the pad portion may include a material primarily composed of nickel.

[0023] In a semiconductor device according to one embodiment of the present invention, the pad portion may include a first portion formed of a material primarily composed of copper, a second portion formed on the first portion of a material primarily composed of nickel, and a third portion formed on the second portion of a material primarily composed of palladium, forming the surface of the pad portion. <Detailed Description of the Embodiments of the Present Invention> Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. <Overall structure of semiconductor device A1> 1 to 6 show a semiconductor device A1 according to one embodiment of the present invention.

[0024] The semiconductor device A1 includes a plurality of first semiconductor elements 1, a second semiconductor element 2, a plurality of first conductive members 31, a plurality of second conductive members 32, a lead frame 4, and a sealing resin 5. In this embodiment, the first conductive members 31 may be an example of the "conductive member" set forth in the claims.

[0025] FIG. 1 is a plan view of the semiconductor device A1. FIG. 2 is a front view of the semiconductor device A1. FIG. 3 is a side view of the semiconductor device A1. FIG. 4 is a view in which the sealing resin 5 is omitted from the plan view shown in FIG. 1. In this figure, the sealing resin 5 is indicated by an imaginary line (a two-dot chain line). FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. For convenience of explanation, three mutually orthogonal directions are defined as the X direction, Y direction, and Z direction. The Z direction is the thickness direction of the semiconductor device A1. The X direction is the left-right direction in the plan view of the semiconductor device A1 (see FIG. 1). The Y direction is the up-down direction in the plan view of the semiconductor device A1 (see FIG. 1).

[0026] The semiconductor device A1 is a type that is surface-mounted on a circuit board of various electronic devices, etc. In this embodiment, the semiconductor device A1 is a semiconductor package called an SOP (Small Outline Package). In this embodiment, the semiconductor device A1 is, for example, a power supply IC, but is not limited to this.

[0027] The plurality of first semiconductor elements 1 and second semiconductor elements 2 are elements that are central to the function of the semiconductor device A1.

[0028] Each of the multiple first semiconductor elements 1 may be a power semiconductor element. In this embodiment, each first semiconductor element 1 may be, for example, a horizontal MOSFET. Note that each first semiconductor element 1 is not limited to a MOSFET. In this embodiment, the semiconductor device A1 includes two first semiconductor elements 1. Note that, for ease of understanding, these two first semiconductor elements 1 may be distinguished and referred to as first semiconductor element 1A and first semiconductor element 1B. The two first semiconductor elements 1A and 1B are aligned in the X direction, and the first semiconductor element 1B is sandwiched between the first semiconductor element 1A and the second semiconductor element 2.

[0029] The second semiconductor element 2 may be a control IC for controlling the driving of the plurality of first semiconductor elements 1. The second semiconductor element 2 may be electrically connected to each of the first semiconductor elements 1 and control each of the first semiconductor elements 1.

[0030] All of the multiple first semiconductor elements 1 and second semiconductor elements 2 are rectangular when viewed in the Z direction (hereinafter also referred to as "plan view"). Furthermore, the multiple first semiconductor elements 1 and second semiconductor elements 2 as a whole are rectangular when viewed in a plan view. Therefore, the Y-direction dimension of the multiple first semiconductor elements 1 and the Y-direction dimension of the second semiconductor elements 2 are approximately the same. Furthermore, the combined X-direction dimension of the multiple first semiconductor elements 1 and second semiconductor elements 2 is approximately 3 mm, and the Y-direction dimension is approximately 2 mm.

[0031] Each first semiconductor element 1 includes a semiconductor substrate 11, a plurality of element electrodes 12, a wiring layer 13, an insulating layer 19, a plurality of vias 20, and a protective layer 23. The first semiconductor elements 1A and 1B may share the semiconductor substrate 11.

[0032] 7A, 7B, 7C to 7A are diagrams illustrating the detailed configuration of the first semiconductor element 1. Fig. 7A is an exploded perspective view illustrating the wiring layer 13, insulating layer 19, and vias 20 in the first semiconductor elements 1. Note that the element electrodes 12 and some of the insulating layer 19 are omitted in this figure.

[0033] 7B is an enlarged plan view of a main portion of the first via portion 201a in FIG. 7A. FIG. 7C is an enlarged plan view of a main portion of the second via portion 202a in FIG. 7A. For ease of explanation, the size ratios between components in FIGS. 7B and 7C are different from those in FIG. 7A. FIG. 8 is an enlarged plan view of a main portion obtained by enlarging a portion of the plan view shown in FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8. FIG. 10 is a cross-sectional view taken along line XX in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8.

[0034] The semiconductor substrate 11 is made of a semiconductor material. Examples of the semiconductor material include Si (silicon), SiC (silicon carbide), and GaN (gallium nitride). In this embodiment, one of the two first semiconductor elements 1 (first semiconductor element 1A) may be an n-channel MOSFET, and the other of the two first semiconductor elements 1 (first semiconductor element 1B) may be a p-channel MOSFET. As shown in FIGS. 9 to 11, the semiconductor substrate 11 may have a substrate main surface 111 and a substrate back surface 112 facing opposite to each other in the Z direction.

[0035] As shown in FIGS. 9 to 11 , the multiple element electrodes 12 are formed so as to be exposed from the substrate main surface 111 of the semiconductor substrate 11. In this embodiment, each first semiconductor element 1 includes a first electrode 121, a second electrode 122, and a third electrode 123 as the multiple element electrodes 12. In this embodiment, the first electrode 121 may be a source electrode, the second electrode 122 may be a drain electrode, and the third electrode 123 may be a gate electrode. The arrangement of the first electrode 121, the second electrode 122, and the third electrode 123 in a plan view is not particularly limited, and the rectangular element electrodes 12 may be arranged in a lattice pattern or may be aligned in a line in the X direction or the Y direction. In this embodiment, the first electrode 121 and the second electrode 122 may be examples of the "first element electrode" and the "second element electrode" recited in the claims, respectively.

[0036] The first electrode 121 and the second electrode 122 are formed on the substrate main surface 111 with a third electrode 123 sandwiched therebetween. The region of the substrate main surface 111 below the third electrode 123 is a channel region where a channel is formed when an appropriate voltage is applied to the third electrode 123. When an appropriate voltage is applied to the third electrode 123, a channel current flows between the first electrode 121 and the second electrode 122 that are aligned in the horizontal direction along the substrate main surface 111.

[0037] As shown in FIGS. 9 to 11 , the wiring layer 13 is formed on the substrate main surface 111 of the semiconductor substrate 11 and is electrically connected to the plurality of element electrodes 12. The wiring layer 13 includes, for each first semiconductor element 1, a first conductive layer 14, a second conductive layer 15, a third conductive layer 16, a fourth conductive layer 17, and a fifth conductive layer 18 that are spaced apart from one another in the Z direction. The number of conductive layers in the wiring layer 13 is not limited to five. The first conductive layer 14, the second conductive layer 15, the third conductive layer 16, the fourth conductive layer 17, and the fifth conductive layer 18 are insulated from one another by an insulating layer 19.

[0038] 9 to 11, the first conductive layer 14 is an outer layer of the wiring layer 13, and is disposed at a position farther from the substrate main surface 111 than the second conductive layer 15, the third conductive layer 16, the fourth conductive layer 17, and the fifth conductive layer 18. The first conductive layer 14 includes a plurality of first plate-shaped members 141.

[0039] Each of the multiple first plate-shaped members 141 is made of a conductive material. The conductive material may be, for example, a material containing Al (aluminum) and Cu (copper) as its main components, but is not particularly limited to this. In this embodiment, the material of each first plate-shaped member 141 is a material containing Al as its main component, preferably an Al-based alloy, and more preferably an Al-Cu-based alloy, an Al-Si-based alloy, or an Al-Si-Cu-based alloy that contains 90 wt% or more of Al.

[0040] In plan view, each first plate-shaped member 141 has a rectangular shape with its longitudinal direction aligned along the Y direction. The width (dimension in the short direction) of each first plate-shaped member 141 is, for example, approximately 350 μm. The thickness (dimension in the Z direction) of each first plate-shaped member 141 (first pad portion 142a and second pad portion 142b described below) is, for example, 1.6 μm to 6.0 μm. If the thickness of the first pad portion 142a and the second pad portion 142b is 1.6 μm to 6.0 μm, the force applied to the first pad portion 142a and the second pad portion 142b when the first conductive member 31 is bonded can be made less likely to be transmitted to the insulating layer 19. As a result, the occurrence of cracks in the insulating layer 19 can be suppressed.

[0041] The multiple first plate-shaped members 141 are lined up in the X direction in a plan view. For ease of understanding, in Fig. 4, the first plate-shaped members 141 adjacent to each other in the X direction are shown as being in contact with each other, but an insulating layer 19 is interposed between the adjacent first plate-shaped members 141. Therefore, in the first conductive layer 14, the multiple first plate-shaped members 141 are insulated from each other by the insulating layer 19.

[0042] As shown in Fig. 7A and Figs. 8 to 11, each first plate-shaped member 141 includes a first pad portion 142a and a second pad portion 142b exposed from the protective layer 23. For ease of understanding, the first pad portion 142a and the second pad portion 142b are hatched in Fig. 7A. In this embodiment, the first pad portion 142a and the second pad portion 142b may be an example of a "pad portion" as defined in the claims.

[0043] The first pad portion 142a and the second pad portion 142b are arranged on the same plane of each first plate-shaped member 141. The first pad portion 142a and the second pad portion 142b are spaced apart from each other and aligned in the Y direction on each first plate-shaped member 141. One end of the first conductive member 31 (joint portion 311, described below) is joined to the first pad portion 142a. An intermediate portion of the first conductive member 31 (joint portion 312, described below) is joined to the second pad portion 142b.

[0044] As shown in FIGS. 9 to 11, the second conductive layer 15 is an intermediate layer in the wiring layer 13, and is disposed between the first conductive layer 14 and the third conductive layer 16. The second conductive layer 15 includes a plurality of second plate-shaped members 151. In this embodiment, the second plate-shaped members 151 may be an example of the "first wiring layer" recited in the claims.

[0045] Each of the second plate-shaped members 151 is made of a conductive material. The conductive material may be, for example, a material containing Al (aluminum) and Cu (copper) as its main components, but is not particularly limited to this. In this embodiment, the material of each second plate-shaped member 151 is a material containing Al as its main component, preferably an Al-based alloy, and more preferably an Al-Cu-based alloy, an Al-Si-based alloy, or an Al-Si-Cu-based alloy that contains 90 wt% or more of Al.

[0046] Each second plate-shaped member 151 has a rectangular shape in plan view with its longitudinal direction D1 aligned along the Y direction. In this embodiment, the direction D1 may be an example of the "first direction" described in the claims. Each second plate-shaped member 151 is formed in a solid pattern below the first plate-shaped member 141. For example, the second plate-shaped member 151 may be formed so as to cover the entire area below the first plate-shaped member 141 (the area overlapping the first plate-shaped member 141 in plan view), may be formed without divisions in the area below the first plate-shaped member 141, or may be formed without gaps in the area below the first plate-shaped member 141. In other words, each second plate-shaped member 151 may be formed in substantially the same shape as each first plate-shaped member 141 in plan view.

[0047] The width (dimension in the short side direction) of each second plate-shaped member 151 is, for example, approximately 350 μm. The thickness (dimension in the Z direction) of each second plate-shaped member 151 is, for example, approximately 0.5 μm. The multiple second plate-shaped members 151 are lined up in the X direction in a plan view, and an insulating layer 19 is interposed between the second plate-shaped members 151 adjacent to each other in the X direction. Therefore, in the second conductive layer 15, the multiple second plate-shaped members 151 are insulated from each other by the insulating layer 19.

[0048] As shown in FIGS. 9 to 11, the third conductive layer 16 is an intermediate layer in the wiring layer 13, and is disposed between the second conductive layer 14 and the fourth conductive layer 17. The third conductive layer 16 includes a plurality of third plate-shaped members 161. In this embodiment, the third plate-shaped members 161 may be an example of the "third wiring layer" recited in the claims.

[0049] Each of the third plate-shaped members 161 is made of a conductive material. The conductive material may be, for example, a material containing Al (aluminum) and Cu (copper) as its main components, but is not particularly limited to this. In this embodiment, the material of each third plate-shaped member 161 is a material containing Al as its main component, preferably an Al-based alloy, and more preferably an Al-Cu-based alloy, an Al-Si-based alloy, or an Al-Si-Cu-based alloy that contains 90 wt% or more of Al.

[0050] Each third plate-shaped member 161 has a rectangular shape in plan view, with its longitudinal direction D2 aligned along the Y direction. In this embodiment, the direction D2 may be an example of the "second direction" described in the claims. Each third plate-shaped member 161 is formed in a solid pattern below the second plate-shaped member 151. For example, the third plate-shaped member 161 may be formed so as to cover the entire area below the second plate-shaped member 151 (the area overlapping the second plate-shaped member 151 in plan view), may be formed without divisions in the area below the second plate-shaped member 151, or may be formed without gaps in the area below the second plate-shaped member 151. In other words, each third plate-shaped member 161 may be formed in substantially the same shape as each second plate-shaped member 151 in plan view.

[0051] The width (dimension in the short side direction) of each third plate-shaped member 161 is, for example, approximately 350 μm. The thickness (dimension in the Z direction) of each third plate-shaped member 161 is, for example, approximately 0.5 μm. The multiple third plate-shaped members 161 are lined up in the X direction in a plan view, and an insulating layer 19 is interposed between the third plate-shaped members 161 adjacent to each other in the X direction. Therefore, in the third conductive layer 16, the multiple third plate-shaped members 161 are insulated from each other by the insulating layer 19.

[0052] 9 to 11, the fourth conductive layer 17 is an intermediate layer in the wiring layer 13, and is disposed between the third conductive layer 16 and the fifth conductive layer 18. The fourth conductive layer 17 includes a plurality of fourth plate-shaped members 171.

[0053] Each of the multiple fourth plate-shaped members 171 is made of a conductive material. The conductive material may be, for example, a material containing Al (aluminum) and Cu (copper) as its main components, but is not particularly limited to this. In this embodiment, the material of each fourth plate-shaped member 171 is a material containing Al as its main component, preferably an Al-based alloy, and more preferably an Al-Cu-based alloy, an Al-Si-based alloy, or an Al-Si-Cu-based alloy that contains 90 wt% or more of Al.

[0054] Each fourth plate-shaped member 171 has a rectangular shape with its longitudinal direction aligned with the X direction in plan view. That is, each fourth plate-shaped member 171 is perpendicular to the first plate-shaped member 141, the second plate-shaped member 151, and the third plate-shaped member 161 in plan view. The width (dimension in the short side direction) of each fourth plate-shaped member 171 may be narrower than those of the first plate-shaped member 141, the second plate-shaped member 151, and the third plate-shaped member 161, and is, for example, approximately 20 μm to 50 μm. The thickness (dimension in the Z direction) of each fourth plate-shaped member 171 is, for example, approximately 0.5 μm. The multiple fourth plate-shaped members 171 are aligned in the Y direction in plan view, and an insulating layer 19 is interposed between adjacent fourth plate-shaped members 171 in the Y direction. Therefore, in the fourth conductive layer 17, the multiple fourth plate-shaped members 171 are insulated from each other by the insulating layer 19.

[0055] 9 to 11, the fifth conductive layer 18 is an inner layer in the wiring layer 13, and is disposed closer to the substrate main surface 111 than the first conductive layer 14, the second conductive layer 15, the third conductive layer 16, and the fourth conductive layer 17. The fifth conductive layer 18 includes a plurality of fifth plate-shaped members 181.

[0056] Each of the plurality of fifth plate-shaped members 181 is made of a conductive material. The conductive material may be, for example, a material containing Al (aluminum) and Cu (copper) as its main components, but is not particularly limited to this. In this embodiment, the material of each fifth plate-shaped member 181 is a material containing Al as its main component, preferably an Al-based alloy, and more preferably an Al-Cu-based alloy, an Al-Si-based alloy, or an Al-Si-Cu-based alloy that contains 90 wt% or more of Al.

[0057] In plan view, each fifth plate-shaped member 181 has a rectangular shape with its longitudinal direction aligned along the Y direction. The width (short-side dimension) of each fifth plate-shaped member 181 may be narrower than those of the first plate-shaped member 141, the second plate-shaped member 151, the third plate-shaped member 161, and the fourth plate-shaped member 171, and may be, for example, approximately 1.0 μm. The thickness (Z-direction dimension) of each fifth plate-shaped member 181 is, for example, approximately 0.5 μm. The multiple fifth plate-shaped members 181 are aligned in the X direction in plan view, and an insulating layer 19 is interposed between the fifth plate-shaped members 181 adjacent to each other in the X direction. Therefore, in the fifth conductive layer 18, the multiple fifth plate-shaped members 181 are insulated from each other by the insulating layer 19. In this embodiment, the multiple fifth plate-shaped members 181 are arranged in the X direction at a pitch of approximately 0.6 μm.

[0058] In the wiring layer 13, the numbers of first plate-shaped members 141, second plate-shaped members 151, and third plate-shaped members 161 are the same, the number of first plate-shaped members 141, second plate-shaped members 151, and third plate-shaped members 161 is fewer than the number of fourth plate-shaped members 171, and the number of fourth plate-shaped members 171 is fewer than the number of fifth plate-shaped members 181. In addition, the number of fifth plate-shaped members 181 is fewer than the number of element electrodes 12. In the wiring layer 13, the fifth conductive layer 18 and the fourth conductive layer 17 aggregate the multiple element electrodes 12 and electrically connect them to the first to third conductive layers 14 to 16 above.

[0059] In the wiring layer 13, as shown in FIG. 7A, the longitudinal direction of each of the first plate-shaped members 141, second plate-shaped members 151 and third plate-shaped members 161 is perpendicular to the longitudinal direction of each of the fourth plate-shaped members 171 on a plane (xy plane) perpendicular to the Z direction, and the longitudinal direction of each of the fourth plate-shaped members 171 is perpendicular to the longitudinal direction of each of the fifth plate-shaped members 181 on the xy plane.

[0060] In the wiring layer 13, the multiple first plate-shaped members 141 include first electrode conduction members 141a that are electrically connected to the first electrodes 121 and second electrode conduction members 141b that are electrically connected to the second electrodes 122. The first electrode conduction members 141a and the second electrode conduction members 141b are arranged alternately in the X direction.

[0061] 4, the first conductive layer 14 may include two first electrode conductive members 141a that are electrically connected to the first electrode 121 of the first semiconductor element 1A, and may also include two first electrode conductive members 141a that are electrically connected to the first electrode 121 of the first semiconductor element 1B. The first conductive layer 14 may also include one second electrode conductive member 141b that is electrically connected to the second electrode 122 of the first semiconductor element 1A, and may also include one second electrode conductive member 141b that is electrically connected to the second electrode 122 of the first semiconductor element 1B.

[0062] Similarly, the multiple second plate-like members 151 include first electrode conduction members 151a that are electrically connected to the first electrodes 121 and second electrode conduction members 151b that are electrically connected to the second electrodes 122. The first electrode conduction members 151a and the second electrode conduction members 151b are arranged alternately in the X direction. In this embodiment, the first electrode conduction members 151a and the second electrode conduction members 151b may be examples of the "first wiring layer" and the "second wiring layer" recited in the claims, respectively.

[0063] The third plate-shaped members 161 include first electrode conduction members 161a electrically connected to the first electrodes 121 and second electrode conduction members 161b electrically connected to the second electrodes 122. The first electrode conduction members 161a and the second electrode conduction members 161b are alternately arranged in the X direction.

[0064] The plurality of fourth plate-shaped members 171 include first electrode conduction members 171a electrically connected to the first electrodes 121 and second electrode conduction members 171b electrically connected to the second electrodes 122. The first electrode conduction members 171a and the second electrode conduction members 171b are arranged alternately in the Y direction.

[0065] The plurality of fifth plate-shaped members 181 also include a first electrode conduction member 181a electrically connected to the first electrode 121 and a second electrode conduction member 181b electrically connected to the second electrode 122. The plurality of fifth plate-shaped members 181 also include a third electrode conduction member 181c electrically connected to the third electrode 123. The third electrode conduction member 181c is disposed between adjacent first electrode conduction members 181a and second electrode conduction members 181b.

[0066] As shown in FIGS. 9 to 11, the insulating layer 19 is formed between the first conductive layer 14 and the semiconductor substrate 11 (substrate main surface 111). The material of the insulating layer 19 is not particularly limited as long as it has insulating properties, and may be made of SiO2, for example. The insulating layer 19 includes a first interlayer insulating film 191, a second interlayer insulating film 192, a third interlayer insulating film 193, a fourth interlayer insulating film 194, and a fifth interlayer insulating film 195. In this embodiment, the first interlayer insulating film 191 may be an example of an "insulating layer" recited in the claims.

[0067] The first interlayer insulating film 191 is interposed between the first conductive layer 14 and the second conductive layer 15 to insulate them. The second interlayer insulating film 192 is interposed between the second conductive layer 15 and the third conductive layer 16 to insulate them. The third interlayer insulating film 193 is interposed between the third conductive layer 16 and the fourth conductive layer 17 to insulate them. The fourth interlayer insulating film 194 is interposed between the fourth conductive layer 17 and the fifth conductive layer 18 to insulate them. The fifth interlayer insulating film 195 is interposed between the fifth conductive layer 18 and the semiconductor substrate 11 (substrate main surface 111) to insulate the fifth conductive layer 18 from each element electrode 12.

[0068] Insulating layers 19 are also formed between the first plate-shaped members 141 adjacent to each other in the X direction on the first conductive layer 14, between the second plate-shaped members 151 adjacent to each other in the X direction on the second conductive layer 15, between the third plate-shaped members 161 adjacent to each other in the X direction on the third conductive layer 16, between the fourth plate-shaped members 171 adjacent to each other in the X direction on the fourth conductive layer 17, and between the fourth plate-shaped members 171 adjacent to each other in the X direction on the fifth conductive layer 18. Note that the insulating layers 19 interposed therebetween are omitted in Fig. 7A.

[0069] Each of the vias 20 is made up of a through hole penetrating the insulating layer 19 and a conductive material filled in the through hole. In this embodiment, the conductive material is, for example, W (tungsten). The material of each via 20 is not limited to this, and may be aluminum, copper, or the like. Furthermore, the conductive material may be formed so as to cover the inner surface of the through hole rather than being filled in the through hole.

[0070] Each via 20 extends along the Z direction. In this embodiment, the shape of each via 20 in a plan view is circular as shown in FIG. 7A . However, the shape of each via 20 in a plan view is not limited to this and may be, for example, rectangular or polygonal. In this embodiment, the multiple vias 20 include multiple first vias 201, multiple second vias 202, multiple third vias 203, multiple fourth vias 204, and multiple fifth vias 205.

[0071] As shown in FIGS. 7A, 7B, and 9 to 11, each of the plurality of first vias 201 penetrates the first interlayer insulating film 191 and is interposed between the first conductive layer 14 and the second conductive layer 15. Each of the first vias 201 provides electrical continuity between the first conductive layer 14 and the second conductive layer 15. As shown in FIGS. 7A and 7B, the plurality of first vias 201 are arranged below the first plate-shaped member 141 so as to form a solid pattern of first via portions 201a.

[0072] More specifically, as shown in FIG. 7B, the first via portion 201a is formed by gathering multiple first vias 201 in a certain area, making it visually distinguishable from the portion of the first interlayer insulating film 191 surrounding the first via portion 201a (non-first via portion 201b).

[0073] In this embodiment, as shown by dashed hatching in FIG. 7B , a lower region 143 of the first plate-shaped member 141 (a region of the first interlayer insulating film 191 that overlaps the first plate-shaped member 141 in plan view) is defined in the first interlayer insulating film 191, and this lower region 143 is formed as the first via portion 201a. In the first via portion 201a, for example, a plurality of first vias 201 that are circular in plan view are densely arranged regularly and uniformly (for example, in a matrix). Here, densely arranged first vias 201 may refer to, for example, a state in which the plurality of first vias 201 are spaced apart from each other by a distance equal to or less than the width (in this embodiment, the diameter) of each first via 201. Thus, a strip-shaped region having a certain width and occupied by the plurality of first vias 201 is defined as the first via portion 201a.

[0074] In other words, "the first via portion 201a is a solid pattern below the first plate-shaped member 141" may mean that the strip-shaped first via portion 201a is formed so as to cover the entire surface of the lower region 143 of the first plate-shaped member 141, that it is formed without divisions in the lower region 143 of the first plate-shaped member 141, or that it is formed without gaps in the lower region 143 of the first plate-shaped member 141. In other words, it may mean that each first via portion 201a is formed in substantially the same shape as each first plate-shaped member 141 in a plan view.

[0075] A plurality of first via portions 201a are formed in one-to-one correspondence with the plurality of first plate-shaped members 141, and are lined up in the X direction. The regions of the first interlayer insulating film 191 between adjacent first via portions 201a are non-first via portions 201b. As a result, the first via portions 201a and the non-first via portions 201b are lined up alternately in the X direction.

[0076] In this embodiment, the non-first via portion 201b is defined as a strip-shaped region having a certain width in the first interlayer insulating film 191 extending along the Y direction. The non-first via portion 201b is a strip-shaped blank region in the xy plane where no first vias 201 are formed, and its width may be, for example, several times or more the width of each first via 201.

[0077] 7B, boundary 144 between first via portion 201a and non-first via portion 201b is shown by a straight dashed line, but in reality it does not have to be a clear straight line. For example, when the top surface of first interlayer insulating film 191 is visually observed, for example, via an SEM image, a vague boundary between a plurality of first vias 201 arranged in a line along the Y direction at the outermost side of first via portion 201a and a blank region of first interlayer insulating film 191 adjacent to them may be defined as boundary 144.

[0078] 7A, 7C, and 9 to 11, each of the plurality of second vias 202 penetrates the second interlayer insulating film 192 and is interposed between the second conductive layer 15 and the third conductive layer 16. Each second via 202 provides electrical continuity between the second conductive layer 15 and the third conductive layer 16. As shown in FIGS. 7A and 7C, the plurality of second vias 202 are arranged below the second plate-shaped member 151 so as to form a solid pattern of second via portions 202a.

[0079] More specifically, the second via portion 202a is formed by gathering multiple second vias 202 in a certain area, as shown in FIG. 7C, and is therefore visually distinguishable from the portion of the second interlayer insulating film 192 surrounding the second via portion 202a (non-second via portion 202b).

[0080] In this embodiment, as shown by dashed hatching in FIG. 7C , a lower region 153 of the second plate-shaped member 151 (a region of the second interlayer insulating film 192 that overlaps the second plate-shaped member 151 in plan view) is defined in the second interlayer insulating film 192, and this lower region 153 is formed as the second via portion 202a. In the second via portion 202a, for example, a plurality of second vias 202 that are circular in plan view are densely arranged regularly and uniformly (for example, in a matrix). Here, densely arranged second vias 202 may refer to, for example, a state in which the plurality of second vias 202 are spaced apart from each other by a distance equal to or less than the width (in this embodiment, the diameter) of each second via 202. As a result, a strip-shaped region having a certain width and occupied by the plurality of second vias 202 is defined as the second via portion 202a.

[0081] In other words, "the second via portions 202a are a solid pattern below the second plate-shaped member 151" may mean that the strip-shaped second via portions 202a are formed so as to cover the entire surface of the lower region 153 of the second plate-shaped member 151, that they are formed without divisions in the lower region 153 of the second plate-shaped member 151, or that they are formed without gaps in the lower region 153 of the second plate-shaped member 151. In other words, it may mean that each second via portion 202a is formed in substantially the same shape as each second plate-shaped member 151 in a plan view.

[0082] A plurality of second via portions 202a are formed in one-to-one correspondence with the plurality of second plate-shaped members 151, and are lined up in the X direction. The regions of the second interlayer insulating film 192 between adjacent second via portions 202a are non-second via portions 202b. As a result, the second via portions 202a and the non-second via portions 202b are lined up alternately in the X direction.

[0083] In this embodiment, the non-second via portion 202b is defined as a strip-shaped region having a certain width in the second interlayer insulating film 192 extending along the Y direction. The non-second via portion 202b is a strip-shaped blank region in the xy plane where no second vias 202 are formed, and its width may be, for example, several times or more the width of each second via 202.

[0084] 7C, the boundary 154 between the second via portion 202a and the non-second via portion 202b does not have to be a clear straight line. For example, when the top surface of the second interlayer insulating film 192 is viewed, for example, via an SEM image, the vague boundary between the second vias 202 arranged in a line along the Y direction at the outermost side of the second via portion 202a and the adjacent blank region of the second interlayer insulating film 192 may be defined as the boundary 154.

[0085] 7A and 9 to 11, each of the plurality of third vias 203 penetrates the third interlayer insulating film 193 and is interposed between the third conductive layer 16 and the fourth conductive layer 17. Each third via 203 provides electrical continuity between the third conductive layer 16 and the fourth conductive layer 17. The arrangement of the plurality of third vias 203 is not particularly limited, and may be appropriately designed based on the arrangement of the plurality of third plate-shaped members 161 and the plurality of fourth plate-shaped members 171 of the third conductive layer 16.

[0086] 7A and 9 to 11, each of the plurality of fourth vias 204 penetrates the fourth interlayer insulating film 194 and is interposed between the fourth conductive layer 17 and the fifth conductive layer 18. Each fourth via 204 electrically connects the fourth conductive layer 17 and the fifth conductive layer 18. The arrangement of the plurality of fourth vias 204 is not particularly limited, and may be appropriately designed based on the arrangement of the plurality of fourth plate-shaped members 171 and the plurality of fifth plate-shaped members 181 of the fourth conductive layer 17.

[0087] 7A and 9 to 11, each of the plurality of fifth vias 205 penetrates the fifth interlayer insulating film 195 and is interposed between the fifth conductive layer 18 and the element electrode 12. Each fifth via 205 electrically connects the fifth conductive layer 18 and the element electrode 12. The arrangement of the plurality of fifth vias 205 is not particularly limited and may be appropriately designed based on the arrangement of the plurality of fifth plate-shaped members 181 of the fifth conductive layer 18 and the plurality of element electrodes 12.

[0088] 9 to 11, the protective layer 23 is formed to cover the upper surface of the wiring layer 13 (first conductive layer 14). The protective layer 23 may be, for example, a SiN layer or SiO layer formed by plasma CVD, or a polyimide resin layer formed by coating. Alternatively, the protective layer 23 may be formed by a combination of these. In this embodiment, a portion of the protective layer 23 is opened, and the first pad portion 142a and the second pad portion 142b are each exposed through the opened portion.

[0089] The second semiconductor element 2 has an element main surface 21 and an element back surface 22 facing opposite to each other in the Z direction. The element main surface 21 faces the same direction as the substrate main surface 111 of the semiconductor substrate 11. The element back surface 22 faces the same direction as the substrate back surface 112 of the semiconductor substrate 11. As shown in FIG. 4 , the second semiconductor element 2 has a plurality of pad portions 211 formed on the element main surface 21. The pad portions 211 are portions to which the second conductive member 32 is bonded.

[0090] Each of the multiple first conductive members 31 electrically connects one of the multiple first semiconductor elements 1 to the lead frame 4. In a plan view, each first conductive member 31 intersects the outer periphery of one of the multiple first semiconductor elements 1. Each first conductive member 31 includes bonding portions 311 bonded to first pad portions 142a of the multiple first semiconductor elements 1, bonding portions 312 bonded to second pad portions 142b of the multiple first semiconductor elements 1, and bonding portions 313 bonded to a portion of the lead frame 4 (bonding pad portions 42 described below).

[0091] Each first conductive member 31 is formed using, for example, a wedge tool (wedge tool 503 described below), and the joints 311, 312, and 313 are formed by wedge bonding using the wedge tool. As shown in FIG. 8, each joint 311 has a substantially rectangular shape with its longitudinal direction aligned along the Y direction. The longitudinal dimensions of the joints 311, 312, and 313 depend on the wedge tool used. In this embodiment, the joints 311 and 312 may be an example of a "joint of conductive members" as defined in the claims.

[0092] 8, each first conductive member 31 may have a connection portion 314 that extends from the first pad portion 142a to the second pad portion 142b and connects the first pad portion 142a and the second pad portion 142b. The connection portion 314 is a portion of the first conductive member 31 that is bridged between the first pad portion 142a and the second pad portion 142b, and therefore may also be referred to as a bridge portion of the first conductive member 31.

[0093] In plan view, all of the connection portions 314 of the first conductive members 31 overlap one of the plurality of first semiconductor elements 1. Therefore, in plan view, the connection portions 314 of each first conductive member 31 do not intersect with the periphery of any of the plurality of first semiconductor elements 1. The connection portions 314 of each first conductive member 31 are formed in a line shape along the longitudinal direction (Y direction) of the first plate-like member 141. In this embodiment, the direction D in which the connection portions 314 of the first conductive members 31 extend is W1 is parallel to the direction D1 (Y direction) in which the second plate-shaped member 151 extends. W1 The angle between the direction D1 and the connecting portion 314 of each first conductive member 31 extends is 0°. W1 8, the angle θ1 with respect to the direction D1 may be in the range of −30° to 30°. W1 However, this may be an example of the "first direction" described in [B9] below.

[0094] 8, the second plate-shaped member 151 and the third plate-shaped member 161 are formed below the first plate-shaped member 141 and cannot be seen. However, the second plate-shaped member 151 and the third plate-shaped member 161 are formed in a solid pattern on the first plate-shaped member 141. Therefore, the shapes of the second plate-shaped member 151 and the third plate-shaped member 161 may be considered to be the same as the shape of the first plate-shaped member 141.

[0095] Furthermore, each first conductive member 31 may include an extension 315 extending from the second pad portion 142b to the outside of each first semiconductor element 1. In plan view, the extension 315 of each first conductive member 31 intersects the outer periphery of one of the plurality of first semiconductor elements 1. The extension 315 of each first conductive member 31 extends in a direction D1 that forms an angle θ2 of -30° to 30° with respect to the longitudinal direction D1 (Y direction) of the second plate-like member 151. W2 It is formed in a line along the

[0096] Such a direction D W1 The angle θ1 between the direction D1 and the direction D W2The range of the angle θ2 between the direction D1 and the bonding portions 311, 312 may be applied to the relationship between the directionality of the bonding portions 311, 312 and the directionality of the second plate-shaped member 151. As described above, the bonding portions 311, 312 are formed by wedge bonding, and in a plan view, the bonding portions 311, 312 are oriented in one direction D W3 In other words, each of the joints 311 and 312 is formed in a long shape that is long in one direction D W3 8, the longitudinal direction D1 (Y direction) of the second plate-shaped member 151 is oriented in the direction perpendicular to the longitudinal direction D2 of the second plate-shaped member 151. W3 The angle θ3 may also be in the range of −30° to 30°.

[0097] It is not necessary that all of the angles θ1, θ2, and θ3 are in the range of −30° to 30° with respect to the longitudinal direction D1 of the second plate-shaped member 151. For example, some of the angles θ1 and θ3 may be in the range of −30° to 30° with respect to the direction D1, and some of the angles θ2 may be outside the range of −30° to 30° with respect to the direction D1.

[0098] Each of the multiple second conductive members 32 provides electrical conduction between the third electrode 123 of the first semiconductor element 1 and the lead frame 4, and between the second semiconductor element 2 and the lead frame 4. Each second conductive member 32 intersects the outer periphery of the first semiconductor element 1 and the second semiconductor element 2 in a plan view.

[0099] In this embodiment, all of the first conductive members 31 and second conductive members 32 are so-called bonding wires, which are linear members with a circular cross section. The materials are not limited to linear members, and may be strip-shaped members called ribbon wires. The main component of the material of the linear members is Al. That is, in this embodiment, all of the first conductive members 31 and second conductive members 32 are Al wires. The materials of the first conductive members 31 and second conductive members 32 are not limited to these materials and may be, for example, Cu or Au. In this embodiment, all of the first conductive members 31 and second conductive members 32 may have a thickness (wire diameter) of 100 μm to 600 μm.

[0100] The lead frame 4 is a portion that forms a conductive path between the plurality of first semiconductor elements 1 and second semiconductor elements 2 and the circuit board on which the semiconductor device A1 is mounted. The lead frame 4 supports the plurality of first semiconductor elements 1 and second semiconductor elements 2 and is electrically connected to the plurality of first semiconductor elements 1 and second semiconductor elements 2. The lead frame 4 is formed by punching, cutting, bending, or the like from a thin metal plate made of Cu or the like that is rectangular in plan view. Therefore, the main component of the material of the lead frame 4 is Cu. However, the material of the lead frame 4 is not limited to this.

[0101] The lead frame 4 includes a die pad portion 41, a plurality of bonding pad portions 42a, 42b, 42c, 42d, and 42e, a plurality of lead portions 43a, 43b, 43c, 43d, 43e, and 43f, and a plurality of lateral extension portions 44. For ease of explanation, the plurality of bonding pad portions 42a to 42e will be referred to as bonding pad portion 42 unless otherwise specified. Similarly, the plurality of lead portions 43a to 43f will be referred to as lead portion 43 unless otherwise specified.

[0102] The die pad portion 41 is a portion on which a plurality of first semiconductor elements 1 and second semiconductor elements 2 are mounted. The plurality of first semiconductor elements 1 and second semiconductor elements 2 are bonded to the die pad portion 41 by a bonding material 411. The bonding material 411 is, for example, a solder paste or an Ag paste. The material of the bonding material 411 is not particularly limited.

[0103] Each of the plurality of bonding pad portions 42a-42e is a portion to which either the first conductive member 31 or the second conductive member 32 is bonded. The bonding pad portions 42a-42e are arranged apart from one another. In this embodiment, the bonding pad portions 42a-42e are arranged apart from the die pad portion 41. Any one of the plurality of bonding pad portions 42a-42e and the die pad portion 41 may be formed integrally. In this case, the lead frame 4 does not need to include the plurality of lateral extension portions 44.

[0104] In this embodiment, each of the bonding pad portions 42a and 42b includes a protrusion 421a or 421b protruding from one edge in the x direction. The protrusions 421a and 421b overlap the lead portion 43f when viewed in the y direction. The bonding pad portion 42c is rectangular in plan view, and each of the bonding pad portions 42d and 42e has a recessed edge in the x direction.

[0105] The bonding pad portions 42a, 42b are electrically connected to the first electrodes 121 of the first semiconductor elements 1A, 1B via the first conductive member 31. Two lead portions 43a, 43b are connected to the bonding pad portions 42a, 42b, respectively.

[0106] The bonding pad portion 42c is electrically connected to the second electrodes 122 of the first semiconductor elements 1A and 1B via the first conductive member 31. Three lead portions 43c are connected to the bonding pad portion 42c.

[0107] The bonding pads 42d, 42e are the same size. Each bonding pad 42d is electrically connected to the second semiconductor element 2 via the second conductive member 32. Each bonding pad 42e is electrically connected to the third electrode 123 of the first semiconductor element 1 via the second conductive member 33.

[0108] The lead portion 43f is not connected to any of the bonding pad portions 42a to 42e and is not electrically connected to any of the plurality of first semiconductor elements 1 and second semiconductor elements 2. As shown in FIG. 4, the lead portion 43f is disposed between the lead portions 43a and 43b that are adjacent in the x direction. In this embodiment, the two lead portions 43a and the two lead portions 43b are disposed on opposite sides of the lead portion 43f in the x direction. In addition, the width of the portion of the lead portion 43f covered by the sealing resin 5 is larger than the width of the portion exposed from the sealing resin 5, but the widths may be the same or smaller. However, by increasing the width as shown in FIG. 4, it is possible to prevent the lead portion 43f from falling out of the sealing resin 5.

[0109] As shown in FIG. 4, each of the plurality of lead portions 43a to 43d is connected to one of the bonding pad portions 42a to 42d and extends from the bonding pad portions 42a to 42d. A portion of each lead portion 43 is exposed from the sealing resin 5, and the portion exposed from the sealing resin 5 serves as a terminal for mounting the semiconductor device A1 on a circuit board. At least the portion of each lead portion 43 exposed from the sealing resin 5 is covered with plating. Each lead portion 43 is bent at the portion exposed from the sealing resin 5. In this embodiment, eight lead portions 43 are exposed from each edge of the sealing resin 5 in the Y direction in plan view. The arrangement and number of the plurality of lead portions 43 are not limited to those shown in FIGS. 1 and 4.

[0110] Each of the plurality of lead portions 43a is connected to a bonding pad portion 42a. As described above, the bonding pad portion 42a is electrically connected to the first electrode 121 of the first semiconductor element 1A, and the first electrode 121 is a source electrode, so the plurality of lead portions 43a are source terminals of the first semiconductor element 1A.

[0111] Each of the plurality of lead portions 43b is connected to a bonding pad portion 42b. As described above, the bonding pad portion 42b is electrically connected to the first electrode 121 of the first semiconductor element 1B, and the first electrode 121 is the source electrode, so the plurality of lead portions 43b are the source terminal of the first semiconductor element 1B.

[0112] Each of the plurality of lead portions 43c is connected to a bonding pad portion 42c. As described above, the bonding pad portion 42c is electrically connected to the second electrode 122 of each of the first semiconductor elements 1A and 1B, and since each of the second electrodes 122 is a drain electrode, the plurality of lead portions 43c are drain terminals of each of the first semiconductor elements 1A and 1B. In this embodiment, the drain terminals of the first semiconductor elements 1A and 1B are shared by the bonding pad portion 42c and the plurality of lead portions 43c, but the drain terminals of the first semiconductor elements 1A and 1B may be separate.

[0113] Each of the plurality of lead portions 43d is connected to a respective bonding pad portion 42d. As described above, each of the bonding pad portions 42d is electrically connected to the second semiconductor element 2. Each of the plurality of lead portions 43d is electrically connected to the second semiconductor element 2 as needed to function as, for example, a power grid terminal, a device control terminal, an analog power input terminal, a feedback terminal, a soft start time setting terminal, a spread spectrum setting terminal, a mode switching terminal, an internal constant voltage control terminal, or an ERRAMP output terminal. Note that these are merely examples, and the lead portions 43d may be electrically connected to the second semiconductor element 2 to function as other terminals. Note that, although not shown in FIG. 4 , in this embodiment, the third electrode 123 of each first semiconductor element 1 is electrically connected to the second semiconductor element 2.

[0114] Each of the multiple side extending portions 44 is a portion extending from an X-direction edge of the die pad portion 41. One X-direction edge of each side extending portion 44 is connected to the die pad portion 41, and the other X-direction edge is exposed from the sealing resin 5. In this embodiment, in a plan view, the side extending portions 44 include two side extending portions 44 extending from each X-direction edge of the die pad portion 41, and the two side extending portions 44 are respectively arranged on each Y-direction edge side of the die pad portion 41.

[0115] As shown in FIGS. 1 to 6, the sealing resin 5 covers the plurality of first semiconductor elements 1, the second semiconductor elements 2, the plurality of first conductive members 31, the plurality of second conductive members 32, and a portion of the lead frame 4. The sealing resin 5 is made of an insulating material. In this embodiment, the sealing resin 5 is made of, for example, a black epoxy resin. The sealing resin 5 has a rectangular shape in a plan view. <Manufacturing method of semiconductor device A1> Next, a description will be given of a method for manufacturing semiconductor device A1, particularly a method for bonding first conductive member 31. Figures 12A to 12C are diagrams showing steps related to bonding first conductive member 31 in the manufacturing process of semiconductor device A1.

[0116] After forming a plurality of element electrodes 12, a wiring layer 13, an insulating layer 19, a plurality of vias 20 and a protective layer 23 on the aforementioned semiconductor substrate 11, the semiconductor substrate 11 is bonded to the die pad portion 41 via a bonding material 411.

[0117] 12A to 12C, first conductive member 31 is bonded to first pad portion 142a. For example, a wedge bonder 50 is used to bond first conductive member 31. Wedge bonder 50 includes wire guide 502 that holds thin metal wire 501 that is the material for first conductive member 31, a wedge tool 503 that applies a load and ultrasonic waves to thin metal wire 501, and a cutter 504 that cuts thin metal wire 501 after bonding.

[0118] First, as shown in FIG. 12A, with the end of the thin metal wire 501 clamped by the wedge tool 503, the wedge bonder 50 is lowered until the thin metal wire 501 comes into contact with the first pad portion 142a.

[0119] Next, as shown in FIG. 12B, ultrasonic waves US are applied to the thin metal wire 501 from top to bottom while a load F is being applied to the thin metal wire 501. US 13, the vibration direction D1 is a direction along the longitudinal direction D1 (Y direction) of the second plate-shaped member 151. In this embodiment, the vibration direction D US The angle between the direction D1 and the direction D2 is 0° (vibration direction D US and direction D1 are parallel), but the vibration direction D US The angle may be in the range of −30° to 30°. As a result, the end of the thin metal wire 501 is joined to the first pad portion 142a, and a joint portion 311 is formed.

[0120] 12C, wedge bonder 50 moves to a position above second pad portion 142b while holding thin metal wire 501 in a clamped state with wedge tool 503. Then, load F and ultrasonic waves US are applied as in FIG. 12B to form bonded portion 312. Thereafter, thin metal wire 501 is bonded to bonding pad portion 42a in a similar manner and cut by cutter 504, thereby completing the bonding of first conductive member 31.

[0121] After this series of wire bonding processes is performed on all of the first conductive members 31 and all of the second conductive members 32, the lead frame 4 and the structure on the lead frame 4 are sealed with sealing resin 5 to obtain the semiconductor device A1. <<Function and Effect of Semiconductor Device A1>> Next, the effects of the semiconductor device A1 according to this embodiment will be described.

[0122] As shown in FIG. 13, according to the manufacturing method of the semiconductor device A1 described above, the vibration direction D of the ultrasonic waves US relative to the longitudinal direction D1 (Y direction) of the second plate-like member 151 isUS The angle is in the range of -30° to 30°. The vibration direction D of the ultrasonic US by wedge bonding US By defining in this way, as shown in FIG. 8, the extension direction D1 of the first conductive member 31 relative to the extension direction D2 (Y direction) of the second plate-shaped member 151 is W1 ,D W2 The angles θ1 and θ2 can be set to −30° to 30°.

[0123] This can prevent cracks from occurring in the insulating layer 19 (first interlayer insulating film 191) around the first plate-shaped member 141. For example, it can prevent cracks from occurring in the first interlayer insulating film 191 near the boundary 144 (see FIG. 7B) between the first via portion 201a and the non-first via portion 201b. The presence or absence of this type of crack can be confirmed by removing the structure above the first interlayer insulating film 191 with, for example, an etching solution to expose the boundary 144 between the first via portion 201a and the non-first via portion 201b.

[0124] Furthermore, according to semiconductor device A1, second plate-shaped member 151 is formed in a solid pattern below first pad portion 142a and second pad portion 142b. This allows the force applied to first pad portion 142a and second pad portion 142b during ultrasonic bonding of first conductive member 31 to be received evenly across second plate-shaped member 151.

[0125] Furthermore, in this embodiment, the first via portion 201a, which is a collection of first vias 201 between the first plate-shaped member 141 and the second plate-shaped member 151, is also formed in a solid pattern, similar to the second plate-shaped member 151. Therefore, in the first interlayer insulating film 191, the boundary portion 144 (see FIG. 7B) between the first via portion 201a and the non-first via portion 201b can be separated laterally from the region below the first pad portion 142a and the second pad portion 142b.

[0126] This also makes it possible to prevent cracks from occurring in the insulating layer 19 (first interlayer insulating film 191) around the first plate-shaped member 141. For example, it is possible to prevent cracks from occurring in the first interlayer insulating film 191 near the boundary 144 (see FIG. 7B) between the first via portion 201a and the non-first via portion 201b.

[0127] When a horizontal MOSFET such as each first semiconductor element 1 is formed on a semiconductor substrate 11, wiring layers that should be insulated from each other may be adjacent to each other below the pad portion due to space constraints on the semiconductor substrate 11. In this embodiment, the first electrode conductive member 141a (source side wiring) and the second electrode conductive member 141b (drain side wiring) are adjacent to each other as wiring layers that should be insulated from each other. Even in such a case, if cracks can be prevented from occurring in the first interlayer insulating film 191 as described above, short circuits between the first electrode conductive member 151a (source side wiring) and the second electrode conductive member 151b (drain side wiring) can be effectively prevented. As a result, a highly reliable semiconductor device A1 can be provided.

[0128] Ultrasonic vibration direction D US The change in the rate of cracking of the insulating layer due to the temperature difference is shown in Figures 15 and 16. The evaluations in Figures 15 and 16 were obtained when an aluminum wire was bonded to pad portion 609 on the top layer of wiring layer 60 shown in Figure 14.

[0129] The wiring layer 60 has a three-layer structure and includes a first plate-shaped member 601, a second plate-shaped member 602, and a third plate-shaped member 603, which are arranged alternately and orthogonally from top to bottom. The first plate-shaped member 601 and the third plate-shaped member 603 extend in the Y direction, and the second plate-shaped member 602 extends in the X direction. A first interlayer insulating film 606 having a plurality of first vias 604 formed therein is interposed between the first plate-shaped member 601 and the second plate-shaped member 602. A second interlayer insulating film 607 having a plurality of second vias 605 formed therein is interposed between the second plate-shaped member 602 and the third plate-shaped member 603. The surface of the first plate-shaped member 601 is covered with a protective layer 608, and a portion of the first plate-shaped member 601 is exposed as a pad portion 609 through an opening in the protective layer 608.

[0130] 12B and 13, ultrasonic waves were applied at an angle of 0° (parallel to direction D1) to the direction D1 (X direction) in which the second plate-shaped member 602 extends, and aluminum wires were joined. On the other hand, Fig. 16 shows the results when ultrasonic waves were applied at an angle of 90° (perpendicular to direction D1) to the direction D1 (X direction) in which the second plate-shaped member 602 extends, and aluminum wires were joined.

[0131] As shown in FIG. 15, if ultrasonic waves are applied at an angle of 0° (parallel to the X direction) with respect to the direction D1 (X direction) in which the second plate-shaped member 602 extends to join the aluminum wire, an A rating with a crack occurrence rate of 0% can be achieved not only within the range of the process margin (the allowable variation taking into account process variations) when joining the aluminum wire, but also outside the range of the process margin.

[0132] Furthermore, since the second plate-like member 151 is formed on the entire lower area of ​​the first pad portion 142a and the second pad portion 142b, the vibration direction D of the ultrasonic waves shown in FIG. US For example, the directivity of the second plate-shaped member 151 with respect to the vibration direction D US13 from being parallel to direction D1 to being perpendicular to direction D1, the force applied to solid-pattern second plate-shaped member 151 does not change significantly. As a result, first conductive member 31 can be joined to first pad portion 142a and second pad portion 142b from various directions, thereby increasing the degree of freedom in the directionality of first conductive member 31. <<Variations in Materials for the First Pad Portion 142a and the Second Pad Portion 142b>> 17 and 18 are diagrams for explaining variations in the material of the first pad portion 142a and the second pad portion 142b.

[0133] The conductive material of the first plate-shaped member 141 forming the first pad portion 142a and the second pad portion 142b may be a material containing Al as the main component alone, as described above, or the materials shown in Figures 17 and 18 may be applied.

[0134] 17 includes a first layer 1411a that forms the shape of the first plate-shaped member 1411, and a second layer 1411b formed on the first layer 1411a. The conductive material of the first layer 1411a may be, for example, a material containing Al (aluminum) and Cu (copper) as its main components. On the other hand, the conductive material of the second layer 1411b may be, for example, a material containing Ni (nickel) as its main component. The material containing Ni as its main component may be, for example, simple Ni or a Ni alloy containing 90 wt % or more of Ni.

[0135] Second layer 1411b may be, for example, a sputtered layer formed on first layer 1411a by sputtering, or a plated layer formed on first layer 1411a by plating. First layer 1411a may have a thickness of, for example, 1.6 μm to 6.0 μm, and second layer 1411b may have a thickness of, for example, 1.0 μm to 5.0 μm.

[0136] In this way, by using second layer 1411b made of a material mainly containing Ni, the surface of first plate-shaped member 1411, i.e., first pad portion 142a and second pad portion 142b, can be formed of a material mainly containing Ni. This increases the affinity between first conductive member 31 and first pad portion 142a and second pad portion 142b when Al wire is used as first conductive member 31, allowing first conductive member 31 to be joined to first pad portion 142a and second pad portion 142b with good joining strength.

[0137] Furthermore, when two or more of Al wire, Cu wire, and Au wire are used in combination for the first conductive member 31, the material of the first pad portion 142a and the second pad portion 142b may be changed to match the material of the first conductive member 31 bonded to each of the first pad portion 142a and the second pad portion 142b. For example, the material mainly containing Ni shown in Fig. 17 may be used for the first pad portion 142a and the second pad portion 142b to which the Al wire is bonded, and the material mainly containing Al shown in Figs. 9 to 11 may be used for the first pad portion 142a and the second pad portion 142b to which the Au wire is bonded.

[0138] 18 includes a first layer 1412a that forms the shape of the first plate-shaped member 1412, a second layer 1412b formed on the first layer 1412a, and a third layer 1412c formed on the second layer 1412b. In this embodiment, the first layer 1412a, the second layer 1412b, and the third layer 1412c may be examples of the "first portion," "second portion," and "third portion" recited in the claims, respectively.

[0139] The conductive material of the first layer 1412a is, for example, a material mainly composed of Cu (copper), and may be Cu alone or a Cu alloy containing 90 wt% or more of Cu. The conductive material of the second layer 1412b is, for example, a material mainly composed of Ni (nickel), and may be Ni alone or a Ni alloy containing 90 wt% or more of Ni. The conductive material of the third layer 1412c is, for example, a material mainly composed of Pd (palladium), and may be Pd alone or a Pd alloy containing 90 wt% or more of Pd.

[0140] Second layer 1412b and third layer 1412c may be, for example, sputtered layers formed in sequence on first layer 1412a by sputtering, or plated layers formed in sequence on first layer 1412a by plating. The thickness of first layer 1412a may be, for example, 6.0 μm to 10.0 μm, the thickness of second layer 1412b may be, for example, 1.0 μm to 5.0 μm, and the thickness of third layer 1412c may be, for example, 0.01 μm to 0.4 μm.

[0141] In this way, by applying the third layer 1412c made of a material primarily composed of Pd, the surface of the first plate-shaped member 1412, i.e., the first pad portion 142a and the second pad portion 142b, can be formed of a material primarily composed of Pd.

[0142] Furthermore, the materials of the first pad portion 142a and the second pad portion 142b do not need to be unified to any one of the Al-based material of Figures 9 to 11, the Ni-based material of Figure 17, and the Pd-based material of Figure 18, and for example, a combination of two or more of the three types of materials may be used. <<Variations in the shape of the second plate-shaped member 151>> 19 and 20 are diagrams for explaining variations in the shape of the second plate-shaped member 151. FIG.

[0143] As described above, the second plate-shaped member 151 may be formed in a solid pattern in the lower region 143 of the first plate-shaped member 141, but it does not have to be formed in a solid pattern, as shown in Figures 19 and 20.

[0144] 19 is thinner than the lower region 143 of the first plate-shaped member 141 (the region overlapping the first plate-shaped member 141 in a plan view), and is formed, for example, in a line shape. A plurality of second plate-shaped members 1511 (two in FIG. 19) are formed in the lower region 143 of the first plate-shaped member 141. That is, in the lower region 143 of one first plate-shaped member 141, two second plate-shaped members 1511 extend in the Y direction with a gap between them.

[0145] 19. The first via portion 2011a between the second plate-shaped member 1511 and the first plate-shaped member 141 may be thinner than the first plate-shaped member 141, similar to the second plate-shaped member 1511, and may be formed in the same shape as the second plate-shaped member 1511 in a plan view. Furthermore, the third plate-shaped member 1611 and the second via portion 2021a may be formed in the same shape as the second plate-shaped member 1511 and the first via portion 2011a in a plan view, respectively.

[0146] 19, the second plate-shaped members 1512 shown in Fig. 20 are thinner than the lower region 143 of the first plate-shaped members 141 (the region overlapping the first plate-shaped members 141 in a plan view) and are formed, for example, in a line shape. The second plate-shaped members 1512 are formed in one-to-one correspondence with the first plate-shaped members 141, and in the lower region 143 of one first plate-shaped member 141, one second plate-shaped member 1512 extends in the Y direction.

[0147] Also, the first via portion 2012a between the second plate-shaped member 1512 and the first plate-shaped member 141 may be thinner than the first plate-shaped member 141, similar to the second plate-shaped member 1512, and may be formed in the same shape as the second plate-shaped member 1512 in a planar view. Furthermore, the third plate-shaped member 1612 and the second via portion 2022a may have the same shape as the second plate-shaped member 1512 and the first via portion 2012a in a planar view, respectively, in FIG.

[0148] 19 and 20, the second plate-shaped members 1511 and 1512 extend in the Y direction. Therefore, the extension direction D1 of the first conductive member 31 relative to the extension direction D2 (Y direction) of the second plate-shaped members 1511 and 1512 is W1 ,D W2 The angles θ1 and θ2 can be set to −30° to 30°, which makes it possible to prevent cracks from occurring in the insulating layer 19 (first interlayer insulating film 191) around the first plate-shaped member 141.

[0149] Although one embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0150] For example, in the above-described embodiment, the semiconductor device A1 includes a plurality of first semiconductor elements 1 and second semiconductor elements 2. However, the present invention is not limited to this. For example, the semiconductor device A1 may include only one first semiconductor element 1, or may not include any second semiconductor elements 2.

[0151] In the above embodiment, the longitudinal direction D2 of the third plate-shaped member 161 is parallel to the longitudinal direction D1 of the second plate-shaped members 151, 1511, and 1512, but it may be perpendicular to the longitudinal direction D1.

[0152] Furthermore, in the above embodiment, the first conductive member 31 is formed on the first pad portion 142a and the second pad portion 142b by wedge bonding, but it may also be formed by ball bonding.

[0153] In addition, various design modifications can be made within the scope of the claims.

[0154] In addition to the invention described in the claims, the following features can be extracted from the description in this specification and drawings. [B1] A pad portion; an insulating layer supporting the pad portion; a first wiring layer formed in a layer below the pad portion and having a solid pattern below the pad portion; a conductive member bonded to a surface of the pad portion.

[0155] According to this configuration, the first wiring layer is formed in a solid pattern below the pad portion. This makes it possible to prevent cracks from occurring in the insulating layer. Note that the first wiring layer having a solid pattern below the pad portion may mean, for example, that the first wiring layer is formed so as to cover the entire area below the pad portion, that the first wiring layer is not divided in the area below the pad portion, or that the first wiring layer is formed without gaps in the area below the pad portion. [B2] The semiconductor device according to B1, wherein the pad portion includes a material containing aluminum as a main component. [B3] The semiconductor device according to B1 or B2, wherein the conductive member includes a material containing either aluminum or copper as a main component. [B4] The semiconductor device according to any one of B1 to B3, wherein the bonding portion of the conductive member to the pad portion includes a bonding portion formed by wedge bonding. [B5] The semiconductor device according to B4, wherein the conductive member has two or more joints. [B6] The semiconductor device according to any one of B1 to B5, wherein the conductive member includes a linear member having a thickness of 100 μm to 600 μm. [B7] The semiconductor device according to any one of B1 to B6, wherein the pad portion has a thickness of 1.6 μm to 6.0 μm. [B8] a semiconductor substrate having a substrate main surface; a first element electrode formed on the main surface of the substrate and electrically connected to the first wiring layer; a second element electrode formed on the main surface of the substrate at a distance from the first element electrode, through which a channel current flows between the second element electrode and the first element electrode via the semiconductor substrate; The semiconductor device according to any one of B1 to B7, further comprising: a second wiring layer formed in the same layer as the first wiring layer at a distance from the first wiring layer, and electrically connected to the second element electrode.

[0156] When an element structure in which a channel current flows laterally along the substrate main surface is formed on a semiconductor substrate, a second wiring layer may be formed around a first wiring layer due to space constraints on the semiconductor substrate. In such a case, if cracks in the insulating layer can be suppressed as described above, short circuits between the first wiring layer and the second wiring layer can be suppressed. As a result, a highly reliable semiconductor device can be provided. [B9] the conductive member extends in a first direction in a plan view, The semiconductor device according to any one of B1 to B8, further comprising a third wiring layer formed below the first wiring layer and extending in the first direction below the first wiring layer. [B10] The semiconductor device according to B9, further comprising a via portion formed between the first wiring layer and the third wiring layer, connecting the first wiring layer and the third wiring layer, and extending in the first direction in a planar view. [B11] the pad portion includes a surface to which the conductive member is bonded, The semiconductor device according to any one of B1 to B10, wherein the surface of the pad portion contains a material containing nickel as a main component. [B12] The semiconductor device according to any one of B1 to B10, wherein the pad portion includes a first portion formed of a material primarily composed of copper, a second portion formed on the first portion of a material primarily composed of nickel, and a third portion formed on the second portion of a material primarily composed of palladium, forming the surface of the pad portion.

[0157] This application corresponds to Japanese Patent Application No. 2020-054750 filed with the Japan Patent Office on March 25, 2020, and Japanese Patent Application No. 2020-054751 filed with the Japan Patent Office on March 25, 2020, the entire disclosures of which are incorporated herein by reference. [Explanation of symbols]

[0158] A1: Semiconductor device D1: Direction D2: Direction D US :direction D W1 :direction D W2 :direction D W3 : Longitudinal direction θ1: Angle θ2: Angle θ3: Angle 1: First semiconductor element 1A: First semiconductor element 1B: First semiconductor element 2: Second semiconductor element 11: Semiconductor substrate 12: Element electrode 13: Wiring layer 14: First conductive layer 15: Second conductive layer 16: Third conductive layer 19: Insulating layer 20: Beer 31: First conductive member 60: Wiring layer 111: Main surface of substrate 121: 1st electrode 122: 2nd electrode 141: First plate-shaped member 142a: First pad section 142b: Second pad section 151: Second plate-shaped member 151a: First electrode conductive member 151b: Second electrode conductive member 161: Third plate-shaped member 161a: First electrode conductive member 161b: Second electrode conductive member 191: First interlayer insulating film 311: Joint 312: Joint 315: Extension part 501: Fine metal wire 601: First plate-shaped member 602: Second plate-shaped member 606: First interlayer insulating film 609: Pad section 1411: First plate-shaped member 1411a: 1st layer 1411b: 2nd layer 1412: First plate-shaped member 1412a: 1st layer 1412b: 2nd layer 1412c: 3rd layer 1511: Second plate-shaped member 1512: Second plate-shaped member

Claims

1. A semiconductor substrate, a plurality of pad portions spaced apart from each other in a same region on the semiconductor substrate; an insulating layer supporting the pad portion; a first wiring layer formed in a layer below the pad portion and extending in a first direction below the pad portion; the semiconductor device including: a bridge portion that joins and bridges the surfaces of adjacent ones of the plurality of pad portions; and a conductive member that extends in a direction that forms an angle of -30° to 30° with respect to the first direction.

2. The semiconductor device according to claim 1 , wherein a bonding portion of said conductive member to said pad portion includes a bonding portion that is long in one direction in a plan view.

3. A semiconductor substrate; a plurality of pad portions spaced apart from each other in a same region on the semiconductor substrate; an insulating layer supporting the pad portion; a first wiring layer formed in a layer below the pad portion and extending in a first direction below the pad portion; a bridge portion that bridges the surfaces of adjacent pad portions among the plurality of pad portions, and a conductive member having a joint portion that is long in one direction in a plan view, The semiconductor device, wherein an angle of the longitudinal direction of the joint with respect to the first direction is −30° to 30°.

4. 4. The semiconductor device according to claim 1, wherein the pad portion includes a material containing aluminum as a main component.

5. 5. The semiconductor device according to claim 1, wherein the conductive member contains a material containing either aluminum or copper as a main component.

6. The semiconductor device according to claim 2 , wherein the conductive member has two or more joints.

7. 7. The semiconductor device according to claim 1, wherein the conductive member includes a linear member having a thickness of 100 μm to 600 μm.

8. 8. The semiconductor device according to claim 1, wherein the pad portion has a thickness of 1.6 μm to 6.0 μm.

9. The semiconductor substrate has a substrate main surface, a first element electrode formed on the main surface of the substrate and electrically connected to the first wiring layer; a second element electrode formed on the main surface of the substrate at a distance from the first element electrode, and a channel current flows between the second element electrode and the first element electrode via the semiconductor substrate; 9. The semiconductor device according to claim 1, further comprising: a second wiring layer formed in the same layer as the first wiring layer at a distance from the first wiring layer and electrically connected to the second element electrode.

10. a third wiring layer formed below the first wiring layer and extending in a second direction below the first wiring layer; 10. The semiconductor device according to claim 1, wherein the second direction is parallel to or perpendicular to the first direction.

11. the pad portion includes a surface to which the conductive member is bonded, 11. The semiconductor device according to claim 1, wherein the surface of the pad portion contains a material containing nickel as a main component.

12. The semiconductor device according to any one of claims 1 to 10, wherein the pad portion includes a first portion formed of a material mainly composed of copper, a second portion formed on the first portion of a material mainly composed of nickel, and a third portion formed on the second portion of a material mainly composed of palladium, forming the surface of the pad portion.

13. A step of preparing a semiconductor substrate including a plurality of pad portions spaced apart from each other, an insulating layer supporting the pad portions, and a first wiring layer formed in a layer below the pad portions and extending in a first direction below the pad portions; and bonding the conductive member to each of the surfaces of adjacent ones of the plurality of pad portions by ultrasonic vibration applied along a direction forming an angle of -30° to 30° with respect to the first direction, so that a conductive member having a bridge portion that bridges between the plurality of pad portions in the same region on the semiconductor substrate is formed.

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