substrate

Abstract

To provide a substrate where the design can be smoothly changed in accordance with a determination whether a waveform correction IC is mounted or not mounted.SOLUTION: A substrate is used for mounting a semiconductor chip and an electronic component. The substrate comprises: a first face; a second face at an opposite side of the first face; a first via and a second via penetrating the substrate; a first pad-on-via connected to the first via; a second pad-on-via connected to the second via; a third pad-on-via connected to the first via; a fourth pad-on-via connected to the second via; a first wire which is positioned between the first via and the second via and provided separately from the first via; a second wire which is positioned between the first via and the second via and provided separately from the second via and the first wire; and a third wire which is provided between the first via and the second via on the second face and provided separately from the first via and the second via.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a substrate. [Background technology]

[0002] A high-speed digital transmission circuit is known (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4616861 Summary of the Invention [Problem to be solved by the invention]

[0004] In high-speed digital transmission circuits, it is important to ensure the quality of the signal waveforms that operate the CPU (Central Processing Unit) and peripheral electronic components. In designing a board that includes a high-speed digital transmission circuit, a decision is made as to whether or not to mount a waveform correction integrated circuit (IC) that corrects the signal waveform on the board, depending on the results of a compliance test.

[0005] The present invention has been made in consideration of the above problems, and has an object to provide a board that allows smooth design changes depending on whether or not a waveform correction IC is to be installed. [Means for solving the problem]

[0006] A substrate according to one aspect of the present invention is a substrate for mounting a semiconductor chip and an electronic component, the substrate having a first surface, a second surface opposite to the first surface, a first via penetrating the substrate and provided between the first surface and the second surface, a second via penetrating the substrate and provided between the first surface and the second surface, a first pad-on-via provided on the first surface and connected to the first via, a second pad-on-via provided on the first surface and connected to the second via, a third pad-on-via provided on the second surface and connected to the first via, a fourth pad-on-via provided on the second surface and connected to the second via, a first wiring located between the first via and the second via on the first surface and spaced apart from the first via, a second wiring located between the first via and the second via on the first surface and spaced apart from the second via and the first wiring, and a third wiring located between the first via and the second via on the second surface and spaced apart from the first via and the second via. a first mounting area in which the semiconductor chip is mounted, a second mounting area in which the electronic components are mounted, and a third mounting area in which a waveform correction IC is mounted; has. The first mounting area and the second mounting area are part of the second surface. The third mounting area is part of the first surface. A part of a first connection wiring electrically connected to the first via is arranged in the first mounting area. A part of a second connection wiring electrically connected to the second via is arranged in the second mounting area. A part of the first wiring and a part of the second wiring are arranged in the third mounting area.

[0007] According to the board of the above-mentioned embodiment, the board can be selectively used to mount a waveform correction IC or not, and the board design can be smoothly changed depending on whether or not the waveform correction IC is mounted.

[0009] According to the substrate of the above-mentioned embodiment, a substrate having a first mounting area, a second mounting area, and a third mounting area can be realized as areas in which a semiconductor chip, an electronic component, and a waveform correction IC are to be mounted.

[0010] A substrate according to one embodiment of the present invention may have a first conductive region overlapping the first pad-on-via and the first wiring when viewed in a thickness direction of the substrate, a second conductive region overlapping the second pad-on-via and the second wiring when viewed in the thickness direction of the substrate, and a third conductive region overlapping the third pad-on-via and the third wiring and overlapping the fourth pad-on-via and the third wiring when viewed in the thickness direction of the substrate.

[0011] According to the substrate of the above-mentioned embodiment, a substrate having a first conductive region, a second conductive region, and a third conductive region can be realized as regions in which conductive parts that electrically connect a semiconductor chip, electronic components, and a waveform correction IC to the substrate are to be arranged.

[0012] A substrate according to one embodiment of the present invention may have a first conductive portion formed on the first surface and electrically connecting the first pad-on-via and the first wiring, and a second conductive portion formed on the first surface and electrically connecting the second pad-on-via and the second wiring.

[0013] According to the substrate of the above-mentioned aspect, a substrate can be realized having a first conductive portion that electrically connects the first pad-on-via and the first wiring, and a second conductive portion that electrically connects the second pad-on-via and the second wiring.

[0014] The substrate according to one aspect of the present invention comprises: A substrate for mounting a semiconductor chip and an electronic component, the substrate having a first surface, a second surface opposite to the first surface, a first via penetrating the substrate and provided between the first surface and the second surface, a second via penetrating the substrate and provided between the first surface and the second surface, a first pad-on-via provided on the first surface and connected to the first via, a second pad-on-via provided on the first surface and connected to the second via, a third pad-on-via provided on the second surface and connected to the first via, a fourth pad-on-via provided on the second surface and connected to the second via, and a first via and a second via on the first surface. a first wiring located between the first via and the second via and spaced apart from the first via; a second wiring located between the first via and the second via on the first surface and spaced apart from the second via and the first wiring; a third wiring located between the first via and the second via on the second surface and spaced apart from the first via and the second via; a first conductive portion formed on the first surface and electrically connecting the first pad-on-via and the first wiring; and a second conductive portion formed on the first surface and electrically connecting the second pad-on-via and the second wiring. A waveform correction IC is mounted on the first surface and connected to the first wiring and the second wiring. do .

[0015] According to the board according to the above aspect, it is possible to realize a board on which a waveform correction IC is mounted.

[0016] A substrate according to one embodiment of the present invention has a semiconductor chip electrically connected to the first via and an electronic component electrically connected to the second via, and the semiconductor chip may be electrically connected to the electronic component via the first via, the first pad-on-via, the first conductive portion, the first wiring, the waveform correction IC, the second wiring, the second conductive portion, the second pad-on-via, the second via, and the fourth pad-on-via.

[0017] According to the board according to the above aspect, it is possible to realize a board on which a semiconductor chip, an electronic component, and a waveform correction IC are mounted.

[0018] A substrate according to one embodiment of the present invention may have a third conductive portion formed on the second surface, the third conductive portion electrically connecting the third pad-on-via and the third wiring, and electrically connecting the fourth pad-on-via and the third wiring.

[0019] According to the substrate according to the above-mentioned embodiment, it is possible to realize a substrate having a third conductive portion that electrically connects the third pad-on-via and the third wiring and electrically connects the fourth pad-on-via and the third wiring.

[0020] A substrate according to one embodiment of the present invention may have a semiconductor chip electrically connected to the first via and an electronic component electrically connected to the second via, and the semiconductor chip may be electrically connected to the electronic component via the first via, the third pad-on-via, the third wiring, the third conductive portion, and the fourth pad-on-via.

[0021] According to the above-described embodiment, a substrate on which a semiconductor chip and an electronic component are mounted can be realized. In this configuration, the waveform correction IC is not mounted on the substrate.

[0022] The length of the line from the semiconductor chip to the electronic component may be longer than the length of the line defined in the specifications of the semiconductor chip.

[0023] According to the substrate according to the above aspect, a substrate that meets the specifications of a semiconductor chip can be realized. Effect of the Invention

[0024] According to the board of this embodiment of the present invention, it is possible to smoothly change the design depending on whether or not a waveform correction IC is to be mounted. [Brief description of the drawings]

[0025] [Figure 1] 1 is a cross-sectional view partially illustrating a substrate according to a first embodiment of the present invention. [Diagram 2]FIG. 1 is a cross-sectional view partially showing a substrate according to a first embodiment of the present invention, illustrating a state in which a waveform correction IC is mounted on the substrate in a structure in which a semiconductor chip and electronic components are mounted. [Diagram 3] FIG. 1 is a cross-sectional view partially showing a substrate according to a first embodiment of the present invention, illustrating a state in which a waveform correction IC is not mounted on the substrate in a structure in which a semiconductor chip and electronic components are mounted. [Figure 4] FIG. 11 is a perspective view showing the whole of an electronic device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] A substrate according to an embodiment of the present invention will be described with reference to the drawings. In the description of the embodiments, the same reference numerals are used for components having the same or similar functions. The redundant description of those components may be omitted. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones.

[0027] In the drawings referred to in the description of the embodiments, the X, Y, and Z directions corresponding to a three-dimensional Cartesian coordinate system are shown (symbols X, Y, and Z). The X direction corresponds to the width direction (longitudinal direction) of the substrate. The Y direction corresponds to the depth direction (shortitudinal direction) of the substrate. The Z direction corresponds to the thickness direction of the substrate. A drawing in which the substrate is viewed from the Z direction may be referred to as a "planar view." Note that the X, Y, and Z directions are terms used to describe the relative positions of multiple components that make up the substrate, and do not limit the attitude of the substrate.

[0028] First Embodiment <Substrate> 1, the substrate 10A has a first surface F and a second surface S opposite to the first surface F. The first surface F and the second surface S are parallel to the X direction and the Y direction, respectively.

[0029] The substrate 10A has a first via 11F, a second via 11S, a first pad on via 12A, a second pad on via 12B, a third pad on via 12C, a fourth pad on via 12D, a first wiring 13A, a second wiring 13B, a third wiring 13C, a first connection wiring 14, and a second connection wiring 15.

[0030] The substrate 10A is used for mounting semiconductor chips and electronic components, which will be described later, and is further used for mounting a waveform correction IC, if necessary. Therefore, the substrate 10A is provided with areas for mounting the semiconductor chip, the electronic components, and the waveform correction IC in advance. The substrate 10A has a first mounting area 17A, a second mounting area 17B, and a third mounting area 17C.

[0031] The substrate 10A has regions where conductive parts are arranged to electrically connect the wirings 13A, 13B, and 13C to the pad-on-vias 12A, 12B, 12C, and 12D according to the mounting structure of the semiconductor chip, the electronic components, and the waveform correction IC. The substrate 10A has a first conductive region 18A, a second conductive region 18B, and a third conductive region 18C.

[0032] The substrate 10A is a laminated substrate formed by stacking a plurality of insulating layers and a plurality of conductive layers. The above-mentioned plurality of wirings 13A, 13B, 14, and 15 form a conductive layer of the substrate 10A. The conductive layer is formed of, for example, a copper circuit wiring. In such a laminated substrate, impedance adjustment is performed as necessary. For example, a high-density interconnector (HDI) substrate is used as the substrate 10A.

[0033] <First and second vias> The first via 11F penetrates the substrate 10A. The first via 11F is provided between the first surface F and the second surface S. The first via 11F is a conductive wiring that extends in the Z direction. The second via 11S penetrates the substrate 10A. The second via 11S is provided between the first surface F and the second surface S. The second via 11S is a conductive wiring that extends in the Z direction. The first via 11F and the second via 11S are made of a known material, such as copper.

[0034] <1st to 4th pad on via> The first pad-on-via 12A is provided on the first surface F and is connected to the first via 11F. In other words, the first pad-on-via 12A is connected to one of the two ends of the first via 11F extending in the Z direction. The second pad-on-via 12B is provided on the first surface F and is connected to the second via 11S. In other words, the second pad-on-via 12B is connected to one of the two ends of the second via 11S extending in the Z direction.

[0035] The third pad-on-via 12C is provided on the second surface S and is connected to the first via 11F. In other words, the third pad-on-via 12C is connected to the other of the two ends of the first via 11F extending in the Z direction. The fourth pad-on-via 12D is provided on the second surface S and is connected to the second via 11S. In other words, the fourth pad-on-via 12D is connected to the other of the two ends of the second via 11S extending in the Z direction. The pad-on-vias 12A to 12D are made of a known material, such as copper.

[0036] <1st to 3rd wiring> The first wiring 13A is provided on the first surface F. The first wiring 13A is a conductive wiring extending in the X direction. The first wiring 13A is located between the first via 11F and the second via 11S in the X direction. The first wiring 13A is provided apart from the first via 11F in the X direction. That is, the first wiring 13A is not electrically connected to the first via 11F.

[0037] The second wiring 13B is provided on the first surface F. The second wiring 13B is a conductive wiring extending in the X direction. The second wiring 13B is located between the first via 11F and the second via 11S in the X direction. The second wiring 13B is provided apart from the second via 11S and the first wiring 13A in the X direction. In other words, the second wiring 13B is not conductive with the second via 11S.

[0038] The third wiring 13C is provided on the second surface S. The third wiring 13C is a conductive wiring extending in the X direction. The third wiring 13C is located between the first via 11F and the second via 11S in the X direction. The third wiring 13C is provided apart from the first via 11F and the second via 11S in the X direction. In other words, the third wiring 13C is not conductive with the first via 11F and the second via 11S.

[0039] <First and second connection wires> The first connection wiring 14 includes a horizontal wiring 14A, a vertical wiring 14B, and an exposed wiring 14C. The horizontal wiring 14A is a conductive wiring that extends in the X-direction. The horizontal wiring 14A is provided inside the substrate 10A. Inside the substrate 10A, an end of the first connection wiring 14 is connected to the first via 11F.

[0040] The vertical wiring 14B is a conductive wiring extending in the Z direction. The vertical wiring 14B is provided inside the substrate 10A. Inside the substrate 10A, the vertical wiring 14B is connected to an end of the first connection wiring 14 and an end of the exposed wiring 14C. The exposed wiring 14C is a conductive wiring extending in the X direction. The exposed wiring 14C is provided on the second surface S. The exposed wiring 14C is a wiring exposed on the second surface S. The exposed wiring 14C is connected to the vertical wiring 14B.

[0041] The second connection wiring 15 is a conductive wiring extending in the X direction. The second connection wiring 15 is provided on the second surface S. The second connection wiring 15 is a wiring exposed on the second surface S. The second connection wiring 15 is connected to the second via 11S through the fourth pad-on-via 12D.

[0042] In this embodiment, all of the above-mentioned multiple wirings 13A, 13B, 13C, 14A, 14B, 14C, and 15 extend in the X direction. The direction in which each of the multiple wirings extends is not limited to the X direction. At least one of the multiple wirings may extend in the Y direction or in a direction inclined toward the X direction.

[0043] <1st to 3rd mounting areas> The first mounting area 17A is a part of the second surface S. The exposed wiring 14C is arranged in the first mounting area 17A. That is, a part of the first connection wiring 14 is arranged in the first mounting area 17A. In other words, the first mounting area 17A overlaps the exposed wiring 14C of the first connection wiring 14 on the second surface S when viewed from the Z direction. The first mounting area 17A is an area where a semiconductor chip, which will be described later, is to be mounted.

[0044] The second mounting area 17B is a part of the second surface S. A part of the second connection wiring 15 is arranged in the second mounting area 17B. In other words, the second mounting area 17B overlaps with the second connection wiring 15 on the second surface S when viewed from the Z direction. The second mounting area 17B is an area where an electronic component, which will be described later, is to be mounted.

[0045] The third mounting area 17C is a part of the first surface F. A part of the first wiring 13A and a part of the second wiring 13B are arranged in the third mounting area 17C. In other words, the third mounting area 17C overlaps the first wiring 13A and the second wiring 13B on the first surface F when viewed from the Z direction. In the third mounting area 17C, the first wiring 13A is provided apart from the first pad-on-via 12A, and the second wiring 13B is provided apart from the second pad-on-via 12B. Furthermore, in the third mounting area 17C, the first wiring 13A is provided apart from the second wiring 13B. The third mounting area 17C is an area where a waveform correction IC to be described later is to be mounted.

[0046] <1st to 3rd conduction area> When viewed from the Z direction, the first conductive region 18A overlaps with the first pad-on-via 12A and the first wiring 13A on the first face F. The first conductive region 18A is a region where a first conductive portion that electrically connects the first pad-on-via 12A and the first wiring 13A is to be disposed. When viewed from the Z direction, the second conductive region 18B overlaps with the second pad-on-via 12B and the second wiring 13B on the first surface F. The second conductive region 18B is a region where a second conductive portion that electrically connects the second pad-on-via 12B and the second wiring 13B is to be disposed.

[0047] The third conduction region 18C overlaps the third pad-on-via 12C and the third wiring 13C on the second surface S, and also overlaps the fourth pad-on-via 12D and the third wiring 13C on the second surface S, when viewed from the Z direction. That is, two third conductive regions 18C are provided on the second surface S. One of the two third conductive regions 18C is a region where a third conductive portion that electrically connects one of the two third wirings 13C and the third pad-on-via 12C is to be disposed. The other of the two third conductive regions 18C is a region where a third conductive portion that electrically connects the other of the two third wirings 13C and the fourth pad-on-via 12D is to be disposed.

[0048] The conductive structures in the conductive regions 18A, 18B, and 18C are selected according to the mounting structures of the substrate 10B shown in FIG. 2 and the substrate 10C shown in FIG. 3, which will be described later.

[0049] <Selection of mounting structure for board> Depending on the result of a compliance test described later, it is possible to select a mounting structure in which the waveform correction IC is mounted on the substrate 10A, or a non-mounting structure in which the waveform correction IC is not mounted on the substrate 10A. In other words, the substrate 10A can be selectively used to become either a "structure with a waveform correction IC mounted" or a "structure with no waveform correction IC mounted". Next, a waveform correction IC mounting structure and a waveform correction IC non-mounting structure will be described. In the following description, the "waveform correction IC mounting structure" may be simply referred to as the "mounting structure," and the "waveform correction IC non-mounting structure" may be simply referred to as the "non-mounting structure."

[0050] <Waveform correction IC mounting structure> 2, the substrate 10B has a first conductive portion 16A, a second conductive portion 16B, a semiconductor chip 20, an electronic component 30, and a waveform correction IC 40. The substrate 10B differs from the substrate 10A in that the substrate 10B has the semiconductor chip 20, the electronic component 30, and the waveform correction IC 40. In FIG. 2, the same members as those in FIG. 1 are denoted by the same reference numerals, and their description will be omitted or simplified.

[0051] <Semiconductor chip> The semiconductor chip 20 is a chip including functions of a processor and a controller, and is, for example, a System-on-a-chip (SoC). The semiconductor chip 20 is disposed in the first mounting area 17A on the second surface S. The semiconductor chip 20 is connected to the exposed wiring 14C. As a result, the semiconductor chip 20 is electrically connected to the first via 11F.

[0052] <Electronic components> The electronic components 30 are appropriately selected depending on the circuit configuration of the board 10B and the components mounted on the board 10B. The electronic components 30 are, for example, a connector, a LAN controller IC, an SD controller IC, etc. Various modules can be connected to the connector. The electronic component 30 is disposed in the second mounting area 17B on the second surface S. The electronic component 30 is connected to the second connection wiring 15. As a result, the electronic component 30 is electrically connected to the second via 11S.

[0053] <Waveform correction IC> The waveform correction IC 40 has a waveform correction circuit. The waveform correction IC 40 has a function of correcting the signal waveform output from the semiconductor chip 20. As the waveform correction IC 40, a known IC is used. The waveform correction IC 40 is mounted on the first surface F. Specifically, the waveform correction IC 40 is disposed in the third mounting area 17C. The waveform correction IC 40 is connected to the first wiring 13A and the second wiring 13B.

[0054] <1st and 2nd conduction section> The substrate 10B has a first conductive portion 16A and a second conductive portion 16B. The first conductive portion 16A is formed on the first face F, and electrically connects the first pad-on-via 12A and the first wiring 13A. The first conductive portion 16A is disposed in the first conductive region 18A. The second conductive portion 16B is formed on the first surface F, and electrically connects the second pad-on-via 12B and the second wiring 13B. The second conductive portion 16B is disposed in the second conductive region 18B. The first conductive portion 16A and the second conductive portion 16B are made of a known material, such as copper.

[0055] In the structure shown in Figure 2, the semiconductor chip 20 is electrically connected to the electronic component 30 via the first via 11F, the first pad-on-via 12A, the first conductive portion 16A, the first wiring 13A, the waveform correction IC 40, the second wiring 13B, the second conductive portion 16B, the second pad-on-via 12B, the second via 11S, and the fourth pad-on-via 12D.

[0056] The line length from the semiconductor chip 20 to the electronic component 30 is longer than the line length specified in the specifications (design guide) of the semiconductor chip 20. Here, the line length from the semiconductor chip 20 to the electronic component 30 is the distance from the connection end 20T where the semiconductor chip 20 and the exposed wiring 14C are connected to the connection end 30T where the electronic component 30 and the second connection wiring 15 are connected. Specifically, in the mounting structure of the waveform correction IC shown in FIG. 2, the line length is the distance from the connection end 20T to the connection end 30T via the first connection wiring 14, the first via 11F, the first pad-on-via 12A, the first conductive portion 16A, the first wiring 13A, the waveform correction IC 40, the second wiring 13B, the second conductive portion 16B, the second pad-on-via 12B, the second via 11S, the fourth pad-on-via 12D, and the second connection wiring 15. This makes it possible to realize the substrate 10B according to the specifications of the semiconductor chip 20.

[0057] <Structure without waveform correction IC> 3, the substrate 10C has a semiconductor chip 20 and an electronic component 30. The substrate 10C differs from the substrate 10B in that the waveform correction IC 40 is not mounted thereon and that the substrate 10C has a third conductive portion 16C instead of the first conductive portion 16A and the second conductive portion 16B. In FIG. 3, the same members as those in FIG. 2 are denoted by the same reference numerals, and their description will be omitted or simplified.

[0058] <Third conductive part> The substrate 10C has two third conductive parts 16C. The two third conductive parts 16C are formed on the second surface S and arranged in a third conductive region 18C. One of the two third conductive parts 16C electrically connects the third pad-on-via 12C and the third wiring 13C. The other of the two third conductive parts 16C electrically connects the fourth pad-on-via 12D and the third wiring 13C. The third conductive portion 16C is made of a known material, such as copper.

[0059] 3, the semiconductor chip 20 is electrically connected to the electronic component 30 through the first via 11F, the third pad-on-via 12C, the two third conductive parts 16C, the third wiring 13C, and the fourth pad-on-via 12D. In other words, the waveform correction IC 40 is not disposed between the semiconductor chip 20 and the electronic component 30.

[0060] The line length from the semiconductor chip 20 to the electronic component 30 is longer than the line length specified by the specifications of the semiconductor chip 20. Here, the line length from the semiconductor chip 20 to the electronic component 30 is the distance from the connection end 20T where the semiconductor chip 20 and the exposed wiring 14C are connected to the connection end 30T where the electronic component 30 and the second connection wiring 15 are connected. Specifically, in the structure in which the waveform correction IC is not mounted as shown in FIG. 3, the line length is the distance from the connection end 20T to the connection end 30T via the first connection wiring 14, the first via 11F, the third pad-on-via 12C, the two third conductive parts 16C, the third wiring 13C, the fourth pad-on-via 12D, and the second connection wiring 15. This makes it possible to realize the substrate 10C according to the specifications of the semiconductor chip 20.

[0061] <Judgment based on compliance testing> Next, a procedure for determining whether to select the mounting structure shown in FIG. 2 or the non-mounting structure shown in FIG. 3 based on the result of the compliance test will be described.

[0062] First, a substrate 10C shown in FIG. 3 is prepared. A compliance test is performed on this substrate 10C by a known method. In the compliance test, the suitability of signal quality is judged, specifically, whether or not there is any deformation in the signal waveform supplied from the semiconductor chip to the electronic component, and whether or not the deformation of the signal waveform is acceptable.

[0063] <Judgment 1> If the compliance test results show that there is no need to correct the signal waveform, it is decided not to mount the waveform correction IC on the substrate 10A. In this case, the non-mounted structure including the substrate 10C is maintained as shown in FIG.

[0064] <Judgment 2> On the other hand, if the compliance test results in a determination that the signal waveform needs to be corrected, it is decided that the waveform correction IC should be mounted on the substrate 10A. In this case, a mounting structure having a substrate 10B as shown in Fig. 2 is prepared. A compliance test is performed on the mounting structure to confirm that the signal quality is suitable.

[0065] <Effects> As described above, the substrate 10A can be selectively used as the substrate 10B having a structure for mounting a waveform correction IC, or the substrate 10C having a structure for not mounting a waveform correction IC. This allows the substrate design to be smoothly changed depending on whether or not the waveform correction IC 40 is to be mounted.

[0066] Furthermore, in the design of a circuit board equipped with a conventional high-speed digital transmission circuit, the circuit is designed taking into consideration both the wiring pattern where the waveform correction IC is mounted and the wiring pattern where the waveform correction IC is not mounted. In such a circuit design, a stub to which the terminal of the waveform correction IC is connected is required regardless of whether the waveform correction IC is mounted or not. However, if the waveform correction IC is not mounted, the waveform correction IC is not mounted at the end of the stub, and an unused stub remains on the board. The unused stub causes signal disturbance. For example, signal reflection occurs at the end of the stub. The reflected signal causes signal disturbance.

[0067] In contrast, according to this embodiment, no stubs are used in the substrate 10A, and therefore no signal reflection occurs at the end of the stub as occurs in the conventional case.

[0068] <Second embodiment> Next, an electronic device according to a second embodiment of the present invention will be described. 4, the electronic device 100 according to the present embodiment is a clamshell (notebook) type PC (Personal Computer). The electronic device 100 may be a tablet type PC, a smartphone, or the like. The electronic device 100 includes a substrate 10B or a substrate 10C.

[0069] In addition, in the structure shown in FIG. 4, known devices constituting a clamshell PC, such as a storage device (hard disk or solid state drive), a battery, a keyboard, an external connection terminal, and the like, are omitted.

[0070] According to this embodiment, it is possible to realize electronic device 100 including substrate 10B on which a waveform correction IC is mounted, or electronic device 100 including substrate 10C on which no waveform correction IC is mounted.

[0071] Although preferred embodiments of the present invention have been described, it should be understood that these are illustrative of the present invention and should not be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the present invention. Thus, the present invention should not be considered as limited by the foregoing description, but rather by the scope of the claims. [Explanation of symbols]

[0072] 10A, 10B, 10C substrate, 11F first via, 11S second via, 12A first pad on via, 12B second pad on via, 12C third pad on via, 12D fourth pad on via, 13A first wiring, 13B second wiring, 13C third wiring, 14 first connection wiring, 14A horizontal wiring, 14B vertical wiring, 14C exposed wiring, 15 second connection wiring, 16A first conductive part, 16B second conductive part, 16C third conductive part, 17A first mounting area, 17B second mounting area, 17C third mounting area, 18A first conductive area, 18B second conductive area, 18C third conductive area, 20 semiconductor chip, 20T connection end, 30 electronic component, 30T connection end, 40 waveform correction IC, 100 electronic device, F first surface, S second surface

Claims

1. A substrate for mounting semiconductor chips and electronic components, The first page and a second surface opposite the first surface; and a first via extending through the substrate and disposed between the first surface and the second surface; a second via extending through the substrate and disposed between the first surface and the second surface; a first pad-on-via provided on the first surface and connected to the first via; a second pad-on-via provided on the first surface and connected to the second via; a third pad-on-via provided on the second surface and connected to the first via; a fourth pad-on-via provided on the second surface and connected to the second via; a first wiring located between the first via and the second via on the first surface and spaced apart from the first via; a second wiring located between the first via and the second via on the first surface and spaced apart from the second via and the first wiring; a third wiring located between the first via and the second via on the second surface and spaced apart from the first via and the second via; a first mounting area in which the semiconductor chip is mounted; a second mounting area in which the electronic component is mounted; a third mounting area in which a waveform correction IC is mounted; having the first mounting area and the second mounting area are parts of the second surface, the third mounting area is a part of the first surface, a portion of a first connection wiring electrically connected to the first via is disposed in the first mounting region; a portion of a second connection wiring electrically connected to the second via is disposed in the second mounting region; A part of the first wiring and a part of the second wiring are disposed in the third mounting region. substrate.

2. a first conductive region overlapping the first pad-on-via and the first wiring when viewed in a thickness direction of the substrate; a second conductive region overlapping the second pad-on-via and the second wiring when viewed in a thickness direction of the substrate; a third conductive region overlapping the third pad-on-via and the third wiring and overlapping the fourth pad-on-via and the third wiring when viewed from a thickness direction of the substrate; having The substrate of claim 1 .

3. a first conductive portion formed on the first surface and electrically connecting the first pad-on-via and the first wiring; a second conductive portion formed on the first surface and electrically connecting the second pad-on-via and the second wiring; having The substrate of claim 1 .

4. A substrate for mounting a semiconductor chip and an electronic component, comprising: The first page and a second surface opposite the first surface; and a first via extending through the substrate and disposed between the first surface and the second surface; a second via extending through the substrate and disposed between the first surface and the second surface; a first pad-on-via provided on the first surface and connected to the first via; a second pad-on-via provided on the first surface and connected to the second via; a third pad-on-via provided on the second surface and connected to the first via; a fourth pad-on-via provided on the second surface and connected to the second via; a first wiring located between the first via and the second via on the first surface and spaced apart from the first via; a second wiring located between the first via and the second via on the first surface and spaced apart from the second via and the first wiring; a third wiring located between the first via and the second via on the second surface and spaced apart from the first via and the second via; a first conductive portion formed on the first surface and electrically connecting the first pad-on-via and the first wiring; a second conductive portion formed on the first surface and electrically connecting the second pad-on-via and the second wiring; a waveform correction IC mounted on the first surface and connected to the first wiring and the second wiring; having substrate.

5. a semiconductor chip electrically connected to the first via; an electronic component electrically connected to the second via; having the semiconductor chip is electrically connected to the electronic component through the first via, the first pad-on-via, the first conductive portion, the first wiring, the waveform correction IC, the second wiring, the second conductive portion, the second pad-on-via, the second via, and the fourth pad-on-via; The substrate according to claim 4.

6. a third conductive portion formed on the second surface; the third conductive portion electrically connects the third pad-on-via to the third wiring and electrically connects the fourth pad-on-via to the third wiring; The substrate according to claim 1 or claim 4.

7. a semiconductor chip electrically connected to the first via; an electronic component electrically connected to the second via; having the semiconductor chip is electrically connected to the electronic component through the first via, the third pad-on-via, the third wiring, the third conductive portion, and the fourth pad-on-via. The substrate according to claim 6.

8. The line length from the semiconductor chip to the electronic component is longer than the line length defined in the specifications of the semiconductor chip. The substrate according to claim 5 .

9. The length of the line from the semiconductor chip to the electronic component is longer than the length of the line defined in the specifications of the semiconductor chip. The substrate according to claim 7.

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