Fault detection method and related device

Abstract

This application discloses a fault detection method, which is related to the field of computer technology. The fault detection method includes the steps of: obtaining a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit configured to execute a first task, the first task being executed in a target fault detection time interval FDTI; detecting whether the first test pattern is executed in the target FDTI; and executing the first test pattern in the target FDTI based on the first scheduling table when it is detected that the first test pattern is not executed in the target FDTI. This application ensures that the same test pattern is executed only once in the FDTI and is not executed repeatedly. This reduces the burden of the test patterns in the STL on the processor, shortens the time spent by the processor in detecting faults, and improves the operating efficiency of the processor.

Description

[Technical field]

[0001]

[0001] This application claims priority to Chinese Patent Application No. 202110657038.6, entitled "Fault Detection Method and Related Apparatus," filed with the State Intellectual Property Office of the People's Republic of China on June 11, 2021, the entire contents of which are incorporated herein by reference.

[0002]

[0002] TECHNICAL FIELD FIELD OF THE DISCLOSURE This application relates to the field of computer technology, and more particularly to fault detection methods and related apparatus. [Background technology]

[0003]

[0003] In the field of computers, random hardware failures can occur in data processing devices, either permanent failures caused by shorts or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle bombardment.

[0004]

[0004] In some application fields with high safety requirements, for example the vehicle field where safety is critical, in order to ensure functional safety, a fault detection mechanism can be provided in the processor to detect hardware faults and to ensure that a conservation action is performed in case of a hardware fault.

[0005]

[0005] Currently, in the prior art, a processor uses a software test library (SWTL) to detect faults in the logic circuit. Test Library, Test patterns in STL However, the STL contains a large number of test patterns, and periodically executing the test patterns in the STL by a processor results in a heavy burden on the processor, i.e., the processor needs to spend a long time on fault detection, thereby affecting the operation efficiency of the processor. Summary of the Invention

[0006]

[0006] A first aspect of the present invention provides a fault detection method that is applied to terminals in fields that require safety, such as vehicle-mounted terminals and control terminals in aerospace.

[0007] The method includes obtaining a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit configured to perform a first task, the first task being a target fault detection time interval. detection time The test is performed in the FDTI (Frequency-Domain Interval).

[0008]

[0008] The first task may be a task that needs to be executed in a target FDTI in the terminal, for example, a process or thread that needs to be executed in a target FDTI in the terminal. The manner in which the terminal determines the first task may be to obtain the first task from a task queue. A task in the task queue is a task that should be executed but is not being executed (or is called a task in a ready state). The terminal may determine the first task by obtaining an identifier (ID) of the first task, or may determine the first task based on a data structure corresponding to the first task. The scheduling table corresponding to the first task may include at least one test pattern (for example, including a first test pattern and a second test pattern referred to in the embodiments of the present application). The at least one test pattern corresponds to a machine instruction code of the first task, and the at least one test pattern is used to detect a fault in the target logic circuit. The at least one test pattern corresponds to the machine instruction code of the first task, meaning that fault detection of a target logic circuit on which execution of the machine instruction code of the first task relies may be performed based on the at least one test pattern.

[0009]

[0009] The method further includes: detecting whether the first test pattern is being executed in the target FDTI; and when it is detected that the first test pattern is not being executed in the target FDTI, executing the first test pattern in the target FDTI based on the first scheduling table to detect a fault in the target logic circuit.

[0010]

[0010] Test pattern sets corresponding to different tasks in the same FDTI may overlap (i.e., the union of the two sets is not empty). In order to avoid repeated execution of test patterns in the FDTI period, the executed test patterns in the FDTI are analyzed and an appropriate scheduling set is generated. Before a test pattern included in the first scheduling table is executed, it needs to be detected whether the test pattern included in the first scheduling table has been executed in the current FDTI period. If the test pattern has been executed, the execution of the test pattern may be skipped, or if the test pattern has not been executed, the test pattern may be executed.

[0011]

[0011] In this case, the first test pattern is executed only when it is necessary that the first test pattern is executed for the first time in the target FDTI. However, if the first test pattern is executed in the target FDTI, the first test pattern is not executed again in the target FDTI, so that the same test pattern is executed only once in the FDTI, and not repeatedly. This reduces the burden of the test patterns of the STL on the processor, reduces the time spent by the processor in detecting faults, and improves the operating efficiency of the processor.

[0012] In some possible implementations, after executing the first test pattern on the target FDTI, the method further includes: obtaining a second scheduling table for a second task, the second scheduling table including a first test pattern, the target logic circuit being a logic circuit used to execute the second task, the second task being executed in a fault detection time interval FDTI of the target; and skipping execution of the first test pattern in the target FDTI based on the first test pattern being executed in the target FDTI.

[0013]

[0013] When a first test pattern requires to be executed in the target FDTI first, the first test pattern may be executed and further requires a second task (the second task different from the first task) to be executed in the FDTI. In this case, a second scheduling table for the second task may be obtained, the second scheduling table also including the first test pattern. During the task scheduling, based on the fact that the first test pattern is executed in the target FDTI, the execution of the first test pattern may be skipped in the target FDTI. In this way, the first test pattern is executed only once in the FDTI and is not executed repeatedly.

[0014] In some possible implementations, the step of detecting whether the first test pattern is running in the target FDTI includes: The method includes obtaining a first identifier corresponding to the first test pattern, the first identifier being used to indicate whether the first test pattern is being executed in the target FDTI.

[0015]

[0015] The first identifier may be represented by a bit mask (e.g., the bit mask may be STLMask). For example, if the bit STLMask corresponding to the first test pattern in the mask is 1, it indicates that the first test pattern has already been executed in the current FDTI period; and if the bit STLMask corresponding to the first test pattern in the mask is 0, it indicates that the first test pattern has not been executed in the current FDTI period. When an initialization for the FDTI is performed, the first identifier STLMask is set to 0 and a timer is enabled. The period of the timer is FDTI. Each time the timer is triggered, the first identifier is reset to 0 and the timer is reset. For example, before the first task is executed, it may be determined that the first test pattern has not been executed in the target FDTI based on detecting that the first identifier STLMask corresponding to the first test pattern is 0.

[0016] In some possible implementations, the step of detecting that the first test pattern is not executed in the target FDTI includes: detecting that a first identifier corresponding to the first test pattern indicates that the first test pattern has not been performed on the target FDTI; and after executing the first test pattern at the target FDTI, the method further comprising: Modifying the first identifier such that the first identifier specifies that the first test pattern is being performed in the target FDTI.

[0017] In some possible implementations, after detecting that the first test pattern has not been executed in the target FDTI, the method further includes: obtaining a second identifier corresponding to the first test pattern, the second identifier being used to indicate whether the first test pattern needs to be executed; and Prior to running the first test pattern on the target FDTI, the method may further include: Detecting that the second identifier indicates that the first test pattern requires that the first test pattern be performed.

[0018]

[0018] The second identifier may be used to indicate whether the first test pattern needs to be executed. The first test pattern is executed in the target FDTI only if the second identifier indicates that the first test pattern needs to be executed. The second identifier is associated with the first identifier. The second identifier indicates that the first test pattern needs to be executed only if the first identifier indicates that the first test pattern is not executed in the target FDTI. The first identifier indicates that the first test pattern is executed in the target FDTI and the second identifier indicates that the first test pattern does not need to be executed.

[0019] In some possible implementations, after executing the first test pattern on the target FDTI, the method further includes: Modifying the second identifier such that the second identifier specifies that the first test pattern does not need to be executed.

[0020] In some possible implementations, the target task includes a process or a thread.

[0021]

[0021] A second aspect of the present application provides a terminal. The terminal includes a processing unit and an acquisition unit. The acquisition unit is configured to acquire a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect a fault in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being executed in a target fault detection time interval FDTI. The processing unit is configured to detect whether the first test pattern is executed in the target FDTI; and, when it is detected that the first test pattern is not executed in the target FDTI, to execute the first test pattern in the target FDTI to detect a fault in the target logic circuit.

[0022]

[0022] In some possible implementations, the processing unit is further configured to: skip execution of the first test pattern in the target FDTI when it is detected that the first test pattern is being executed in the target FDTI.

[0023]

[0023] In some possible implementations, the acquisition unit is configured to acquire a second scheduling table for a second task after the first test pattern is executed in the target FDTI, the second scheduling table including the first test pattern, and the target logic circuit is a logic circuit configured to execute a second task, and the second task is executed in the target fault detection time interval FDTI.

[0024]

[0024] The processing unit is further configured to skip execution of the first test pattern in the target FDTI when the first test pattern is being executed in the target FDTI.

[0025]

[0025] In some possible implementations, the acquisition unit is further configured to acquire a first identifier corresponding to the first test pattern, and the first identifier is used to indicate whether the first test pattern is being executed in the target FDTI.

[0026]

[0026] In some possible implementations, the processing unit detects that a first identifier corresponding to the first test pattern indicates that the first test pattern has not been performed on the target FDTI; and The method is further configured to modify the first identifier after the first test pattern has been executed at the target FDTI such that the first identifier specifies that the first test pattern has been executed at the target FDTI.

[0027] In some possible implementations, the processing unit further comprises: obtaining a second identifier corresponding to the first test pattern after detecting that the first test pattern has not been executed in the target FDTI, the second identifier being used to indicate whether the first test pattern needs to be executed; and and detecting that the second identifier indicates that the first test pattern is required to be performed before the first test pattern is performed on the target FDTI.

[0028]

[0028] In some possible implementations, the processing unit is further configured to modify the second identifier after the first test pattern is executed on the target FDTI, such that the second identifier specifies that the first test pattern does not need to be executed.

[0029] In some possible implementations, the target task includes a process or a thread.

[0030]

[0030] In the present embodiment, the first test pattern is executed only when it is necessary that the first test pattern is executed for the first time in the target FDTI. However, if the first test pattern is executed in the target FDTI, the first test pattern is not executed again in the target FDTI, so that the same test pattern is executed only once in the FDTI, and not repeatedly. This reduces the burden of the test patterns in the STL on the processor, reduces the time spent by the processor in detecting faults, and improves the operating efficiency of the processor.

[0031] A third aspect of the present application provides a terminal, the terminal including a processor, the processor comprising: obtaining a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit configured to perform a first task, the first task being executed in a target fault detection time interval FDTI; detecting whether a first test pattern is executed in the target FDTI; and When it is detected that the first test pattern has not been executed in the target FDTI, the step of executing the first test pattern in the target FDTI to detect faults in the target logic circuit is configured.

[0032] In a possible implementation, the processor further comprises: The method is configured to skip execution of the first test pattern in the target FDTI if the first test pattern is detected to be executing in the target FDTI.

[0033] In a possible implementation, the processor further comprises: obtaining a second scheduling table for a second task after the first test pattern is executed at the target FDTI, the second scheduling table including the first test pattern, the logic circuit of the target being a logic circuit configured to execute a second task, the second task being executed at a fault detection time interval FDTI of the target; and based on the first test pattern being executed in the target FDTI, skipping execution of the first test pattern in the target FDTI.

[0034] In a possible implementation, the processor specifically: and configured to obtain a first identifier corresponding to the first test pattern, the first identifier being used to indicate whether the first test pattern is being executed in the target FDTI.

[0035]

[0035] In a possible implementation, the processor specifically: detecting that a first identifier corresponding to a first test pattern indicates that the first test pattern has not been performed on the target FDTI; and The first identifier is configured to be modified after the first test pattern has been run on the target FDTI, such that the first identifier designates that the first test pattern has been run on the target FDTI.

[0036] In a possible implementation, the processor further comprises: obtaining a second identifier corresponding to the first test pattern after detecting that the first test pattern has not been executed in the target FDTI, the second identifier being used to indicate whether the first test pattern needs to be executed; and detecting that the second identifier indicates that the first test pattern is required to be performed before the first test pattern is performed at the target FDTI.

[0037] In a possible implementation, the processor further comprises: The second identifier is configured to modify the second identifier such that the second identifier specifies that the first test pattern does not need to be executed after the first test pattern has been executed at the target FDTI.

[0038] In some possible implementations, the target task includes a process or a thread.

[0039]

[0039] A fourth aspect of the present application provides a computer-readable storage medium storing a computer program which, when executed on a computer, enables the computer to perform a method according to any implementation of the first aspect.

[0040]

[0040] A fifth aspect of the present application provides a computer program product which, when run on a computer, enables the computer to perform a method according to any implementation of the first aspect.

[0041]

[0041] A sixth aspect of the present application provides a chip including one or more processors. All or a part of the processors are configured to read and execute a computer program stored in a memory to perform a method according to any of the possible implementations of the previous aspects. Optionally, the chip includes a memory, and the memory and the processor are connected to the memory by using a circuit or a wire. Furthermore, optionally, the chip further includes a communication interface, and the processor is connected to the communication interface. The communication interface is configured to receive data, information, or both that need to be processed. The processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result via the communication interface. The communication interface may be an input / output interface. The method provided in the embodiments of the present application may be implemented by one chip, or may be implemented in cooperation by multiple chips.

[0042]

[0042] An embodiment of the present application provides a fault detection method, the method including: obtaining a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being executed in a target fault detection time interval FDTI; detecting whether the first test pattern is executed in the target FDTI; and, if it is detected that the first test pattern is not executed in the target FDTI, executing the first test pattern in the target FDTI based on the first scheduling table to detect faults in the target logic circuit. The first test pattern is executed only if it is required that the first test pattern is executed in the target FDTI for the first time. However, if the first test pattern is executed in the target FDTI, the first test pattern is not executed again in the target FDTI, so that the same test pattern is executed only once in the FDTI, and is not executed repeatedly. This reduces the burden of STL test patterns on the processor, shortens the time spent by the processor in finding faults, and improves the processor's operating efficiency. [Brief description of the drawings]

[0043] [Figure 1a] FIG. 1a is a schematic diagram of an FDTI and an FHTI according to an embodiment of the present application. [Figure 1b]

[0044] FIG. 1b is a schematic diagram of a structure of a terminal according to an embodiment of the present application. [Figure 1c]

[0045] FIG. 1c is a schematic diagram of an application architecture according to an embodiment of the present application. [Diagram 2]

[0046] FIG. 2 is a schematic flowchart of a fault detection method according to an embodiment of the present application. [Diagram 3]

[0047] FIG. 3 is a schematic flowchart of a fault detection method according to an embodiment of the present application. [Figure 4]

[0048] FIG. 4 is a schematic flowchart of a fault detection method according to an embodiment of the present application. [Diagram 5]

[0049] FIG. 5 is a schematic flowchart of a fault detection method according to an embodiment of the present application. [Figure 6]

[0050] FIG. 6 is a schematic diagram of a fault detection method according to an embodiment of the present application. [Figure 7]

[0051] FIG. 7 is a schematic flowchart of a fault detection method according to an embodiment of the present application. [Figure 8]

[0052] FIG. 8 is a schematic diagram of a fault detection method according to an embodiment of the present application. [Figure 9]

[0053] FIG. 9 is a schematic diagram of state transitions according to an embodiment of the present application. [Figure 10]

[0054] FIG. 10 is a schematic diagram of a structure of a terminal according to an embodiment of the present application. [Figure 11]

[0054] FIG. 11 is a schematic diagram of the structure of a terminal according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044]

[0055] The following describes the embodiments of the present application with reference to the accompanying drawings. It is clear that the described embodiments are only a part, not all, of the embodiments of the present application. Those skilled in the art can know that with the emergence of new scenarios and technological developments, the technical solutions provided in the embodiments of the present application can also be applied to similar technical problems.

[0045]

[0056] In the specification, claims, and accompanying drawings of this application, terms such as "first," "second," and the like are intended to distinguish between similar objects, but do not necessarily indicate a particular order or sequence. It should be understood that such designated data are interchangeable under appropriate circumstances, such that the embodiments described herein may be performed in orders other than those illustrated or described herein. Furthermore, the terms "include," "contain," and any other derivatives are intended to cover a non-exclusive inclusion, e.g., a process, method, system, product, or device that includes a list of steps or modules is not necessarily limited to those steps or modules, and may include other steps or modules that are not expressly listed or that are essential to such process, method, system, product, or device. The naming or numbering of steps in this application does not imply that the steps in a method procedure must be performed in the temporal / logical order indicated by the naming or numbering. The order of execution of steps in the named or numbered procedures may be varied based on the technical problem to be achieved, so long as the same or similar technical effect can be achieved.

[0046]

[0057] In the computer field, for example, permanent failures caused by shorts or opens in integrated circuits, or random hardware failures such as bit flips caused by exposure to natural radiation or particle strikes can occur in data processing devices.

[0047]

[0058] With the wide application of data processing devices in many fields, the "functional safety" has become more and more important in order to avoid losses caused by hardware failures in data processing devices. The concept of “functional safety” is proposed. Functional safety means that there is no unacceptable risk caused by electronic system failure. The ultimate goal of functional safety is to prevent human injury and significant losses caused by electronic system failure.

[0048]

[0059] For example, in fields with high safety requirements, such as aerospace, transportation, and medical, corresponding safety mechanisms are provided to meet the functional safety requirements. These safety mechanisms are required to ensure that the system is in a safe state after an injury is detected to prevent harm. For example, in the automotive field, a typical safety risk is usually caused by a failure in the electronic control unit of the anti-lock system or the power steering system. If the electronic control unit of the anti-lock system or the power steering system fails, a fatal crash may occur in the vehicle. To ensure that the system is safe and prevent the safety risk, the occurring failure needs to be detected and addressed in a timely manner.

[0049]

[0060] Generally speaking, when a fault occurs in a system, the safety mechanism needs to detect the fault and handle it in a timely manner to ensure that the system can reach a safe state before danger occurs. Usually, the interval between the time a fault occurs and the time the fault is detected is called the fault detection time interval. Detection Time Interval, The interval between the time a fault is detected and the time the system enters a safe state is called the Fault Handling Time Interval (FDTI). Handle Time Interval, In this case, the FDTI is called the safe state (FDTI:FHTI). For example, FIG. 1a is a schematic diagram of the FDTI and FHTI according to an embodiment of the present application. In order to avoid danger, the system needs to reach a safe state within a certain period of time after a fault occurs in the system. That is, the sum of the FDTI and the FHTI needs to be less than or equal to a time threshold. Therefore, in order to ensure that the FHTI is long enough to handle the fault, it is important to shorten the FDTI as much as possible to ensure that the fault can be handled smoothly.

[0050]

[0061] Currently, the fault detection method in the related art is dual-core lockstep. Lockstep, The implementation of DCLS is described as follows: two processors execute the same program, and the output results of the two processors are input to a comparison logic to compare whether the output results of the two processors are the same. If the output results of the two processors are the same, it can be determined that no fault occurs; or if the output results of the two processors are different, it can be determined that a fault occurs in the processor. Although this fault detection method can effectively detect faults, it needs to use two processors to execute the same program, which has the disadvantages of high cost and low flexibility.

[0051]

[0062] Therefore, in the prior art, software-based built-in self-test built-in self-test, Another software-based fault detection method, called SBIST (Software Based Test and Sequential Isolation System), is provided, in which a processor periodically executes test patterns in an STL to detect faults in logic circuits. Compared with DCLS, the fault detection method has lower cost and higher flexibility. However, since a system usually has a large number of logic circuits, an STL usually contains a large number of test patterns to perform fault detection for all logic circuits. Therefore, the processor periodically executing the test patterns in an STL creates a fairly heavy burden on the processor, i.e., the processor needs to spend more time in detecting faults, thereby affecting the operation efficiency of the processor.

[0052]

[0063] In view of this, in the process of performing fault detection, the terminal can determine a scheduling table corresponding to the currently running task and execute the test patterns included in the scheduling table. Since the scheduling table only includes test patterns corresponding to the machine instruction code of the task, the terminal can detect the fault based on the scheduling table and, as a result, avoid executing all the test patterns in the software test library. This reduces the load on the processor and effectively improves the operating efficiency of the processor.

[0053]

[0064] As shown in Figure 1c, SBIST scheduling is performed at a low level. level,LL) scheduling and high level It can be divided into two parts: full level (HL) scheduling. LL scheduling is mainly used for saving and restoring the context of test pattern switching in STL and calling specific test patterns. HL scheduling uses SBIST as task scheduling. Full STL takes a long time and has a large impact on the real-time performance of the system. HL scheduling can enter kernel mode to increase scheduling flexibility. It is more friendly to real-time systems and is also recommended.

[0054]

[0065] However, in the existing implementation, the HL scheduler obtains the execution time and duration of the STL at a coarse granularity, is not very aware of the information about the test patterns in the STL, and is unable to implement fine-grained control. In a certain FDTI, there may be multiple tasks that need to be executed, and in the FDTI, a test pattern corresponding to each of the multiple tasks that need to be executed needs to be executed. However, test patterns corresponding to different tasks may be repeated, and multiple repeated test patterns may be executed if the test pattern corresponding to each task to be executed is fully executed in the FDTI. In a certain FDTI, the same test pattern needs to be executed only once to ensure the safety of the system. Therefore, the aforementioned SBIST scheduling scheme causes a long SBIST task blocking time, which further generates a heavy burden on the processor. That is, the processor needs to spend more time to detect faults, thereby affecting the operating efficiency of the processor.

[0055]

[0066] The terminal in the embodiment of the present application may be a data processing device in the field with safety requirements. Currently, for example, terminals include: vehicle-mounted terminals in transportation, control terminals in aerospace, industrial control Wireless terminals in self control Wireless terminals in remote driving, remote medical surgery medical Wireless terminals in surgery, smart grid Wireless terminals in the grid, transportation safety Wireless terminals in smart safety, smart cities Wireless terminals in the city, smart homes The wireless terminals in the home may be involved.

[0056]

[0067] FIG. 1b is a schematic diagram of the structure of a terminal 101 according to an embodiment of the present application.

[0057]

[0068] As shown in FIG. 1b, terminal 101 includes processor 103, which is coupled to system bus 105. Processor 103 may be one or more processors. Each processor may include one or more processor cores. A video adapter The system further includes a video adapter 107 capable of driving a display 109, which is coupled to a system bus 105. The system bus 105 is coupled to an input / output (I / O) bus via a bus bridge 111. An I / O interface 115 is coupled to the I / O bus. The I / O interface 115 can interface with a number of I / O devices, such as input devices 117 (such as a touch screen), a multimedia disk (media tray) 121 (compact disk read only memory (CDROM)), and a USB 2.0 port 122 (USB 2.0 port). disc Read-only The I / O interface 115 communicates with a variety of external devices, including a computer, a mobile phone, a mobile device (such as a mobile phone, a mobile phone), a mobile phone (such as ...

[0058]

[0069] The processor 103 performs reduced instruction set operations. Instructions set Computing, RISC processor, complex instruction set computing (complex Instructions set computing, The processor may be any conventional processor, including a CISC (Computer Integrated Circuit and System) processor, or a combination thereof. Optionally, the processor may be a special purpose device such as an ASIC.

[0059]

[0070] The terminal 101 may communicate with the software deployment server 149 via a network interface 129. For example, the network interface 129 is a hardware network interface, such as a network adapter. The network 127 may be an external network, such as the Internet, or may be a private network, such as an Ethernet or a virtual private network. private network, Optionally, network 127 may alternatively be a wireless network, such as a Wi-Fi network or a cellular network.

[0060]

[0071] A hard disk drive interface 131 is coupled to the system bus 105. The hard disk drive interface is connected to a hard disk drive 133. A system memory 135 is coupled to the system bus 105. Data running in the system memory 135 may include an operating system (OS) 137, applications 143, and scheduling tables for the terminal 101.

[0061]

[0072] The operating system includes a shell 139 and a kernel 141. The shell 139 is the interface between the user and the kernel of the operating system. The shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for input from the user, interpreting the input from the user to the operating system, and handling various output results of the operating system.

[0062]

[0073] Kernel 141 comprises the components of an operating system configured to manage memory, files, peripherals, and system resources. Kernel 141 interacts directly with the hardware, and an operating system kernel typically runs processes, provides inter-process communication, and provides functions such as CPU time slice management, interrupts, memory management, and I / O management.

[0063]

[0074] For example, if the terminal 101 is an in-vehicle terminal, the application 143 includes a program related to vehicle driving control, such as a program for managing an interaction between the autonomous vehicle and an obstacle on a road, a program for controlling a path or speed of the autonomous vehicle, and a program for controlling an interaction between the autonomous vehicle and another autonomous vehicle on a road. In an embodiment, when the application 143 needs to be executed, the terminal 101 may download the application 143 from the software deployment server 149. In an embodiment, when the terminal 101 downloads the application 143 from the software deployment server 149, the terminal 101 may also download a scheduling table corresponding to the application 143 from the software deployment server 149.

[0064]

[0075] The sensor 153 is associated with the terminal 101. The sensor 153 is configured to detect the environment around the terminal 101. For example, the sensor 153 may detect animals, cars, obstacles, crosswalks, etc. The sensor 153 may also detect the environment around objects such as the above-mentioned animals, cars, obstacles, and crosswalks, the environment around an animal, for example, other animals appearing around an animal, weather, brightness of the surrounding environment, etc. Optionally, when the terminal 101 is located in an autonomous vehicle, the sensor may be a radar system, etc.

[0065]

[0076] The above describes the application scenario of the fault detection method provided in the embodiments of the present application. The following describes in detail the execution process of the fault detection method.

[0066]

[0077] 2 is a schematic flowchart of a fault detection method 200 according to an embodiment of the present application. As shown in FIG. 2, the fault detection method 200 includes the following steps:

[0067]

[0078] Step 201: Obtain a first scheduling table for a first task, where the first scheduling table includes a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit configured to execute a first task, and the first task being executed in a target fault detection time interval FDTI.

[0068]

[0079] In this embodiment, in order to ensure that a fault that occurs during the normal execution process of the terminal can be detected in time, the terminal may periodically execute the fault detection method 200, for example, every 30 milliseconds or 50 milliseconds.

[0069]

[0080] In a possible embodiment, the first task may be a task that needs to be executed in a target FDTI in the terminal, for example, a process or thread that needs to be executed in a target FDTI in the terminal. The manner of determining the first task by the terminal may be to obtain the first task from a task queue. Tasks in the task queue are tasks that should be executed but are not being executed (or are referred to as tasks that are ready to be executed). The terminal may determine the first task by obtaining an identifier (ID) of the first task, or may determine the first task based on a data structure corresponding to the first task, for example, a particular thread that the first task refers to based on a thread ID. For example, if the first task is a process, the first task may be a process such as a vehicle video inspection process, a vehicle speed calculation process, a radar detection process, a vehicle anti-lock process, a tire pressure detection process, etc.

[0070]

[0081] In a possible embodiment, in a non-deterministic scheduling scenario, the scheduler does not predict which tasks need to be executed in the next FDTI, but only detects in real time which tasks need to be executed in the next FDTI when the FDTI is entered. Thus, a priority preemption scheme is used. Preemption In this scenario, the scheduler may detect in real time which task needs to be executed in the current FDTI in order to detect the first task, which is the STL subset (including at least one test pattern) corresponding to the task.

[0071]

[0082] In a possible embodiment, in a deterministic scheduling scenario, the scheduler is able to predict which tasks need to be executed in the next FDTI. To ensure deterministic scheduling, the worst case execution time is calculated. Case execution time, The WCET (Coefficient of Average Expected Threshold) is statically determined for most tasks and must be used to determine their priority. Therefore, in this scenario, the default high priority is not suitable for SBIST tasks and the scheduling algorithm needs to be adapted to SBIST tasks in order to implement a deterministic scheduling scheme. In this scenario, the scheduler is able to detect tasks that need to be executed in the FDTI before the current FDTI in order to detect the first task.

[0072]

[0083] In this embodiment, any task that can be executed in the terminal may have a corresponding scheduling table. These scheduling tables may, for example, be pre-configured in the terminal, or may be generated by the terminal based on a task-based machine instruction code. Thus, the terminal may determine a first scheduling table corresponding to a first task in a plurality of scheduling tables. For example, if the first task is a process, the terminal may determine a first scheduling table corresponding to the first task based on a process ID.

[0073]

[0084] The scheduling table corresponding to the first task may include at least one test pattern (e.g., including the first test pattern and the second test pattern referred to in the embodiments of the present application), where the at least one test pattern corresponds to the machine instruction code of the first task, and the at least one test pattern is used to detect faults in the target logic circuit. The at least one test pattern corresponding to the machine instruction code of the first task means that fault detection of the target logic circuit on which the execution of the machine instruction code of the first task depends can be performed based on the at least one test pattern.

[0074]

[0085] Simply, when executing the machine instruction code, the terminal needs to rely on logic circuitry in the terminal, i.e., execute the machine instruction code based on the logic circuitry. Thus, once at least one test pattern corresponding to the machine instruction code of the first task is determined, fault detection may be performed on the logic circuitry used when the terminal executes the machine instruction code of the first task based on the at least one test pattern.

[0075]

[0086] It can be understood that in the process of the terminal performing the first task, if a fault occurs in the logic circuit that needs to be used in the process of performing the first task, when the terminal performs the first task, a safety risk may occur due to the fault of the logic circuit. Therefore, the test pattern is executed based on the scheduling table corresponding to the first task, so that it is possible to perform fault detection of the logic circuit that needs to be used, and the occurrence of the safety risk is avoided. As for the other logic circuit, since the current terminal does not perform the corresponding task, that is, the other logic circuit does not need to be used, even if a fault occurs in this part of the logic circuit, no safety risk will occur.

[0076]

[0087] In a possible embodiment, at least one test pattern in the first scheduling table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes a mapping relationship between an instruction type and the test pattern, and the at least one instruction type is determined based on a second mapping relationship and a machine instruction code set of the target task, the second mapping relationship includes a mapping relationship between a machine instruction code and an instruction type, and the machine instruction code set includes a plurality of machine instruction codes. For example, the first test pattern may be determined based on the first mapping relationship and at least one instruction type.

[0077]

[0088] Referring to Figure 3, in the pre-processing process, instruction scanning may be performed for tasks in the system execution process, and a corresponding scheduling table is generated for each task (each scheduling table includes at least one test pattern). In the STL scheduling analysis process, the analyzer of the HL scheduler analyzes the SBIST test sequence in the current period based on the task queue information, the FDTI time, and the scheduling table of each task generated in the pre-processing stage. In the STL scheduling generation process, the analysis result passes through the generator to generate an STL test pattern set to be scheduled, and in the LL scheduling process, the STL test set transferred by the HL is scheduled and executed in the highest privilege hierarchical layer via LL scheduling.

[0078]

[0089] Step 202: Detect whether a first test pattern is executed in a target FDTI.

[0079]

[0090] In a possible embodiment, after the first scheduling table for the first task is obtained, it may be detected whether a first test pattern is executed in the target FDTI.

[0080]

[0091] In this embodiment of the present application, test pattern sets corresponding to different tasks in the same FDTI may overlap (i.e., the union of the two sets is not empty). To avoid repeated execution of test patterns within the FDTI period, the test patterns executed in the FDTI are analyzed and an appropriate scheduling set is generated.

[0081]

[0092] In a possible embodiment, before a test pattern included in the first scheduling table is executed, it is necessary to detect whether the test pattern included in the first scheduling table is executed within the current FDTI period, and if the test pattern is executed, the execution of the test pattern can be simply skipped, or if the test pattern is not executed, the test pattern can be executed.

[0082]

[0093] The following describes how to detect if the first test pattern is being executed in the target FDTI.

[0083]

[0094] In a possible embodiment, the first identifier may be used to indicate whether the first test pattern is running in the target FDTI. When an initialization of the FDTI is performed, the first identifier may indicate that the first test pattern is not running in the target FDTI, and after the first test pattern is run for the first time in the FDTI, the first identifier is modified, so that the first identifier may indicate that the first test pattern is running in the target FDTI.

[0084]

[0095] For example, it may be determined that the first test pattern has not been performed in the target FDTI based on detecting that before the first task is performed, a first identifier corresponding to the first test pattern indicates that the first test pattern has not been performed in the target FDTI.

[0085]

[0096] For example, the first identifier may be represented by a bit mask (e.g., the bit mask may be STLMask). For example, if the bit STLMask corresponding to the first test pattern in the mask is 1, it indicates that the first test pattern has already been executed in the current FDTI period; and if the bit STLMask corresponding to the first test pattern in the mask is 0, it indicates that the first test pattern has not been executed in the current FDTI period. When an initialization for the FDTI is performed, the first identifier STLMask is set to 0 and a timer is enabled. The period of the timer is FDTI. Each time the timer is triggered, the first identifier is reset to 0 and the timer is reset. For example, before the first task is executed, it may be determined that the first test pattern has not been executed in the target FDTI based on detecting that the first identifier STLMask corresponding to the first test pattern is 0.

[0086]

[0097] Additionally, the second identifier may be further used to indicate whether the first test pattern requires to be executed. The first test pattern is executed in the target FDTI only if the second identifier indicates that the first test pattern requires to be executed. The second identifier is associated with the first identifier. The second identifier indicates that the first test pattern requires to be executed only if the first identifier indicates that the first test pattern is not executed in the target FDTI. The first identifier indicates that the first test pattern is executed in the target FDTI and the second identifier indicates that the first test pattern does not require to be executed.

[0087]

[0098] For example, it may be determined that the first test pattern requires to be executed based on detecting that the second identifier indicates that the first test pattern requires to be executed before the first task is executed.

[0088]

[0099] For example, referring to FIG. 4, the second identifier may be represented by a bit mask (e.g., the bit mask may be STLNeedExcuteMask). If the bit STLNeedExcuteMask corresponding to the first test pattern in the mask is 1, it indicates that the first test pattern still needs to be executed in the current FDTI period; if the bit STLNeedExcuteMask corresponding to the first test pattern in the mask is 0, it indicates that the first test pattern does not need to be executed in the current FDTI period.

[0089]

[0100] When initialization for FDTI is performed, the second identifier STLNeedExcuteMask is set to 0 and a timer is enabled. The period of the timer is FDTI. Each time the timer is triggered, the second identifier STLNeedExcuteMask is reset to 0 and the timer is reset. For example, it may be determined that the first test pattern needs to be executed based on detecting that the second identifier STLNeedExcuteMask corresponding to the first test pattern is 1 before the first task is executed.

[0090]

[0101] Step 203: When it is detected that the first test pattern has not been executed in the target FDTI, the first test pattern is executed in the target FDTI based on the first scheduling table to detect a fault in the target logic circuit.

[0091]

[0102] In this embodiment of the present application, when it is detected that the first test pattern is not executed in the target FDTI, the first test pattern may be executed in the target FDTI based on the first scheduling table; alternatively, when it is detected that the first test pattern is executed in the target FDTI, the execution of the first test pattern is skipped in the target FDTI. In other words, the first test pattern is executed only if it is required to be executed in the target FDTI for the first time, and when it is executed in the target FDTI, the first test pattern is not executed again in the target FDTI.

[0092]

[0103] In a possible embodiment, the first test pattern may be executed when the first test pattern requires execution in the target FDTI for the first time, and further requires a second task (the second task different from the first task) to be executed in the FDTI. In this case, a second scheduling table for the second task may be obtained, the second scheduling table also including the first test pattern. During task scheduling, based on the fact that the first test pattern is executed in the target FDTI, execution of the first test pattern may be skipped in the target FDTI. In this way, the first test pattern is executed only once in the FDTI and is not executed repeatedly.

[0093]

[0104] In possible embodiments, after the first test pattern is executed in the target FDTI, the first identifier may be modified to cause the first identifier to specify that the first test pattern is being executed in the target FDTI. Similarly, after the first test pattern is executed in the target FDTI, the second identifier may be modified to cause the second identifier to specify that the first test pattern does not need to be executed. For example, based on the fact that the second identifier indicates that the first test pattern does not need to be executed, execution of the first test pattern may be skipped in the target FDTI, such that the first test pattern is executed once in the FDTI and not repeatedly executed.

[0094]

[0105] For example, referring to FIG. 5, in a non-deterministic scheduling scenario, the scheduler does not predict which tasks need to be executed in the next FDTI, but only detects in real time which tasks need to be executed in the next FDTI after entering the FDTI. Therefore, a priority preemption scheme is set for SBIST tasks. Before each common task (non-SBIST task) is executed in the FDTI, the STL subset (including at least one test pattern) corresponding to the task is executed in an uninterrupted manner. In this scenario, the scheduler may detect in real time which tasks need to be executed in the current FDTI to detect the tasks. The scheduler schedules a ready task from the task queue, gets the task ID of the task, finds the corresponding STL subset, i.e., test pattern set, based on the task ID of the task, and determines whether the test pattern in each STL subset will be executed within the current FDTI period based on the STLMask. If a test pattern has been executed, the next round of decisions is executed; otherwise, if a test pattern has not been executed, the corresponding bit in STLNeedExcuteMask is set to 1, the test pattern is executed, and the bits in STLMask and STLNeedExcuteMask corresponding to the executed test pattern are set to 1 and need not be executed until all test patterns have been traversed. After the SBIST task of the currently scheduled task has been executed, the scheduled task may continue to be executed. Other tasks in the task queue are executed sequentially.

[0095]

[0106] Referring to FIG. 6, the horizontal coordinate represents time, the vertical coordinate represents the priority of the task, and each colored block represents the time slice in which the task is currently running and occupies the CPU. The FDTI period starts from the origin and ends at the dashed line. In this period, when tasks 1, 2, and 3 are scheduled by the scheduler, the SBSIT tasks corresponding to the tasks are executed first. The SBIST tasks execute the STL test pattern sets associated with the tasks. The SBIST tasks have a higher priority and cannot interrupt the test sequence. In the FDTI scheduling time, the test pattern subsets of each task must be unique. For example, before task 3 is executed, the test pattern subset corresponding to task 3 (the test patterns in the test pattern subset other than the test patterns corresponding to task 2) may be executed.

[0096]

[0107] For example, referring to FIG. 7, in a deterministic scheduling scenario, the scheduler is able to predict which tasks need to be executed in the next FDTI. To ensure deterministic scheduling, the worst case execution time is calculated. Case execution time, The WCET (Coefficient of Average Expected Threshold) needs to be statically determined for most tasks to determine their priority. Therefore, in this scenario, the default high priority is not suitable for SBIST tasks, and the deterministic scheduling algorithm needs to be adapted to SBIST tasks to implement the deterministic scheduling configuration. In this scenario, the scheduler can detect tasks that need to be executed in the FDTI before the current FDTI. The scheduler may schedule a ready task from the task queue. If the task is a common task, the common task is executed. Specifically, the task ID of the task can be obtained, and the corresponding STL set, i.e., test pattern set, is found based on the task ID of the task to determine whether the current FDTI has timed out. If the current FDTI has not timed out, for the test patterns in each STL subset, it is determined whether the test pattern has been executed within the current FDTI period based on the STLMask. If the test pattern has been executed, the next round of determination is executed until all test patterns are traversed. If no test pattern is executed, the corresponding bit in STLNeedExcuteMask is set to 1. When FDTI times out, all bits in STLmask are reset to 0. If the scheduled task is an SBIST task, the SBIST test sequence is executed based on STLNeedExcuteMask. After execution, the corresponding bit in STLNeedExcuteMask is set to 0 and the corresponding bit in STLmask is set to 1.

[0097]

[0108] In this embodiment of the present application, with reference to FIG. 9, the test patterns in the SBIST task can be classified into three states: (not executed, does not need to be executed), (not executed, needs to be executed), and (executed, does not need to be executed), and the initial state is (not executed, does not need to be executed). After the analyzer is used, the test pattern status remains unchanged or is (not executed, needs to be executed). After the test pattern is executed, the status of (not executed, needs to be executed) is changed to (executed, does not need to be executed).

[0098]

[0109] As shown in the table below, compared to SBIST scheduling in the prior art, the method in this embodiment of the present application reduces the SBIST test sequence execution time by approximately 75% in the present invention compared to that in the prior art.

[0099] [Table 1]

[0110] An embodiment of the present application provides a fault detection method, the method including: obtaining a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being executed in a target fault detection time interval FDTI; detecting whether the first test pattern is being executed in the target FDTI; and if it is detected that the first test pattern is not being executed in the target FDTI, executing the first test pattern in the target FDTI based on the first scheduling table to detect faults in the target logic circuit.

[0100] The first test pattern is executed only if it is required that the first test pattern is executed for the first time in the target FDTI. However, if the first test pattern is executed in the target FDTI, the first test pattern is not executed again in the target FDTI, so that the same test pattern is executed only once in the FDTI and not repeatedly. This reduces the burden of the STL test patterns on the processor, reduces the time spent by the processor in finding faults, and improves the efficiency of the processor's operation.

[0101]

[0111] Based on the embodiment corresponding to Fig. 1a to Fig. 9, in order to better implement the aforementioned solution in the embodiment of the present application, the following further provides a related device configured to implement the aforementioned solution. Specifically, Fig. 10 is a schematic diagram of the structure of a terminal 1000 according to the embodiment of the present application. The terminal 1000 includes a processing unit 1001 and an acquisition unit 1002. The acquisition unit 1002 is configured to acquire a first scheduling table of a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect a fault in a target logic circuit, the target logic circuit being a logic circuit used to execute a first task, and the first task being executed in a target fault detection time interval FDTI. The processing unit 1001 is configured to detect whether the first test pattern is executed in the target FDTI; and, when it is detected that the first test pattern is not executed in the target FDTI, to execute the first test pattern in the target FDTI to detect a fault in the target logic circuit.

[0102]

[0112] In some possible implementations, the processing unit 1001 is further configured to: skip execution of the first test pattern in the target FDTI if it is detected that the first test pattern is being executed in the target FDTI.

[0103]

[0113] In some possible implementations, the acquisition unit 1002 is configured to acquire a second scheduling table for a second task after the first test pattern is executed in the target FDTI, the second scheduling table including the first test pattern, and the target logic circuit is a logic circuit configured to execute a second task, the second task being executed in the fault detection time interval FDTI of the target.

[0104]

[0114] The processing unit 1001 is further configured to skip execution of the first test pattern in the target FDTI if the first test pattern is being executed in the target FDTI.

[0105]

[0115] In some possible implementations, the acquiring unit 1002 is further configured to acquire a first identifier corresponding to the first test pattern, the first identifier being used to indicate whether the first test pattern is being executed in the target FDTI.

[0106]

[0116] In some possible implementations, the processing unit 1001 detects that a first identifier corresponding to a first test pattern indicates that the first test pattern has not been performed on the target FDTI; and The method is further configured to modify the first identifier after the first test pattern has been executed at the target FDTI such that the first identifier specifies that the first test pattern has been executed at the target FDTI.

[0107]

[0117] In some possible implementations, the processing unit 1001 further comprises: obtaining a second identifier corresponding to the first test pattern after detecting that the first test pattern has not been executed in the target FDTI, the second identifier being used to indicate whether the first test pattern needs to be executed; and and detecting that the second identifier indicates that the first test pattern is required to be performed before the first test pattern is performed on the target FDTI.

[0108]

[0118] In some possible implementations, the processing unit 1001 is further configured to modify the second identifier after the first test pattern is executed on the target FDTI, such that the second identifier specifies that the first test pattern does not need to be executed.

[0109]

[0119] In some possible implementations, the target task includes a process or a thread.

[0110]

[0120] In the present embodiment, the first test pattern is executed only if it is required that the first test pattern is executed for the first time in the target FDTI. However, if the first test pattern has been executed in the target FDTI, the first test pattern is not executed again in the target FDTI, so that the same test pattern is executed only once in the FDTI and not repeatedly. This reduces the burden of the STL test patterns on the processor, reduces the time spent by the processor in detecting faults, and improves the operating efficiency of the processor.

[0111]

[0121] The following describes a terminal device provided in an embodiment of the present application. The terminal device may be an information recommendation device in FIG. 11. FIG. 11 is a schematic diagram of a structure of a terminal device according to an embodiment of the present application. The terminal device 1100 may specifically be a virtual reality VR device, a mobile phone, a tablet computer, a notebook computer, an intelligent wearable device, etc. This is not limited in the present application. Specifically, the terminal device 1100 includes a receiver 1101, a transmitter 1102, a processor 1103, and a memory 1104 (there may be one or more processors 1103 in the terminal device 1100, and in FIG. 11, one processor is used as an example). The processor 1103 may include an application processor 11031 and a communication processor 11032. In some embodiments of the present application, the receiver 1101, the transmitter 1102, the processor 1103, and the memory 1104 may be connected via a bus or in another manner.

[0112]

[0122] The memory 1104 includes read-only memory and random access memory, and is capable of providing instructions and data to the processor 1103. A portion of the memory 1104 is non-volatile random access memory. random access memory, The memory 1104 may further include a non-volatile random access memory (NVRAM). The memory 1104 stores processor and operating instructions, executable modules or data structures, a subset thereof, or an extended set thereof. The operating instructions may include various operating instructions for performing various operations.

[0113]

[0123] The processor 1103 controls the operation of the terminal device. In a particular application, the components of the terminal device are coupled to each other via a bus system. In addition to the data bus, the bus system may further include a power bus, a control bus, a status signal bus, etc. However, for clarity of explanation, various types of buses are depicted in the drawings as a bus system.

[0114]

[0124] The methods disclosed in the above embodiments of the present application may be applied to or realized by the processor 1103. The processor 1103 may be an integrated circuit chip and has signal processing capabilities. In the implementation process, each step of the above methods may be completed by using instructions in the form of integrated logic circuits of hardware or software in the processor 1103. The processor 1103 may be a general-purpose processor, a digital signal processor, a signal processor, The processor 1103 may be an application-specific integrated circuit (DSP), a microprocessor, or a microcontroller. integrated circuit, ASIC), Field Programmable Gate Array (field Programmable gate array, The hardware decoding processor 1103 may further include a FPGA (field programmable gate array) or another programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The processor 1103 may realize or perform the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc. The steps of the methods disclosed with reference to the embodiments of the present application may be performed and completed directly by the hardware decoding processor, or may be performed and completed by using a combination of hardware modules and software modules in the decoding processor. The software modules may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory 1104, and the processor 1103 reads the information in the memory 1104 and completes the steps of the aforementioned method in combination with the hardware of the processor. Specifically, the processor 1103 can read the information in the memory 1104, and in combination with the hardware of the processor 1103, complete the steps related to data processing from step 201 to step 203 in the above embodiment.

[0115]

[0125] The receiver 1101 may be configured to receive input digital or character information and generate signal inputs related to relevant setting and function control of the terminal device. The transmitter 1102 may be configured to output the digital or character information via the first interface. The transmitter 1102 may be further configured to send instructions to the disk group via the first interface to modify data in the disk group.

[0116]

[0126] An embodiment of the present application further provides a computer program product, which, when implemented in a computer, enables the computer to perform the steps of the fault detection method described in the embodiment corresponding to FIG.

[0117]

[0127] An embodiment of the present application further provides a computer-readable storage medium, which stores a program for signal processing, and when the program is executed on a computer, the computer is capable of performing the steps of the image processing method in the above-mentioned method embodiments.

[0118]

[0128] The image processing device provided in this embodiment of the present application may be a chip. The chip includes a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, pins, circuits, etc. The processing unit may execute computer-executable instructions stored in the storage unit, such that the chip in the execution device executes the data processing method described in the embodiment, or the chip in the training device executes the data processing method described in the embodiment. Optionally, the storage unit is a storage unit in the chip, for example a register or a buffer. Alternatively, the storage unit is a storage unit in the wireless access device but outside the chip, for example a read-only memory. memory, ROM), another type of static storage device capable of storing static information and instructions, or random access memory (ROM). access memory, The memory may be a RAM.

[0119]

[0129] For the purpose of convenience and brevity of description, it will be clearly understood by those skilled in the art that the detailed operation processes of the above-mentioned systems, devices and units can be referred to the corresponding processes in the above-mentioned method embodiments, and the details will not be described again here.

[0120]

[0130] In some embodiments provided in the present application, it is possible to understand that the disclosed system, device, and method may be implemented in other ways. For example, the described device embodiment is merely an example. For example, the division into units is merely a logical division of functions, and there may be other divisions in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. Furthermore, the illustrated or described mutual couplings or direct couplings or communication connections may be implemented by using some interfaces. Indirect couplings or communication connections between devices or units may be realized in electronic, mechanical, or other forms.

[0121]

[0131] The units described as individual parts may or may not be physically separate, and the parts shown as units may or may not be physical units, and may be located in one place or distributed over multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0122]

[0132] Furthermore, the functional units in the embodiments of the present application may be integrated into one processing unit, and each of the units may exist physically alone, or two or more units may be integrated into one unit. The integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0123]

[0133] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application essentially or the part that contributes to the prior art, or all or part of the technical solution may be realized in the form of a software product. The computer software product is stored in a storage medium and includes some instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

Claims

1. A computer implemented fault detection method comprising: obtaining a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit configured to execute the first task, the first task being executed in a target fault detection time interval FDTI; detecting whether the first test pattern is executed in the target FDTI; and executing the first test pattern in the target FDTI based on the first scheduling table when it is detected that the first test pattern has not been executed in the target FDTI; A fault detection method comprising:

2. The fault detection method of claim 1, further comprising: skipping execution of the first test pattern in the target FDTI when it is detected that the first test pattern is being executed in the target FDTI; A fault detection method comprising:

3. 2. The fault detection method of claim 1, after executing the first test pattern on the target FDTI, the method further comprising: obtaining a second scheduling table for a second task, the second scheduling table including the first test pattern, the target logic being a logic circuit configured to execute the second task, the second task being executed during a fault detection time interval (FDTI) of the target; and skipping execution of the first test pattern in the target FDTI based on the first test pattern being executed in the target FDTI; A fault detection method comprising:

4. 2. The fault detection method of claim 1, wherein the step of detecting whether the first test pattern is executed in the target FDTI comprises: obtaining a first identifier corresponding to the first test pattern, the first identifier being used to indicate whether the first test pattern is being executed in the target FDTI; A fault detection method comprising:

5. 5. The fault detection method of claim 4, wherein the step of detecting that the first test pattern has not been executed in the target FDTI comprises: detecting that the first identifier corresponding to the first test pattern indicates that the first test pattern has not been executed in the target FDTI; after executing the first test pattern on the target FDTI, the method further comprising: modifying the first identifier such that the first identifier specifies that the first test pattern is being executed in the target FDTI; A fault detection method comprising:

6. 2. The fault detection method of claim 1, after detecting that the first test pattern has not been executed in the target FDTI, the method further comprising: obtaining a second identifier corresponding to the first test pattern, the second identifier being used to indicate whether the first test pattern needs to be executed; and Prior to executing the first test pattern on the target FDTI, the method further comprises: detecting that the second identifier indicates that the first test pattern requires to be executed; A fault detection method comprising:

7. 7. The fault detection method of claim 6, after executing the first test pattern on the target FDTI, the method further comprising: modifying the second identifier such that the second identifier specifies that the first test pattern does not need to be executed; A fault detection method comprising:

8. 2. The method of claim 1, wherein the target task comprises a process or a thread.

9. 1. A terminal including a processor, the processor comprising: obtaining a first scheduling table for a first task, the first scheduling table including a first test pattern, the first test pattern being used to detect faults in a target logic circuit, the target logic circuit being a logic circuit configured to execute the first task, the first task being executed in a target fault detection time interval FDTI; detecting whether the first test pattern is executed in the target FDTI; and executing the first test pattern in the target FDTI when it is detected that the first test pattern has not been executed in the target FDTI; A terminal configured to:

10. 10. The terminal of claim 9, wherein the processor further comprises: skipping execution of the first test pattern in the target FDTI when it is detected that the first test pattern is being executed in the target FDTI; A terminal configured to:

11. 10. The terminal of claim 9, wherein the processor further comprises: obtaining a second scheduling table for a second task after the first test pattern is executed on the target FDTI, the second scheduling table including the first test pattern, the target logic circuit being a logic circuit configured to execute the second task, and the second task being executed during a fault detection time interval FDTI of the target; and skipping execution of the first test pattern in the target FDTI based on the first test pattern being executed in the target FDTI; A terminal configured to:

12. In the terminal of claim 9, the processor specifically: obtaining a first identifier corresponding to the first test pattern, the first identifier being used to indicate whether the first test pattern is being executed in the target FDTI; A terminal configured to:

13. In the terminal of claim 12, the processor specifically: detecting that the first identifier corresponding to the first test pattern indicates that the first test pattern has not been executed in the target FDTI; and after the first test pattern has been executed on the target FDTI, modifying the first identifier such that the first identifier specifies that the first test pattern has been executed on the target FDTI; A terminal configured to:

14. 10. The terminal of claim 9, wherein the processor further comprises: obtaining a second identifier corresponding to the first test pattern after detecting that the first test pattern has not been executed in the target FDTI, the second identifier being used to indicate whether the first test pattern needs to be executed; and detecting that the second identifier indicates that the first test pattern needs to be executed before the first test pattern is executed in the target FDTI; A terminal configured to:

15. 15. The terminal of claim 14, wherein the processor further comprises: modifying the second identifier such that the second identifier specifies that the first test pattern does not need to be executed after the first test pattern is executed on the target FDTI; A terminal configured to:

16. 10. The terminal of claim 9, wherein the target task comprises a process or a thread.

17. A computer readable storage medium comprising computer readable instructions which, when executed on the computer, cause the computer to operate to perform the method of any one of claims 1 to 8.

18. A computer program comprising computer readable instructions, which when executed on the computer, cause the computer to operate to perform the method according to any one of claims 1 to 8.

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