Semiconductor Device

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor device comprises: a die pad DP which has an upper surface DPt that is opposed to a semiconductor chip CP; a metal film MF1 which is formed on the upper surface DPt; and a joint material DB which is formed so as to cover the metal film MF1. The upper surface DPt includes: a region DPR1 overlapping the semiconductor chip CP; a region DPR2 not overlapping the semiconductor chip CP; a region DPR3 included in the region DPR1 and covered by the metal film MF1; and a region DPR4 included in the region DPR1, adjacent to the region DPR3 and not covered by the metal film MF1. The metal film MF1 is made of a metal material that is hard to be oxidized in comparison to a metal material constituting the die pad DP. The semiconductor chip CP is mounted on the die pad DP such that the center of the semiconductor chip CP overlaps the region DPR3. The surface roughness of the upper surface DPt in the region DPR4 is rougher than the surface roughness of a contact surface of the metal film MF1 with which the joint material DB is brought into contact. The area of the region DPR3 is between 11% and 55% with respect to the area of the region DPR1.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] One technique for improving the heat dissipation of a semiconductor chip is to form a plating film on the chip mounting surface of a die pad and then mount the semiconductor chip on this plating film via a silver paste material (see, for example, JP 2018-85480 A (Patent Document 1) and JP 2019-40994 A (Patent Document 2)). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-85480 A [Patent Document 2] JP 2019-40994 A Summary of the Invention [Problem to be solved by the invention]

[0004] According to the study by the inventors of the present application, it was found that in the case of a semiconductor device in which a semiconductor chip is mounted on a plating film via a silver paste material, peeling occurs at the interface between the plating film and the silver paste material. As another study example, the inventors of the present application also studied a semiconductor device in which a semiconductor chip is mounted on a roughened chip mounting surface via a silver paste material and without a plating film. In this study example, it was found that peeling occurs at the interface between the silver paste and the chip mounting surface due to air bubbles trapped between the roughened chip mounting surface and the silver paste. Heat generated by the operation of the semiconductor chip is dissipated to the outside of the semiconductor device (semiconductor package) via the die pad, but if peeling occurs at the interface between the die bond material and the die pad, the heat dissipation efficiency decreases.

[0005] It is an object of the present invention to improve the performance of a semiconductor device. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes a chip mounting section having a first surface facing a semiconductor chip, a first metal film formed on the first surface, and a bonding material formed to cover the first metal film. The first surface includes a first region overlapping the semiconductor chip, a second region not overlapping the semiconductor chip, a third region included in the first region and covered by the first metal film, and a fourth region included in the first region, adjacent to the third region, and not covered by the first metal film. The semiconductor chip is mounted on the chip mounting section such that a center of the semiconductor chip overlaps with the third region. The first metal film is made of a metal material that is less susceptible to oxidation than a metal material constituting the chip mounting section. The surface roughness of the first surface in the fourth region is rougher than the surface roughness of a contact surface of the first metal film with which the bonding material comes into contact. The area of ​​the third region is 11% or more and 55% or less of the area of ​​the first region. Effect of the Invention

[0007] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 2 is a perspective plan view showing the internal structure of the semiconductor device seen through the sealing body shown in FIG. [Figure 4] 3 is an enlarged cross-sectional view showing a state in which the semiconductor device shown in FIG. 2 is mounted on a mounting board. [Diagram 5]4 is an enlarged plan view of the die pad in which the wires shown in FIG. 3 are omitted and the outlines of the semiconductor chip and bonding material shown in FIG. 3 are indicated by dotted lines. [Figure 6] FIG. 6 is an enlarged cross-sectional view taken along line BB in FIG. 5. [Figure 7] 6 is an explanatory diagram showing the relationship between the area ratio of the region where the metal film shown in FIG. 5 is formed and the peeling rate of the bonding material. FIG. [Figure 8] 7 is an enlarged cross-sectional view showing a modification of FIG. 6. [Figure 9] 6 is an enlarged plan view showing a modified example of the shape of the metal film shown in FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] (Description format, basic terms and usage in this application) In this application, the description of the embodiment is conveniently divided into multiple sections, etc., as necessary, but unless otherwise specified, these are not mutually independent and separate, and regardless of the description, each part of a single example, one is a partial detail of the other, or a partial or complete modified example, etc. In addition, as a general rule, repeated explanations of similar parts will be omitted. In addition, each component in the embodiment is not essential, unless otherwise specified, when it is theoretically limited to that number, or when it is clearly not from the context.

[0010] Similarly, in the description of the embodiments, when a material, composition, etc. is described as "X made of A," it does not exclude those containing elements other than A, unless otherwise specified or clearly indicated from the context. For example, when it comes to components, it means "X containing A as a main component." For example, when it comes to "silicon components," it goes without saying that it is not limited to pure silicon, but also includes SiGe (silicon germanium) alloys and other multi-component alloys whose main component is silicon, and components containing other additives. In addition, when it comes to gold plating, Cu layer, nickel plating, etc., it includes not only pure ones, but also components whose main components are gold, Cu, nickel, etc., unless otherwise specified.

[0011] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, it may be a number greater than that specific number, or a number less than that specific number, unless it is theoretically limited to that number or unless it is clearly different from the context.

[0012] In addition, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated as a general rule.

[0013] In the accompanying drawings, hatching and the like may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, the background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the explanation, etc. Furthermore, hatching or dot patterns may be added even if the drawing is not a cross section in order to clearly indicate that it is not a void or to clearly indicate the boundaries of the area.

[0014] The technology described in the following embodiments can be widely applied to semiconductor devices in which a semiconductor chip mounted on a chip mounting portion is sealed with a sealing body. In the present embodiments, as an example, a mode applied to a QFP (Quad Flat Package) type semiconductor device in which leads protrude from each of the four sides of a sealing body that is rectangular in plan view will be described.

[0015] <Semiconductor device> First, an outline of the configuration of the semiconductor device PKG1 of this embodiment will be described with reference to Figs. 1 to 4. Fig. 1 is a top view of the semiconductor device of this embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 3 is a perspective plan view showing the internal structure of the semiconductor device in a state where the sealing body shown in Fig. 1 is seen through. Fig. 4 is an enlarged cross-sectional view showing a state where the semiconductor device shown in Fig. 2 is mounted on a mounting board.

[0016] As shown in Figures 1 to 3, the semiconductor device PKG1 has a semiconductor chip CP (see Figures 2 and 3) and a die pad (chip mounting portion) DP (see Figures 2 and 3) on which the semiconductor chip CP is mounted. The die pad DP has an upper surface (chip mounting surface) DPt (see Figure 2) facing the semiconductor chip CP and a lower surface (back surface) DPb (see Figure 2) opposite to the upper surface DPt. The semiconductor chip CP further has a plurality of leads LD arranged at a distance from the die pad DP, a plurality of wires BW (see Figures 2 and 3) connected to the semiconductor chip CP and the plurality of leads LD, and a sealing body (resin body) MR (see Figures 1 and 2) that seals the plurality of wires BW and the semiconductor chip CP.

[0017] The sealing body MR is a resin body mainly composed of a resin material, and contains, for example, filler particles such as silica, black pigment, etc. As shown in Fig. 1, the planar shape of the sealing body MR provided in the semiconductor device PKG1 is a rectangle. The sealing body MR has an upper surface MRt, a lower surface (back surface, mounted surface) MRb (see Fig. 2) opposite to the upper surface MRt, and a plurality of (four) side surfaces MRs located between the upper surface MRt and the lower surface MRb. In the example shown in Fig. 1, the corners where the side surfaces MRs of the sealing body MR intersect are chamfered.

[0018] The semiconductor chip CP shown in FIG. 2 and FIG. 3 has a rectangular shape in a plan view, and a plurality of pads (bonding pads) PD are provided on the front surface CPt along each of the four sides constituting the outer edge of the front surface CPt. The semiconductor chip CP (more specifically, a semiconductor substrate) is made of, for example, silicon (Si). Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (more specifically, a semiconductor element formation region provided on the upper surface of the semiconductor substrate of the semiconductor chip CP). The plurality of pads PD are electrically connected to the semiconductor elements via wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip CP (more specifically, between the front surface CPt and the semiconductor element formation region, not shown). That is, the plurality of pads PD are electrically connected to the circuits formed on the semiconductor chip CP.

[0019] An insulating film is formed on the surface CPt of the semiconductor chip CP to cover the substrate and wiring of the semiconductor chip CP, and the surfaces of the pads PD are exposed from the insulating film at openings formed in the insulating film. The pads PD are made of metal, and in this embodiment, are made of aluminum (Al), for example.

[0020] The semiconductor chip CP is mounted on a die pad DP, which is a chip mounting portion. In the example shown in Fig. 3, the upper surface (chip mounting surface) DPt of the die pad DP is a rectangle whose plane area is larger than the area of ​​the front surface CPt of the semiconductor chip CP. The die pad DP is a support member that supports the semiconductor chip CP, and various modified shapes and sizes can be applied in addition to the example shown in Fig. 3.

[0021] As shown in Fig. 3, a plurality of hanging leads HL are arranged around the die pad DP. The hanging leads HL are members for supporting the die pad DP on a supporting portion (frame portion) of a lead frame in a manufacturing process of the semiconductor device PKG1, and in the example shown in Fig. 3, four hanging leads HL are arranged from a corner of the die pad DP toward a corner of the sealing body MR. More specifically, one end of each of the hanging leads HL is connected to a corner (corner) of the die pad DP. The other end of each of the hanging leads HL extends toward the corner of the sealing body MR, branches into two in the vicinity of the corner, and is exposed from the sealing body MR at a side surface MRs of the sealing body MR.

[0022] In this embodiment, the upper surface DPt of the die pad DP and the upper surface of the inner lead portion ILD of the lead LD are disposed at different heights. In the example shown in Fig. 2, the upper surface DPt of the die pad DP is disposed at a lower position than the position of the upper surface LDt of the inner lead portion ILD. For this reason, the multiple suspension leads HL shown in Fig. 3 are each provided with an offset portion OSP that is bent so that the upper surface DPt of the die pad DP is positioned at a different height from the upper surface LDt of the inner lead portion ILD of the lead LD (see Fig. 2).

[0023] The semiconductor chip CP is mounted at the center of the die pad DP. As shown in FIG. 2, the semiconductor chip CP is mounted on the die pad DP via a bonding material (die bond material) DB with the back surface CPb facing the upper surface DPt of the die pad DP. The bonding material DB is made of a conductive resin containing a resin body RB and a plurality of metal particles CF contained in the resin body RB, as shown in FIG. 6 described later. An example of the conductive resin is an adhesive material called silver paste, in which metal particles CF made of silver or the like are contained in an epoxy-based thermosetting resin (resin body RB). The bonding material DB is arranged so as to cover a metal film MF1 formed on a part of the upper surface DPt of the die pad DP. A detailed structure of the portion that bonds the semiconductor chip CP and the die pad DP will be described later.

[0024] For example, a plurality of leads LD are arranged around the semiconductor chip CP (in other words, around the die pad DP). Each of the plurality of leads LD is an external terminal having a function of electrically connecting the semiconductor device PKG1 to an external device (not shown). In the case of the semiconductor device PKG1, a plurality of leads LD are arranged along each side (each main side) of the sealing body MR having a rectangular planar shape. Each inner lead part ILD (see FIG. 2 and FIG. 3) of the plurality of leads LD is sealed in the sealing body MR, and each outer lead part OLD of the plurality of leads LD is exposed from the sealing body MR. The outer lead parts OLD of the plurality of leads LD protrude toward the outside of the sealing body MR at the side surface MRs of the sealing body MR. A plurality of pads (bonding pads) PD exposed on the front surface CPt of the semiconductor chip CP are electrically connected to the inner lead parts ILD of the plurality of leads LD located inside the sealing body MR via a plurality of wires (conductive members) BW.

[0025] The die pad DP and the leads LD are made of the same metal material, such as copper, an alloy containing copper, or an alloy containing iron (42 alloy).

[0026] Each of the wires BW is a thin metal wire that electrically connects a plurality of pads (bonding pads) PD (see FIGS. 2 and 3) provided on the front surface CPt (see FIG. 2) of the semiconductor chip CP to a plurality of leads. One end of the wire BW is bonded to the pad PD, and the other end is bonded to a metal film MF2 (see FIG. 2) formed on the upper surface LDt (see FIG. 2) of the lead LD. In detail, the metal film MF2 is formed on an inner lead portion ILD (see FIG. 2) of the lead LD that is sealed in a sealing body MR. Each of the wires BW is sealed in the sealing body MR. This makes it possible to prevent deformation of the wires BW.

[0027] The wire BW is made of, for example, gold (Au) or copper (Cu), and a part of the wire BW (for example, one end) is bonded to the pad PD, and the other part (for example, the other end) is bonded to the tip of the inner lead part ILD. A metal film (plated film, plated metal film) MF2 (see FIG. 2) is formed on the surface of the tip of the inner lead part ILD. The metal film MF2 is made of, for example, silver (Ag) or gold. By forming the metal film MF2 made of a material mainly composed of silver or gold on the surface of the bonding part WBR of the inner lead part ILD, the bonding strength with the wire BW can be improved.

[0028] 2, a metal film (external plating film) MC is formed on the exposed surfaces of the outer lead parts OLD of the multiple leads LD, for example, on the surface of a substrate. Also, a lower surface DPb of the die pad DP is exposed from the sealing body MR. A metal film (external plating film) MC is formed on the exposed surface of the die pad DP from the sealing body MR, i.e., the lower surface DPb. By exposing the lower surface DPb of the die pad DP from the sealing body MR, it is possible to improve the efficiency of heat dissipation from the die pad DP to the outside of the semiconductor device PKG1.

[0029] The metal film MC is made of a metal material, such as solder, that has better wettability with solder than the copper substrate, and is a metal coating that covers the surface of the copper substrate. By forming a metal film MC made of solder or the like on each of the outer lead parts OLD of the leads LD that are the external terminals of the semiconductor device PKG1, as shown in Fig. 4, it is possible to improve the wettability of the solder material SD, which is a conductive connecting material, when the semiconductor device PKG1 is mounted on the mounting board MB1. This increases the bonding area between the leads LD and the solder material SD, and therefore improves the bonding strength between the leads LD and the terminals TM on the mounting board MB1 side.

[0030] Moreover, when the die pad DP and the heat sink TB of the mounting board MB1 are thermally connected via a solder material SD as shown in Fig. 4, the heat dissipation efficiency can be further improved. When the die pad DP and the solder material SD are connected, from the viewpoint of improving the wettability of the solder material SD on the lower surface DPb of the die pad DP, it is preferable to form a metal film MC (see Fig. 2) made of solder or the like on the lower surface DPb of the die pad DP exposed from the sealing body MR.

[0031] <Detailed structure of the chip mounting area> Next, a detailed structure on the die pad DP shown in Fig. 3 will be described. Fig. 5 is an enlarged plan view of the die pad, in which the wires shown in Fig. 3 are omitted and the outlines of the semiconductor chip and bonding material shown in Fig. 3 are indicated by dotted lines. Fig. 6 is an enlarged cross-sectional view taken along line BB in Fig. 5. Fig. 6 illustrates the bonding material DB and the semiconductor chip CP, which are omitted in Fig. 5.

[0032] As shown in Fig. 5, the semiconductor device PKG1 has a metal film MF1 formed on an upper surface DPt of a die pad DP, and a bonding material DB. As shown in Fig. 6, the bonding material DB includes a resin body RB and a plurality of metal particles CF contained in the resin body RB. Each of the metal film MF1 and the bonding material DB is interposed between the semiconductor chip CP and the die pad DP.

[0033] As shown in Figures 5 and 6, the upper surface DPt of the die pad DP includes a region DPR1 overlapping with the semiconductor chip CP, a region DPR2 adjacent to the periphery of the region DPR1 and not overlapping with the semiconductor chip CP, a region DPR3 included in the region DPR1 and covered with the metal film MF1, and a region DPR4 included in the region DPR1 and adjacent to the region DPR3 and not covered with the metal film MF1. As shown in Figure 5, the metal film MF1 (i.e., the region DPR3 on whose upper surface the metal film MF1 is formed) is formed in the center of the upper surface DPt of the die pad DP. Also, as shown in Figures 5 and 6, the semiconductor chip CP is mounted on the die pad DP so that the center of the semiconductor chip CP overlaps with the region DPR3.

[0034] The metal film MF1 is made of a metal material that is less susceptible to oxidation than the metal material that constitutes the die pad DP. The "resistance to oxidation" of a metal material can be defined by comparing the ionization tendencies of metals. If the metal material that constitutes the die pad is copper or iron (more specifically, 42 alloy, an alloy that contains iron), the metal film MF1 is made of a metal material that has a lower ionization tendency than copper (or a copper alloy) and iron. Examples of metal materials that have a lower ionization tendency than copper and iron include silver (Ag) and gold (Au).

[0035] As shown in FIG. 6, the roughness (surface roughness) of the upper surface DPt in the region DPR4 is rougher than the roughness (surface roughness) of the surface (contact surface) of the metal film MF1 with which the bonding material DB comes into contact. In this embodiment, after the entire upper surface DPt of the die pad DP is roughened, the metal film MF1 is formed by plating in the region DPR3 of the upper surface DPt of the die pad DP. In this case, of the metal film MF1 shown in FIG. 6, the surface roughness of the lower surface MF1b facing the die pad DP is rougher than the surface roughness of the upper surface MF1t not facing the die pad DP. The surface roughness of the metal film MF1 at the contact interface between the metal film MF1 and the bonding material DB means the surface roughness of the upper surface MF1t shown in FIG. 6.

[0036] Here, the area of ​​the region DPR3 is preferably 11% or more and 55% or less with respect to the area of ​​the region DPR1. In the example shown in FIG. 5, it is 11% with respect to the area of ​​the region DPR1. The reason will be explained below. FIG. 7 is an explanatory diagram showing the relationship between the area ratio of the region where the metal film shown in FIG. 5 is formed and the peeling rate of the bonding material. In FIG. 7, the horizontal axis shows the area ratio of the region DPR3 with respect to the region DPR1 shown in FIG. 5. The first test section TP1 on the leftmost side of the paper shows the evaluation of a product in which the metal film MF1 is not formed. The fifth test section TP5 on the rightmost side of the paper shows the evaluation of a product in which the metal film MF1 is formed so as to cover the entire region DPR1 shown in FIG. The second test section TP2, the third test section TP3, and the fourth test section TP4 between the first test section TP1 and the fifth test section TP5 show the evaluation of products in which the area of ​​the region DPR3 covered by the metal film MF1 is different. In addition, in Fig. 7, the vertical axis shows the peeling rate, which is the area of ​​the portion where peeling occurred at the interface between the bonding material DB shown in Fig. 6 and the die pad DP (or metal film MF1) in each test group, divided by the area of ​​the region DPR1 shown in Fig. 5. From the viewpoint of improving the heat dissipation efficiency of the semiconductor device, it is preferable that the bonding material DB shown in Fig. 6 is not peeled from the die pad DP and metal film MF1. Therefore, it can be said that a lower peeling rate is preferable.

[0037] When mounting a semiconductor chip on a chip mounting part made of a metal material that easily oxidizes, such as copper (Cu) or iron (Fe), by directly contacting the resin adhesive containing metal particles, the upper surface of the chip mounting part is likely to oxidize before the die-bonding process in which the semiconductor chip is mounted. If the die-bonding process is performed in an oxidized state, peeling is likely to occur between the oxidized upper surface and the resin adhesive. Therefore, as shown in Figure 6, we investigated whether peeling can be suppressed by interposing a metal film MF1 made of a metal material that is less likely to oxidize than the metal material of the die pad DP between the die pad DP and the bonding material DB. First, we performed an evaluation on the case where the metal film MF1 was formed over the entire die pad DP (see Figure 6), as shown as the fifth test area TP5 in Figure 7.

[0038] As shown in FIG. 7, it was confirmed that the peeling rate exceeded 25% in the product of the fifth test group TP5. This is considered to be because the stress applied to the peripheral portion of the semiconductor chip CP due to the heat applied in the heating process in the manufacturing process of the product or the heating process during the mounting of the product exceeded the adhesive force between the bonding material DB (see FIG. 6) and the metal film MF1. The linear expansion coefficients of silicon (Si) used in the semiconductor substrate of the semiconductor chip CP and the metal material constituting the die pad DP, which is a plate-shaped metal member, are significantly different. Therefore, when the planar size of the semiconductor chip CP increases, the stress applied to the vicinity of the peripheral portion of the semiconductor chip CP increases. Also, in this embodiment, the adhesive force between the bonding material DB and the metal film MF1 is lower than the adhesive force between the bonding material DB and the die pad DP. Therefore, when the stress applied to the vicinity of the peripheral portion of the semiconductor chip CP increases, peeling occurs at the interface between the bonding material DB and the metal film MF1 near the peripheral portion of the semiconductor chip CP (see FIG. 6), and this peeling progresses toward the center.

[0039] Also, it was confirmed that the peeling rate exceeded 25% in the product of the first test section TP1 shown in FIG. 7. The roughening treatment of the adhesive surface is performed for the purpose of increasing the contact area between the bonding material and the die pad, which is the object to be bonded, or for the purpose of obtaining an anchor effect by the roughened surface. Therefore, it was considered that the peeling rate could be suppressed in the product of the first test section TP1, in which the metal film MF1 was not formed and the upper surface DPt (see FIG. 6) of the die pad DP (see FIG. 6) was roughened. However, as shown in the evaluation result in FIG. 7, it was found that peeling occurred over a wide area. This is considered to be caused by gas trapped between the roughened upper surface DPt of the die pad DP and the bonding material DB (see FIG. 6) expanding due to heat, causing peeling. In this mode, peeling was confirmed in the center of the die pad DP and progressing toward the peripheral area. From this, it is considered that even if gas is contained between the upper surface DPt of the die pad DP and the bonding material DB in the peripheral area of ​​the die pad DP, this gas is likely to escape to the periphery of the bonding material DB in the process of mounting the semiconductor chip CP (see FIG. 6) on the die pad DP. On the other hand, it is believed that gas was more likely to be trapped in the center of the die pad DP due to the longer path for gas to leak.

[0040] Here, the peeling rate is less than 5% (about 0.5 to 2.5%) in each of the second test plot TP2 (area rate 11%), the third test plot TP3 (area rate 28%), and the fourth test plot TP4 (area rate 55%) shown in Figure 7. In other words, in the cases of the second test plot TP2, the third test plot TP3, and the third test plot TP4, the peeling rate value was reduced by 90% or more compared to the peeling rates of the first test plot TP1 and the fifth test plot TP5.

[0041] In each of the second test area TP2, the third test area TP3, and the third test area TP3, a metal film MF1 made of a metal material less susceptible to oxidation than the metal constituting the die pad DP (see FIG. 6) is formed in the center where gas is likely to be trapped. This makes it possible to suppress the occurrence of peeling due to an oxide film in the region DPR3 (see FIG. 5) located in the center of the region DPR1. In addition, the surface roughness of the metal film MF1 is smoother than the surface roughness of the top surface DPt (see FIG. 6) of the die pad DP. This makes it possible to suppress the occurrence of peeling due to the trapping of gas in the region DPR3 (see FIG. 5) located in the center of the region DPR1.

[0042] In addition, in the case of each of the second test area TP2, the third test area TP3, and the third test area TP3, in the peripheral portion (area DPR4 shown in FIG. 5) to which stress from the semiconductor chip CP (see FIG. 6) is likely to be applied, the roughened upper surface DPt (see FIG. 6) of the die pad DP (see FIG. 6) and the bonding material DB (see FIG. 6) are in close contact with each other. In the peripheral portion, when the upper surface DPt of the die pad DP is roughened, even if an oxide film is formed on the upper surface DPt, interfacial peeling with the bonding material DB can be suppressed. In addition, in the peripheral portion, gas between the bonding material DB and the die pad DP is likely to be discharged to the periphery of the bonding material DB. For this reason, the occurrence of peeling in the peripheral portion can be suppressed.

[0043] As described above, it is believed that the peeling rate was reduced in the second test area TP2, the third test area TP3, and the third test area TP3 by taking different peeling measures in areas DPR3 and DPR4, respectively.

[0044] From the results shown in Fig. 7 and the above considerations, it was found that peeling of the bonding material DB shown in Fig. 6 can be suppressed when the area of ​​the region DPR3 shown in Fig. 5 is 11% or more and 55% or less of the area of ​​the region DPR1. In other words, when the area of ​​the semiconductor chip CP (i.e., the area of ​​the region DPR1) is 25 mm 2In the above cases, even if the upper surface DPt of the die pad DP, which is roughened at the periphery where stress from the semiconductor chip CP is likely to be applied, is in close contact with the bonding material DB, peeling of the bonding material DB may occur if the area ratio of the region DPR3 is less than 11% or 56% or more. It was also found that suppressing peeling of the bonding material DB can improve the heat dissipation characteristics of the heat dissipation path from the semiconductor chip CP to the die pad DP.

[0045] Incidentally, the metal film MF1 shown in FIG. 6 only needs to prevent the formation of an oxide film at the adhesive interface with the bonding material DB until the die bonding process is performed. For this reason, various metal materials can be used as the metal material constituting the metal film MF1, so long as they are less susceptible to oxidation (in other words, have a smaller tendency to ionize) than the metal material constituting the die pad DP. However, from the viewpoint of improving the heat dissipation characteristics, it is preferable that the metal film MF1 itself has high thermal conductivity characteristics. From this viewpoint, it is particularly preferable that the metal film MF1 is made of silver or gold, as in this embodiment.

[0046] In addition, the peeling phenomenon in the fifth test area TP5 shown in FIG. 7 occurred when the area of ​​the semiconductor chip CP (see FIG. 6), in other words the area of ​​the region DPR1, was 25 mm 2 It was found that this problem was particularly noticeable when the area of ​​the semiconductor chip CP, in other words, the area of ​​the region DPR1, was 25 mm 2 More than 100mm 2 It was found that the peeling rate shown in FIG. 7 can be significantly reduced by taking the above measures in the following range. The data shown in FIG. 7 is for the area of ​​region DPR1 of 54.76 mm 2 The graph shows the results when a semiconductor device having a square shape (each side having a length of 7.4 mm) was evaluated.

[0047] 2, the upper surface DPt of the die pad DP and the sealing body MR are in contact around the bonding material DB. In other words, the region DPR2 of the upper surface DPt of the die pad DP shown in FIG. 5 is in contact with the sealing body MR shown in FIG. 2. If gas remains between the bonding material DB and the die pad DP, this can cause peeling between the sealing body MR and the die pad DP. In the case of this embodiment, the gas that exists between the bonding material DB and the die pad DP is discharged into the atmosphere in the die bonding process. This makes it possible to prevent peeling caused by this gas.

[0048] Also, as shown in FIG. 2, a metal film MF2 is formed on a portion of each of the multiple leads LD (the tip portion of the upper surface LDt of the inner lead portion ILD). Each of the multiple wires BW is bonded to the metal film MF2. The metal film MF2 is a plating film formed to improve the reliability of the electrical connection between the wire BW and the lead LD. The metal films MF1 and MF2 are formed of the same metal material (e.g., silver or gold). In this way, when the metal films MF1 and MF2 are formed of the same metal material, the metal films MF1 and MF2 can be formed collectively in the same manufacturing process.

[0049] 2, the lower surface DPb of the die pad DP is exposed from the sealing body MR. Considering the heat dissipation efficiency from the die pad DP, it is particularly preferable that the lower surface DPb of the die pad DP is exposed from the sealing body MR. However, although not shown, as a modified example, there is also a case where the lower surface DPb of the die pad DP is not exposed from the sealing body MR and is sealed in the sealing body MR.

[0050] <Modification> Next, some modified examples will be described. Fig. 8 is an enlarged cross-sectional view showing a modified example of Fig. 6. In the case of the semiconductor device PKG1 shown in Fig. 6, only the upper surface DPt of the die pad DP is roughened, and the side surface DPs and the lower surface DPb are not roughened. The side surface DPs is a surface that intersects with the upper surface DPt and the lower surface DPb. From the viewpoint of the above-mentioned peeling countermeasures, it is sufficient that at least the upper surface DPt of the die pad DP is roughened.

[0051] However, when only the top surface DPt is selectively roughened as shown in Fig. 6, the bottom surface DPb and the side surface DPs must be masked when the roughening process is performed. In the case of the semiconductor device PKG2 shown in Fig. 8, the side surface DPs and the bottom surface DPb are each roughened in the same manner as the top surface DPt. In this case, the surface roughness of each of the top surface DPt, the bottom surface DPb, and the side surface DPs of the die pad DP is rougher than the surface roughness of the metal film MF1 at the contact interface (top surface MF1t) between the metal film MF1 and the bonding material DB.

[0052] In the case of the semiconductor device PKG2, since it is not necessary to mask the bottom surface DPb and the side surface DPs in the roughening process, the work efficiency can be improved. In addition, since the side surface DPs is roughened, the adhesive strength between the sealing body MR (see FIG. 2) and the side surface DPs can be improved.

[0053] FIG. 9 is an enlarged plan view showing a modified shape of the metal film shown in FIG. 5. The semiconductor device PKG3 differs from the semiconductor device PKG1 shown in FIG. 5 in the shape of the metal film MF1. The planar shape of the metal film MF1 of the semiconductor device PKG3 is, for example, circular. A circular metal film MF1 without corners has the advantage that stress concentration is less likely to occur compared to a rectangular metal film with corners. Therefore, even if the area of ​​the metal film MF1 is large, there is an advantage that peeling due to stress can be easily suppressed. In addition to the circle shown in FIG. 9, various modified shapes such as an ellipse and a polygon can be applied to the planar shape of the metal film MF1.

[0054] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0055] BW Wire (conductive material) CF metal particles CP Semiconductor Chip CPb back side CPt surface DB Bonding material (die bond material) DP die pad (chip mounting area) DPb bottom side (back side) DPR1, DPR2, DPR3, DPR4 regions DPs Side DPt top surface (chip mounting surface) HL Hanging Lead ILD Inner lead part LD Lead LDt top surface MB1 mounting board MC Metal Film (External Plating Film) MF1, MF2 Metal film (plated film, plated metal film) MF1b bottom side MF1t top surface MR sealing body (resin body) MRb bottom surface (back surface, mounted surface) MRs side MRt top surface OLD Outer lead part PD Pad (Bonding Pad) PKG1, PKG2, PKG3 Semiconductor device RB resin body SD solder material TB heat sink TM terminal TP1 First test area TP2 Second test area TP3 Third test area TP4 4th test area TP5 5th test area

Claims

1. A semiconductor chip; a chip mounting portion having a first surface facing the semiconductor chip and a second surface opposite to the first surface; a first metal film formed on the first surface of the chip mounting portion; a bonding material formed so as to cover the first metal film, the bonding material including a resin body and a plurality of metal particles contained in the resin body; having the first metal film and the bonding material are each interposed between the semiconductor chip and the chip mounting portion, The first surface of the chip mounting portion is a first region overlapping the semiconductor chip; a second region adjacent to the periphery of the first region and not overlapping with the semiconductor chip; a third region included in the first region and covered with the first metal film; a fourth region that is included in the first region, that is adjacent to the third region, and that is not covered by the first metal film; Including, the semiconductor chip is mounted on the chip mounting portion such that a center of the semiconductor chip overlaps with the third region; the first metal film is made of a metal material which is less susceptible to oxidation than a metal material constituting the chip mounting portion, a surface roughness of the first surface in the fourth region is greater than a surface roughness of a contact surface of the first metal film with which the bonding material comes into contact; A semiconductor device, wherein an area of ​​the third region is 11% or more and 55% or less of an area of ​​the first region.

2. In claim 1, the chip mounting portion further includes a third surface intersecting the first surface and the second surface, A semiconductor device, wherein the surface roughness of each of the first surface, the second surface, and the third surface of the chip mounting portion is rougher than the surface roughness of the first metal film at the contact interface between the first metal film and the bonding material.

3. In claim 1, A semiconductor device, wherein the first metal film is made of silver or gold.

4. In claim 1, The semiconductor device, wherein the chip mounting portion is made of copper, an alloy containing copper, or an alloy containing iron.

5. In claim 1, The area of ​​the first region is 25 mm ２ More than 100 mm ２ The semiconductor device is as follows:

6. In claim 1, A plurality of leads arranged apart from the chip mounting portion; a plurality of wires connected to the semiconductor chip and the plurality of leads; an encapsulant that encapsulates the plurality of wires and the semiconductor chip; and The second region of the first surface of the chip mounting portion is in contact with the sealing body.

7. In claim 6, a second metal film is formed on a portion of each of the plurality of leads; Each of the plurality of wires is bonded to the second metal film; The first metal film and the second metal film are formed of the same metal material.

8. In claim 6, The second surface of the chip mounting portion is exposed from the sealing body.

9. In claim 1, The semiconductor device, wherein the semiconductor chip is rectangular in plan view.

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