A split-type capacitance calibration circuit applied to pure capacitor array structures.

Abstract

To provide a split type capacitance calibration circuit.SOLUTION: A calibration circuit includes: a first correction unit, a second correction unit and a changeover switch Sc connected to a scaling capacitor Cs of a pure capacitor array structure. The first correction unit and second correction unit each includes at least one capacitor, and the changeover switch turns ON or OFF to select the first correction unit or second correction unit and connect the selected one to the pure capacitor array structure, wherein: when an error of the scaling capacitor is a negative number, the changeover switch turns ON and the first correction unit is connected to the pure capacitor array structure and connected to the scaling capacitor in parallel so as to correct the error which is the negative number, of the scaling capacitor; and when the error of the scaling capacitor is a positive number, the changeover switch turns OFF and the second correction unit is connected to the pure capacitor array structure and connected to the scaling capacitor in series so as to correct the error which is the positive number, of the scaling capacitor.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to the field of integrated circuits, and more particularly to a split capacitance calibration circuit applied to a pure capacitor array structure. [Background technology]

[0002] Digital-to-analog converters play an important role in bridging analog circuits, and SAR ADC (successive approximation register) circuits are the most widely used. SAR ADC structures include resistor-resistor type, capacitor-resistor type, and capacitor-capacitor type. Resistor-resistor (pure resistor) type is rarely used due to power issues, and capacitor-capacitor (pure capacitor) type is rarely used in high-precision ADCs because the total capacitor area is too large. The most commonly used structure is the capacitor-resistor (mixed) structure, which is between the two.

[0003] The total capacitor area of ​​the capacitor-capacitor structure should not be ignored, but it is highly valued in some important cases due to its fast response speed and small power. In the process of use, traditional designs generally reduce the total capacitance by adding a scaling capacitor to the circuit structure.

[0004] Figure 1 is a comparison diagram of the pure capacitor array structure with the addition of a scaling capacitor and the original array, and Cs in the following drawings is the scaling capacitor. Due to the scaling capacitor Cs, all the capacitors in the MSB array (large capacity array) do not follow the two-fold relationship. Also, due to the scaling capacitor Cs, the weighting of all the capacitors in the LSB array (small capacity array) is the same as the original array (above drawings). The total capacitance value of the original array is 32C (C is a predetermined capacitance value, and the specific value can be set comprehensively based on the domain design and cost, and here only the capacitance value relationship between each capacitor is shown), and by improving the scaling capacitor, the size of the capacitor of the entire array is 31C / 8+Cs. The series connection combination of the scaling capacitor Cs and the LSB array must be connected to the left of the MSB array, and the total capacitance value of the LSB array is C / 8, so JPEG0007676523000001.jpg11170, and by calculating the above formula, the capacitance value of the scaling capacitor Cs is 2C / 15, and the total capacitance value of the entire capacitor array is 31C / 8+2C / 15. Obviously, after adding the scaling capacitor Cs, the total capacitance is about 8 times smaller than that of the original array, which is a great improvement for high-precision SAR ADC, and greatly improves the capacitor area of ​​the entire array.

[0005] However, the drawback of the improvement by adding the scaling capacitor Cs is that the magnitude of the scaling capacitor Cs is generally a non-integer multiple of C. Considering the case of capacitance mismatch, the minimum capacitor (capacitor with the smallest capacitance) in the LSB array is also generally a non-integer multiple of C. Therefore, in the actual application process, the capacitance value of the scaling capacitor Cs is difficult to match, so a certain error occurs in the capacitance value of the scaling capacitor Cs. Furthermore, errors also occur in all weighted value bits (each capacitor) of the LSB array. Summary of the Invention [Problem to be solved by the invention]

[0006] Therefore, to overcome the above deficiencies, there is a need to provide a split capacitance calibration circuit that can calibrate the scaling capacitors and is applied to a pure capacitor array structure.

[0007] The present invention aims to provide a split-type capacitance calibration circuit applicable to a pure capacitor array structure, which can perform high-precision calibration for errors in the scaling capacitors in a pure capacitor array, and solves the problem of nonlinearity caused by the accuracy errors of the scaling capacitors in the pure capacitor array structure. [Means for solving the problem]

[0008] In order to achieve the above object, the present invention provides a split-type capacitance calibration circuit applied to a pure capacitor array structure, which is disposed between a large-capacity array and a small-capacity array of the pure capacitor array structure, and includes a first compensation unit, a second compensation unit and a change-over switch, each of which is connected to a scaling capacitor of the pure capacitor array structure, and the first compensation unit and the second compensation unit each include at least one capacitor, and the change-over switch is turned on / off to select the first compensation unit or the second compensation unit to be connected to the pure capacitor array structure, when the error of the scaling capacitor is a negative number, the change-over switch is turned on, and the first compensation unit is connected to the pure capacitor array structure and is connected in parallel to the scaling capacitor to correct the negative error of the scaling capacitor, and when the error of the scaling capacitor is a positive number, the change-over switch is turned off, and the second compensation unit is connected to the pure capacitor array structure and is connected in series to the scaling capacitor to correct the positive error of the scaling capacitor.

[0009] Preferably, the first correction unit includes n sets of first correction subunits, each of the first correction subunits of each set includes a first switch and two identical first capacitors, the two first capacitors and the first switches are connected in series, the first switch of any one of the first correction subunits is turned on, and the first correction subunit of the current set is connected in parallel to the scaling capacitor, where n is the number of predetermined positions for correcting negative errors and is a natural number greater than or equal to 1.

[0010] Preferably, the reference capacitance value is set to twice the product of the total capacitance value of the small-capacity capacitor array and a predetermined correction value, the first capacitance value in the first set of first correction subunits is set to the reference capacitance value, and the capacitance value of the first capacitor in any other set of first correction subunits is set to the sum of the first capacitance value of the previous set of first correction subunits and the reference capacitance value.

[0011] Preferably, the second compensation unit includes m sets of second compensation subunits, each set of second compensation subunits includes a second switch and a second capacitor, the second capacitor is connected in series to the second switch, the second switch of the second compensation subunit of any one set is turned on, and the second compensation subunit of the current set is connected in series to the scaling capacitor, m is a predetermined position number for compensating for a positive error, and is a natural number greater than or equal to 1.

[0012] Preferably, the capacitance value of the scaling capacitor is set as Cs, the error of the scaling capacitor Cs corrected by the xth second correction sub-unit is set as bx, the capacitance value of the second capacitor of the xth second correction sub-unit is set as Cx (1≦x≦m), and the formula for calculating the capacitance value Cx of the second capacitor is: JPEG0007676523000002.jpg10170.

[0013] Preferably, when the changeover switch is turned off, each of the first switches is turned off.

[0014] Preferably, the changeover switch, each of the first switches and each of the second switches are switches in the form of a transmission gate.

[0015] Preferably, the changeover switch, each of the first switches and each of the second switches are composed of a P-type MOS transistor and an N-type MOS transistor having the same size, the sources of the P-type MOS transistor and the N-type MOS transistor are connected together to form one input / output end of the switch, the drains of the P-type MOS transistor and the N-type MOS transistor are connected together to form another input / output end of the switch, and the gates of the P-type MOS transistor and the N-type MOS transistor respectively form the control end of the switch. Effect of the Invention

[0016] Compared with the prior art, the split-type capacitance calibration circuit applied to the pure capacitor array structure of the present invention is provided with a first compensation unit for compensating for negative errors and a second compensation unit for compensating for positive errors, and the selector switch is used to select the compensation unit currently connected to the pure capacitor array structure. When the first compensation unit is selected, the first compensation unit is connected in parallel to the scaling capacitor, thereby increasing the total capacitance value in the circuit and offsetting some of the negative errors of the scaling capacitor; when the second compensation unit is selected, the second compensation unit is connected in series to the scaling capacitor, thereby decreasing the total capacitance value in the circuit and offsetting some of the positive errors of the scaling capacitor, thereby realizing error calibration for the scaling capacitor and solving the problem of nonlinearity caused by accuracy errors of the scaling capacitor in the pure capacitor array structure.

[0017] The invention will become clearer in combination with the following description and the drawings, which illustrate embodiments of the invention. [Brief description of the drawings]

[0018] [Figure 1]FIG. 1 is an example of a structural schematic diagram of a pure capacitor array according to the prior art; [Diagram 2] FIG. 2 is an example of a structural schematic diagram of a split-type capacitance calibration circuit applied to a pure capacitor array structure according to an embodiment of the present invention; [Diagram 3] FIG. 2 is an example of a structural schematic diagram of a switch in a split-type capacitance calibration circuit applied to a pure capacitor array structure according to an embodiment of the present invention. [Figure 4] FIG. 2 is an example of a structural schematic diagram of one embodiment of a split-type capacitance calibration circuit applied to a pure capacitor array structure of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment of the present invention will be described with reference to the drawings, in which like reference numerals refer to like elements throughout the drawings. As described above, the present invention provides a split-type capacitance calibration circuit adapted to a pure capacitor array structure, which can calibrate with high accuracy the errors of the scaling capacitors in the pure capacitor array, and solves the problem of nonlinearity caused by the accuracy errors of the scaling capacitors in the pure capacitor array structure.

[0020] Please refer to Fig. 2, Fig. 2 is a structural schematic diagram of a split type capacitance calibration circuit applied to a pure capacitor array structure of the present invention according to one embodiment. As shown in the drawing, the split type capacitance calibration circuit of this embodiment applied to a pure capacitor array structure is disposed between the large-capacity array and the small-capacity array of the pure capacitor array structure, and in Fig. 2, the capacitor Cmsb is equivalent to the large-capacity capacitor array, and the capacitor Clsb is equivalent to the small-capacity capacitor array. The calibration circuit includes a first compensation unit, a second compensation unit and a change-over switch Sc, each of which is connected to a scaling capacitor Cs of a pure capacitor array structure, and the first compensation unit and the second compensation unit each include at least one capacitor. The change-over switch Sc is turned on / off to select the first compensation unit or the second compensation unit to be connected to the pure capacitor array structure. When the error of the scaling capacitor Cs is negative, the change-over switch Sc is turned on, and the first compensation unit is connected to the pure capacitor array structure and is connected in parallel to the scaling capacitor to correct the negative error of the scaling capacitor Cs. When the error of the scaling capacitor Cs is positive, the change-over switch Sc is turned off, and the second compensation unit is connected to the pure capacitor array structure and is connected in series to the scaling capacitor to correct the positive error of the scaling capacitor Cs. The on / off of the change-over switch Sc may be controlled by an external circuit, which is not mentioned in the present invention.

[0021] As can be seen from the above, in the divided capacitance calibration circuit applied to the pure capacitor array structure of this embodiment, when the error of the scaling capacitor Cs is negative, the changeover switch Sc is turned on, the first correction unit is connected in parallel to the scaling capacitor and includes at least one capacitor, that is, at least one capacitor is connected in parallel to the scaling capacitor Cs, so that the total capacitance value of the circuit is large, and some of the negative errors of the scaling capacitor Cs can be offset; correspondingly, when the error of the scaling capacitor Cs is positive, the changeover switch Sc is turned off, the second correction unit is connected in series to the scaling capacitor and includes at least one capacitor, that is, at least one capacitor is connected in series to the scaling capacitor Cs, so that the total capacitance value of the circuit is small, and some of the positive errors of the scaling capacitor can be offset, thereby realizing error calibration for the scaling capacitor Cs, and solving the problem of nonlinearity caused by accuracy errors of the scaling capacitor Cs in the pure capacitor array structure.

[0022] Specifically, referring to FIG. 2 again, the first compensation unit of the divided capacitance calibration circuit applied to the pure capacitor array structure of this embodiment includes n sets of first compensation sub-units, each set of first compensation sub-units includes a first switch Sn (Sn1, Sn2...Snn) and two identical first capacitors Cn1 (Cn11, Cn21...Cnn1), Cn2 (Cn12, Cn22...Cnn2), the two first capacitors Cn1, Cn2 and the first switch Sn are all connected in series, the first switch of any one set of first compensation sub-units is turned on, and the first compensation sub-unit of the current set is connected in parallel to the scaling capacitor Cs, where n is the number of predetermined positions for compensating for a negative error, in this embodiment, each first compensation sub-unit Each compensation subunit is provided with two identical first capacitors Cn1, Cn2 connected in series. After the two capacitors are connected in series, an equivalent capacitor with a smaller capacitance value is obtained. If the capacitor with a smaller capacitance value is directly used, the capacitance is too small, so that the mismatch coefficient of the entire circuit is large, which affects the compensation accuracy of the entire circuit. Therefore, in this embodiment, two first capacitors Cn1, Cn2 with large capacitance values ​​are connected in series to obtain an equivalent capacitor with a smaller capacitance value, thereby solving the problem of mismatch and obtaining an equivalent capacitor with a small capacitance value, which works together to realize compensation for the scaling capacitor Cs, where n is a natural number greater than or equal to 1. Taking the first set of first compensation sub-unit as an example, the compensation sub-unit includes a first switch Sn1 and two first capacitors Cn11 and Cn12, the two first capacitors Cn11 and Cn12 are connected in series and then connected to the first switch Sn1, when the first switch Sn1 is turned on, the first set of first compensation sub-unit is connected in parallel to the scaling capacitor Cs, that is, the first capacitors Cn11 and Cn12 are connected in series and then connected in parallel to the scaling capacitor Cs, which is connected to the pure capacitor array circuit, thereby increasing the total capacitance value connected to the circuit and further offsetting some negative value errors of the scaling capacitors Cs.Specifically, the capacitance value of the smallest capacitor (the capacitor with a capacitance value of c / 8 in FIG. 1) in the small capacitor array is set to k, the compensation accuracy coefficient is set to a, and twice the product of the compensation accuracy coefficient a and the capacitance value k of the smallest capacitor is set to the reference capacitance value g, that is, g=2k*a. The capacitance values ​​of the first capacitors Cn11 and Cn12 in the first set of first compensation sub-units are the reference capacitance value, that is, All of the capacitance values ​​are g, and the capacitance value of the first capacitors Cn1, Cn1 of any other set of first correction subunits is the sum of the first capacitance values ​​Cn1, Cn1 of the previous set of first correction subunits and the reference capacitance value g, that is, the capacitance value of the first capacitors Cn21, Cn22 of the second set of first correction subunits is 2g, and correspondingly, the capacitance value of the first capacitors Cn31, Cn32 of the third set is 3g, and the capacitance value of the first capacitors Cnn1, Cnn2 of the nth set is ng.

[0023] Further, referring to FIG. 4 in combination, the negative error correction of the scaling capacitor Cs by the first correction unit will be described by taking an example in which four (i.e., n=4) sets of first correction sub-units are provided. When the changeover switch Sc and the first switch S41 are turned on and the first switches S42, S43, and S4 are turned off, the scaling capacitor Cs has a 0.5g capacitor connected in parallel, and the total capacitance value of the capacitor (the capacitor after the first capacitors Cn11 and Cn12 are connected in series) is increased by 0.5g. When the changeover switch Sc and the first switch S42 are turned on and the first switches S41, S43, and S44 are turned off, the scaling capacitor Cs has a 1g capacitor (the first capacitors Cn21 and Cn22 are connected in series). When the changeover switch Sc and the first switch S43 are turned on and the first switches S41, S42, and S44 are turned off, a 1.5g (capacitor after the first capacitors Cn31 and Cn32 are connected in series) capacitor with a total capacitance value increased by 1.5g is connected in parallel to the scaling capacitor Cs, and when the changeover switch Sc and the first switch S44 are turned on and the first switches S41, S42, and S43 are turned off, a 2g (capacitor after the first capacitors Cn41 and Cn42 are connected in series) capacitor with a total capacitance value increased by 2g is connected in parallel to the scaling capacitor Cs. As described above, the adjustable capacitance value range of the first correction unit structure in which four sets of first correction sub-units are provided is a*k-4a*k, and the accuracy of the capacitance value to be corrected is a*k. Obviously, the more first correction sub-units connected in parallel to the scaling capacitor Cs (the larger the value of n), the higher the calibration range, and of course the accuracy of the correction will remain unchanged. Therefore, in the application process, an appropriate value of n can be selected according to the actual situation to obtain an appropriate calibration range, and is not specifically limited in the present invention.

[0024] Also, as shown in FIG. 2, in this embodiment, the second compensation unit includes m sets of second compensation subunits, m being a natural number greater than or equal to 1, and each set of second compensation subunits includes a second switch Sm (Sm1, Sm2...Smm) and a second capacitor Cm (Cm1, Cm2...Cmm), the second switch Sm is connected in series to the second capacitor Cm, the second switch Sm of any one set of second compensation subunits is turned on, and the second compensation subunit of the current set is connected in series to the scaling capacitor Cs, and m is a predetermined position number for compensating for a positive error, and is a natural number greater than or equal to 1. Taking the first set of second compensation subunits as an example, the compensation subunits include a second switch Sm1 and a second capacitor Cm1, when the second switch Sm1 is turned on, the first set of second compensation subunits is connected in parallel with the scaling capacitor Cs, that is, the second capacitor Cm1 is connected in series with the scaling capacitor Cs to the pure capacitor array circuit, so that the total capacitance value connected to the circuit is small, and some positive errors of the scaling capacitor Cs can be offset. Specifically, the capacitance value of the scaling capacitor Cs is set as Cs, the error of the scaling capacitor Cs compensated by the xth set of second compensation subunits is set as bx, and the capacitance value of the second capacitor Cmx of the xth set of second compensation subunits is set as Cx (1≦x≦m), and the formula for calculating the capacitance value Cx of the second capacitor Cmx of any one set of second compensation subunits is: JPEG0007676523000003.jpg10170. In this way, by selecting a second capacitor Cm having an appropriate capacitance value from each set of second correction sub-units according to the formula, error correction can be performed on the scaling capacitor Cs according to a predetermined error value.

[0025] Specifically, referring to FIG. 4 in combination, the compensation process of the second compensation unit is described by an example. Since the scaling capacitor Cs is close to the capacitance value k of the smallest capacitance capacitor of the small capacitance capacitor array, in the compensation process, Cs=k is assumed, the reference compensation error is set as h, and h=bx / x=b1. Take the example of providing 4 (i.e. m=4) sets of second compensation sub-units to describe the positive error compensation of the scaling capacitor Cs by the second compensation unit. When the errors of each position are h, 2h, 3h, and 4h, respectively, , the sum of the capacitance value and the error capacitance value of the corresponding scaling capacitor Cs is k+h, k+2h, k+3h, k+4h, respectively. Specifically, when the error of the first position is h (error b1), (x=1), the second switch Sm1 is turned on, the changeover switch Sc and the second switches Sm2, Sm3, and Sm4 are turned off, and the capacitor in the circuit is formed by connecting a capacitor with a capacitance value of k+h and a second capacitor Cm1 with a capacitance value of k / h (which can be obtained by calculating according to formula (1)) in series. After being connected in series, the capacitance value of the equivalent capacitor obtained is 1 / [1 / (k+h)+h / k]. When the error in the second position is 2h (error b2), (x=2), the second switch Sm2 is turned on, the changeover switch Sc and the second switches Sm1, Sm3, and Sm4 are turned off, and the capacitor in the circuit is a capacitor formed after a capacitor with a capacitance value of k+2h and a second capacitor Cm2 with a capacitance value of k / 2h (which can be obtained by calculating using formula (1)) are connected in series. After being connected in series, the capacitance value of the equivalent capacitor obtained is 1 / [1 / (k+2h)+2h / k]. When the error in the third position is 3h (error b3), (x=3), the second switch Sm3 is turned on, the change-over switch Sc and the second switches Sm1, Sm2, and Sm4 are turned off, and the capacitor in the circuit is a capacitor formed by connecting in series a capacitor having a capacitance value of k+3h and a second capacitor Cm3 having a capacitance value of k / 3h (which can be obtained by calculating using formula (1));The capacitance value of the equivalent capacitor obtained by the series connection is 1 / [1 / (k+3h)+3b / k]. When the error in the fourth position is 4h (error b4), (x=4), the second switch Sm4 is turned on, the changeover switch Sc and the second switches Sm1, Sm2, and Sm3 are turned off, and the capacitor in the circuit is a capacitor formed by connecting in series a capacitor having a capacitance value of k+4h and a second capacitor Cm4 having a capacitance value of k / 4h (which can be obtained by calculating using formula (1)). The capacitance value of the equivalent capacitor obtained by the series connection is 1 / [1 / (k+4h)+4b / k]. Therefore, it can be seen from the calculation of the above four sets of second compensation sub-units that the capacitance value of any one set of equivalent capacitors obtained by series connection is smaller than k, and specifically, the value smaller than k is related to the selected position (specific value of x), and this position corresponds to the magnitude of error of the scaling capacitor Cs; therefore, by connecting the second compensation sub-unit corresponding to this position to the pure capacitor array structure, the error of the scaling capacitor Cs can be compensated, and the compensation is performed within the range of hm*h for the scaling capacitor Cs, and the accuracy of the compensated capacitance is h. Obviously, the more second compensation sub-units are connected in series to the scaling capacitor Cs (the larger the value of m), the higher the calibration range, and of course the accuracy of the compensation remains unchanged; therefore, in the application process, a suitable value of m can be selected according to the actual situation to obtain a suitable calibration range, and there is no specific limitation in the present invention.

[0026] In addition, since each of the first correction subunits and the scaling capacitor Cs are connected in parallel, and each of the second correction subunits and the scaling capacitor Cs are connected in series, when the changeover switch is turned off and the second correction unit is selected, each of the first switches Sn (Sn1, Sn2...Snn) is turned off, thereby avoiding any influence on the second correction subunit.

[0027] In the preferred embodiment of the present invention, the switches, including the changeover switch, the first switches and the second switches, are all transmission gate type switches, thereby solving the problem of nonlinearity caused by charge injection. Specifically, as shown in Fig. 3, each switch is composed of a P-type MOS transistor and an N-type MOS transistor having the same size, the sources of the P-type MOS transistor and the N-type MOS transistor are connected together to form one input / output end Vin of the switch, the drains of the P-type MOS transistor and the N-type MOS transistor are connected together to form another input / output end Vout of the switch, and the gates (CT, CTN) of the P-type MOS transistor and the N-type MOS transistor form the control end of the switch. In addition, in the present invention, the control of each switch may be manually controlled one by one by a correction operator or may be realized by an external control circuit, and the present invention does not limit the specific control form, and it is sufficient to control one by one based on the position.

[0028] Although the present invention has been described above by combining the best embodiments, the present invention is not limited to the above disclosed embodiments, and should cover various modifications and equivalent combinations according to the essence of the present invention.

Claims

1. 1. A divided capacitance calibration circuit applied to a pure capacitor array structure, comprising: a first correction unit, a second correction unit, and a change-over switch, the first correction unit and the second correction unit each including at least one capacitor and at least one switch, the change-over switch being turned on / off to select the first correction unit or the second correction unit to be connected to the pure capacitor array structure, when an error of the scaling capacitor is a negative number, the change-over switch being turned on, the first correction unit being connected to the pure capacitor array structure and connected in parallel to the scaling capacitor to correct the negative error of the scaling capacitor, and when an error of the scaling capacitor is a positive number, the change-over switch being turned off, the second correction unit being connected to the pure capacitor array structure and connected in series to the scaling capacitor to correct the positive error of the scaling capacitor.

2. 2. The divided capacitance calibration circuit applied to a pure capacitor array structure according to claim 1, wherein the first correction unit includes n sets of first correction subunits, each set of first correction subunits includes a first switch and two identical first capacitors, the two first capacitors and the first switches are connected in series, the first switch of any one set of first correction subunits is turned on, and the first correction subunit of the current set is connected in parallel to the scaling capacitor, n is a predetermined position number for correcting a negative error, and is a natural number greater than or equal to 1.

3. The divided capacitance calibration circuit applied to the pure capacitor array structure according to claim 2, characterized in that the reference capacitance value is set to twice the product of the total capacitance value of the small capacitance array and a predetermined correction value, the first capacitance value in the first set of first correction subunits is set to the reference capacitance value, and the capacitance value of the first capacitor in any other set of first correction subunits is set to the sum of the first capacitance value of the previous set of first correction subunits and the reference capacitance value.

4. 3. The split-type capacitance calibration circuit applied to a pure capacitor array structure as claimed in claim 2, wherein the second correction unit includes m sets of second correction subunits, each set of second correction subunits includes a second switch and a second capacitor, the second capacitor is connected in series to the second switch, the second switch of the second correction subunit of any one set is turned on, and the second correction subunit of the current set is connected in series to the scaling capacitor, m is a predetermined position number for correcting a positive error, and is a natural number greater than or equal to 1.

5. The capacitance value of the scaling capacitor is set as Cs, the error of the scaling capacitor Cs corrected by the second correction sub-unit of the xth group is set as bx, and the capacitance value of the second capacitor of the second correction sub-unit of the xth group is set as Cx (1≦x≦m), and the formula for calculating the capacitance value Cx of the second capacitor is:

5. The split capacitance calibration circuit applied to a pure capacitor array structure according to claim 4,

6. 5. The split-type capacitance calibration circuit applied to a pure capacitor array structure as claimed in claim 4, wherein when the changeover switch is turned off, each of the first switches is turned off.

7. 5. The division type capacitance calibration circuit for use in a pure capacitor array structure as claimed in claim 4, wherein the changeover switch, each of the first switches and each of the second switches are transmission gate type switches.

8. 8. The split-type capacitance calibration circuit applied to the pure capacitor array structure according to claim 7, wherein the changeover switch, each of the first switches and each of the second switches are composed of a P-type MOS transistor and an N-type MOS transistor having the same size, the sources of the P-type MOS transistor and the N-type MOS transistor are connected together to form one input / output end of the switch, the drains of the P-type MOS transistor and the N-type MOS transistor are connected together to form another input / output end of the switch, and the gates of the P-type MOS transistor and the N-type MOS transistor respectively form the control end of the switch.

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