Variable gain differential amplifier circuit and semiconductor integrated circuit

Abstract

To improve the linearity of an output signal over a wide frequency band.SOLUTION: A gain-variable differential amplifier circuit 100 includes: input terminals 91a, 91b for receiving input signals; output terminals 92a, 92b for outputting output signals; transistors 10a, 10b having bases connected to the input terminals 91a, 91b, and collectors connected to the output terminals 92a, 92b; and a degeneration circuit 35 connected between emitters of the transistors 10a, 10b. The degeneration circuit 35 includes: MOS transistors 30a, 30b whose two current terminals are connected in series between the emitters of the transistors 10a, 10b; a series resistance circuit 22; current sources 61a, 61b; resistance elements 24a, 24b connected between the current sources 61a, 61b and the gates of the MOS transistors 30a, 30b; and resistance elements 23a, 23b connected between the current sources 61a, 61b and nodes D, E of the series resistance circuit 22.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a variable gain differential amplifier circuit and a semiconductor integrated circuit. [Background technology]

[0002] Conventionally, a differential amplifier circuit that amplifies and outputs an input differential voltage signal has been used as a circuit built into an optical transmission module, etc. For example, a configuration including a pair of amplifying transistors and a gain control transistor connected between the sources of the pair of amplifying transistors is known as a differential amplifier circuit (see Patent Documents 1 to 4 below). With such a configuration, the gain of the differential amplifier circuit can be variably controlled. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-256039 [Patent Document 2] Japanese Patent Application Publication No. 11-168334 [Patent Document 3] JP 2004-304775 A [Patent Document 4] JP 2019-36817 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional differential amplifier circuit described above, gain control is achieved by a control voltage applied to the gate of the gain control transistor, which can make it difficult to maintain the linearity of the output signal over a wide frequency band.

[0005] Therefore, the present disclosure has been made in consideration of such problems, and aims to provide a variable gain differential amplifier circuit capable of improving the linearity of an output signal over a wide frequency band, and a semiconductor integrated circuit including the same. [Means for solving the problem]

[0006] In order to solve the above problem, a variable gain differential amplifier circuit according to one aspect of the present disclosure includes a first input terminal and a second input terminal each for receiving an input signal, a first output terminal and a second output terminal each for outputting an output signal, a first transistor having a control terminal connected to the first input terminal and one current terminal connected to the first output terminal, a second transistor having a control terminal connected to the second input terminal and one current terminal connected to the second output terminal, and a second transistor having one end connected to the other current terminal of the first transistor and the other current terminal of the second transistor. a current source connected to the other current terminal and the other end connected to a first power supply; a first load resistor element connected between the first output terminal and the second power supply; a second load resistor element connected between the second output terminal and the second power supply; and a variable resistor circuit having a first node and a second node, the first node being connected to the other current terminal of the first transistor and the second node being connected to the other current terminal of the second transistor, and variably setting a resistance value between the first node and the second node, wherein the variable resistor circuit has a first control terminal a first field effect transistor having a second control terminal, a first current terminal and a second current terminal, the first current terminal being connected to a first node; a second field effect transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal being connected to a second node and the fourth current terminal being connected to a second current terminal of the first field effect transistor; a first voltage dividing resistor connected between the first node and a first voltage dividing node; a second voltage dividing resistor connected between the first voltage dividing node and a second voltage dividing node; the first field effect transistor and a second node; a first gate connection resistor; a second gate connection resistor; a first variable current source connected to a first control terminal of the first field effect transistor via the first gate connection resistor; a second variable current source connected to a second control terminal of the second field effect transistor via the second gate connection resistor; a first bias resistor connected between the first variable current source and the first voltage division node; and a second bias resistor connected between the second variable current source and the second voltage division node.

[0007] Alternatively, a variable gain differential amplifier circuit according to another aspect of the present disclosure includes a first input terminal and a second input terminal each for receiving an input signal, a first output terminal and a second output terminal each for outputting an output signal, a first transistor having a control terminal connected to the first input terminal and one current terminal connected to the first output terminal, a second transistor having a control terminal connected to the second input terminal and one current terminal connected to the second output terminal, and a second transistor having one end connected to the other current terminal of the first transistor and the other current terminal of the second transistor and the other end connected to a first power supply. a first load resistor element connected between the first output terminal and the second power supply; a second load resistor element connected between the second output terminal and the second power supply; and a variable resistor circuit having a first node and a second node, the first node being connected to the other current terminal of the first transistor and the second node being connected to the other current terminal of the second transistor, the variable resistor circuit variably setting a resistance value between the first node and the second node, the variable resistor circuits each having two current terminals and a control terminal, and each connected between the first node and the second node. two current terminals of the first field effect transistor are connected in series; N field effect transistors (N is an integer of 3 or more) from a first field effect transistor to an Nth field effect transistor, the first field effect transistor is connected to a first node, the ith (i is an integer of 2 or more and N-1 or less) field effect transistor is connected to the i-1th field effect transistor, and the Nth field effect transistor is connected between the N-1th field effect transistor and a second node; N field effect transistors connected in series between the first node and a second node; N+1 voltage divider resistors from a voltage divider resistor to an N+1 voltage divider resistor, where a first voltage divider resistor is connected between a first node and a first voltage divider node, a jth voltage divider resistor (j is an integer between 2 and N) is connected between a j-1th voltage divider node and a jth voltage divider node, and the N+1th voltage divider resistor is connected between the Nth voltage divider node and a second node; N variable current sources from a first variable current source to an Nth variable current source, each of which provides a variable current; and N gate connection resistors from a first gate connection resistor to an Nth gate connection resistor;The kth (k is an integer between 1 and N) gate connection resistor includes N gate connection resistors connected between the kth variable current source and the control terminal of the kth field effect transistor, and N bias resistors from the first bias resistor to the Nth bias resistor, and the mth (m is an integer between 1 and N) bias resistor includes N bias resistors connected between the mth voltage division node and the mth variable current source. Effect of the Invention

[0008] According to the present disclosure, it is possible to improve the linearity of an output signal over a wide frequency band. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram showing a schematic configuration of a drive circuit 200 according to the embodiment. [Diagram 2] 2 is a circuit diagram showing a configuration of a variable gain differential amplifier circuit 100 of FIG. [Diagram 3] 3 is a graph showing frequency dependence of small signal gain of the gate to source of the MOS transistor 30a of FIG. 2; [Figure 4] FIG. 2 is a block diagram showing a configuration of an optical transmission module 400 according to the embodiment. [Diagram 5] 1 is a block diagram showing a configuration of an optical transceiver module 500 according to an embodiment. [Figure 6] 4 is a graph showing a change in output amplitude and a change in total harmonic distortion of an output voltage signal when the gain of the variable gain differential amplifier circuit 100 according to the embodiment is changed. [Figure 7] 4 is a graph showing signal waveforms at each terminal in the variable gain differential amplifier circuit 100 according to the embodiment. [Figure 8] 4 is a graph showing frequency dependence of change in output amplitude and change in total harmonic distortion with respect to gain of the variable gain differential amplifier circuit 100 according to the embodiment. [Figure 9] 1 is a circuit diagram showing a modified example of the configuration of the variable gain differential amplifier circuit 100. FIG. [Figure 10]11 is a circuit diagram showing a configuration of a variable gain differential amplifier circuit 100A according to a modified example. FIG. [Figure 11] FIG. 13 is a circuit diagram showing a configuration of a variable gain differential amplifier circuit 100B according to another modified example. [Figure 12] FIG. 1 is a circuit diagram showing a configuration of a conventional variable gain differential amplifier circuit 900. [Figure 13] 1 is a graph showing signal waveforms at each terminal in a conventional variable gain differential amplifier circuit 900. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A variable gain differential amplifier circuit according to one aspect of the present disclosure includes a first input terminal and a second input terminal each for receiving an input signal, a first output terminal and a second output terminal each for outputting an output signal, a first transistor having a control terminal connected to the first input terminal and one current terminal connected to the first output terminal, a second transistor having a control terminal connected to the second input terminal and one current terminal connected to the second output terminal, and a second transistor having one end connected to the other current terminal of the first transistor and the other current terminal of the second transistor. a current source having a first output terminal and the other end connected to a first power supply, a first load resistor element connected between the first output terminal and the second power supply, a second load resistor element connected between the second output terminal and the second power supply, and a variable resistor circuit having a first node and a second node, the first node being connected to the other current terminal of the first transistor and the second node being connected to the other current terminal of the second transistor, and variably setting a resistance value between the first node and the second node, the variable resistor circuit having a first control terminal, a first current a first field effect transistor having a first control terminal and a second current terminal, the first current terminal being connected to a first node; a second field effect transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal being connected to a second node and the fourth current terminal being connected to the second current terminal of the first field effect transistor; a first voltage dividing resistor connected between the first node and a first voltage dividing node; a second voltage dividing resistor connected between the first voltage dividing node and a second voltage dividing node; a third voltage dividing resistor connected between the first node and the second node, a first gate connecting resistor, a second gate connecting resistor, a first variable current source connected to a first control terminal of the first field effect transistor via the first gate connecting resistor, a second variable current source connected to a second control terminal of the second field effect transistor via the second gate connecting resistor, a first bias resistor connected between the first variable current source and the first voltage dividing node, and a second bias resistor connected between the second variable current source and the second voltage dividing node.

[0011] According to the above aspect, the currents at one current terminals of the first transistor and the second transistor are modulated by the input signals inputted from the first input terminal and the second input terminal, respectively, to output the output signals from the first output terminal and the second output terminal. At this time, the resistance value of the variable resistor circuit connected between the other current terminal of the first transistor and the other current terminal of the second transistor is set to be variable, thereby making it possible to adjust the voltage gain of the output signal. Here, the variable resistor circuit includes a first field effect transistor and a second field effect transistor, each of whose two current terminals are connected in series between the other current terminal of the first transistor and the other current terminal of the second transistor, and a variable DC voltage component based on the first voltage division node and the second voltage division node can be applied to the control terminal of each field effect transistor. Furthermore, since the first voltage division node and the second voltage division node are connected to the control terminals of the first and second field effect transistors via the first and second bias resistors and the first and second gate connection resistors, the potentials of the control terminals of the first and second field effect transistors can be varied in accordance with the potential fluctuations of the first and third current terminals of the first and second field effect transistors in response to the fluctuations of the input voltage signal in a wide frequency band. As a result, highly linear differential amplification is achieved, and the linearity of the output voltage signal in a wide frequency band can be improved.

[0012] Here, in the above aspect, it is preferable that the variable resistance circuit further includes a first capacitor connected between the first variable current source and the first voltage division node, and a second capacitor connected between the second variable current source and the second voltage division node. With this configuration, the potentials of the control terminals of the first and second field effect transistors can be varied in accordance with the potential fluctuations of the first and third current terminals of the first and second field effect transistors in a wide frequency range including the mid-range (e.g., 100 MHz to 10 GHz). As a result, the linearity of the output voltage signal in a wider frequency band can be improved.

[0013] In the above aspect, it is also preferable that the resistance value of the first voltage dividing resistor is equal to the resistance value of the third voltage dividing resistor, and the resistance value of the second voltage dividing resistor is twice the resistance value of the first voltage dividing resistor. With this configuration, the voltages of the control terminals of the two field effect transistors can be fluctuated by half the magnitude of the potential fluctuations of the first and third current terminals of the field effect transistors. As a result, the linearity of the output voltage signal in a wide frequency band can be further improved.

[0014] Furthermore, in the above aspect, it is also preferable that the first voltage division node is connected to the back gate of the first field effect transistor, and the second voltage division node is connected to the back gate of the second field effect transistor. With this configuration, the influence of the body bias effect occurring in the first and second field effect transistors can be made almost equal. As a result, the linearity of the output voltage signal in a wide frequency band can be stably improved.

[0015] A variable gain differential amplifier circuit according to another aspect of the present disclosure includes a first input terminal and a second input terminal each for receiving an input signal, a first output terminal and a second output terminal each for outputting an output signal, a first transistor having a control terminal connected to the first input terminal and one current terminal connected to the first output terminal, a second transistor having a control terminal connected to the second input terminal and one current terminal connected to the second output terminal, and a current source having one end connected to the other current terminal of the first transistor and the other current terminal of the second transistor and the other end connected to a first power supply. a first load resistor element connected between the first output terminal and the second power supply; a second load resistor element connected between the second output terminal and the second power supply; and a variable resistor circuit having a first node and a second node, the first node being connected to the other current terminal of the first transistor and the second node being connected to the other current terminal of the second transistor, the variable resistor circuit variably setting a resistance value between the first node and the second node, the variable resistor circuits each having two current terminals and a control terminal, and each having two current terminals and a control terminal connected to the other current terminal of the first node and the second node. A first division circuit includes N field effect transistors (N is an integer of 3 or more) from a first field effect transistor to an Nth field effect transistor, in which the first field effect transistor is connected to a first node, the i-th field effect transistor (i is an integer of 2 to N-1) is connected to the i-1th field effect transistor, and the Nth field effect transistor is connected between the N-1th field effect transistor and a second node, and the N field effect transistors are connected in series between the first node and a second node. the N+1 voltage divider resistors from a first voltage divider resistor to an N+1 voltage divider resistor, where the first voltage divider resistor is connected between a first node and a first voltage divider node, the jth (j is an integer between 2 and N) voltage divider resistor is connected between the j-1th voltage divider node and the jth voltage divider node, and the N+1th voltage divider resistor is connected between the Nth voltage divider node and a second node; N variable current sources from a first variable current source to an Nth variable current source, each of which provides a variable current; and N gate connection resistors from a first gate connection resistor to an Nth gate connection resistor;The kth (k is an integer between 1 and N) gate connection resistor includes N gate connection resistors connected between the kth variable current source and the control terminal of the kth field effect transistor, and N bias resistors from the first bias resistor to the Nth bias resistor, and the mth (m is an integer between 1 and N) bias resistor includes N bias resistors connected between the mth voltage division node and the mth variable current source.

[0016] According to the other aspect, the currents at one current terminals of the first transistor and the second transistor are modulated by the input signals inputted from the first input terminal and the second input terminal, respectively, to output the output signals from the first output terminal and the second output terminal. At this time, the resistance value of the variable resistance circuit connected between the other current terminal of the first transistor and the other current terminal of the second transistor is set to be variable, thereby making it possible to adjust the voltage gain of the output signal. Here, the variable resistance circuit includes N field effect transistors, each of whose two current terminals are connected in series between the other current terminal of the first transistor and the other current terminal of the second transistor, and a variable DC voltage component based on the first to Nth voltage division nodes can be applied to the control terminals of each of the N field effect transistors. Furthermore, since the first to Nth voltage division nodes are connected to the control terminals of the first to Nth field effect transistors via bias resistors and gate connection resistors, respectively, the potentials of the control terminals of the first to Nth field effect transistors can be varied in accordance with the potential fluctuations of the current terminals of the first and Nth field effect transistors in response to fluctuations in the input voltage signal over a wide frequency band. As a result, highly linear differential amplification is achieved, and the linearity of the output voltage signal over a wide frequency band can be improved.

[0017] Here, in the above-mentioned other aspect, it is preferable that the variable resistance circuit further includes N capacitors from a first capacitor to an Nth capacitor, where the nth capacitor (n is an integer between 1 and N) is connected between the nth voltage division node and the nth variable current source. With this configuration, the potentials of the control terminals of the first to Nth field effect transistors can be varied in accordance with the potential fluctuations of the current terminals of the first and Nth field effect transistors in a wide frequency range including the mid-range (e.g., 100 MHz to 10 GHz). As a result, the linearity of the output voltage signal in a wider frequency band can be improved.

[0018] In the above other aspect, it is also preferable that the resistance value of the first voltage dividing resistor is equal to the resistance value of the (N+1)th voltage dividing resistor, and the resistance values ​​of each of the second voltage dividing resistor to the Nth voltage dividing resistor are twice the resistance value of the first voltage dividing resistor. With this configuration, the voltages of the control terminals of the N field effect transistors can be varied according to the magnitude of the potential fluctuation of the current terminals of the first and Nth field effect transistors. As a result, the linearity of the output voltage signal in a wide frequency band can be further improved.

[0019] Furthermore, in the above-mentioned other aspect, it is also preferable that, among the N voltage division nodes from the first voltage division node to the Nth voltage division node, the pth voltage division node (p is an integer between 1 and N) is connected to the back gate of the pth field effect transistor. With this configuration, the influence of the body bias effect occurring in the first to Nth field effect transistors can be made substantially equal. As a result, the linearity of the output voltage signal in a wide frequency band can be stably improved.

[0020] Furthermore, in the above one aspect and the other aspect, it is also preferable to further include a first inductor connected between one end of the current source and the first node, and a second inductor connected between one end of the current source and the second node. With this configuration, it is possible to maintain the impedance of the variable resistance circuit at high frequencies. As a result, it is possible to suppress an increase in the voltage gain of the variable gain differential amplifier circuit in the high frequency band and maintain excellent linearity.

[0021] A semiconductor integrated circuit according to another aspect of the present disclosure includes the variable gain differential amplifier circuit according to the one aspect or the other aspect, which realizes highly linear differential amplification and improves the linearity of an output voltage signal over a wide frequency band.

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicated description will be omitted.

[0023] 1 is a block diagram showing a configuration of a driving circuit 200 according to an embodiment. The driving circuit 200 is built into an optical communication device such as an optical transmission module, and is, for example, a semiconductor integrated circuit (IC) with a size of 2 mm×4 mm manufactured by a SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process, and amplifies and outputs an input voltage signal. The driving circuit 200 has a pair of input terminals 130a, 130b, a pair of output terminals 131a, 131b, a variable gain differential amplifier circuit 100, and an output circuit 110.

[0024] The input terminals 130a and 130b receive an input of a differential signal consisting of two voltage signals having the same amplitude but inverted phases. The variable gain differential amplifier circuit 100 amplifies the input differential signal and sends it to the output circuit 110. The output circuit 110 is a differential amplifier circuit that further amplifies the differential signal sent from the variable gain differential amplifier circuit 100 and outputs it to the outside of the drive circuit 200. The output circuit 110 is configured by being cascade-connected to the variable gain differential amplifier circuit 100.

[0025] The circuit configuration of the drive circuit 200 may be modified as appropriate, the output circuit 110 may be omitted, or various other circuits may be added. For example, a differential amplifier for signal amplification may be inserted on the input side or output side of the variable gain differential amplifier circuit 100. An automatic gain control circuit for controlling the gain of the variable gain differential amplifier circuit 100 may be mounted. In addition, the signal transmission path (channel) is not limited to a single configuration, and multiple channels (e.g., four channels) may be arranged in parallel.

[0026] Next, the configuration of the variable gain differential amplifier circuit 100 according to this embodiment will be described with reference to FIG.

[0027] Fig. 2 is a circuit diagram showing the configuration of the variable gain differential amplifier circuit 100 of Fig. 1. The variable gain differential amplifier circuit 100 is a differential amplifier circuit that amplifies an input voltage signal, which is an input differential signal, to generate an output voltage signal, which is a differential signal, and is an integrated circuit formed on a Si substrate using a SiGe BiCMOS process. The maximum power supply voltage of the integrated circuit on which the variable gain differential amplifier circuit 100 is mounted is, for example, 3.3 V. The two input voltage signals are, for example, 32QAM signals modulated by quadrature amplitude modulation (QAM) with 32 signal points, and the modulation speed of these signals is 100 GBaud.

[0028] The variable gain differential amplifier circuit 100 includes bipolar transistors 10a, 10b, 11a, and 11b, resistance elements (first and second load resistance elements) 21a and 21b, current sources 60a and 60b, a degeneration circuit (variable resistance circuit) 35, input terminals (first and second input terminals) 91a and 91b to which an input voltage signal is input, output terminals (first and second output terminals) 92a and 92b that output an output voltage signal, ground terminals 70a and 70b, a bias supply terminal 93, and power supply terminals 80a, 80b, 80c, and 80d.

[0029] The components constituting the variable gain differential amplifier circuit 100 will be described below.

[0030] In the bipolar transistors (first and second transistors) 10a and 10b, the bases (control terminals) are connected to the input terminals 91a and 91b, the collectors (one current terminal) are connected to the emitters of the bipolar transistors 11a and 11b, and the emitters (the other current terminals) are connected to one end of the current sources 60a and 60b via the resistor elements 20a and 20b of the degeneration circuit 35. The bipolar transistors 10a and 10b modulate the collector currents by the input voltage signal. The bipolar transistors 10a and 10b may be, for example, NPN-type heterojunction bipolar transistors (HBT: Heterojunction Bipolar Transistors). The bipolar transistors 10a and 10b may be, for example, n-type MOS (Metal Oxide Semiconductor) transistors. In that case, in the MOS transistor, the gate functions as the control terminal, the drain functions as one current terminal, and the source functions as the other current terminal.

[0031] In the bipolar transistors 11a and 11b, the bases are connected to the bias supply terminal 93, the emitters are connected to the collectors of the bipolar transistors 10a and 10b, and the collectors are connected to a pair of output terminals 92a and 92b. These bipolar transistors 11a and 11b are cascode transistors whose bases are applied with a DC voltage supplied to the bias supply terminal 93. With this configuration, the voltage amplitude at the collectors of the bipolar transistors 10a and 10b is suppressed, and the mirror capacitance of the bipolar transistors 10a and 10b is reduced, so that the variable gain differential amplifier circuit 100 can have a wide bandwidth. In addition, the presence of the bipolar transistors 11a and 11b increases the output resistance of the variable gain differential amplifier circuit 100, so that the voltage gain of the variable gain differential amplifier circuit 100 can be improved. The bipolar transistors 11a and 11b may be replaced with, for example, n-type MOS transistors. Furthermore, if the variable gain differential amplifier circuit 100 has a wide band, the bipolar transistors 11a and 11b may be omitted.

[0032] In the resistance elements 21a and 21b, one end is connected to the output terminals 92a and 92b, and the other end is connected to the power supply terminals 80c and 80d having a second power supply potential (for example, 3.3V). These resistance elements 21a and 21b are loads for converting the collector current modulated by the bipolar transistors 10a and 10b into an output voltage signal. For example, n-type polysilicon resistors can be used for the resistance elements 21a and 21b. In this embodiment, the load is only the resistance elements 21a and 21b, but a shunt inductor connected in series to the resistance elements 21a and 21b may be included in the load. By including the shunt inductor, it is possible to suppress a decrease in load impedance at high frequencies, and it is possible to widen the bandwidth of the variable gain differential amplifier circuit 100.

[0033] The current sources 60a and 60b have one end connected to the emitters of the bipolar transistors 10a and 10b via the resistive elements 20a and 20b of the degeneration circuit 35, and the other end connected to ground terminals 70a and 70b (first power supply) having a ground potential (first power supply potential) of 0V. For example, a current mirror circuit made of bipolar transistors or MOS transistors is used as the current sources 60a and 60b. Also, the current sources 60a and 60b may have a configuration including only resistors without transistors, or a configuration including only resistors and inductors. Furthermore, the current sources 60a and 60b may be changed to a single current source configuration.

[0034] The degeneration circuit 35 is a circuit that variably sets the emitter-to-emitter resistance of the bipolar transistors 10a, 10b to control the voltage gain of the variable gain differential amplifier circuit 100. In other words, the voltage gain of the variable gain differential amplifier circuit 100 is mainly determined by the ratio between the emitter resistance of the bipolar transistors 10a, 10b set by the degeneration circuit 35 and the collector resistance of the bipolar transistors 10a, 10b determined by the resistor elements 21a, 21b. The degeneration circuit 35 has a node (first node) A connected to the emitter of the bipolar transistor 10a and a node (second node) C connected to the emitter of the bipolar transistor 10b, and includes MOS transistors (first and second field effect transistors) 30a and 30b connected in series between the nodes A and C, a series resistance circuit 22 connected between the nodes A and C, current sources (first and second variable current sources) 61a and 61b that generate variable currents, resistance elements 20a and 20b, resistance elements (first and second gate connection resistances) 24a and 24b, resistance elements (first and second bias resistances) 23a and 23b, and capacitors (first and second capacitors) 45a and 45b. The components of the degeneration circuit 35 will be described in detail below.

[0035] The resistor elements 20a and 20b are connected between the emitters of the bipolar transistors 10a and 10b and one end of the current sources 60a and 60b, respectively. These resistor elements 20a and 20b are elements for enabling the linear input range of the variable gain differential amplifier circuit 100 to be expanded, and the resistance value is set to, for example, 100Ω. 。

[0036] In the MOS transistors 30a and 30b, the sources (current terminals) are connected to the nodes A and C, respectively, and the drains (current terminals) are connected to each other at a node B. These MOS transistors 30a and 30b are preferably of the same type and of the same size. The MOS transistors 30a and 30b are, for example, n-type MOS transistors. These MOS transistors 30a and 30b include parasitic capacitances 40a and 40d between the gate and source, and parasitic capacitances 40b and 40c between the gate and drain, respectively. It is preferable that these parasitic capacitances 40a, 40b, 40c, and 40d are approximately equal, and therefore it is preferable to set the layout of the MOS transistors 30a and 30b symmetrically on the source side and the drain side. When the parasitic capacitances 40a, 40d are different from the parasitic capacitances 40b, 40c, it is preferable to add a capacitor and set the gate-source capacitances of the MOS transistors 30a, 30b and the gate-drain capacitances of the MOS transistors 30a, 30b to be approximately equal to each other.

[0037] The series resistance circuit 22 is a circuit in which three resistance elements (first to third voltage dividing resistances) 22a, 22b, and 22c are connected in series between a node A and a node C. The series resistance circuit 22 divides the voltage between the node A and the node C into a node (connection point, first voltage dividing node) D between the resistance elements 22a and 22b, and a node (connection point, second voltage dividing node) E between the resistance elements 22b and 22c, to generate two set voltages (first and second set voltages) V1 and V2. Specifically, the resistance element 22a has one end connected to the node A and the other end connected to the node D. The resistance element 22b has one end connected to the node D and the other end connected to the node E. The resistance element 22c has one end connected to the node E and the other end connected to the node C. The resistance values ​​of the resistor elements 22a, 22b, and 22c are preferably set to be approximately equal in a ratio of 1:2:1, for example, 1 kΩ, 2 kΩ, and 1 kΩ, respectively. In addition, the nodes D and E of the series resistor circuit 22 are connected to the back gates of the MOS transistors 30a and 30b, respectively. This makes it possible to make the influence of the substrate bias effect occurring in the MOS transistors 30a and 30b approximately equal.

[0038] The resistive elements 24a and 24b are connected between the gate connection nodes F and G and the gates of the MOS transistors 30a and 30b, respectively. These resistive elements 24a and 24b are elements for isolating the parasitic capacitance at the nodes F and G from the MOS transistors 30a and 30b. The presence of the resistive elements 24a and 24b reduces the parasitic capacitance when the gates are viewed from the sources and drains of the MOS transistors 30a and 30b. It is preferable that the resistance values ​​of the resistive elements 24a and 24b are set to be approximately equal, for example, 5 kΩ.

[0039] The resistive element 23a and the capacitor 45a are connected in parallel between the node F and the node D. The resistive element 23b and the capacitor 45b are connected in parallel between the node G and the node E. These parallel circuits form a voltage transmission path for matching the voltage fluctuation at the gates of the MOS transistors 30a and 30b with the voltage fluctuation at the nodes D and E in the low frequency band (for example, 100 MHz or less) and the mid frequency band (for example, 100 MHz to 10 GHz). The resistance value of the resistive elements 23a and 23b is set to, for example, 15 kΩ, and the capacitance of the capacitors 45a and 45b is set to, for example, 1 pF.

[0040] The current sources 61a and 61b are connected between the power supply terminals 80a and 80b having the second power supply potential and the nodes F and G, respectively, and generate variable currents flowing from the output terminals toward the nodes F and G. The currents output by the current sources 61a and 61b flow into the current sources 60a and 60b via the resistance elements 23a and 23b and the resistance elements 22a, 22b and 22c. This allows DC voltage components based on the back gate voltages of the MOS transistors 30a and 30b to be applied to the gates of the MOS transistors 30a and 30b. Since the output resistance of the current sources 61a and 61b is high, the voltage fluctuations of the gate and back gate of the MOS transistors 30a and 30b can be made almost equal, as described later. The current values ​​output by these current sources 61a and 61b are set to, for example, 50 μA. The current sources 61a and 61b are formed, for example, by current mirror circuits including MOS transistors, and it is preferable that the current values ​​output by these current sources are set to be almost equal to each other.

[0041] Next, the operation of the variable gain differential amplifier circuit 100 will be described.

[0042] When an input voltage signal is input to input terminals 91a and 91b, the emitter potentials of bipolar transistors 10a and 10b fluctuate. These emitter potentials follow the base potential, so the amount of fluctuation depends on the input amplitude. When the potential of input terminal 91a drops, the emitter potential of bipolar transistor 10a drops. Similarly, when the potential of input terminal 91b rises, the emitter potential of bipolar transistor 10b rises. As a result, the source potential of MOS transistor 30a (potential at node A) drops, and the source potential of MOS transistor 30b (potential at node C) rises.

[0043] The gates of the MOS transistors 30a and 30b fluctuate in the same manner over a wide range of frequencies. First, in a high frequency band (e.g., 10 GHz or higher), the gate potentials of the MOS transistors 30a and 30b fluctuate due to the voltage division action of the parasitic capacitances 40a, 40b, 40c, and 40d. In this embodiment, since the parasitic capacitances 40a, 40b, 40c, and 40d are approximately equal to each other, if the voltage fluctuation at node A is Va and the voltage fluctuation at node C is Vc, the fluctuation in the gate potential of the MOS transistor 30a is Va+(1 / 4)(Vc-Va)=(3 / 4)Va+(1 / 4)Vc The fluctuation of the gate potential of the MOS transistor 30b is calculated as follows: Va+(3 / 4)(Vc-Va)=(1 / 4)Va+(3 / 4)Vc In this embodiment, the variable gain differential amplifier circuit 100 amplifies a differential signal, so the voltage fluctuation Va=-Vc. In this case, the fluctuation in the gate potential of the MOS transistor 30a is (1 / 2)Va, and the fluctuation in the gate potential of the MOS transistor 30b is -(1 / 2)Va, and these fluctuations are equal in amplitude and opposite in phase.

[0044] In the above-mentioned low and mid-frequency bands, the fluctuations in the gate potentials of the MOS transistors 30a and 30b are approximately equal to the fluctuations in the potentials of the nodes D and E, respectively. In this embodiment, since the resistance ratio of the resistive elements 22a, 22b, and 22c is 1:2:1, the fluctuation in the potential of the node D is Va+(1 / 4)(Vc-Va)=(3 / 4)Va+(1 / 4)Vc =(1 / 2)Va The voltage fluctuation at node E is Va+(3 / 4)(Vc-Va)=(1 / 4)Va+(3 / 4)Vc =-(1 / 2)Va In the low range, the potential fluctuations become approximately equal between the gates of the MOS transistors 30a and 30b and the nodes D and E via the resistor elements 23a, 23b, 24a, and 24b. In the medium range, the potential fluctuations become approximately equal between the gates of the MOS transistors 30a and 30b and the nodes D and E via the capacitors 45a and 45b and the resistor elements 24a and 24b.

[0045] FIG. 3 shows the frequency dependence of the small signal gain of the gate with respect to the source (node ​​A) of the MOS transistor 30a, where the solid line G1 shows the frequency dependence when the capacitors 45a and 45b are present, and the dotted line G2 shows the frequency dependence when the capacitors 45a and 45b are not present. As shown by these characteristics, when the capacitors 45a and 45b are present, the small signal gain is about -6 dB over the range from 1 kHz to 50 GHz, and the potential fluctuation of the gate of the MOS transistor 30a is about half the potential fluctuation of the source. On the other hand, when the capacitors 45a and 45b are not present, the small signal gain is small in the range from 100 MHz to 10 GHz, and the potential fluctuation of the gate of the MOS transistor 30a is smaller than half the potential fluctuation of the source. From these characteristics, it can be understood that the potential fluctuation of the gate of the MOS transistors 30a and 30b in the range from 100 MHz to 10 GHz is due to the capacitors 45a and 45b. That is, in the low frequency band (100 MHz or less), the resistance elements 22a, 22b, 22c and the resistance elements 23a, 23b, 24a, 24b are used, in the mid frequency band (100 MHz to 10 GHz), the resistance elements 22a, 22b, 22c, the capacitors 45a, 45b, and the resistance elements 24a, 24b are used, and in the high frequency band (10 GHz or more), the parasitic capacitances 40a, 40b, 40c, 40d are used, so that the fluctuation in the gate potential of each of the MOS transistors 30a, 30b is set to about half of the fluctuation in the source potential (potentials of the nodes A and C). Thus, in a wide frequency band, the fluctuation in the gate potential of the MOS transistors 30a, 30b is about half of the fluctuation in the source potential.

[0046] FIG. 4 shows the configuration of an optical transmission module 400 according to this embodiment. The optical transmission module 400 includes the above-mentioned drive circuit 200 and optical modulation device 300. The drive circuit 200 amplifies and outputs, for example, four input differential signals, and the optical modulation device 300 generates an optical signal modulated based on the four differential signals output from the drive circuit 200, and outputs, for example, one optical signal modulated by polarization multiplexing QAM. The optical transmission module 400 is, for example, an optical module in which the drive circuit 200 and the optical modulation device 300 are integrated and mounted in a ceramic package, and has an external size of, for example, 30 mm×15 mm×5 mm. According to the optical transmission module 400 with the above configuration, the drive circuit 200 equipped with the variable gain differential amplifier circuit 100 is used, so that a small-area optical transmission module capable of wideband modulation with excellent linearity is realized.

[0047] 5 shows the configuration of an optical transmitting / receiving module 500 according to this embodiment. The optical transmitting / receiving module 500 includes a receiving circuit 600 and an optical receiving device 700 in addition to the driving circuit 200 and the optical modulation device 300 described above. The optical receiving device 700 receives an optical signal input from the outside via an optical transmission line, and separates and outputs four signals (receiving currents) from, for example, a polarization multiplexed QAM modulated optical signal. The receiving circuit 600 converts the four receiving currents into voltages, amplifies them, and outputs them. According to the optical transmitting / receiving module 500 with the above configuration, the driving circuit 200 equipped with the variable gain differential amplifier circuit 100 is used, so that a small-area optical transmitting / receiving module capable of wideband modulation with excellent linearity is realized.

[0048] According to the variable gain differential amplifier circuit 100 of the present embodiment described above, the collector currents of the bipolar transistors 10a and 10b are modulated by the input voltage signals, which are differential signals inputted from the input terminals 91a and 91b, and output voltage signals, which are differential signals, are outputted from the output terminals 92a and 92b. At this time, the resistance value of the degeneration circuit 35 connected between the emitters of the bipolar transistors 10a and 10b is set to be variable, so that the voltage gain of the two output voltage signals can be adjusted. Here, the degeneration circuit 35 includes MOS transistors 30a and 30b connected in series between the emitters of the bipolar transistors 10a and 10b, and variable DC voltage components based on nodes D and E can be applied to the gates of the MOS transistors 30a and 30b, respectively. Furthermore, since the nodes D and E are connected to the gates of the MOS transistors 30a and 30b via the resistive elements 23a, 23b, 24a and 24b, the gate potentials of the MOS transistors 30a and 30b can be varied in accordance with the fluctuations in the source potentials of the MOS transistors 30a and 30b, which correspond to the fluctuations in the input voltage signal over a wide frequency band. As a result, highly linear differential amplification is achieved, and the linearity of the output voltage signal over a wide frequency band can be improved.

[0049] In this embodiment, the degeneration circuit 35 further includes capacitors 45a and 45b connected between the output terminals of the current sources 61a and 61b and the nodes D and E, respectively. With this configuration, the gate potentials of the MOS transistors 30a and 30b can be varied in accordance with the fluctuation of the source potentials of the MOS transistors 30a and 30b in a wide frequency range including the mid-range. As a result, the linearity of the output voltage signal can be improved in a wider frequency range.

[0050] In the present embodiment, the degeneration circuit 35 includes, as the series resistance circuit 22, a resistance element 22a connected between the node A and the node D, a resistance element 22b connected between the node D and the node E, and a resistance element 22c connected between the node E and the node C. The resistance elements 22a and 22c have the same resistance value, and the resistance value of the resistance element 22b is twice as high as the resistance values ​​of the resistance elements 22a and 22c. The resistance values ​​being equal may be different resistance values ​​within the range of expected manufacturing variations, and are not limited to being resistance values ​​that are completely equal to each other. The resistance value being twice as high may be different from the resistance value twice as high as the resistance value within the range of expected manufacturing variations, and is not limited to being resistance values ​​that are completely equal to the resistance value twice as high as the resistance value. With this configuration, the gate voltages of the two MOS transistors 30a and 30b can be fluctuated by half the magnitude of the fluctuation of the source potentials of the MOS transistors 30a and 30b. As a result, the linearity of the output voltage signal over a wide frequency band can be further improved.

[0051] Furthermore, in this embodiment, the nodes D and E of the series resistor circuit 22 are connected to the back gates of the MOS transistors 30a and 30b, respectively. With this configuration, the influence of the substrate bias effect occurring in the MOS transistors 30a and 30b can be made almost equal. As a result, the linearity of the output voltage signal in a wide frequency band can be improved more stably. Note that the nodes D and E do not have to be connected to the back gates of the MOS transistors 30a and 30b, respectively.

[0052] Moreover, the driving circuit 200 according to this embodiment includes the variable gain differential amplifier circuit 100. Therefore, the driving circuit 200 enables signal amplification with excellent linearity over a wide frequency band.

[0053] Here, the effects of this embodiment will be explained in comparison with the conventional example.

[0054] 12 is a circuit diagram showing the configuration of a conventional variable gain differential amplifier circuit 900. The variable gain differential amplifier circuit 900 includes bipolar transistors 910a, 910b, 911a, and 911b, resistor elements 921a and 921b, a degeneration circuit 935, current sources 960a and 960b, input terminals 991a and 991b, output terminals 992a and 992b, ground terminals 970a and 970b, bias supply terminals 993 and 994, and power supply terminals 980a and 980b. The degeneration circuit 935 includes a MOS transistor 930 and resistor elements 920a and 920b.

[0055] The conventional variable gain differential amplifier circuit 900 differs from the variable gain differential amplifier circuit 100 in the configuration of the degeneration circuit 935. That is, the degeneration circuit 935 functions to change the source-drain resistance of the MOS transistor 930 according to a DC voltage supplied from a bias supply terminal 994 to the gate of the MOS transistor 930. This makes it possible to control the voltage gain of the variable gain differential amplifier circuit 900. The size of the MOS transistor 930 is set to half the size of the MOS transistors 30a and 30b. With this configuration, the minimum value of the resistance between nodes A' and C' of the variable gain differential amplifier circuit 900 can be made equal to the minimum value of the resistance between nodes A and C of the variable gain differential amplifier circuit 100.

[0056] 6 is a graph showing the change in output amplitude and the change in total harmonic distortion (THD) of the output voltage signal when the gain of the variable gain differential amplifier circuits 100 and 900 is changed, where (A) shows the change in output amplitude and (B) shows the change in THD. In these graphs, the horizontal axis indicates the magnitude of gain (larger on the right), the vertical axis indicates the magnitude of output amplitude or THD (larger on the upper side), the solid line indicates the characteristics of the variable gain differential amplifier circuit 100, and the dotted line indicates the characteristics of the variable gain differential amplifier circuit 900. As shown in these graphs, the variable gain differential amplifier circuit 100 and the variable gain differential amplifier circuit 900 obtain almost the same output amplitude. On the other hand, at the gain indicated by the arrow, the THD of the variable gain differential amplifier circuit 900 increases, whereas the THD of the variable gain differential amplifier circuit 100 is kept small.

[0057] The signal waveforms at each terminal at the gains indicated by the arrows in FIG. 6 are shown in FIG. 7 and FIG.

[0058] 13 shows, as signal waveforms of the variable gain differential amplifier circuit 900, voltage waveforms C1 and C2 at the input terminals 991a and 991b, a voltage waveform C3 at the source (node ​​A') of the MOS transistor 930, a voltage waveform C4 at the drain (node ​​C') of the MOS transistor 930, a voltage waveform C5 at the gate of the MOS transistor 930, a waveform C6 of the gate-source voltage of the MOS transistor 930, a waveform C7 of the gate-drain voltage of the MOS transistor 930, a waveform C8 of a current flowing from node A' to node C', and a waveform C9 of a current flowing from node C' to node A'. Thus, in the conventional example, the gate voltage of the MOS transistor 930 rises (waveform C5), and the gate-source voltage (waveform C6) and gate-drain voltage (waveform C7) of the transistor become close to the threshold voltage (e.g., 250 mV). In this state, when input voltage signals (waveforms C1, C2) are applied to the input terminals 991a, 991b, the source-drain voltage of the MOS transistor 930 fluctuates (waveforms C3, C4). This causes the gate-source voltage (waveform C6) and gate-drain voltage (waveform C7) of the MOS transistor 930 to fluctuate, and when these voltages rise, they exceed the threshold voltage. As a result, currents flow between the drain and source of the MOS transistor 930 (waveforms C8, C9). These currents have triangular waveforms and have large THD (e.g., 9%). Therefore, as shown in FIG. 6, the THD in the output waveform becomes large.

[0059] FIG. 7 shows, as signal waveforms of the variable gain differential amplifier circuit 100, voltage waveforms N1 and N2 at input terminals 91a and 91b, a voltage waveform N3 at the source (node ​​A) of MOS transistor 30a, a voltage waveform N4 at the source (node ​​C) of MOS transistor 30b, a voltage waveform N5 at the drain (node ​​B) of MOS transistors 30a and 30b, a voltage waveform N6 at the gate of MOS transistor 30a, a voltage waveform N7 at the gate of MOS transistor 30b, a waveform N8 of the gate-source voltage of MOS transistor 30a, a waveform N9 of the gate-drain voltage of MOS transistor 30a, a waveform N10 of a current flowing from node A to node C, and a waveform N11 of a current flowing from node C to node A. Thus, in the embodiment, the gate voltages of the MOS transistors 30a and 30b rise (waveforms N6 and N7), and the gate-source voltage (waveform N8) and the gate-drain voltage (waveform N9) of the MOS transistor 30a become close to the threshold voltage (for example, 250 mV). In this state, when an input voltage signal (waveforms N1 and N2) is applied to the input terminals 91a and 91b, the source voltages of the MOS transistors 30a and 30b fluctuate (waveforms N3 and N4), and the gate voltages of the MOS transistors 30a and 30b also fluctuate (waveforms N6 and N7). As described above, these fluctuations are about half of the fluctuations of the source voltages of the MOS transistors 30a and 30b. As a result, the fluctuations of the gate-source voltage (waveform N8) and the gate-drain voltage (waveform N9) of the MOS transistor 30a are about half of those of the variable gain differential amplifier circuit 900. The same applies to the fluctuations of the gate-source voltage and the gate-drain voltage of the MOS transistor 30b. As a result, the current (waveforms N10 and N11) flowing between nodes A and C is smaller than that of the variable gain differential amplifier circuit 900, and the THD is also smaller (for example, 3.5%). Therefore, as shown in FIG. 6, the THD in the output waveform is kept small.

[0060] 8 is a graph showing the frequency dependence of the change in output amplitude and the change in THD with respect to the gain of the variable gain differential amplifier circuit 100, where (A) shows the change in output amplitude and (B) shows the change in THD. In these graphs, the horizontal axis shows the magnitude of gain (larger on the right) and the vertical axis shows the magnitude of output amplitude or THD (larger on the upper side), and the changes are shown at frequencies of 1 MHz, 1 GHz, and 10 GHz. As shown in these graphs, it can be seen that the frequency dependence of the output amplitude and THD of the variable gain differential amplifier circuit 100 is low. This is because, as described above, in a wide frequency band, the potential fluctuation of the gates of the MOS transistors 30a and 30b is about half the potential fluctuation of the sources.

[0061] As described above, according to this embodiment, it is possible to provide a variable gain differential amplifier circuit having excellent linearity over a wide frequency band.

[0062] In the prior art described in JP-A-8-256039, JP-A-11-168334, JP-A-2004-304775, etc., two MOS transistors are connected in series between the sources or emitters of two transistors that receive an input voltage signal. Even with this configuration, it is possible to suppress THD in high frequencies (e.g., 10 GHz). However, in this configuration, the gate voltages of the two MOS transistors match and become a constant potential in low to mid frequencies, so THD cannot be suppressed. On the other hand, in this embodiment, the fluctuation of the gate voltage can be made almost constant in the range from low to high frequencies, so it is possible to suppress THD low over a wide range of frequencies.

[0063] In this embodiment, node D is connected to the back gate of MOS transistor 30a, and node E is connected to the back gate of MOS transistor 30b. However, since the mutual conductance at the back gate is generally smaller than the mutual conductance at the gate, when the influence of the substrate bias effect is small, the back gates of MOS transistors 30a and 30b may be set to independent fixed potentials.

[0064] The configuration of the variable gain differential amplifier circuit 100 may be changed to the configuration shown in Fig. 9. That is, the resistor elements 20a and 20b may be configured to be connected in series between one end of the current source 60a and one end of the current source 60b. Even with such a configuration, the emitter-to-emitter resistance of the bipolar transistors 10a and 10b is maintained. This eliminates the drop in DC voltage caused by the resistor elements 20a and 20b, and allows the bias voltage of the current sources 60a and 60b to be increased.

[0065] Also, a configuration in which the resistive elements 20a and 20b are omitted may be adopted by adjusting the resistance values ​​of the resistive elements 22a, 22b, and 22c. For example, in the above-mentioned embodiment, the resistive elements 22a, 22b, and 22c are set to 1 kΩ, 2 kΩ, and 1 kΩ, respectively, and the resistive elements 20a and 20b are set to 100 Ω, respectively, but the resistive elements 20a and 20b can be omitted by setting the resistive elements 22a, 22b, and 22c to 50 Ω, 100 Ω, and 50 Ω, respectively.

[0066] Although the principles of the present disclosure have been illustrated and described in the above preferred embodiments, it will be recognized by those skilled in the art that the present disclosure may be modified in arrangement and detail without departing from such principles. The present disclosure is not limited to the specific configurations disclosed in the present embodiments. Accordingly, we claim all modifications and changes that come within the scope and spirit of the following claims.

[0067] 10 shows the configuration of a variable gain differential amplifier circuit 100A according to a modified example. The configuration of this variable gain differential amplifier circuit 100A differs from the above-described embodiment in that inductors 50a and 50b are newly added.

[0068] That is, the variable gain differential amplifier circuit 100A is newly provided with an inductor (first inductor) 50a connected between one end of the current source 60a and the node A, and an inductor (second inductor) 50b connected between one end of the current source 60b and the node C. These inductors 50a, 50b are elements for compensating for high-frequency loss in the degeneration circuit 35. As the inductors 50a, 50b, spiral inductors having wiring laid out in a spiral shape can be used.

[0069] In the above-described embodiment, the linearity can be improved by connecting two MOS transistors 30a, 30b in series between the emitters of the bipolar transistors 10a, 10b. However, in order to maintain the resistance between the node A and the node C, it is necessary to double the size of the MOS transistors 30a, 30b compared to the case where one MOS transistor is connected. In this case, the parasitic capacitance between the source and ground at the nodes A, C increases, so that the impedance of the degeneration circuit 35 decreases at high frequencies, and the voltage gain of the variable gain differential amplifier circuit 100A increases, increasing the THD, which may result in degradation of the linearity. On the other hand, according to this modification, since the inductors 50a, 50b are included, the impedance of the degeneration circuit 35 can be maintained at high frequencies. As a result, it is possible to suppress the increase in the voltage gain of the variable gain differential amplifier circuit 100A in the high frequency band and maintain excellent linearity.

[0070] 11 shows the configuration of a variable gain differential amplifier circuit 100B according to another modified example. The variable gain differential amplifier circuit 100B differs from the variable gain differential amplifier circuit 100A according to the modified example described above in terms of the configuration of the degeneration circuit 35.

[0071] That is, two current terminals (source and drain) of the first to Nth (N is an integer of 3 or more) MOS transistors 30(1) to 30(N) are connected in series between the node A and the node C. Specifically, the source of the MOS transistor 30(1) is connected to the node A, the MOS transistors 30(i) (i is an integer of 2 to N-1) and the MOS transistor 30(i-1) are connected in series by the current terminals, and the MOS transistor (N) is connected between the MOS transistor (N-1) and the node C. These MOS transistors 30(1) to 30(N) are preferably of the same type and size, and the gate-source capacitance and the gate-drain capacitance of the MOS transistors 30(1) to 30(N) are preferably approximately equal. Such a configuration can be regarded as 2×N capacitors having the same capacitance connected in series. Therefore, in the high frequency range, the absolute values ​​of the gate-source voltage and the gate-drain voltage of the MOS transistors 30(1) to 30(N) are |Va| / N. Furthermore, when m is an integer between 1 and N, the gate voltage of the MOS transistor 30(m) is expressed as follows: Va-(2m-1)Va / N It becomes.

[0072] Furthermore, resistive elements (gate-connected resistors) 24(1) to 24(N) are connected to the gates of the MOS transistors 30(1) to 30(N), respectively, and are connected to current sources 61(1) to 61(N) that generate variable currents via the resistive elements 24(1) to 24(N). These N current sources 61(1) to 61(N) are connected between power supply terminals 80(1) to 81(N) having a second power supply potential and the resistive elements 24(1) to 24(N), respectively.

[0073] Furthermore, a series resistance circuit 22 in which 1st to N+1th resistance elements (voltage dividing resistances) 22(1) to 22(N+1) are connected in series is provided between the node A and the node C. This series resistance circuit 22 divides the voltage between the node A and the node C to generate 1st to Nth set voltages at a first voltage dividing node (connection point) between the resistance elements 22(1) and 22(2), a second voltage dividing node between the resistance elements 22(2) and 22(3), ..., an Nth voltage dividing node between the resistance elements 22(N) and 22(N+1), respectively. Specifically, one end of the resistance element 22(1) is connected to the node A, and the other end is connected to the first voltage dividing node. Resistance element 22(j) (j is an integer greater than or equal to 2 and less than or equal to N) has one end connected to the (j-1)th voltage division node and the other end connected to the jth voltage division node, and resistance element 22(N+1) has one end connected to the Nth voltage division node and the other end connected to node C.

[0074] Further, the first voltage division node between the resistance elements 22(1) and 22(2), the second voltage division node between the resistance elements 22(2) and 22(3), ..., the Nth voltage division node between the resistance elements 22(N) and 22(N+1) are connected to the back gates of the MOS transistors 30(1) to 30(N). Here, it is preferable that the resistance values ​​of the resistance elements 22(2) to 22(N) are equal to each other, the resistance values ​​of the resistance elements 22(1) and 22(N+1) are equal to each other, and the resistance values ​​of the resistance elements 22(2) to 22(N) are set to about twice the resistance values ​​of the resistance elements 22(1) and 22(N+1). In other words, it is preferable that the resistance ratio of the resistance elements 22(1) to 22(N+1) is 1:2: ...:2:1. As a result, the back gate voltage of the MOS transistor 30(m) is Va-(2m-1)Va / N It is set as follows.

[0075] In addition, parallel circuits including resistance elements (bias resistors) 23(1) to 23(N) and capacitors 45(1) to 45(N) are connected between the first to Nth voltage dividing nodes of the series resistance circuit 22 and the gates (output terminals of the current sources 61(1) to 61(N)) of the MOS transistors 30(1) to 30(N), respectively. Due to the presence of these parallel circuits, the gate voltages of the MOS transistors 30(1) to 3(N) become approximately equal to the back gate voltage in the low and mid ranges, and the gate voltage of the MOS transistor 30(m) becomes Va-(2m-1)Va / N is set to.

[0076] In the variable gain differential amplifier circuit 100B according to this modified example, the gate voltage of the MOS transistor 30(m) is set to a value determined by Va-(2m-1)Va / N over a wide frequency band, making it possible to realize a variable gain differential amplifier circuit with excellent linearity over a wide frequency band.

[0077] In this modification, the larger the number N of MOS transistor stages, the smaller the gate-source voltage and gate-drain voltage of the MOS transistors 30(1)-30(N), making it possible to suppress an increase in THD. On the other hand, in order to make the resistance between node A and node C equal to that when N=1, the size of the MOS transistors 30(1)-30(N) needs to be N times larger, which tends to increase the parasitic capacitance at nodes A and C. For this reason, it is preferable to include inductors 50a and 50b in this modification. [Explanation of symbols]

[0078] 10a, 10b...Bipolar transistors (first and second transistors) 11a, 11b, 910a, 910b, 911a, 911b...Bipolar transistors 20a, 20b, 920a, 920b, 921a, 921b...resistance elements 21a, 21b...resistance elements (first and second load resistance elements) 22a, 22b, 22c, 22(1) to 22(N+1) ... Resistance elements (voltage dividing resistors) 22...Series resistor circuit 23a, 23b, 23(1) to 23(N)...resistance elements (bias resistors) 24a, 24b, 24(1) to 24(N)...resistance elements (gate connection resistors) 30a, 30b, 30(1) to 30(N)...MOS transistors (field effect transistors) 930...MOS transistor 35…Degeneration circuit (variable resistor circuit) 935…Degeneration circuit 45a, 45b, 45(1) to 45(N)... Capacitors 50a...inductor (first inductor) 50b...inductor (second inductor) 60a,60b,960a,960b…Current source 61a, 61b, 61(1) to 61(N)...Current source (variable current source) 70a, 70b...Ground terminals (first power source) 970a,970b…Ground terminal 80a, 80b, 80c, 80d, 80(1) to 80(N)...Power supply terminals (second power supply) 980a, 980b...Power terminals 91a, 91b...input terminals (first and second input terminals) 92a, 92b...output terminals (first and second output terminals) 100, 100A, 100B, 900... Variable gain differential amplifier circuit 130a, 130b, 991a, 991b...Input terminals 131a, 131b, 992a, 992b...Output terminals A…node (first node) C...node (second node) D…node (first voltage divider node) E…node (second voltage divider node) A', B, C', F, G...nodes 93,993,994...Bias supply terminal 110...Output circuit 200...Drive circuit 300...Optical modulation device 400...Optical transmitter module 500...Optical transceiver module 600…Receiver circuit 700…Light receiving device

Claims

1. a first input terminal and a second input terminal each for receiving an input signal; a first output terminal and a second output terminal each for outputting an output signal; a first transistor having a control terminal connected to the first input terminal and one current terminal connected to the first output terminal; a second transistor having a control terminal connected to the second input terminal and one current terminal connected to the second output terminal; a current source having one end and another end, the other end being connected to a first power supply; a first load resistive element connected between the first output terminal and a second power supply; a second load resistive element connected between the second output terminal and the second power supply; a variable resistance circuit having a first node and a second node, the first node being connected to the other current terminal of the first transistor and the second node being connected to the other current terminal of the second transistor, and variably setting a resistance value between the first node and the second node; Equipped with The variable resistance circuit includes: a first field effect transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal connected to the first node; a second field effect transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal being connected to the second node and the fourth current terminal being connected to the second current terminal of the first field effect transistor; a first voltage dividing resistor connected between the first node and a first voltage dividing node; a second voltage dividing resistor connected between the first voltage dividing node and a second voltage dividing node; a third voltage dividing resistor connected between the second voltage dividing node and the second node; a first gate connection resistor; a second gate connection resistor; and a first variable current source connected to the first control terminal of the first field effect transistor via the first gate connected resistor; a second variable current source connected to the second control terminal of the second field effect transistor via the second gate connected resistor; a first bias resistor connected between the first variable current source and the first voltage division node; a second bias resistor connected between the second variable current source and the second voltage division node; a first resistive element connected between the first node and the one end of the current source; a second resistive element connected between the second node and the one end of the current source; Variable gain differential amplifier circuit.

2. The variable resistance circuit includes: a first capacitor connected between the first variable current source and the first voltage division node; a second capacitor connected between the second variable current source and the second voltage division node; 2. The variable gain differential amplifier circuit according to claim 1.

3. a resistance value of the first voltage dividing resistor is equal to a resistance value of the third voltage dividing resistor; The resistance value of the second voltage dividing resistor is twice the resistance value of the first voltage dividing resistor.

3. The variable gain differential amplifier circuit according to claim 1.

4. the first voltage division node is connected to a back gate of the first field effect transistor; the second voltage division node is connected to a back gate of the second field effect transistor; 4. The variable gain differential amplifier circuit according to claim 1.

5. a first input terminal and a second input terminal each for receiving an input signal; a first output terminal and a second output terminal each for outputting an output signal; a first transistor having a control terminal connected to the first input terminal and one current terminal connected to the first output terminal; a second transistor having a control terminal connected to the second input terminal and one current terminal connected to the second output terminal; a current source having one end and another end, the other end being connected to a first power supply; a first load resistive element connected between the first output terminal and a second power supply; a second load resistive element connected between the second output terminal and the second power supply; a variable resistance circuit having a first node and a second node, the first node being connected to the other current terminal of the first transistor and the second node being connected to the other current terminal of the second transistor, and variably setting a resistance value between the first node and the second node; Equipped with The variable resistance circuit includes: N field effect transistors from a first field effect transistor to an Nth field effect transistor (N is an integer of 3 or more), each having two current terminals and a control terminal, the two current terminals being connected in series between the first node and the second node, the first field effect transistor being connected to the first node, the ith field effect transistor (i is an integer of 2 to N-1) being connected to the i-1th field effect transistor, and the Nth field effect transistor being connected between the N-1th field effect transistor and the second node; N+1 voltage dividing resistors, from a first voltage dividing resistor to an N+1th voltage dividing resistor, are connected in series between the first node and the second node, the N+1 voltage dividing resistors being connected between the first node and a first voltage dividing node, a jth voltage dividing resistor (j is an integer between 2 and N) is connected between a j-1th voltage dividing node and a jth voltage dividing node, and the N+1th voltage dividing resistor is connected between the Nth voltage dividing node and the second node; N variable current sources, from a first variable current source to an Nth variable current source, each of which provides a variable current; N gate connection resistors from a first gate connection resistor to an N-th gate connection resistor, the k-th gate connection resistor (k is an integer between 1 and N) being connected between the k-th variable current source and a control terminal of the k-th field effect transistor; N bias resistors from a first bias resistor to an N-th bias resistor, the m-th bias resistor (m is an integer between 1 and N) being connected between the m-th voltage division node and the m-th variable current source; a first resistive element connected between the first node and the one end of the current source; a second resistive element connected between the second node and the one end of the current source; Variable gain differential amplifier circuit.

6. the variable resistance circuit further includes N capacitors from a first capacitor to an Nth capacitor, the nth capacitor (n is an integer between 1 and N) being connected between an nth voltage division node and an nth variable current source; 6. The variable gain differential amplifier circuit according to claim 5.

7. the resistance value of the first voltage dividing resistor is equal to the resistance value of the N+1 voltage dividing resistor; a resistance value of each of the second voltage dividing resistor to the Nth voltage dividing resistor is twice the resistance value of the first voltage dividing resistor; 7. The variable gain differential amplifier circuit according to claim 5.

8. Among the N voltage dividing nodes from the first voltage dividing node to the Nth voltage dividing node, a pth voltage dividing node (p is an integer not less than 1 and not more than N) is connected to a back gate of a pth field effect transistor.

8. The variable gain differential amplifier circuit according to claim 5.

9. a first inductor connected between the one end of the current source and the first resistive element; a second inductor connected between the one end of the current source and the second resistive element; Further comprising:

9. The variable gain differential amplifier circuit according to claim 1.

10. A semiconductor integrated circuit comprising the variable gain differential amplifier circuit according to claim 1 .

11. a first input terminal and a second input terminal each for receiving an input signal; a first output terminal and a second output terminal each for outputting an output signal; a first transistor having a control terminal connected to the first input terminal and one current terminal connected to the first output terminal; a second transistor having a control terminal connected to the second input terminal and one current terminal connected to the second output terminal; a first current source having a first end and a first other end, the first other end being connected to a first power supply; a second current source having a second end and a second other end, the second other end being connected to the first power supply; a first load resistive element connected between the first output terminal and a second power supply; a second load resistive element connected between the second output terminal and the second power supply; a variable resistance circuit having a first node and a second node, the first node being connected to the other current terminal of the first transistor and the first one end of the first current source, and the second node being connected to the other current terminal of the second transistor and the second one end of the second current source, and variably setting a resistance value between the first node and the second node; Equipped with The variable resistance circuit includes: a first field effect transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal connected to the first node; a second field effect transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal being connected to the second node and the fourth current terminal being connected to the second current terminal of the first field effect transistor; a first voltage dividing resistor connected between the first node and a first voltage dividing node; a second voltage dividing resistor connected between the first voltage dividing node and a second voltage dividing node; a third voltage dividing resistor connected between the second voltage dividing node and the second node; a first gate connection resistor; a second gate connection resistor; and a first variable current source connected to the first control terminal of the first field effect transistor via the first gate connected resistor; a second variable current source connected to the second control terminal of the second field effect transistor via the second gate connected resistor; a first bias resistor connected between the first variable current source and the first voltage division node; a second bias resistor connected between the second variable current source and the second voltage division node; Variable gain differential amplifier circuit.

12. the variable resistance circuit further includes a resistive element connected between the first node and the second node; 12. The variable gain differential amplifier circuit according to claim 11.

13. A semiconductor integrated circuit comprising the variable gain differential amplifier circuit according to claim 11 or 12.

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