Semiconductor device and motor drive system

Abstract

This semiconductor device is provided with: a semiconductor chip on which a semiconductor integrated circuit is formed; a plurality of leads that are disposed in the periphery of the semiconductor chip; a chip wire that connects between the semiconductor chip and the leads; and a package that seals these components. The semiconductor integrated circuit detects a detection target current flowing through a sense resistor, on the basis of a voltage drop at the sense resistor, and performs a predetermined operation on the basis of the detection result. The plurality of leads include first and second leads that are connected to one end and the other end of the sense resistor. In the package, the sense resistor is formed by using a sense metal body that connects between the first and the second leads without passing through the semiconductor chip.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a motor drive system. [Background technology]

[0002] There is known a motor drive system that includes a three-phase motor, an inverter circuit that supplies coil current to each coil of the three-phase motor, and a motor control device that controls the rotation of the three-phase motor by controlling the inverter circuit based on the detection results of the coil current of each phase. In such a motor drive system, the motor control device is often formed by a semiconductor device (so-called motor driver IC) in which a semiconductor integrated circuit is packaged.

[0003] In systems in which the coil current to be detected is relatively large (e.g., 10 A or more), it is common to externally connect a detection resistor (a resistor of about 10 mΩ) to the semiconductor device to detect the coil current, and to input a signal indicating the voltage between both terminals of the detection resistor to the semiconductor device from outside the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-139892 A Summary of the Invention [Problem to be solved by the invention]

[0005] In this case, the resistance value of the detection resistor connected externally to the semiconductor device varies, and the variation in the resistance value of the detection resistor deteriorates the current detection accuracy, and in turn hinders the realization of the desired motor control (e.g., vector control). Although it has been considered to incorporate a detection resistor into the semiconductor device, when the current to be detected is large (e.g., 10 A or more), this is not easy to achieve due to heat generation and other factors.

[0006] Although circumstances relating to current detection have been explained using a motor drive system as an example, such circumstances are not limited to motor drive systems and similarly apply to various devices or systems requiring current detection.

[0007] An object of the present disclosure is to provide a semiconductor device that utilizes a resistance component within a package to enable good current detection, and a motor drive system using the same. [Means for solving the problem]

[0008] The semiconductor device according to the present disclosure comprises a semiconductor chip on which a semiconductor integrated circuit is formed, a plurality of leads arranged around the semiconductor chip, two or more chip-directed wires connecting two or more leads included in the plurality of leads to the semiconductor chip, and a package having sealing resin and sealing the semiconductor chip, the plurality of leads, and the two or more chip-directed wires so that a portion of each of the plurality of leads is exposed from the sealing resin, wherein the semiconductor integrated circuit comprises a current detection circuit configured to detect a current to be detected flowing through a sense resistor based on a voltage drop in the sense resistor, and a main circuit configured to perform a predetermined operation based on a detection result of the current to be detected, wherein the plurality of leads include first and second leads connected to one end and the other end of the sense resistor, and the sense resistor is formed within the package using a sense metal body connecting the first and second leads without passing through the semiconductor chip (first configuration). Effect of the Invention

[0009] According to the present disclosure, it is possible to provide a semiconductor device that enables good current detection, and a motor drive system using the same. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is an overall configuration diagram of a motor drive system according to a first embodiment of the present disclosure. [Diagram 2]FIG. 2 is a diagram showing a state in which the semiconductor device is mounted on a substrate according to the first embodiment of the present disclosure. [Diagram 3] FIG. 3 is a diagram illustrating an example of an internal configuration of the current detection circuit of FIG. [Figure 4] FIG. 4 is an external perspective view of the semiconductor device according to the first embodiment of the present disclosure, observed obliquely from above. [Diagram 5] FIG. 5 is a plan view of the semiconductor device observed from below according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is an external perspective view of the semiconductor device according to the first embodiment of the present disclosure, observed obliquely from below. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a transparent plan view of the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a plan view of the die pad according to the first embodiment of the present disclosure. [Figure 10A] FIG. 10A is a see-through plan view of a semiconductor device (with one sensing wire) according to an example EX1_1 belonging to the first embodiment of the present disclosure. [Figure 10B] FIG. 10B is a see-through plan view of a semiconductor device (in the case where there is one sensing wire) according to Example EX1_1 belonging to the first embodiment of the present disclosure. [Figure 11] FIG. 11 relates to Example EX1_1 belonging to the first embodiment of the present disclosure, and is a transparent plan view of a semiconductor device (attention is paid to external terminals). [Figure 12] FIG. 12 is a diagram showing a relationship between a sensing wire and two leads according to Example EX1_1 belonging to the first embodiment of the present disclosure. [Figure 13] FIG. 13 is a see-through plan view of a semiconductor device (in the case of two sense wires) according to an example EX1_1 belonging to the first embodiment of the present disclosure. [Figure 14] FIG. 14 relates to Example EX1_1 belonging to the first embodiment of the present disclosure, and is a see-through plan view of a semiconductor device (a case in which there are three sensing wires). [Figure 15] FIG. 15 relates to Example EX1_1 belonging to the first embodiment of the present disclosure, and is a diagram showing the relationship between the external terminals of a semiconductor device and the wiring pattern on a substrate. [Figure 16] FIG. 16 is a flowchart of a test process according to Example EX1_2 belonging to the first embodiment of the present disclosure. [Figure 17] FIG. 17 relates to Example EX1_2 belonging to the first embodiment of the present disclosure, and is a diagram showing the relationship between a test substrate, a socket, and a semiconductor device in a test process. [Figure 18] FIG. 18 relates to example EX1_3 belonging to the first embodiment of the present disclosure and is a plan view of each lead. [Figure 19] FIG. 19 relates to Example EX1_3 belonging to the first embodiment of the present disclosure, and is a diagram showing a state in which two leads are connected by two sensing wires. [Figure 20] FIG. 20 is a diagram showing a state in which two leads are connected by four sensing wires according to Example EX1_3 belonging to the first embodiment of the present disclosure. [Figure 21] FIG. 21 is a plan view of a plurality of leads related to current detection and their surroundings, provided for comparison with the first embodiment. [Figure 22] FIG. 22 is a plan view of a plurality of leads related to current detection and their surroundings, provided for comparison with the first embodiment, and shows the flow of current. [Diagram 23] FIG. 23 relates to Example EX1_4 belonging to the first embodiment of the present disclosure, and is a plan view of a plurality of leads related to current detection and their surroundings, showing the flow of current. [Figure 24] FIG. 24 is a see-through plan view of a semiconductor device according to the second embodiment of the present disclosure. [Diagram 25] FIG. 25 is a see-through plan view of a semiconductor device according to a third embodiment of the present disclosure. [Figure 26] FIG. 26 is a plan view of two leads and a connecting metal portion according to the third embodiment of the present disclosure. [Figure 27]FIG. 27 is a see-through plan view of a modified semiconductor device according to the third embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, examples of the embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are omitted as a rule. In this specification, for the sake of simplicity, a symbol or a code referring to information, a signal, a physical quantity, an element, or a part may be written, and the name of the information, signal, physical quantity, element, or part corresponding to the symbol or code may be omitted or abbreviated. For example, the high-side transistor referred to by "MH[1]" described later (see FIG. 1) may be written as high-side transistor MH[1] or abbreviated as transistor MH[1], but they all refer to the same thing.

[0012] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part is formed of a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0013] For any transistor configured as a FET (field effect transistor) including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Hereinafter, the on state and off state of any transistor may be expressed simply as on and off.

[0014] <<First embodiment>> A first embodiment of the present disclosure will be described. Fig. 1 shows the overall configuration of a motor drive system SYS according to the first embodiment. The motor drive system SYS includes a semiconductor device 10 that functions as a motor control device, an inverter circuit 20, a three-phase motor 30, and a higher-level circuit 40 formed by an MPU (Micro Processing Unit) or the like.

[0015] The three-phase motor 30 is a three-phase brushless synchronous motor equipped with three star-connected coils L[1], L[2], and L[3]. The coils L[1], L[2], and L[3] correspond to the U-phase, V-phase, and W-phase coils, respectively, and in this embodiment, the U-phase, V-phase, and W-phase are referred to as the first phase, the second phase, and the third phase, respectively. The circuit configuration corresponding to the first phase, the circuit configuration corresponding to the second phase, and the circuit configuration corresponding to the third phase are common to each other. Therefore, hereinafter, the configuration of each circuit will be described using the symbol i representing an arbitrary integer as appropriate. A circuit, element, physical quantity, etc. referred to by a symbol including the symbol "[i]" (for example, L[i]) represents a circuit, element, physical quantity, etc. in the i-th phase.

[0016] The three-phase motor 30 has a stator and a rotor equipped with a permanent magnet, and the stator is provided with coils L[1], L[2], and L[3]. One end of the coil L[1] is connected to an external wiring WR O [1] via the external terminal OUT (described later)O [1], SNS N [1] and OUT MNT [1] is commonly connected to the external wiring WR. O [2] via the external terminal OUT (described later) O [2], Social media N [2] and OUT MNT [2] is commonly connected to the coil L[3]. One end of the coil L[3] is connected to the external wiring WR O [3] via the external terminal OUT (described later) O [3], Social Networking N [3] and OUT MNT [3]. The other ends of the coils L[1] to L[3] are connected together at the neutral point NP. External wiring WR O [1] ~WR O [3] and WR described below IN [1] ~WR IN [3] denotes wiring provided outside the semiconductor device 10, and includes a wiring pattern on a substrate (substrate SUB described below) on which the semiconductor device 10 is mounted. Fig. 2 shows the substrate SUB on which the semiconductor device 10 is mounted. However, in Fig. 2, among the components mounted on the substrate SUB, components other than the semiconductor device 10 are not shown, and the wiring pattern is also not shown.

[0017] The currents flowing through the coils L[1], L[2], and L[3] are referred to as coil currents IL[1], IL[2], and IL[3], respectively. If we ignore the regeneration of power by the three-phase motor 30, the coil currents IL[1], IL[2], and IL[3] are respectively connected to the external terminals OUT O [1], OUT O [2] OUT O [3] to the neutral point NP. In the following, unless otherwise stated, the coil current IL[1] flows from the external terminal OUT O It flows from [i] toward the neutral point NP.

[0018] The semiconductor device 10 is formed by enclosing and sealing a semiconductor chip on which a semiconductor integrated circuit is formed, in a package made of sealing resin, and the package of the semiconductor device 10 has a plurality of external terminals provided so as to be exposed.

[0019] In the semiconductor device 10 according to the configuration example of FIG. 1, the plurality of external terminals include external terminals CP1 and CP2 for charge pumping and an external terminal P VCP and P VM and the external terminal OUT through which the coil current passes IN [1]~OUT IN [3] and OUT O [1]~OUT O [3] and the external terminal SNS for detecting the coil current P [1] ~SNS P [3] and SNS N [1] ~SNS N [3] and the external terminal OUT for monitoring the coil terminal voltage MNT [1]~OUT MNT [3] and external terminal P for gate signal output HG [1]~P HG [3] and P LG [1]~P LG [3] and the external terminal P, which is the ground terminal GND External terminal P GND is connected to ground. Although not shown in Fig. 1, the plurality of external terminals includes a communication terminal group consisting of two or more external terminals, and communication between the semiconductor device 10 (a control circuit 120 described below) and the upper circuit 40 is performed via the communication terminal group. Furthermore, other external terminals may also be provided in the semiconductor device 10.

[0020] The inverter circuit 20 includes a first phase half-bridge circuit 210[1], a second phase half-bridge circuit 210[2], and a third phase half-bridge circuit 210[3], and under the control of the semiconductor device 10, supplies coil currents IL[1] to IL[3] to the coils L[1] to L[3].

[0021] Each of the half-bridge circuits 210[1], 210[2], and 210[3] is composed of a high-side transistor and a low-side transistor connected in series between a line to which a power supply voltage VM is applied and ground. The power supply voltage VM is a predetermined positive DC voltage. The high-side transistor and the low-side transistor are configured as N-channel MOSFETs (Metal Oxide Semiconductor Field effect transistors). The high-side transistor and the low-side transistor provided in the half-bridge circuit 210[i] are referred to as MH[i] and ML[i], respectively.

[0022] In each of the half-bridge circuits 210[1] to 210[3], the drain of the high-side transistor MH[i] is connected to a power supply terminal to which a power supply voltage VM is applied and is supplied with the power supply voltage VM, the source of the high-side transistor MH[i] and the drain of the low-side transistor ML[i] are commonly connected at a node ND[i], and the source of the low-side transistor ML[i] is connected to ground.

[0023] The connection node ND[1] between the transistors MH[1] and ML[1] is connected to the external wiring WR IN [1] External terminal OUT IN [1] and SNS P The connection node ND[2] between the transistors MH[2] and ML[2] is connected to the external wiring WR IN [2] External terminal OUT IN [2] and SNS P The connection node ND[3] between the transistors MH[3] and ML[3] is connected to the external wiring WR IN [3] External terminal OUT IN [3] and SNS P [3] is commonly connected.

[0024] The semiconductor device 10 includes a current detection circuit 10, a control circuit 120, a pre-driver circuit 130, an internal power supply circuit 140, a charge pump circuit 150, a calibration information holding unit 160, and a sense resistor RSNS [1], R SNS [2] and R SNS [3] and an external terminal P VM A power supply voltage VM is supplied from outside the semiconductor device 10 to the external terminal P VCP and P VM Capacitor C in between CPA A capacitor C is provided between the external terminals CP1 and CP2. CPB The charge pump circuit 150 is provided with external terminals CP1, CP2, P VCP and P VM is connected to the capacitor C CPA and C CPB The power supply voltage VCP is generated by boosting the power supply voltage VM using the power supply voltage VCP. The power supply voltage VCP is a DC voltage higher than the power supply voltage VM (for example, a DC voltage higher by 5 V). The voltage difference between the power supply voltages VM and VCP is applied to the capacitor C CPA and external terminal P VCP A power supply voltage VCP is generated at the semiconductor device 10. The internal power supply circuit 140 generates one or more internal power supply voltages based on the power supply voltage VM. Each circuit in the semiconductor device 10 is driven based on the internal power supply voltage.

[0025] Sense resistor R SNS [i] is a resistor for detecting the coil current IL[i] provided in the semiconductor device 10. Therefore, the sense resistor R SNS [1] has one end and the other end connected to the external terminal OUT IN [1] and OUT O [1] and sense resistor R SNS [2] has one end and the other end connected to the external terminal OUT IN [2] and OUT O [2] and sense resistor R SNS [3] has one end and the other end connected to the external terminal OUT IN [3] and OUT O [3] is connected.

[0026] In the first phase, the external terminal OUT IN [1] and SNS P [1] Between them is external wiring WRIN [1] is shorted by a part of the external terminal OUT O [1] and SNS N [1] Between them is external wiring WR O The same is true for the second and third phases. That is, the external terminal OUT IN [i] and SNS P Between [i] is external wiring WR IN [i] is shorted by a part of the external terminal OUT O [i] and SNS N Between [i] is external wiring WR O [i] is short-circuited by a part of the sense resistor R SNS [i] causes the coil current IL[i] to flow through the sensing resistor R SNS A voltage drop occurs at [i] according to the coil current IL[i], and the sense resistor R SNS The voltage drop at [i] is the external terminal SNS P [i] and SNS N [i]. Furthermore, for each of the first to third phases, the external terminal SNS P [i] and OUT IN [i] is shorted and the external terminal SNS N [i] and OUT O [i] are short-circuited, and the configuration for realizing this short-circuit will be described later.

[0027] The current detection circuit 110 is connected to an external terminal SNS P [1] ~SNS P [3] and SNS N [1] ~SNS N [3] connected to the external terminal SNS P [1] and SNS N Detects the coil current IL[1] based on the voltage between [1] and the external terminal SNS P [2] and SNS N [2] detects the coil current IL[2] based on the voltage between the external terminal SNS P [3] and SNS N[3], the coil current IL[3] is detected based on the voltage between the input terminals 110 and 160. The detection of the coil current IL[i] means the detection of the current value of the coil current IL[i], and the detected current values ​​of the coil currents IL[1], IL[2], and IL[3] by the current detection circuit 110 are referred to as the detected current values ​​VAL_IL[1], VAL_IL[2], and VAL_IL[3], respectively. A signal IL_DET representing the detected current values ​​VAL_IL[1], VAL_IL[2], and VAL_IL[3] is sent from the current detection circuit 110 to the control circuit 120. The signal IL_DET is generated by referring to the calibration information held in the calibration information holding unit 160, which will be described later.

[0028] 3, the current detection circuit 110 is configured with a first phase current sensor 111[1] and an ADC 112[1], a second phase current sensor 111[2] and an ADC 112[2], and a third phase current sensor 111[3] and an ADC 112[3]. P [i] and SNS N [i] is connected to the external terminal SNS P [i] and SNS N Analog signal S is an analog voltage signal having a voltage value proportional to the voltage (potential difference) between [i]. A The current sensor 111[i] can be configured with an amplifier circuit including an operational amplifier. The ADC 112[i] is an analog-to-digital converter that outputs an analog signal S A [i] is converted to a digital signal S D [i] to generate a digital signal S D [i] is the external terminal SNS P [i] and SNS N [i], and the signal value is proportional to the voltage (potential difference) between them. D In the configuration example of FIG. 3, the signal value of the detected current value VAL_IL[i] is converted into a digital signal S by three analog-to-digital converters (i.e., ADC112[1] to 112[3]). D [1]~S D[3] is generated, but only one analog-to-digital converter is provided in the current detection circuit 110, and the single analog-to-digital converter is used in a time-division manner to generate an analog signal S A [1]~S A [3] to receive digital signal S D [1]~S D [3] may be generated.

[0029] The control circuit 120 generates a drive control signal DRV for driving the three-phase motor 30 to rotate based on the signal IL_DET and a motor drive command signal supplied from the higher-level circuit 40, and outputs the generated drive control signal DRV to the pre-driver circuit 130.

[0030] The pre-driver circuit 130 is connected to the external terminal OUT MNT [1]~OUT MNT [3], P HG [1]~P HG [3], P LG [1]~P LG [3] and P GND Connected to the external terminal OUT MNT [1]~OUT MNT [3], as mentioned above, are the external wiring WR O [1] ~WR O [3] is connected to one end of the coils L[1] to L[3]. HG [1]~P HG [3] and P LG [1]~P LG The pre-driver circuit 130 is connected to the gates of the transistors MH[1] to MH[3] and ML[1] to ML[3] through other external wiring (not shown). MNT [1]~OUT MNTWhile referring to the voltage of [3], gate signals HG[1] to HG[3] and LG[1] to LG[3] are generated based on the drive control signal DRV, and the gate signals HG[1] to HG[3] and LG[1] to LG[3] are supplied to the gates of transistors MH[1] to MH[3] and ML[1] to ML[3], respectively, to turn those transistors on / off individually.

[0031] The gate signals HG[1] to HG[3] and LG[1] to LG[3] each have a high or low signal level. However, the high-level potentials of the gate signals HG[i] and LG[i] are different from each other, and the low-level potentials are also different from each other. When the gate signal HG[i] is at a high level, the transistor MH[i] is turned on, and when the gate signal HG[i] is at a low level, the transistor MH[i] is turned off. The relationship between the gate signal LG[i] and the transistor ML[i] is also the same. The high-level gate signal HG[i] is generated using the power supply voltage VCP.

[0032] Specifically, for example, the control circuit 120 receives a motor drive command signal from the higher-level circuit 40, and can vector-control the three-phase motor 30 based on the detected current values ​​VAL_IL[1], VAL_IL[2], and VAL_IL[3] so that the three-phase motor 30 rotates at a rotation speed specified by the motor drive command signal, or so that a torque specified by the motor drive command signal is generated in the three-phase motor 30. A drive control signal DRV for realizing this vector control is provided to the pre-driver circuit 130, whereby, for example, the three-phase motor 30 is sinusoidally driven.

[0033] Referring to FIG. 4, the semiconductor device 10 has a package called QFN (Dual Flatpack No-leaded). However, the type of package of the semiconductor device 10 is arbitrary. The package described in this embodiment refers to the package of the semiconductor device 10. In this embodiment, a three-dimensional orthogonal coordinate system consisting of X-axis, Y-axis, and Z-axis perpendicular to each other is assumed, and the direction from the negative side to the positive side of the Z-axis is defined as the upward direction, and the opposite direction is defined as the downward direction. A plane parallel to the X-axis and Y-axis is called the XY plane, a plane parallel to the Y-axis and Z-axis is called the YZ plane, and a plane parallel to the Z-axis and X-axis is called the ZX plane. The package has an external shape of a rectangular parallelepiped, and the rectangular parallelepiped as the external shape of the package has an upper surface SF1 and a lower surface SF2 parallel to the XY plane, and four side surfaces SF3. The upper surface SF1 and the lower surface SF2 are two surfaces facing each other, and the upper surface SF1 is located on the positive side of the Z-axis relative to the lower surface SF2. The four side surfaces SF3 include two side surfaces SF3 parallel to the YZ plane and facing each other, and two side surfaces SF3 parallel to the ZX plane and facing each other.

[0034] FIG. 4 is an external perspective view of the semiconductor device 10 when the top surface SF1 and two side surfaces SF3 are observed from the positive side of the Z axis. FIG. 5 is a plan view of the semiconductor device 10 when the bottom surface SF2 is observed from the negative side of the Z axis. FIG. 6 is an external perspective view of the semiconductor device 10 when the bottom surface SF2 and two side surfaces SF3 are observed from the negative side of the Z axis. When the package is observed from a direction parallel to the Z axis, the outer shape of the package is a rectangle, and the four sides of the rectangle are referred to as sides SD1 to SD4 (see FIG. 5). Sides SD1 and SD2 are two sides facing each other, both parallel to the Y axis. Sides SD3 and SD4 are two sides facing each other, both parallel to the X axis. In each of FIGS. 4 to 6, the symbol "ET" represents an external terminal provided on the semiconductor device 10. Here, for the sake of concrete explanation, it is assumed that the number of external terminals ET provided on the semiconductor device 10 is 32. However, in the present disclosure, any number of external terminals ET may be provided in the semiconductor device 10. In addition, in order to prevent the illustration from becoming complicated, the symbol "ET" is attached to only some of the external terminals in Fig. 4 to Fig. 6.

[0035] The total of 32 external terminals ET are composed of a first external terminal row arranged along side SD1, a second external terminal row arranged along side SD2, a third external terminal row arranged along side SD3, and a fourth external terminal row arranged along side SD4, and each external terminal row is composed of eight external terminals ET. In each external terminal row, the eight external terminals ET are arranged at equal intervals. Each external terminal ET is a metal terminal exposed from the package, and is mainly exposed from the bottom surface SF2. However, each external terminal ET in the first external terminal row is exposed from the package from the bottom surface SF2 to the side surface SF3 corresponding to the side SD1, and each external terminal ET in the second external terminal row is exposed from the package from the bottom surface SF2 to the side surface SF3 corresponding to the side SD2. The same is true for each external terminal ET in the third and fourth external terminal rows. Of the total of 32 external terminals ET, 26 external terminals ET are the external terminals CP1, CP2, P shown in FIG. VCP , P VM , OUT IN [1]~OUT IN [3], OUT O [1]~OUT O [3], Social Networking P [1] ~SNS P [3], Social Networking N [1] ~SNS N [3], OUT MNT [1]~OUT MNT [3], P HG [1]~P HG [3], P LG [1]~P LG [3] and P GND This assignment is arbitrary.

[0036] Fig. 7 is a cross-sectional view of the semiconductor device 10 when the semiconductor device 10 is cut along the cutting line AA shown in Fig. 4 (i.e., a cross-sectional view of the semiconductor device 10 taken along a cross section parallel to the ZX plane). However, Fig. 7 is a schematic cross-sectional view showing the positional relationship of components of the semiconductor device 10, and the detailed shapes of the components may differ from the actual shapes.

[0037] The semiconductor device 10 includes a semiconductor chip 510, a die pad 520 that supports the semiconductor chip 510, a plurality of leads 530, a plurality of chip-directed wires 540 for connecting (electrically connecting) the semiconductor chip 510 and the plurality of leads 530, and a sealing resin 550. The wires 540 correspond to what is generally called bonding wires, but are referred to as chip-directed wires in order to clearly distinguish them from sensing wires described below.

[0038] The sealing resin 550 is an insulating material that collectively seals the semiconductor chip 510, the die pad 520, the leads 530, the wires 540 for each chip, and a sensing metal body (such as a sensing wire 560; not shown in FIG. 7) described below, and the package of the semiconductor device 10 is formed by the sealing resin 550. However, the package is formed such that a portion of each of the multiple leads 530 is exposed from the sealing resin 550. Specifically, all or a portion of the lower surface 531 of each lead 530 is exposed from the lower surface of the sealing resin 550 (hence, the lower surface SF2 of the package), and all or a portion of the side surface 532 of each lead 530 is also exposed from the side surface of the sealing resin 550 (hence, the side surface SF3 of the package).

[0039] The semiconductor chip 510 is a component in which a semiconductor integrated circuit is formed on a semiconductor substrate, and the semiconductor integrated circuits in the semiconductor chip 510 form each circuit in the semiconductor device 10, including the blocks 110, 120, 130, 140, 150, and 160 shown in FIG. SNS [1]~R SNS[3] is formed outside the semiconductor chip 510. The semiconductor chip 510 is die-bonded onto the die pad 520 with the surface (front surface) on which each functional element is formed facing upward. In addition, a plurality of pads (not shown) are formed on the front surface of the semiconductor chip 510 by exposing a part of the wiring layer from the surface protection layer. Each pad is connected to a corresponding lead 530 via a chip-directed wire 540. In other words, the semiconductor chip 510 and the plurality of leads 530 are connected via the chip-directed wires 540. The connection via the chip-directed wires 540 or the connection by the chip-directed wires 540 naturally means an electrical connection.

[0040] 7, the entire die pad 520 is sealed with sealing resin 550, but the semiconductor device 10 may be configured so that the lower surface of the die pad 520 is exposed from the lower surface of the sealing resin 550 (hence the lower surface SF2 of the package). In this case, however, a retaining portion (not shown) is formed on the die pad 520 to prevent the die pad 520 from coming off the sealing resin 550.

[0041] Fig. 8 is a transparent plan view of the semiconductor chip 510, the die pad 520, and each lead 530 on the assumption that the sealing resin 550 is transparent (in reality, the sealing resin 550 is opaque). However, the transparent plan view of Fig. 8 is a transparent plan view when the semiconductor device 10 is observed from the positive side of the Z axis. In Fig. 8, components other than the semiconductor chip 510, the die pad 520, and each lead 530 are omitted. In Fig. 8, the outermost rectangle represents the outer edge of the package. Also, in Fig. 8, the reference symbol "530" is attached to only some of the leads to prevent the illustration from becoming too complicated.

[0042] Each of the semiconductor chip 510 and the die pad 520 has a roughly rectangular shape in a plan view. However, as shown in Fig. 9, the die pad 520 has a main body 521 having a rectangular shape in a plan view, and a total of four suspension leads 522 extending from each vertex of the rectangle to the corresponding corners of the package are added to the main body 521. In a plan view, the rectangle of the die pad 520 is larger than the rectangle of the semiconductor chip 510, and the entire semiconductor chip 510 is placed on the surface of the die pad 520. In this embodiment, a plan view refers to observing the observation target from above along the Z axis.

[0043] The leads 530 are provided eight on each of the positive side of the X-axis, the negative side of the X-axis, the positive side of the Y-axis, and the negative side of the Y-axis when viewed from the center of the semiconductor chip 510 or the center of the die pad 520. That is, a total of 32 leads 530 are distributed around the periphery of the semiconductor chip 510 and the die pad 520. The total of 32 leads 530 are made up of a first lead row arranged along the side SD1, a second lead row arranged along the side SD2, a third lead row arranged along the side SD3, and a fourth lead row arranged along the side SD4, and each lead row is made up of eight leads 530. In each lead row, the eight leads 530 are arranged side by side at equal intervals.

[0044] Each lead 530 is composed of a metal part that fits inside the package and a metal part that is exposed from the package, the former metal part being called an inner lead while the latter metal part being called an outer lead. In each lead 530, the outer lead functions as a corresponding metal terminal ET. Depending on the type of package, the outer lead may protrude from the package as a pin-shaped metal terminal ET. The eight leads 530 that form the first lead row constitute eight external terminals ET that form the first external terminal row, and the eight leads 530 that form the second lead row constitute eight external terminals ET that form the second external terminal row. The same applies to the third and fourth lead rows.

[0045] Each lead 530 is made of a thin metal plate having a thickness direction in the Z-axis direction. In FIG. 8, the shape of each lead 530 in a plan view is approximately rectangular, but the shape of each lead 530 in a plan view may be arbitrary. The material of the lead 530 is copper. However, the lead 530 may be formed using a metal other than copper. For example, the lead 530 may be formed using a so-called 42 alloy (an alloy containing nickel and iron). The material of the die pad 520 may be the same as the material of the lead 530. Each lead 530 is formed with a retaining portion 533 for preventing each lead 530 from being removed from the package (see FIG. 7). Although not clear from FIGS. 7 and 8, a metal plating layer having solder wettability is formed on the exposed portion of each lead 530.

[0046] The chip-to-wire 540 is a metal wire made of gold, aluminum, or copper. One end of each chip-to-wire 540 is connected to a desired pad on the semiconductor chip 510, and the other end of the chip-to-wire 540 is connected to a desired position on a desired lead 530, so that the desired pad and the desired lead 530 are electrically connected via the chip-to-wire 540. The connection point between the lead 530 and the chip-to-wire 540 (the point where the chip-to-wire 540 is wire-bonded to the lead 530) is on the inner lead.

[0047] All of the 32 leads 530 may be connected to the semiconductor chip 510 via the chip-to-wires 540, or some of the 32 leads 530 may not be connected to the semiconductor chip 510. That is, the semiconductor device 10 may be configured to include n leads 530 forming n external terminals ET and m chip-to-wires 540, and to connect the m leads 530 included in the n leads 530 to the semiconductor chip 510 via the m chip-to-wires 540. In the example of this embodiment, "n=32", but the value of n is not limited to 32. m is an arbitrary integer equal to or less than n and equal to or greater than 2. As will be described later, the external terminal OUT IN [i] and OUT OThe wires 540 for the chip may not be connected to each of the leads 530 forming [i].

[0048] The first embodiment includes the following examples EX1_1 to EX1_6. In each example, the sensing resistor R SNS [1]~R SNS [3] The characteristic configuration related to the above will be described. The matters described above in the first embodiment are applied to the following Examples EX1_1 to EX1_6 unless otherwise specified and unless there is a contradiction, and in each Example, the description in each Example may take precedence for matters that contradict the matters described above in the first embodiment. Furthermore, unless there is a contradiction, matters described in any of Examples EX1_1 to EX1_6 can also be applied to any other Example (that is, any two or more of the multiple Examples can be combined).

[0049] <<Example EX1_1>> Example EX1_1 will be described. FIG. 10A is a transparent plan view of the semiconductor device 10 when the sealing resin 550 is assumed to be transparent. However, the transparent plan view of FIG. 10A is a transparent plan view when the semiconductor device 10 is observed from the positive side of the Z axis. In FIG. 10A, only parts necessary for the description of the technology related to Example EX1_1 are illustrated, and some components of the semiconductor device 10 are omitted (the same applies to FIGS. 11, 13, and 14 described later). In FIG. 10A, the outermost rectangle represents the outer edge of the package (the same applies to FIGS. 11, 13, 14, 25, and 27 described later). In FIG. 10A, the reference characters "530a", "530b", "530c", and "530d" are attached to only four specific leads out of the multiple leads 530 (the same applies to FIGS. 13 and 14 described later). The chip-directed wire 540 connecting the lead 530c and the semiconductor chip 510 is specifically referred to as "540c", and the chip-directed wire 540 connecting the lead 530d and the semiconductor chip 510 is specifically referred to as "540d". FIG. 10B is an enlarged view of a portion of FIG. 10A. In FIGS. 10A and 10B, the portion SHORT shown by the hatched area (shaded area) is ac and SHORTbd We will discuss this later. First, let us consider the relevant part, SHORT ac and SHORT bd We will ignore the existence of these and explain the structure of the other parts.

[0050] The leads 530a to 530d are four adjacent leads 530 provided on the side SD1, and are arranged in the order of leads 530d, 530b, 530a, and 530c from the negative side to the positive side of the Y axis. In other words, the leads 530a and 530b are adjacent to each other, the lead 530a is located between the leads 530b and 530c, and the lead 530b is located between the leads 530a and 530d. Here, the leads 530a to 530d are considered to be the four leads 530 assigned to the first phase. Then, as can be understood from a comparison between FIG. 10A and FIG. 11, the leads 530a, 530b, 530c, and 530d are respectively connected to the external terminals OUT IN [1], OUT O [1], SNS P [1], SNS N [1] is assigned. In other words, the external terminal OUT IN [1] is formed, and the external terminal OUT O [1] is formed, and the external terminal SNS P [1] is formed, and the external terminal SNS N [1] is formed.

[0051] In the semiconductor device 10 shown in FIG. 10A, the leads 530a and 530b are connected by a sense wire 560 inside the package. The sense wire 560 is an example of a sense metal body that connects the leads 530a and 530b. The sense wire 560 is a metal wire made of gold, aluminum, or copper. The material of the sense wire 560 may be the same as the material of the chip-directed wire 540, and the thickness (i.e., the diameter of the cross section) of the sense wire 560 may also be the same as the thickness of the chip-directed wire 540.

[0052] FIG. 12 shows a side view of the leads 530a and 530b and the sense wire 560 observed along the X-axis direction. One end of the sense wire 560 is connected to a predetermined position on the upper surface of the lead 530a (hence a predetermined position on the inner lead of the lead 530a), and the other end of the sense wire 560 is connected to a predetermined position on the upper surface of the lead 530b (hence a predetermined position on the inner lead of the lead 530b). The connection between the sense wire and the leads is realized by well-known wire bonding, as is the connection between the chip-directed wire and the leads. The sense wire 560 connects the leads 530a and 530b via the shortest path or a path close to the shortest path. At least, the sense wire 560 is not connected to the semiconductor chip 510, and therefore connects the leads 530a and 530b without passing through the semiconductor chip 510. Note that the connection via the sense wire 560 or the connection by the sense wire 560 naturally means an electrical connection.

[0053] The number of sense wires 560 connecting the leads 530a and 530b may be one or any number of wires equal to or greater than two. That is, for example, the leads 530a and 530b may be connected by two sense wires 560 as shown in FIG. 13, or the leads 530a and 530b may be connected by three sense wires 560 as shown in FIG. 14. When the leads 530a and 530b are connected by a plurality of sense wires 560, the lengths of the plurality of sense wires 560 are preferably the same. However, the lengths of the plurality of sense wires 560 may all be different from each other, or q types of lengths may be mixed among the p number of sense wires 560 (p is an integer of 3 or more; q is an integer less than p and equal to or greater than 2).

[0054] In the following Example EX1_1, N A The leads 530a and 530b are connected by a sense wire 560. A is an arbitrary integer equal to or greater than 1. A The sense wire 560 is connected to the sense resistor R SNS [1] is formed. That is, “N A= 1”, the resistance value of the sense wire 560 itself is the sense resistor R SNS [1] functions as the resistance of “N A ≧2” then N A The parallel resistance of the sense wires 560 is the sense resistor R SNS Strictly speaking, the resistance components of the leads 530a and 530b themselves also function as the resistance of the sense resistor R SNS [1], but the resistance of each lead is negligibly small compared to the resistance of the sense wire 560 (so it can be ignored).

[0055] FIG. 15 shows a schematic plan view of a portion of the substrate SUB on which a semiconductor device 10 is mounted. A plurality of lands with solder applied are formed at required locations on the substrate SUB (the lands are not shown in FIG. 15). The semiconductor device 10 is disposed in a position where the surface of each land on the substrate SUB faces each external terminal (the lower surface of each lead) of the semiconductor device 10, and reflow is performed with each external terminal (the lower surface of each lead) in contact with the solder on each land, thereby mounting the semiconductor device 10 on the substrate SUB. On the substrate SUB, the external wiring WR shown in FIG. IN [1] Part of the wiring pattern WR IN [1]' is formed, and the external wiring WR shown in FIG. O [1] Part of the wiring pattern WR O [1]' is formed. External terminal OUT IN [1] and the land connected to the external terminal SNS P [1] is connected to the wiring pattern WR on the board SUB. IN [1]' shorts the external terminal OUT IN [1] (hence lead 530a) is the external wiring WR IN [1]' via external terminal SNS P [1] (and thus lead 530c). Similarly, the external terminal OUT O [1] and the land connected to the external terminal SNS N [1] is connected to the wiring pattern WR on the board SUB. O [1]' shorts the external terminal OUTO [1] (hence lead 530b) is the external wiring WR O [1]' via external terminal SNS N [1] (and thus shorted to lead 530d).

[0056] 10A again, a connection point 542c between the semiconductor chip 510 and the chip-directed wire 540c, and a connection point 542d between the semiconductor chip 510 and the chip-directed wire 540d are connected to the current detection circuit 110 (see FIG. 1) formed on the semiconductor chip 510. The connection points 542c and 542d indicate the points at which the chip-directed wires 540c and 540d are wire-bonded to the semiconductor chip 510, respectively. The sense resistor R SNS [1] (here N A A voltage drop proportional to the coil current IL[1] occurs in the sense wire 560), and a potential difference according to the voltage drop occurs between the connection points 542c and 542d. Therefore, the current detection circuit 110 detects the coil current IL[1] based on the potential difference between the connection points 542c and 542d, and can obtain the above-mentioned detected current value VAL_IL[1]. P [1] and SNS N [1] The potential difference between them can be considered to be the same.

[0057] In addition, external terminal OUT IN [1] and OUT O There is no chip wire 540 for connecting each of the semiconductor chips 510 to the external terminals OUT IN [1] and OUT O [1] is not connected to the chip-directed wire 540. IN [1] and the semiconductor chip 510, or the external terminal OUT O [1] and the semiconductor chip 510 may be connected by a specific chip-directed wire 540. In this case, however, the specific chip-directed wire 540 is not connected to any significant circuit on the semiconductor chip 510 and does not have any effect on the operation of the semiconductor device 10 described with reference to FIG. 1.

[0058] 10A, among the eight leads 530 aligned along side SD1, four leads 530 located near the center are assigned to leads 530a to 530d, but which of the eight leads 530 aligned along side SD1 are assigned to leads 530a to 530d can be arbitrarily selected. However, it is preferable that the leads 530a to 530d are aligned in the order of leads 530d, 530b, 530a, and 530c, as described above. In this case, lead 530d or 530c may be the end lead 530 of the eight leads 530 aligned along side SD1.

[0059] The structure related to coil current detection has been described with a focus on the first phase among the first to third phases, but the structure related to coil current detection in the second phase and the structure related to coil current detection in the third phase are also similar to those of the first phase, and the technology described for the first phase is also applicable to the second and third phases. When focusing on the second phase, the symbol "[1]" in the above description of the embodiment EX1_1 may be replaced with the symbol "[2]", and the leads 530a to 530d may be considered to be four leads 530 arranged along the side SD3, for example. Similarly, when focusing on the third phase, the symbol "[1]" in the above description of the embodiment EX1_1 may be replaced with the symbol "[3]", and the leads 530a to 530d may be considered to be four leads 530 arranged along the side SD4, for example.

[0060] More specifically, the semiconductor device 10 is provided with three sets of leads 530a to 530d, and the first set of leads 530a to 530d are connected to the external terminals OUT IN [1], OUT O [1], SNS P [1] and SNS N [1], and the second set of leads 530a to 530d are assigned to the external terminals OUT IN [2] OUT O [2], Social media P [2] and SNS N [2], and the third set of leads 530a to 530d are assigned to the external terminals OUT IN [3], OUT O[3], Social Networking P [3] and SNS N The first set of leads 530a-530d, the second set of leads 530a-530d, and the third set of leads 530a-530d are typically arranged on different sides of the semiconductor device 10, but among the total of 12 leads, a number of leads belonging to different sets may be arranged on a common side.

[0061] The current detection circuit 110 can detect the coil current IL[1] based on the potential difference between the first set of leads 530c and 530d (potential difference between connection points 542c and 542d for the first set) to obtain the above-mentioned detected current value VAL_IL[1], can detect the coil current IL[2] based on the potential difference between the second set of leads 530c and 530d (potential difference between connection points 542c and 542d for the second set) to obtain the above-mentioned detected current value VAL_IL[2], and can detect the coil current IL[3] based on the potential difference between the third set of leads 530c and 530d (potential difference between connection points 542c and 542d for the third set) to obtain the above-mentioned detected current value VAL_IL[3].

[0062] A specific numerical example will be given. Consider a case where the distance between the centers of two adjacent leads 530 on the side SD1, SD2, SD3, or SD4 is 500 μm (micrometers). Assume that the cross-sectional shape of the sense wire 560 is circular, the diameter of the cross section of the sense wire 560 is 30 μm, and the sense wire 560 is made of copper. In this case, if a sense wire 560 with a length of 500 μm is used, the resistance value (resistance value between both ends) of one sense wire 560 is about 12.5 mΩ. The parallel resistance value of two sense wires 560 is about 6.25 mΩ, and the parallel resistance value of three sense wires 560 is about 4.16 mΩ.

[0063] Consider a sinusoidal drive in which a sinusoidal current with an effective value of 14 A (amperes) is supplied to a three-phase motor 30 as the coil current IL[i] of each phase. In this sinusoidal drive, SNSIf two sense wires 560 are used in [i] (i.e., “N A = 2”), then, from “14A × 6.25mΩ = 87.5mV”, the sense resistor R for each phase is SNS A sinusoidal voltage drop with an effective value of 87.5 mV occurs in [i], making it possible to detect the coil current IL[i] with enough accuracy to perform vector control.

[0064] At this time, the sense resistor R SNS The power consumption in [i] is about 1.23W because “14A×14A×6.25mΩ≒1.23”, and the sense resistor R SNS [1]~R SNS The total power consumption in [3] is about 3.7 W. This falls within the allowable power consumption (representing the maximum allowable power consumption within the package, also called package power) of a typical QFN package of about 5 mm square. Taking into account the balance between the accuracy required for detecting the coil current IL[i] and the package power, the number of sense wires 560 (i.e., N A value) or the diameter of the sense wire 560 may be adjusted.

[0065] In a typical motor drive system according to the first hypothetical configuration, a detection resistor (a resistor of about 10 mΩ) is externally connected to the semiconductor device to detect the coil current (particularly a relatively large coil current such as a coil current of 10 A or more). At this time, there is variation in the resistance value of the detection resistor externally connected to the semiconductor device, and the variation in the resistance value of the detection resistor deteriorates the detection accuracy of the coil current, and ultimately prevents the realization of the desired motor control (for example, vector control). In consideration of this, as described above, a sense resistor R equivalent to the above detection resistor is provided within the package of the semiconductor device 10. SNS [i] is formed of a sense metal body (here, one or more sense wires 560) that connects between the leads. This makes it possible to measure the resistance value of the sense metal body (here, one or more sense wires 560) in the shipping inspection process of the semiconductor device 10, and thereafter, the resistance value of the external terminal SNS P [i] and SNS NBy evaluating the potential difference between [i], it is possible to accurately detect the coil current IL[i] (the technology related to the calibration information will be described in detail in the embodiment described later). There is also the advantage that it becomes unnecessary to prepare a detection resistor as an external component.

[0066] As described above, the number of sense wires 560 in each phase (i.e., N A By adjusting the value of the sense resistor R SNS Alternatively or additionally, the resistance value of the sense resistor R SNS It is also possible to adjust the resistance value of [i]. These adjustments make it possible to ensure the required detection accuracy of the coil current IL[i] while taking into account package power.

[0067] The following second hypothetical configuration is also considered. In the second hypothetical configuration, the lead 530a and the semiconductor chip 510 are connected by a wire to the first chip, and the lead 530b and the semiconductor chip 510 are connected by a wire to the second chip, and the connection point between the semiconductor chip 510 and the wire to the first chip and the connection point between the semiconductor chip 510 and the wire to the second chip are connected on the semiconductor chip 510. Then, in the second hypothetical configuration, the series resistance of the wires to the first and second chips forms a sense resistor R SNS However, in the second virtual configuration, compared to the configuration shown in FIG. 10A etc., the sensing resistor R SNS The length of the wires required to form [i] will be longer (for example, several times longer), which will result in excessive power consumption in the wires. In addition, there is concern that the heat generated by the wires will have a large impact on the semiconductor integrated circuit.

[0068] Meanwhile, the lead-to-lead short-circuiting technique is applied to the semiconductor device 10 according to the embodiment EX1_1. By the lead-to-lead short-circuiting technique according to the embodiment EX1_1, the leads 530a and 530c are short-circuited and the leads 530b and 530d are short-circuited within the package without passing through the semiconductor chip 510. More specifically, the semiconductor device 10 according to the embodiment EX1_1 to which the lead-to-lead short-circuiting technique is applied includes a short-circuiting metal body SHORT that short-circuits the leads 530a and 530c within the package without passing through the semiconductor chip 510, as shown in Figs. 10A and 10B, etc. ac and a short-circuiting metal body SHORT for short-circuiting the leads 530b and 530d without passing through the semiconductor chip 510 in the package. bd 10A and 10B, for the sake of convenience, each short-circuit metal body is represented by a shaded area.

[0069] Short circuit metal body SHORT ac is a metal body that integrally connects the leads 530a and 530c. ac The short-circuiting metal body SHORT is made of the same material as the leads 530a and 530c. ac is represented by a shaded area, and the lead 530a or the lead 530c and the short-circuiting metal body SHORT ac Although the figure shows a boundary between the lead 530a and the shorting metal body SHORT ac The lead 530a and the lead 530c may be formed. It can also be considered that a single lead is configured by the integral metal plate, and the lead 530a and the lead 530c are formed by the single lead. ac The length (thickness) of the leads 530a and 530c (particularly, the metal portions 530_p4 of the leads 530a and 530c) in the Z-axis direction may be the same as the length (thickness) of the leads 530a and 530c (particularly, the metal portions 530_p4 of the leads 530a and 530c).

[0070] Short circuit metal body SHORT bd The same applies to the short-circuit metal body SHORT bdis a metal body that integrally connects the leads 530b and 530d. bd The short-circuiting metal body SHORT is made of the same material as the leads 530b and 530d. bd is represented by a shaded area, and the lead 530b or the lead 530d and the short-circuiting metal body SHORT bd Although the figure shows a boundary between the lead 530b and the shorting metal body SHORT bd The lead 530b and the lead 530d may be formed on the metal plate 530. It can also be considered that a single lead is formed by the single lead. bd The length (thickness) of the leads 530b and 530d (particularly, the metal portions 530_p4 of the leads 530b and 530d) in the Z-axis direction may be the same as the length (thickness) of the leads 530b and 530d (particularly, the metal portions 530_p4 of the leads 530b and 530d).

[0071] Short-circuit metal body in the Z-axis direction SHORT ac and SHORT bd The length (thickness) of each of the sense wires 560 is sufficiently larger (for example, 200 μm) than the diameter (for example, 30 μm) of each of the sense wires 560, and the length (thickness) of the shorting metal body SHORT ac and SHORT bd The length (width) of each of the shorting metal bodies SHORT ac and SHORT bd The resistance per unit length of each is N A A sense resistor R consisting of 560 sense wires SNS is sufficiently smaller (small enough to be ignored) than the resistance per unit length of [i]. As mentioned above, N A In addition, in the arrangement direction of the leads 530a to 530d, the short-circuiting metal body SHORT ac and SHORT bdThe length of each of the shorting metal bodies SHORT ac and SHORT bd The resistance value of each resistor (for example, about 10μΩ) is N A A sense resistor R consisting of 560 sense wires SNS The resistance value of [i] is much smaller than that of the short circuit metal body SHORT. ac and SHORT bd The significance of providing this will become clear after the test process is described below.

[0072] <<Example EX1_2>> Example EX1_2 will be described. In Example EX1_2, a method for accurately detecting a coil current using calibration information will be described. FIG. 16 is a flowchart of a test process for acquiring and recording the calibration information. The test process is incorporated into a part of the shipping inspection process of the semiconductor device 10.

[0073] In the test process, a test substrate SUB shown in FIG. 17 is prepared separately from the substrate 10 shown in FIG. TSET The semiconductor device 10 is placed in a test state. TSET A socket SCT for mounting the semiconductor device 10 is mounted on the test board SUB. In a test state, the semiconductor device 10 is mounted in the socket SCT. When the semiconductor device 10 is mounted in the socket SCT, each external terminal of the semiconductor device 10 is connected to the test board SUB through the socket SCT. TSET (The wiring pattern is not shown in FIG. 17.) IN [i]' and WR O The same wiring pattern as [i]' (see Figure 15: in Figure 15, i = 1) is TSET In the test state, the test substrate SUB TSET The wiring pattern of the external terminal OUT IN [i] and SNS P [i] is shorted and the external terminal OUT O [i] and SNS N[i] are short-circuited. Furthermore, in the test state, the sense resistors R SNS [i] is connected to the test board SUB so that it can supply the necessary current. TSET is formed.

[0074] In the test process, first, in step S11, the test substrate SUB TSET The semiconductor device 10 is mounted in the upper socket SCT, and in the next step S12, "1" is substituted for the variable i, and then the process proceeds to step S13. In step S13, in the test state, the sense resistor R SNS [i] for a given test current I TSET (i.e., external terminal OUT IN [i] and OUT O [i] Test current I TSET The test current I TSET is the external terminal OUT IN [i] to external terminal OUT O Let it be assumed that there is a direct current (for example, 10A) flowing towards [i].

[0075] In step S14 following step S13, a test circuit (not shown) in the semiconductor device 10 detects a sense resistor R SNS [i] is the test current I TSET External terminal SNS when is supplied P [i] and SNS N The voltage between [i] is V TEST [i] is detected as the voltage V TEST The calibration information of the i-th phase is obtained based on [i]. The test circuit is a circuit formed on the semiconductor chip 510, and operates effectively only in the test state. The calibration information of the i-th phase is obtained by performing the calibration of the test circuit and the test substrate SUB TSET The above circuit may be implemented in cooperation with the above circuit.

[0076] After step S14, in step S15, the test circuit checks whether or not "i=3". If "i=3", the process proceeds to step S17, but if "i=3" is not the case, in step S16, "1" is added to the variable i, and then the process returns to step S13, and the processes of steps S13 and S14 are repeated. Therefore, by the time step S17 is reached, the calibration information for the first to third phases has already been acquired. In step S17, the calibration information for the first to third phases is written into the calibration information storage unit 160 in FIG. 1, and then the test process in FIG. 16 is completed. The writing of each piece of calibration information is performed by the test circuit, or by a combination of the test circuit and the test substrate SUB TSET This is achieved in cooperation with the circuit above.

[0077] The calibration information holding unit 160 holds the calibration information of the first to third phases written in step S17 in a nonvolatile manner. The calibration information holding unit 160 is configured with a nonvolatile memory (for example, an OTPROM (one time programmable read only memory)). Alternatively, the calibration information of each phase may be held in a nonvolatile manner using a known method such as a Zener zap method, a polysilicon fuse method, or a laser cut method. In the test process of FIG. 16, the processing of steps S13 and S14 for "i=1", the processing of steps S13 and S14 for "i=2", and the processing of steps S13 and S14 for "i=3" may be executed in parallel.

[0078] The calibration information for phase i is the sensing resistor R SNS This is information that is set in advance based on the resistance value (actual resistance value) of [i].

[0079] Now, the sense resistor R SNS The design value of the resistance [i] is represented by the symbol "R IDEAL If the design is as designed, then in steps S13 and S14, TEST ×R IDEAL [i]” (for example, 10A × 10mΩ = 100mV) is applied to the external terminal SNS P [i] and SNSN However, the voltage V TEST [i] stands for "I TEST ×R IDEAL [i]” (for example, V TEST [i]=80mV). Sense resistor R SNS The actual resistance value of [i] (hereinafter referred to as the actual resistance value) is represented by the symbol “R REAL [i]” is “V TEST [i]=I TEST ×R REAL In the test process, the test current I TEST Since the value of is known, the voltage V TEST [i] to the actual resistance value R REAL [i] is known (for example, R REAL [i]=V TEST [i] / I TEST =80mV / 10A=8mΩ). In step S14 of FIG. 16, the actual resistance value R REAL Calibration information for phase i based on [i] is obtained.

[0080] After undergoing a shipping inspection process including a test process, the semiconductor device 10 is mounted on a substrate 10 as shown in FIG. 2 and then incorporated into a motor drive system SYS. The state in which the semiconductor device 10 is incorporated into the motor drive system SYS may be referred to as an actual operation state in order to clearly distinguish it from the above-mentioned test state. In this embodiment, except for the description of the test process, it is understood that the semiconductor device 10 is in an actual operation state. A method for detecting coil currents using calibration information in an actual operation state will be described. The method for detecting coil currents IL[1] to IL[3] using calibration information is the same for the first to third phases, so hereinafter, a method for detecting coil current IL[i] of the i-th phase will be described using variable i.

[0081] The calibration information for phase i is the actual resistance R REAL In this case, in the actual operating state, the current detection circuit 110 in FIG. P [i] and SNS N [i] is the actual resistance R REALBy dividing by [i], the detected current value VAL_IL[i] of the coil current IL[i] can be obtained.

[0082] In practice, for example, the calibration information for the i-th phase may be the calibration information for the ADC 112[i] in FIG. 3. In this case, in the actual operating state, D [i]=k REF ×k C [i]×S A Configure ADC112[i] so that D (i) includes quantization error. That is, in the actual operating state, the digital signal S representing the detected current value VAL_IL[i] D The value of [i] is a fixed, predetermined reference coefficient k REF (k REF = 1 is also acceptable) and the correction coefficient k C [i] and analog signal S A ADC112[i] is configured so that it matches the product of the value of [i] and the correction coefficient k C [i] is the calibration information for phase i, and “k C [i]=R IDEAL [i] / R REAL [i]". For example, "(R IDEAL [i],R REAL [i])=(10mΩ,8mΩ)” then “k C [i]=1,25”, and the actual resistance value R REAL [i] is the design value R IDEAL This eliminates the error in the detected current value VAL_IL[i] in the actual operating state caused by the detected current value VAL_IL[i] being lower than [i].

[0083] In this way, in the current detection circuit 110, the sense resistor R SNS The calibration information of the i-th phase, which is preset according to the actual resistance value of [i], and the external terminal SNS P [i] and SNS N The coil current IL[i] is detected based on the voltage between the connection points 542c and 542d for the i-phase (corresponding to the potential difference between the connection points 542c and 542d for the i-phase; see FIG. 10A, etc.). This makes it possible to accurately detect the coil current IL[i].

[0084] In addition, the sense resistor R SNS [1]~R SNS The current detection circuit 110 may be provided with a temperature detection circuit (not shown) for detecting the temperature [3]. The temperature detection circuit detects the temperatures of the first to third temperature detection locations in the package, and outputs a first temperature detection signal corresponding to the temperature of the first temperature detection location, a second temperature detection signal corresponding to the temperature of the second temperature detection location, and a third temperature detection signal corresponding to the temperature of the third temperature detection location. The current detection circuit 110 may also detect the coil current IL[i] of each phase by referring to the i-th temperature detection signal. This allows the sense resistor R SNS The temperature dependence of the resistance value of [i] is also taken into account, making it possible to detect the coil current IL[i] more accurately.

[0085] The first to third temperature detection points may be three different points. In this case, the i-th temperature detection point is a sense resistor R SNS It is recommended to select a location close to the location of [i]. However, the sensing resistor R SNS [1]~R SNS [3] Variations between temperatures can often be ignored, in which case the temperature detection location may be one. When there is one temperature detection location, the first to third temperature detection locations are interpreted as a common and single temperature detection location, and the first to third temperature detection signals are interpreted as a common and single temperature detection signal.

[0086] Sense resistor R SNS Since the temperature coefficient of [i] (for example, the temperature coefficient of the sense wire 560) is known, the current detection circuit 110 calculates the temperature SNS The detected current value VAL_IL[i] can be corrected based on the temperature coefficient of [i]. D [i]=k REF ×k C [i]×k TC [i]×S A 3. It is sufficient to configure ADC112[i] in FIG. 3 so that D [i] includes quantization error), where k TC[i] is a correction coefficient according to the temperature of the i-th temperature detection point. In the test process, the temperature of the i-th temperature detection point identified from the i-th temperature detection signal is the temperature T REF [i], while the temperature of the i-th temperature detection point identified from the i-th temperature detection signal in the actual operating state is T REAL [i] and the sense resistor R SNS The temperature coefficient of [i] (for example, the temperature coefficient of the sense wire 560) is k R If [i], then “k TC [i]=1 / (1+(T REAL [i]-T REF [i])·k R [i])” can be used.

[0087] <<Example EX1_3>> Example EX1_3 will be described. The specific shape of the lead 530 is arbitrary, but in example EX1_3, one specific example of the shape of the lead 530 will be given. FIG. 18 shows a plan view of the lead 530 according to example EX1_3. In FIG. 18, for the sake of simplicity, only two leads 530 provided on side SD1 are shown as representatives (the same applies to FIGS. 19 and 20 described later). The two leads 530 shown in FIG. 18 are connected to the external terminal OUT IN [i] and OUT O [i] can be configured. In this case, by applying the above-mentioned inter-lead short circuit technology, one lead 530 shown in Fig. 18 is integrally joined to another lead 530 not shown in Fig. 18, and the other lead 530 shown in Fig. 18 is integrally joined to yet another lead 530 not shown in Fig. 18, but the manner of such joining is omitted in Fig. 18 (the same applies to Figs. 19 and 20 described below). Below, the shape of one lead 530 will be described, but the other leads 530 have the same shape.

[0088] The lead 530 is a metal body in which metal portions 530_p1 to 530_p4 are integrated. The metal portions 530_p1, 530_p2, 530_p3, and 530_p4 are arranged in this order from the side on which the lead 530 is provided (side SD1 in FIG. 18) toward the semiconductor chip 510 (and therefore toward the die pad 520). The shapes of the metal portions 530_p1, 530_p2, 530_p3, and 530_p4 in a plan view are each approximately rectangular. However, the corners of the metal portion 530_p4 on the side closer to the semiconductor chip 510 and the die pad 520 are cut.

[0089] In FIG. 18, axis AX represents the central axis of the lead 530 along the arrangement direction of the metal parts 530_p1 to 530_p4. The lead 530 has a plane-symmetric structure with respect to a plane that includes the central axis AX and is parallel to the Z axis. In a direction perpendicular to the Z axis and the central axis AX, the length of the metal part 530_p2 is longer than the lengths of the metal parts 530_p1 and 530_p3, and the length of the metal part 530_p4 is longer than the lengths of the metal parts 530_p1 and 530_p3. Therefore, in the lead 530, recesses 530_p5 and 530_p6 are formed on both sides of the metal part 530_p2 in the arrangement direction of the metal parts 530_p1 to 530_p4, and the sealing resin 550 exists in the recesses 530_p5 and 530_p6 (the sealing resin 550 wraps around in the sealing process). Therefore, even if an external force is applied to the lead 530 in a direction away from the semiconductor chip 510 and the die pad 520, the lead 530 will not come out of the package. It can be said that the depressions 530_p5 and 530_p6 form a retaining portion.

[0090] The first and second leads 530 are connected to the external terminal OUT IN [i] and OUT OWhen configuring [i], as shown in FIG. 19, one end and the other end of the sense wire 560 connecting the first and second leads 530 are connected (wire-bonded) to the metal part 530_p4 in the first lead 530 and the metal part 530_p4 in the second lead 530, respectively, regardless of the number of sense wires 560. When the number of sense wires 560 connecting the first and second leads 530 is multiple (two in FIG. 19), it is desirable to make the lengths of the multiple sense wires 560 the same (however, as described above, they may be different). The multiple sense wires 560 are arranged at a distance from each other. There is no problem even if the multiple sense wires 560 come into contact with each other inside the package.

[0091] For example, when connecting the first and second leads 530 with two sense wires 560, different connection points CP1 and CP2 are set on the metal parts 530_p4 of each lead 530. Then, one end and the other end of one sense wire 560 are connected (wire bonding) to the connection point CP1 of the first lead 530 and the connection point CP1 of the second lead 530, respectively, and one end and the other end of the other sense wire 560 are connected (wire bonding) to the connection point CP2 of the first lead 530 and the connection point CP2 of the second lead 530, respectively. The setting position of the connection point CP1 on the metal part 530_p4 is common among the multiple leads 530, and the setting position of the connection point CP2 on the metal part 530_p4 is also common among the multiple leads 530. Therefore, the lengths of the two sense wires 560 can be made equal. For each metal portion 530_p4 of the first and second leads 530, the positions of the connection points CP1 and CP2 are offset from each other in the arrangement direction of the metal portions 530_p1 to 530_p4 (in the X-axis direction in Figure 19), and are also offset from each other in the arrangement direction of the first and second leads 530 (in the Y-axis direction in Figure 19).

[0092] When the first and second leads 530 are connected with a plurality of sensing wires 560, the metal parts 530_p4 of the first and second leads 530 may be extended toward the semiconductor chip 510 (and therefore toward the die pad 520) as necessary. FIG. 20 shows a plan view of the first and second leads 530 after such extension. In FIG. 20, the first and second leads 530 are connected with the first to fourth sensing wires 560. In the arrangement direction of the metal parts 530_p1 to 530_p4 (in the X-axis direction in FIG. 20), the first to fourth sensing wires 560 are spaced apart from each other and arranged in this order. The lengths of the first to fourth sensing wires 560 are made to match each other. However, as described above, the first to fourth sensing wires 560 may have a plurality of lengths, for example, the first and third sensing wires 560 may have a first length, and the second and fourth sensing wires 560 may have a second length (wherein the first and second lengths are different from each other). The first to fourth sensing wires 560 are disposed spaced apart from each other.

[0093] A configuration for making the lengths of the first to fourth sensing wires 560 the same will be described. First, different connection points CP1 to CP4 are set on the metal part 530_p4 of each lead 530. Then, one end and the other end of the j-th sensing wire 560 are connected (wire bonded) to the connection point CPj of the first lead 530 and the connection point CPj of the second lead 530, respectively. This is satisfied under each of the conditions "j=1", "j=2", "j=3" and "j=4".

[0094] The set position of the connection point CPj on the metal portion 530_p4 is common among the multiple leads 530. This is satisfied under each of the conditions of "j=1", "j=2", "j=3" and "j=4". For each metal portion 530_p4 of the first and second leads 530, the positions of the connection points CP1 to CP4 are shifted from each other in the arrangement direction of the metal portions 530_p1 to 530_p4 (in the X-axis direction in FIG. 20). However, for each metal portion 530_p4 of the first and second leads 530, the positions of the connection points CP1 and CP3 may be aligned with each other in the arrangement direction of the first and second leads 530 (in the Y-axis direction in FIG. 20), and the positions of the connection points CP2 and CP4 may be aligned with each other in the arrangement direction of the first and second leads 530 (in the Y-axis direction in FIG. 20). For each metal portion 530_p4 of the first and second leads 530, the positions of the connection points CP1 and CP3 are shifted from the positions of the connection points CP2 and CP4 in the arrangement direction of the first and second leads 530 (in the Y-axis direction in FIG. 20).

[0095] The extension of the metal portion 530_p4 refers to an extension in comparison with a standard and specified lead shape. The extension of the metal portion 530_p4 may be applied to all the leads 530. Alternatively, the extension of the metal portion 530_p4 may be applied only to the lead 530 to which the sense wire 560 is connected. In this case, the extension of the metal portion 530_p4 may be applied only to the lead 530 to which the sense wire 560 is connected (i.e., the external terminal OUT IN [i] or OUT OUT The length of the metal part 530_p4 of the lead 530 forming the lead [i] in the direction of the central axis AX is P [i] or SNS N [i] forming the lead 530 and the external terminal P GNDThe length in the direction of the central axis AX of the metal part 530_p4 of the lead 530 forming the side SD1 to SD4 is longer than the length in the direction of the central axis AX of the metal part 530_p4 of the lead 530 forming the side SD2. The extension of the metal part 530_p4 may be performed for each side. For example, it is possible to apply the above extension to each lead 530 provided on the side SD1 among the sides SD1 to SD4, while not applying the above extension to each lead 530 provided on the side SD2. In this case, the length in the direction of the central axis AX of the metal part 530_p4 of each lead 530 provided on the side SD1 is longer than the length in the direction of the central axis AX of the metal part 530_p4 of each lead 530 provided on the side SD2.

[0096] <<Example EX1_4>> Example EX1_4 will be described. In example EX1_4, each lead 530 has the shape shown in example EX1_3, and attention is focused on four leads 530A to 530D shown in Figs. 21 and 22. However, the configuration shown in Figs. 21 and 22 is a configuration according to the second embodiment described later, and is provided for comparison with the configuration according to the first embodiment to which the inter-lead short circuit technique is applied. The leads 530A, 530B, 530C, and 540D correspond to the leads 530a, 530b, 530c, and 540d shown in Fig. 10A. That is, the leads 530A, 530B, 530C, and 530D are connected to the external terminal OUT IN [i], OUT O [i], SNS P [i], SNS N[i] is a lead 530 for forming the lead 530. Along the side (any of sides SD1 to SD4) on which the leads 530A to 530D are provided, the leads 530C, 530A, 530B, and 530D are arranged adjacent to each other in this order. According to the method described with reference to FIG. 20, the lead 530A as the first lead 530 and the lead 530B as the second lead 530 are connected by four sense wires 560. In FIG. 21, 540C represents a chip-directed wire that connects the lead 530C and the semiconductor chip 510, and 540D represents a chip-directed wire that connects the lead 530D and the semiconductor chip 510. One end of the chip-directed wire 540C is connected (wire-bonded) to the connection point CP4 on the lead 530C, and one end of the chip-directed wire 540D is connected (wire-bonded) to the connection point CP4 on the lead 530D.

[0097] 22 is a conceptual diagram of the state around the leads 530A to 530D in the above-mentioned test state according to the second embodiment. TEST The wiring patterns formed on the lead 530A (see FIG. 17) include wiring patterns 610 and 620. In the test state, the external terminal OUT IN [i] is an external terminal OUT O [i] is an external terminal SNS which is connected to a part of the wiring pattern 620 via the second terminal 630B of the socket SCT and functions as an outer lead of the lead 530C P [i] is an external terminal SNS which is connected to another part of the wiring pattern 610 via the third terminal 630C of the socket SCT and functions as an outer lead of the lead 530D N [i] is connected via a fourth terminal 630D of the socket SCT to another part of the wiring pattern 620. In Fig. 22, each terminal of the socket SCT is conceptually indicated by a dashed ellipse.

[0098] 22 shows the state of leads 530A to 540D to which the lead short circuit technique is not applied. In the state shown in FIG. 22, leads 530A and 530C are not connected to each other within the package, and leads 530B and 530D are also not connected to each other. In FIG. 22, the two arrows shown at the terminals 630A and 630B indicate the test current I TEST When the test process is performed in the state of FIG. 22, the voltage V detected in step S14 of FIG. 16 is TEST [i] includes the voltage drop due to the contact resistance of the terminals 630A and 630B in addition to the voltage drop in the sense wire 560. The contact resistance of each of the terminals 630A and 630B may have a resistance value that cannot be ignored in comparison with the resistance of the sense wire 560, and varies widely. For example, the sense resistance R SNS While [i] is about 10 mΩ, the contact resistance of each of the terminals 630A and 630B may vary in the range of several mΩ to about 100 mΩ. The presence of such contact resistance prevents the acquisition of desired calibration information, and therefore makes it difficult to detect an accurate coil current IL[i] in an actual operating state.

[0099] Considering this, in the present embodiment including Example EX1_4, the lead-to-lead short circuit technique is applied to the semiconductor device 10. By the lead-to-lead short circuit technique according to Example EX1_4, the leads 530A and 530C are short-circuited and the leads 530B and 530D are short-circuited within the package without passing through the semiconductor chip 510. The lead-to-lead short circuit technique can be commonly applied to the first to third phases. The lead-to-lead short circuit technique for the i-th phase will be explained using a variable i. FIG. 23 shows a conceptual diagram of the state around the leads 530A to 530D in the above-mentioned test state to which the lead-to-lead short circuit technique is applied. The semiconductor device 10 according to Example EX1_4 to which the lead-to-lead short circuit technique is applied includes a short-circuiting metal body SHORT for short-circuiting the leads 530A and 530C within the package without passing through the semiconductor chip 510. AC and a short-circuiting metal body SHORT for short-circuiting the leads 530B and 530D without passing through the semiconductor chip 510 in the package. BDIn Fig. 23, for the sake of convenience, each short-circuit metal body is represented by a shaded area.

[0100] Short circuit metal body SHORT AC is a metal body that integrally connects the metal part 530_p4 of the lead 530A and the metal part 530_p4 of the lead 530C (see Example EX1_3 for the meaning of the metal part 530_p4: FIG. 18). AC is made of the same material as the leads 530A and 530C, and is an integral metal plate that connects the lead 530A and the short-circuiting metal body SHORT AC A shorting metal body SHORT in the Z-axis direction can be formed. AC The length (thickness) of the leads 530A and 530C (particularly, the metal portions 530_p4 of the leads 530A and 530C) in the Z-axis direction may be the same as the length (thickness) of the leads 530A and 530C (particularly, the metal portions 530_p4 of the leads 530A and 530C).

[0101] Short circuit metal body SHORT BD The same applies to the short-circuit metal body SHORT BD is a metal body that integrally connects the metal part 530_p4 of the lead 530B and the metal part 530_p4 of the lead 530D. BD is made of the same material as the leads 530B and 530D, and is an integral metal plate that connects the lead 530B and the short-circuiting metal body SHORT BD A shorting metal body SHORT in the Z-axis direction can be formed. BD The length (thickness) of the leads 530B and 530D (particularly, the metal portions 530_p4 of the leads 530B and 530D) in the Z-axis direction may be the same as the length (thickness) of the leads 530B and 530D (particularly, the metal portions 530_p4 of the leads 530B and 530D).

[0102] Metal short circuit in the Z-axis direction AC and SHORT BD The length (thickness) of the short-circuiting metal body SHORT in the direction of the central axis AX (see FIG. 18) is sufficiently larger (for example, 200 μm) than the diameter (for example, 30 μm) of each sense wire 560. AC and SHORT BDThe length (width) of each of the shorting metal bodies SHORT AC and SHORT BD The resistance per unit length of each is N A A sense resistor R consisting of 560 sense wires SNS [i] (in FIG. 23, the resistance value of the parallel connection circuit of the four sensing wires 560). A In addition, in the arrangement direction of the leads 530A to 530D, the short-circuiting metal body SHORT AC and SHORT BD The length of each of the shorting metal bodies SHORT AC and SHORT BD The resistance value of each resistor (for example, about 10μΩ) is N A A sense resistor R consisting of 560 sense wires SNS It is much smaller than the resistance value of [i] (for example, about 5 mΩ).

[0103] In FIG. 23, the four arrows shown at the terminals 630A to 630D indicate the test current I TEST When the test process is performed in the state of FIG. 23, the voltage V detected in step S14 of FIG. 16 is TEST [i] does not substantially include a voltage drop component due to the contact resistance of the terminals 630A and 630B. The potential at the lead 530A does not pass through the socket SCT but reaches the shorting metal body SHORT AC The potential at lead 530B is applied directly to lead 530C through the socket SCT, and the potential at lead 530B is applied to the shorting metal body SHORT BD This is because the input current IL[i] is directly applied to the lead 530D through the resistor 531. As a result, desirable calibration information can be obtained in the test process, and the coil current IL[i] can be accurately detected in the actual operating state.

[0104] When the lead-to-lead shorting technique is applied, the current (test current I TEST It is assumed that the coil current IL[i] flows not only through the leads 530A and 530B but also through the leads 530C and 530D, but this does not cause any particular problems. On the contrary, this has the advantage that the wiring pattern through which the coil current IL[i] flows can be expanded to cover two external terminals on the substrate SUB. In addition, if a wiring error or the like occurs during actual operation, P [i] or SNS N Even if [i] is disconnected from the substrate SUB, it is possible to correctly detect the coil current IL[i].

[0105] <<Example EX1_5>> Example EX1_5 will be described. An example of a process for manufacturing a semiconductor device 10 using the MAP (Molded Array Packaging) method will be briefly described. In the MAP method, a plurality of semiconductor chips are collectively sealed with a sealing resin on a lead frame, and then cut into individual semiconductor devices each having one semiconductor chip.

[0106] A lead frame (not shown) is prepared for manufacturing the semiconductor device 10. As is well known, the lead frame used in the MAP method is a molded metal sheet that includes a plurality of die pads 520 for forming a plurality of semiconductor devices 10, a lead metal portion that is the source of a plurality of leads 530, and a supporting metal portion that supports them. In a dicing process described later, the supporting metal portion is removed and unnecessary metal portions of the lead metal portion are removed to separate and form a plurality of leads 530.

[0107] Each step will be described. First, in a bonding step, each semiconductor chip 510 is bonded (die-bonded) onto each die pad 520 of the lead frame via a bonding material, and then, the chip-directed wires 540 and the sense wires 560 are connected to the necessary locations (wire-bonded). After that, in a sealing step, the lead frame is set in a molding die, and all the semiconductor chips 510 on the lead frame are collectively sealed together with the lead frame, the chip-directed wires 540, and the sense wires 560 by a sealing resin (corresponding to the sealing resin 550 in FIG. 7). Next, a plating layer is formed on the metal surface of each lead 530 that functions as an external terminal, and then, in a dicing step, the lead frame is cut along a predetermined dicing line to obtain individual semiconductor devices 10. Then, through a shipping inspection step including the above-mentioned test step (see FIG. 16), the semiconductor device 10 that can be incorporated into the motor drive system SYS is completed.

[0108] When the above-mentioned lead shorting technique is used, the above-mentioned lead frame is provided with each shorting metal body (SHORT ac and SHORT bd , or SHORT AC and SHORT BD ) should be included.

[0109] <<Example EX1_6>> An embodiment EX1_6 will be described. Below, the external terminal OUT IN The lead 530 (for example, 530a, 530A) forming the external terminal [i] may be referred to as the first target lead 530. O The lead 530 (e.g., 530b, 530B) forming [i] may be referred to as a second target lead 530 (see FIG. 10A and FIG. 21). P The lead 530 (e.g., 530c, 530C) forming the external terminal SNS NThe leads 530 (for example, 530d, 530D) forming [i] may be particularly referred to as a fourth target lead 530 (see FIGS. 10A and 21). Three sets (three phases) of the first to fourth target leads 530 are provided in the semiconductor device 10.

[0110] Although the above describes a configuration in which the first and second target leads 530 are adjacent to each other, i.e., a configuration in which no other leads 530 are interposed between the first and second target leads 530 (see Figures 10A and 21), it is also possible to interpose (place) one or more other leads 530 between the first and second target leads 530.

[0111] <<Second embodiment>> The second embodiment of the present disclosure will be described. The second embodiment and the third and fourth embodiments described later are based on the first embodiment, and for matters not specifically mentioned in the second to fourth embodiments, the description of the first embodiment also applies to the second to fourth embodiments unless there is a contradiction. When interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that are inconsistent between the first and second embodiments (the same applies to the third and fourth embodiments described later). As long as there is no contradiction, any two or more of the first to fourth embodiments may be combined.

[0112] As described above, the lead-to-lead shorting technique brings about extremely beneficial effects, but if the contact resistance between each terminal of the socket SCT and each external terminal of the semiconductor device when obtaining calibration information can be made sufficiently small, the application of the lead-to-lead shorting technique may be forgone.

[0113] That is, each shorting metal body may be omitted from the semiconductor device 10 according to the first embodiment. ac and SHORT bdmay be deleted (the same applies to the semiconductor device 10 in FIG. 13 or 14). Fig. 24 shows an example of a transparent plan view of the semiconductor device 10 according to the second embodiment, assuming that the sealing resin 550 is transparent. In Fig. 24, the number of sense wires 560 is one, but also in the second embodiment, the number of sense wires 560 may be any number equal to or greater than one.

[0114] From the configuration of the semiconductor device 10 shown in FIG. 10A and FIG. 10B, the short-circuiting metal body SHORT ac and SHORT bd In the case of deleting the side on which the leads 530a and 530b are provided (i.e., the external terminal OUT IN [1] and OUT O [1] is provided) and the side where the lead 530c or 530d is provided (i.e., the side where the external terminal SNS P [1] or SNS N [1] may be provided on different sides of the first phase. For example, it is possible to provide leads 530a and 530b on side SD1, while providing leads 530c and 530d on side SD3, or to provide leads 530c and 530d on sides SD3 and SD4, respectively, for the first phase. The same is true for the second and third phases.

[0115] Moreover, the semiconductor device 10 shown in FIGS. 21 and 22 is an example of the semiconductor device 10 according to the second embodiment.

[0116] <<Third embodiment>> A third embodiment of the present disclosure will be described.

[0117] In the third embodiment, the sensing resistor R SNS [i] is formed by a connecting metal part, not a sense wire. Fig. 25 shows a connecting metal part 570, which is an example of the connecting metal part. In Fig. 25, for the sake of convenience, the connecting metal part is represented by a shaded area (the same applies to Figs. 26 and 27 described later). The connecting metal part is a sensing resistor R SNS25 is an example of a metal body for sensing to form [i]. The connecting metal part is formed integrally with the first and second target leads 530 (leads 530a and 530b in FIG. 25) and connects the first and second target leads 530 within the package. The connecting metal part is made of the same material as the first and second target leads 530, and the first and second target leads 530 and the connecting metal part may be formed from an integral metal plate.

[0118] 25, a connecting metal part 570 formed integrally with a lead 530a, which is an example of a first target lead 530, and a lead 530b, which is an example of a second target lead 530, is provided in place of a sense wire 560 (see FIG. 10A). As described in the first embodiment, the leads 530a and 530b are two leads 530 adjacent to each other, and the leads 530a and 530b connect the external terminal OUT IN [i] and OUT O [i] is formed.

[0119] The connecting metal part 570 may be a metal plate having a thickness (length in the Z-axis direction) that is the same as or approximately the same as the thickness (length in the Z-axis direction) of the leads 530a and 530b, and the thickness is, for example, 200 μm. When the shape shown in Fig. 18 is adopted as the shape of each lead 530a, the connecting metal part 570 can be a metal plate that connects the metal part 530_p4 of the lead 530a and the metal part 530_p4 of the lead 530b along the arrangement direction of the leads 530a and 530b as shown in Fig. 26. In this case, it is preferable that the connecting metal part 570 has a thickness (length in the Z-axis direction) that is the same as or approximately the same as the thickness (length in the Z-axis direction) of each metal part 530_p4 of the leads 530a and 530b.

[0120] When the package of the semiconductor device 10 is a QFN package having a size of about 5 mm square, depending on the shape and size of the leads 530a and 530b and the connecting metal part 570, the external terminal OUT IN [i] via the connecting metal part 570 to the external terminal OUT OThe resistance component up to [i] is about several hundred μΩ. If the resistance component is 0.35 mΩ, when a current of 100 A flows through it, a voltage drop of 35 mV occurs at the external terminal OUT IN [i] and OUT O For this reason, the configuration shown in FIG. 25 allows a current of about 100 A or more to flow through the external terminal OUT IN [i] and OUT O [i] This is particularly useful in systems where

[0121] In addition, the first and second target leads 530 connected by the connecting metal portion do not have to be adjacent to each other. For example, as shown in FIG. 27, the leads 530a' and 530b' that are not adjacent to each other may be connected by a connecting metal portion 570'. The lead 530a' is connected to the external terminal OUT IN [i] (i.e., the first target lead 530), and the lead 530b' is an example of the external terminal OUT O 27 is an example of a lead 530 (i.e., a second target lead 530) that forms [i]. The leads 530a' and 530b' are provided on a common side (any of the sides SD1 to SD4) of the semiconductor device 10, but one or more other leads 530 (two other leads 530 in FIG. 27) are interposed (placed) between the leads 530a' and 530b' on the common side. A connecting metal part 570' is formed integrally with the leads 530a' and 530b' within the package, bypassing these other leads 530.

[0122] The connecting metal part 570' may be a metal plate having a thickness (length in the Z-axis direction) that is the same as or approximately the same as that of the leads 530a' and 530b', and the thickness is, for example, 200 μm. By increasing or decreasing the number of other leads 530 provided between the leads 530a' and 530b', the sense resistance R SNS The resistance value of the sense resistor R[i] can be increased or decreased by adjusting the width of the connecting metal part 570′ (the length of the connecting metal part 570′ in the direction in which the leads 530a′ and 530b′ are arranged and in the direction perpendicular to the Z-axis).SNS The resistance value of [i] can be adjusted. Since it may be difficult to wire bond each lead 530 provided between the leads 530a' and 530b' to the semiconductor chip 510, each lead 530 provided between the leads 530a' and 530b' may be a lead 530 that is not connected to the semiconductor chip 510 (i.e., the lead 530 may be a lead 530 that constitutes an NC terminal).

[0123] Thus, in the semiconductor device 10 of the third embodiment, the connecting metal portion (570, 570') is arranged around the semiconductor chip 510 and the die pad 520, and the first and second target leads 530 are connected by the connecting metal portion (570, 570') without going through the semiconductor chip 510.

[0124] In the manufacturing process of the semiconductor device 10, the connecting metal portion (570, 570') is included in the lead frame described above. That is, a lead frame including a metal portion in which the first and second target leads 530 and the connecting metal portion (570, 570') are integrated is prepared, and an individual semiconductor device 10 is completed through the above-mentioned bonding process, sealing process, dicing process, and shipping inspection process.

[0125] Incidentally, the above-mentioned lead short circuit technique may or may not be applied to the semiconductor device 10 according to the third embodiment. Figures 25 to 27 ignore whether or not the lead short circuit technique is applied.

[0126] <<Fourth embodiment>> A fourth embodiment of the present disclosure will be described.

[0127] The channel types of FETs (field effect transistors) shown in each embodiment are examples, and the configuration of a circuit including FETs may be modified, such as changing an N-channel FET to a P-channel FET, or changing a P-channel FET to an N-channel FET.

[0128] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0129] The application of the semiconductor device (10) according to the present disclosure is not limited to the application of driving a three-phase motor. The semiconductor device (10) according to the present disclosure can be applied to the application of detecting any type of current flowing through any wiring (for example, a current flowing through a coil of a single-phase motor, or a current flowing through a switching element, coil, or output terminal of a switching power supply circuit).

[0130] <<Additional Notes>> The technical ideas embodied in the above-described embodiments will now be considered.

[0131] A semiconductor device (10) according to one aspect of the present disclosure includes a semiconductor chip (510) on which a semiconductor integrated circuit is formed, a plurality of leads (530) arranged around the semiconductor chip, two or more chip-directed wires (540) connecting two or more leads included in the plurality of leads to the semiconductor chip, and a package having a sealing resin (550) that seals the semiconductor chip, the plurality of leads, and the two or more chip-directed wires such that a portion of each of the plurality of leads is exposed from the sealing resin, and the semiconductor integrated circuit includes a sense resistor (R SNSa current detection circuit (110) configured to detect a current to be detected (IL[i]) flowing through a sense resistor based on a voltage drop in the sense resistor, and main circuits (120 and 130) configured to perform a predetermined operation based on a detection result of the current to be detected, wherein the plurality of leads include first and second leads (530a and 530b, 530A and 530B, or 530a' and 530b') connected to one end and the other end of the sense resistor, and the sense resistor is formed within the package using a sense metal body (560, 570 or 570') that connects the first and second leads without going through the semiconductor chip (first configuration).

[0132] In the configuration example of Fig. 1, the main circuit is composed of a control circuit 120 and a pre-driver circuit 130, but in the present disclosure, the main circuit is not limited to this, and the operation performed by the main circuit is arbitrary. For example, a step-down switching power supply circuit is assumed in which an input voltage is switched by an output transistor to generate a rectangular wave switching voltage, and the switching voltage is rectified and smoothed by a rectifying and smoothing circuit consisting of a coil and an output capacitor to generate an output voltage, and the semiconductor device of the present disclosure is used as a component of the step-down switching power supply circuit. In this case, the current flowing through the output transistor or the current flowing through the coil of the rectifying and smoothing circuit may be treated as the current to be detected, and the main circuit in the semiconductor device may perform switching of the output transistor as a predetermined operation based on the detection result of the current to be detected.

[0133] In the semiconductor device of the first configuration described above, specifically, for example (see Figures 10A, 23, etc.), the multiple leads include the first and second leads and third and fourth leads (530c and 530d, or 530C and 530D) to be short-circuited, respectively, on a substrate (SUB) on which the semiconductor device is to be mounted, the two or more chip-directed wires include a first chip-directed wire (540c or 540C) connecting the third lead to the semiconductor chip and a second chip-directed wire (540d or 540D) connecting the fourth lead to the semiconductor chip, and the current detection circuit may be configured (second configuration) to detect the current to be detected based on a potential difference between a connection point (542c) between the semiconductor chip and the wire to the first chip and a connection point (542d) between the semiconductor chip and the wire to the second chip.

[0134] In the semiconductor device relating to the above-mentioned second configuration, the current detection circuit may be configured (third configuration) to detect the current to be detected based on calibration information preset in accordance with the actual resistance value of the sensing metal body and the potential difference.

[0135] In the semiconductor device according to the third configuration, the current detection circuit may be configured (fourth configuration) to detect the current to be detected by also referring to a signal corresponding to the temperature inside the package.

[0136] In the semiconductor device according to any one of the above first to fourth configurations, the sensing metal body may be configured with one or more sensing wires (fifth configuration).

[0137] In the semiconductor device relating to the above-mentioned fifth configuration, a configuration (sixth configuration) may be further provided within the package, a first short-circuiting metal body that short-circuits between the first and third leads without passing through the semiconductor chip, and a second short-circuiting metal body that short-circuits between the second and fourth leads without passing through the semiconductor chip.

[0138] In the semiconductor device according to the sixth configuration, the resistance value of each short-circuiting metal body may be smaller than the resistance value of the sensing metal body formed of the one or more sensing wires (seventh configuration).

[0139] In the semiconductor device according to any one of the first to fourth configurations, the sense resistor as the sense metal body may be formed by a connecting metal portion integrally formed with the first and second leads within the package (eighth configuration).

[0140] In the semiconductor device according to any of the above first to eighth configurations, the first and second leads may be two leads adjacent to each other, or one or more other leads may be interposed between the first and second leads (ninth configuration).

[0141] A motor drive system (SYS) according to one aspect of the present disclosure includes a three-phase motor (30) having first to third coils (L[1] to L[3]), an inverter circuit (20) configured to supply current to each of the coils, and a semiconductor device (10) according to any of the first to ninth configurations described above, wherein the current detection circuit (110) in the semiconductor device includes first to third sense resistors (R SNS [1]~R SNS The semiconductor device is configured to detect first to third currents to be detected (IL[1] to IL[3]) flowing through the first to third coils based on a voltage drop in the first to third sense resistors, the first to third currents to be detected are currents flowing through the first to third coils, three sets of the first and second leads and the sense metal body are provided in the semiconductor device, and each sense resistor is formed using the sense metal body of each set, and the main circuit (120 and 130) in the semiconductor device is configured to control the inverter circuit based on the detection results of the first to third currents to be detected (tenth configuration).

[0142] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course. [Explanation of symbols]

[0143] SYS Motor drive system 10 Semiconductor device 20 Inverter circuit 30 Three-phase motor 40 Upper Circuit 110 Current detection circuit 120 Control circuit 130 Pre-driver circuit 510 Semiconductor Chip 520 Die Pad 530 Leads 540 Chip Wire 550 Sealing resin 560 Sense Wire 570, 570' Connecting metal part SHORT ac , SHORT bd SHORT AC , SHORT BD Shorting metal body

Claims

1. A semiconductor chip on which a semiconductor integrated circuit is formed; a plurality of leads arranged around the semiconductor chip; two or more chip-directed wires connecting two or more leads included in the plurality of leads to the semiconductor chip; a package having a sealing resin and sealing the semiconductor chip, the leads, and the two or more chip-directed wires such that a portion of each of the leads is exposed from the sealing resin; the semiconductor integrated circuit includes a current detection circuit configured to detect a current to be detected flowing through a sense resistor based on a voltage drop across the sense resistor, and a main circuit configured to perform a predetermined operation based on a detection result of the current to be detected; the plurality of leads include first and second leads connected to one end and the other end of the sense resistor, and also include third and fourth leads to be short-circuited with the first and second leads, respectively, on a substrate on which the semiconductor device is to be mounted; forming the sense resistor using a sense metal body that connects the first and second leads without passing through the semiconductor chip in the package; the two or more chip-directed wires include a first chip-directed wire that connects the third lead and the semiconductor chip and a second chip-directed wire that connects the fourth lead and the semiconductor chip; The current detection circuit is configured to detect the detection target current based on a potential difference between a connection point between the semiconductor chip and the wire to the first chip and a connection point between the semiconductor chip and the wire to the second chip. Semiconductor device.

2. The current detection circuit is configured to detect the detection target current based on calibration information preset according to an actual resistance value of the sensing metal body and the potential difference. The semiconductor device according to claim 1 .

3. The current detection circuit is configured to detect the target current by also referring to a signal corresponding to the temperature inside the package. The semiconductor device according to claim 2 .

4. The sensing metal body is composed of one or more sensing wires.

4. The semiconductor device according to claim 1.

5. In the package, a first short-circuiting metal body for short-circuiting the first and third leads without passing through the semiconductor chip, and a second short-circuiting metal body for short-circuiting the second and fourth leads without passing through the semiconductor chip are further provided. The semiconductor device according to claim 4.

6. The resistance value of each short-circuiting metal body is smaller than the resistance value of the sensing metal body constituted by the one or more sensing wires. The semiconductor device according to claim 5 .

7. The sensing resistor as the sensing metal body is formed by a connecting metal portion formed integrally with the first and second leads in the package.

4. The semiconductor device according to claim 1.

8. The first and second leads are two leads adjacent to each other, or one or more other leads are interposed between the first and second leads. The semiconductor device according to any one of claims 1 to 7.

9. a three-phase motor having first to third coils; an inverter circuit configured to supply current to each of the coils; A semiconductor device according to any one of claims 1 to 8, the current detection circuit in the semiconductor device is configured to detect first to third detection target currents flowing through first to third sense resistors based on voltage drops in the first to third sense resistors; the first to third currents to be detected are currents flowing through the first to third coils, In the semiconductor device, three sets of the first and second leads and the sense metal body are provided, and each sense resistor is formed using the sense metal body of each set; The main circuit in the semiconductor device is configured to control the inverter circuit based on the detection results of the first to third detection target currents. Motor drive system.

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