Semiconductor cooling chip and its manufacturing method

Abstract

A semiconductor cooling chip and a manufacturing method thereof are provided, the method including the steps of: providing a semiconductor cooling assembly including a first insulating and thermally conductive layer, a second insulating and thermally conductive layer disposed on an opposite side of the first thermally conductive layer, and a semiconductor layer disposed between the first and second insulating and thermally conductive layers, wherein the side of the semiconductor cooling assembly where the first insulating and thermally conductive layer is provided is a low-temperature side and the side of the semiconductor cooling assembly where the second insulating and thermally conductive layer is provided is a high-temperature side; and forming a packaging structure to cover a sidewall of the semiconductor cooling assembly and to define a first groove together with the first insulating and thermally conductive layer, thereby obtaining the semiconductor cooling chip.

Description

[Technical field]

[0001] The present application relates to the technical field of cooling devices, and in particular to a semiconductor cooling chip and a method for manufacturing the same. [Background technology]

[0002] The semiconductor cooling chip is a new cooler that uses the Peltier effect to achieve the purpose of cooling. When a direct current passes through a thermocouple made of two different semiconductor materials connected in series, the two ends of the thermocouple can absorb and release heat, respectively, to achieve cooling. The semiconductor cooling chip has the functions of refrigeration, cooling, and temperature maintenance, and can realize point-by-point temperature control. It also has the advantages of small volume, no mechanical transmission parts, no noise, fast cooling and heat conversion, high reliability, long service life, no environmental pollution, small size and fine construction, and the ability to switch between cooling and heating.

[0003] However, current semiconductor cooling chips and their manufacturing methods still have room for improvement. Summary of the Invention

[0004] The present application has been made based on the inventor's discoveries and findings regarding the following facts and problems.

[0005] The inventor found that the current semiconductor cooling chip has a problem of low overload resistance. Specifically, the current semiconductor cooling chip is generally composed of a ceramic sheet 30 and a semiconductor die 40 sandwiched between two ceramic sheets 30 (see FIG. 4), and often uses 703 or 704 white silicone rubber 60 to seal and protect the periphery of the semiconductor cooling chip (see FIG. 5). During the actual assembly and use of the semiconductor cooling chip, in order to effectively exert the cooling effect, the semiconductor cooling chip needs to be fixed to the radiator with screws and clamps, and since both the ceramic sheet and the semiconductor die are brittle and prone to cracking, if the force received during assembly is slightly uneven, it is very easy to cause the ceramic sheet and the semiconductor die to crack, causing product failure and affecting the product yield and cooling effect.

[0006] The present application aims to alleviate or solve, at least to some extent, at least one of the above problems.

[0007] In one aspect of the present application, the present application provides a method for manufacturing a semiconductor cooling chip. The method includes the steps of: providing a semiconductor cooling assembly including a first insulating and thermally conductive layer, a second insulating and thermally conductive layer disposed on the opposite side of the first insulating and thermally conductive layer, and a semiconductor layer disposed between the first insulating and thermally conductive layer, the side of the semiconductor cooling assembly on which the first insulating and thermally conductive layer is disposed being a low-temperature side, and the side of the semiconductor cooling assembly on which the second insulating and thermally conductive layer is disposed being a high-temperature side; and forming a package structure to cover a sidewall of the semiconductor cooling assembly and to form a first groove together with the first insulating and thermally conductive layer to obtain the semiconductor cooling chip. This effectively improves the overload resistance of the semiconductor cooling chip in a simple manner, so that the semiconductor cooling chip can withstand pressures of 1000 PSI or more, and significantly reduces the risk of the semiconductor cooling chip cracking during the assembly process, so that the semiconductor cooling chip has a high product yield and good cooling effect.

[0008] In one aspect of the present application, the present application provides a method for manufacturing a semiconductor cooling chip, the method including the steps of: providing a semiconductor cooling assembly including a first insulating and thermally conductive layer, a second insulating and thermally conductive layer disposed on an opposite side of the first thermally conductive layer, and a semiconductor layer between the first insulating and thermally conductive layer and including a plurality of thermocouples connected in series and electrically connected to a conductive wire, the side of the semiconductor cooling assembly on which the first insulating and thermally conductive layer is provided being a low-temperature side, and the side of the semiconductor cooling assembly on which the second insulating and thermally conductive layer is provided being a high-temperature side; forming a package structure to cover a sidewall of the semiconductor cooling assembly and to define a first groove together with the first insulating and thermally conductive layer, and allowing the conductive wire to penetrate the package structure and extend to the outside of the package structure to obtain the semiconductor cooling chip. In this way, the overload resistance of the semiconductor cooling chip can be effectively improved in a simple manner, so that the semiconductor cooling chip can withstand pressure of more than 1000 PSI, and the risk of the semiconductor cooling chip cracking during the assembly process can be significantly reduced, so that the semiconductor cooling chip has a high product yield and good cooling effect. In another aspect of the present application, the present application provides a semiconductor cooling chip. The semiconductor cooling chip includes a semiconductor cooling assembly including a first insulating thermally conductive layer, a second insulating thermally conductive layer disposed on the opposite side of the first thermally conductive layer, and a semiconductor layer disposed between the first insulating thermally conductive layer and the second insulating thermally conductive layer, the semiconductor cooling assembly including a side where the first insulating thermally conductive layer is disposed is a low temperature side and a side where the second insulating thermally conductive layer is disposed is a high temperature side, and a package structure that covers a sidewall of the semiconductor cooling assembly and forms a first groove together with the first insulating thermally conductive layer. As a result, the packaging structure can realize sealing and protection for the semiconductor cooling assembly, and effectively improve the overload resistance ability of the semiconductor cooling chip, so that the semiconductor cooling chip can withstand pressure of more than 1000 PSI, and the risk of the semiconductor cooling chip being cracked during the assembly process can be significantly reduced, so that the semiconductor cooling chip has high product yield and good cooling effect.

[0009] In another aspect of the present application, the present application provides a semiconductor cooling chip, the semiconductor cooling chip including a semiconductor cooling assembly including a first insulating and thermally conductive layer, a second insulating and thermally conductive layer disposed on an opposite side of the first thermally conductive layer, and a semiconductor layer located between the first insulating and thermally conductive layer and including a plurality of thermocouples connected in series and electrically connected to a conductive wire, the semiconductor cooling assembly including a low-temperature side on which the first insulating and thermally conductive layer is disposed and a high-temperature side on which the second insulating and thermally conductive layer is disposed, and a packaging structure covering a sidewall of the semiconductor cooling assembly and constituting a first groove together with the first insulating and thermally conductive layer, the conductive wire penetrating the packaging structure and extending to the outside of the packaging structure. As a result, the packaging structure can realize sealing and protection for the semiconductor cooling assembly, and effectively improve the overload resistance ability of the semiconductor cooling chip, so that the semiconductor cooling chip can withstand pressure of more than 1000 PSI, and the risk of the semiconductor cooling chip being cracked during the assembly process can be significantly reduced, so that the semiconductor cooling chip has high product yield and good cooling effect. [Brief description of the drawings]

[0010] The above and / or additional aspects and advantages of the present application will become apparent and will be readily understood by reference to the following detailed description of the embodiments with reference to the drawings, in which:

[0011] [Figure 1] 1 shows a schematic configuration diagram of a semiconductor cooling chip according to an embodiment of the present application. [Diagram 2] 1 shows a schematic cross-sectional view of a semiconductor cooling chip according to an embodiment of the present application. [Diagram 3] 1 shows a schematic cross-sectional view of a semiconductor cooling chip according to another embodiment of the present application. [Figure 4] FIG. 1 shows a schematic configuration diagram of a portion of a conventional semiconductor cooling chip. [Diagram 5] FIG. 1 shows a schematic configuration diagram of a conventional semiconductor cooling chip. [Figure 6]1 shows a flowchart of a method for manufacturing a semiconductor cooling chip according to an embodiment of the present application. [Figure 7] 1 shows a schematic cross-sectional view of a semiconductor cooling chip according to an embodiment of the present application. [Figure 8] 1 shows a schematic cross-sectional view of a semiconductor cooling chip according to another embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments of the present application will be described in detail, and examples of the embodiments are shown in the drawings, and the same or similar reference numerals throughout indicate the same or similar parts, or parts having the same or similar functions. The embodiments described below with reference to the drawings are illustrative and are only for interpreting the present application, and should not be understood as limiting the present application.

[0013] In one aspect of the present application, the present application provides a method for manufacturing a semiconductor cooling chip. According to an embodiment of the present application, as shown in FIG. 6, the method includes the following steps S100 and S200:

[0014] At S100, a semiconductor cooling assembly is provided.

[0015] According to an embodiment of the present application, in this step, a semiconductor cooling assembly is provided, which includes a first insulating and thermally conductive layer, a second insulating and thermally conductive layer disposed on the opposite side of the first thermally conductive layer, and a semiconductor layer disposed between the first insulating and thermally conductive layer and the second insulating and thermally conductive layer, wherein the side of the semiconductor cooling assembly where the first insulating and thermally conductive layer is provided is a low temperature side, and the side of the semiconductor cooling assembly where the second insulating and thermally conductive layer is provided is a high temperature side.

[0016] Furthermore, the semiconductor layer includes a plurality of thermocouples connected in series and electrically connected to a lead wire, and in use, a direct current can be applied to the semiconductor cooling assembly through the lead wire. As can be understood by those skilled in the art, the plurality of thermocouples in the semiconductor layer are connected in series through copper current-conducting sheets sintered inside the insulating thermally conductive layer, and the lead wire is connected to the outermost copper current-conducting sheet (i.e., the copper current-conducting sheet closest to the edge of the insulating thermally conductive layer), thereby realizing the electrical connection between the thermocouples and the lead wire. The manner of realizing the series connection of the thermocouples and the manner of electrically connecting the thermocouples to the lead wire may be the same as that of a typical semiconductor cooling chip.

[0017] According to an embodiment of the present application, in this step, a semiconductor cooling assembly is provided. According to an embodiment of the present application, the semiconductor cooling assembly includes a first insulating and thermally conductive layer, a second insulating and thermally conductive layer disposed on the opposite side of the first thermally conductive layer, and a semiconductor layer located between the first insulating and thermally conductive layer and including a plurality of thermocouples connected in series, the side of the semiconductor cooling assembly where the first insulating and thermally conductive layer is provided is the low temperature side, and the side of the semiconductor cooling assembly where the second insulating and thermally conductive layer is provided is the high temperature side. The thermocouples are electrically connected to a conductor, and in use, a direct current can be applied to the semiconductor cooling assembly through the conductor. As can be understood by those skilled in the art, the plurality of thermocouples in the semiconductor layer are connected in series through a copper current conducting sheet sintered inside the insulating and thermally conductive layer, and the conductor is connected to the outermost copper current conducting sheet (i.e., the copper current conducting sheet closest to the edge of the insulating and thermally conductive layer), thereby realizing the electrical connection between the thermocouples and the conductor. A method for connecting the thermocouples in series and a method for electrically connecting the thermocouples to the conductors may be a connection method used in a general semiconductor cooling chip.

[0018] The manufacturing process of the semiconductor cooling assembly is not particularly limited, and a person skilled in the art can design it based on the general manufacturing process of the semiconductor cooling chip, so the description will be omitted here.

[0019] The specific constituent materials of the first insulating thermally conductive layer and the second insulating thermally conductive layer are not particularly limited. For example, the first insulating thermally conductive layer and the second insulating thermally conductive layer may each independently include at least one of a ceramic sheet, a glass sheet, an aluminum nitride sheet, and an aluminum sheet having an oxide film.

[0020] In S200, a package structure is formed to obtain a semiconductor cooling chip.

[0021] According to an embodiment of the present application, in this step, a package structure is formed to obtain a semiconductor cooling chip (see FIG. 1). According to an embodiment of the present application, the formed package structure covers the sidewall of the semiconductor cooling assembly, and forms a first groove together with the first insulating and thermally conductive layer, i.e., the package structure forms the first groove together with the cold side surface of the semiconductor cooling assembly. In this way, during assembly, a part of the package structure higher than the first insulating and thermally conductive layer comes into contact with the clamp, and the pressure of the clamp is mainly applied to the package structure, not to the semiconductor cooling assembly, so that the overload resistance of the semiconductor cooling chip can be effectively improved and the risk of the semiconductor cooling chip being cracked can be significantly reduced, so that the semiconductor cooling chip has a high product yield and good cooling effect. Since the package structure forms the first groove together with the first insulating and thermally conductive layer, i.e., at least a part of the first insulating and thermally conductive layer is exposed to the outside, the cooling effect of the semiconductor cooling chip can be guaranteed.

[0022] Furthermore, the conductive wire penetrates the package structure and extends to the outside of the package structure (see FIG. 1, i.e., the conductive wire electrically connected to the thermocouple penetrates the package structure and is exposed to the outside of the package structure, so that an external control circuit applies a direct current to the semiconductor cooling chip via the conductive wire).

[0023] According to an embodiment of the present application, in this step, a package structure is formed to obtain a semiconductor cooling chip (see FIG. 1). According to an embodiment of the present application, the formed package structure covers the sidewall of the semiconductor cooling assembly, and forms a first groove together with the first insulating and thermally conductive layer, i.e., the package structure forms a first groove together with the cold side surface of the semiconductor cooling assembly, and the conductive wire penetrates the package structure and extends to the outside of the package structure (see FIG. 1, i.e., the conductive wire electrically connected to the thermocouple penetrates the package structure and is exposed to the outside of the package structure, so that the external control circuit applies a direct current to the semiconductor cooling chip through the conductive wire). Thus, during assembly, the part of the package structure higher than the first insulating and thermally conductive layer contacts the clamp, and the pressure of the clamp is applied mainly to the package structure, not to the semiconductor cooling assembly, so that the overload resistance ability of the semiconductor cooling chip can be effectively improved and the risk of the semiconductor cooling chip being cracked can be significantly reduced, so that the semiconductor cooling chip has a high product yield and good cooling effect. The package structure forms a first groove together with the first insulating and thermally conductive layer, that is, at least a portion of the first insulating and thermally conductive layer is exposed to the outside, so that the cooling effect of the semiconductor cooling chip can be guaranteed.

[0024] According to an embodiment of the present application, the package structure may be formed by injection molding and cooling solidification. Specifically, firstly, the semiconductor cooling assembly is put into a mold. Then, the material for forming the package structure is heated to a molten state, and the temperature and pressure of the injection molding are adjusted, and the molten material is injected into the mold, and the package structure is formed by cooling solidification after the injection molding is completed.

[0025] According to the embodiment of the present application, the material forming the package structure includes at least one of polyamide hot melt adhesive, polyolefin hot melt adhesive, and reactive polyurethane hot melt adhesive. The above material has advantages such as insulation, temperature resistance, impact resistance, vibration prevention, moisture proof, waterproof, dustproof, chemical corrosion resistance, etc., has a wide temperature resistance range (-40℃~150℃), low temperature flexibility, and high temperature creep resistance. The first insulating thermal conductive layer and the second insulating thermal conductive layer can be firmly bonded, so that the formed package structure has excellent performance, and the semiconductor cooling chip can be applied to various harsh manufacturing and use environments. And the above material can be injection molded under low temperature and low pressure conditions, has a short solidification time, a simple process, and can significantly shorten the manufacturing cycle. In addition, the package structure formed by injection molding is hard and not easily broken, and improves the protective effect on the semiconductor cooling assembly. In addition, the above material is suitable for packaging electronic products (i.e., the above-mentioned semiconductor cooling assembly) and does not cause internal damage to the electronic product.

[0026] The inventor also discovered that the silicone rubber used in the conventional sealing method of semiconductor cooling chips, such as 703 or 704 white silicone rubber, has a complete solidification time of more than 12 hours, which lengthens the manufacturing cycle of the product, and the silicone rubber is soft and easily damaged, providing poor protection for the semiconductor die. The package structure of the present application has low temperature flexibility and high temperature creep resistance, and the material can be injection molded under low temperature and low pressure conditions, with a short solidification time and simple process.

[0027] According to an embodiment of the present application, the mold used in the injection molding process has a cavity with a predetermined shape. After the semiconductor cooling assembly is placed into the mold cavity, the semiconductor cooling assembly occupies a part of the cavity, and the above-mentioned packaging material is injected into the remaining part of the cavity to form a packaging structure. The shape of the part of the cavity into which the packaging material is injected corresponds to the shape of the packaging structure, thereby obtaining a packaging structure that covers the sidewall of the semiconductor cooling assembly and forms a first groove together with the first insulating and thermally conductive layer.

[0028] According to the embodiment of the present application, the shape and size of the cavity can be further adjusted to form a groove (i.e., a second groove) together with the second insulating and thermally conductive layer in the package structure, which can further improve the overload resistance of the semiconductor cooling chip.

[0029] According to an embodiment of the present application, an aluminum mold may be used as the mold used in the injection molding process; on the one hand, the cost of the aluminum mold is low; on the other hand, compared with a steel mold, the adhesion of the aforementioned packaging material to the aluminum mold is smaller, so that it is easier to demold.

[0030] According to the embodiment of the present application, the pressure in the injection molding process may be 2-40 bar, for example, 2 bar, 5 bar, 8 bar, 10 bar, 12 bar, 15 bar, 18 bar, 20 bar, 22 bar, 25 bar, 28 bar, 30 bar, 32 bar, 35 bar, 38 bar, 40 bar, and the temperature in the injection molding process may be 150-240°C, for example, 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C. This allows the packaging material to be in a molten state during the injection molding process and to maintain good performance of the packaging material.

[0031] According to an embodiment of the present application, the time required for cooling and solidifying may be 10 to 50 seconds, which can significantly shorten the production cycle.

[0032] According to the embodiments of the present application, as shown in FIG. 2, the wall thickness (e.g., d shown in the drawings) of the formed package structure 400 may be 0.2 to 1 mm, for example, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, or 1 mm. The inventor has discovered that if the wall thickness of the package structure is too large (e.g., larger than 1 mm), the cooling effect of the semiconductor cooling chip will be reduced, and if the wall thickness of the package structure is too small (e.g., smaller than 0.2 mm), it will not help to significantly improve the overload tolerance of the semiconductor cooling chip. In the present application, by setting the wall thickness of the package structure within the above range, the overload tolerance of the semiconductor cooling chip can be significantly improved, and the semiconductor cooling chip has a good cooling effect.

[0033] According to the embodiments of the present application, as shown in FIG. 2, the package structure 400 forms the first concave groove 10 only together with the first insulating heat conduction layer 100. The depth (e.g., h shown in the drawings) of the first concave groove 10 satisfies 0 < h ≤ 1 mm, and preferably, the depth of the first concave groove is 0.2 to 1 mm, for example, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, or 1 mm. Thereby, the overload tolerance of the semiconductor cooling chip can be significantly improved, and the semiconductor cooling chip has a good cooling effect. Also, the first concave groove has an appropriate depth and is easy to be formed in the manufacturing process of the package structure. The inventor has discovered that if the depth of the first concave groove is too large (e.g., larger than 1 mm), the distance between the semiconductor cooling chip and the clamp is too large, reducing the cooling effect of the semiconductor cooling chip. Therefore, by setting the depth of the first concave groove to 1 mm or less, the overload tolerance of the semiconductor cooling chip can be improved, and it can also be ensured that the semiconductor cooling chip has a good cooling effect.

[0034] According to an embodiment of the present application, as shown in Fig. 3, the package structure 400 forms a first groove 10 together with the first insulating and thermally conductive layer 100, and forms a second groove 20 together with the second insulating and thermally conductive layer 200, and the depths of the first groove 10 and the second groove 20 may be independently 0.2-1 mm. This can further improve the overload resistance of the semiconductor cooling chip, and by having an appropriate distance between the low temperature side of the semiconductor cooling assembly and the clamp, and between the high temperature side of the semiconductor cooling assembly and the radiator, the semiconductor cooling chip can have a good cooling effect.

[0035] The opening areas of the first groove and the second groove are not particularly limited. For example, the opening area of ​​the first groove 10 is smaller than the area of ​​the first insulating and thermally conductive layer 100 (see FIG. 7) or is equal to the area of ​​the first insulating and thermally conductive layer 100 (see FIGS. 1 and 2). The opening area of ​​the second groove 20 is equal to the area of ​​the second insulating and thermally conductive layer 200 (see FIG. 1 and FIG. 2). area (see FIG. 8) or area (See FIG. 3). Preferably, the opening area of ​​the first groove is equal to the area of ​​the first insulating heat conductive layer, and the opening area of ​​the second groove is equal to the area of ​​the second insulating heat conductive layer, so that the overload resistance of the semiconductor cooling chip can be improved and the semiconductor cooling chip can have a good cooling effect.

[0036] From the above, it is possible to effectively improve the overload resistance ability of the semiconductor cooling chip in a simple manner, so that the semiconductor cooling chip can withstand pressure of more than 1000 PSI, and the risk of the semiconductor cooling chip being cracked during the assembly process can be significantly reduced, so that the semiconductor cooling chip has a high product yield and good cooling effect.

[0037] In one aspect of the present application, the present application provides a semiconductor cooling chip, which according to an embodiment of the present application may be manufactured by the above-mentioned method, and thus has the same characteristics and advantages as the semiconductor cooling chip manufactured by the above-mentioned method, and therefore the description thereof is omitted here.

[0038] According to an embodiment of the present application, as shown in FIG. 1 and FIG. 2, the semiconductor cooling chip includes a semiconductor cooling assembly and package structure 400, the semiconductor cooling assembly including a first insulating and thermally conductive layer 100, a second insulating and thermally conductive layer 200 disposed on the opposite side of the first thermally conductive layer, and a semiconductor layer 300 disposed between the first insulating and thermally conductive layer 100 and the second insulating and thermally conductive layer 200, the semiconductor layer 300 including a plurality of thermocouples (not shown) connected in series and electrically connected to the conductive wires 50 (see FIG. 2), the side where the first insulating and thermally conductive layer 100 is disposed is the low temperature side. The side where the second insulating and thermally conductive layer 200 is installed is the high temperature side, the package structure 400 covers the sidewall of the semiconductor cooling assembly and forms the first groove 10 together with the first insulating and thermally conductive layer 100, and the conductive wire 50 penetrates the package structure 400 and extends to the outside of the package structure 400 (see FIG. 1, that is, the conductive wire electrically connected to the thermocouple penetrates the package structure and is exposed to the outside of the package structure, so that the external control circuit can easily apply a direct current to the semiconductor cooling chip through the conductive wire). As a result, the package structure can realize the sealing and protection of the semiconductor cooling assembly and effectively improve the overload resistance ability of the semiconductor cooling chip, so that the semiconductor cooling chip can withstand pressure of more than 1000 PSI, and the risk of the semiconductor cooling chip cracking during the assembly process can be significantly reduced, so that the semiconductor cooling chip has a high product yield and good cooling effect.

[0039] According to an embodiment of the present application, the package structure 400 covers the sidewall of the semiconductor cooling assembly to realize sealing and protection for the semiconductor cooling assembly, and the package structure 400 forms a first groove 10 together with the first insulating thermally conductive layer 100, specifically, the portion of the package structure 400 covering the semiconductor cooling assembly extends toward the first insulating thermally conductive layer 100, and the portion of the package structure 400 higher than the first insulating thermally conductive layer 100 forms the first groove 10 together with the first insulating thermally conductive layer 100 (see Figures 1 and 2), that is, the package structure forms the first groove together with the low-temperature side of the semiconductor cooling assembly. During assembly, the low temperature side of the semiconductor cooling chip is the main force-receiving end, so the package structure forms a first groove together with the low temperature side of the semiconductor cooling assembly, and during assembly, the clamp contacts a part of the package structure that is higher than the first insulating thermally conductive layer, so that the pressure of the clamp is mainly applied to the package structure rather than the semiconductor cooling assembly, which effectively improves the overload resistance of the semiconductor cooling chip and significantly reduces the risk of the semiconductor cooling chip cracking, so that the semiconductor cooling chip has a high product yield and good cooling effect. The package structure forms the first groove together with the first insulating thermally conductive layer, i.e., at least a part of the first insulating thermally conductive layer is exposed to the outside, so that the cooling effect of the semiconductor cooling chip can be guaranteed.

[0040] According to the embodiment of the present application, the pressure that the semiconductor cooling chip can withstand is 1000 PSI or more. In contrast, when the pressure that the conventional semiconductor cooling chip receives exceeds 500 PSI, the semiconductor cooling chip is damaged. As a result, the semiconductor cooling chip of the present application can withstand a significantly increased pressure compared to the conventional semiconductor cooling chip, and even if the pressure is too large or the force received is uneven, it still provides good protection for the insulating thermal conductive layer and the internal semiconductor layer, significantly reducing the risk of the semiconductor cooling chip cracking during assembly, and improving the usage yield and cooling effect of the semiconductor cooling chip.

[0041] According to the embodiment of the present application, as shown in Fig. 3, the package structure 400, in addition to forming the first groove 10 together with the first insulating and thermally conductive layer 100, further forms the second groove 20 together with the second insulating and thermally conductive layer 200, specifically, the part of the package structure 400 covering the semiconductor cooling assembly extends to the second insulating and thermally conductive layer 200 side, and the part of the package structure 400 higher than the second insulating and thermally conductive layer 200 forms the second groove 20 together with the second insulating and thermally conductive layer 200, that is, the package structure further forms the second groove together with the high temperature side of the semiconductor cooling assembly. Thus, during assembly, the part of the package structure higher than the first insulating and thermally conductive layer contacts the clamp, and the part of the package structure higher than the second insulating and thermally conductive layer contacts the radiator, which can further improve the overload resistance of the semiconductor cooling chip.

[0042] According to an embodiment of the present application, as shown in Fig. 2, the wall thickness (for example, d shown in the drawing) of the packaging structure 400 may be 0.2-1mm, which can significantly improve the overload resistance ability of the semiconductor cooling chip, and the semiconductor cooling chip has a good cooling effect.

[0043] According to the embodiments of the present application, as shown in FIG. 2, the package structure 400 forms the first concave groove 10 only with the first insulating and heat-conducting layer 100. The depth of the first concave groove 10 (for example, h shown in the drawing) satisfies 0 < h ≤ 1 mm. Preferably, the depth of the first concave groove is 0.2 - 1 mm. Thereby, the overload resistance of the semiconductor cooling chip can be significantly improved, and the semiconductor cooling chip has a good cooling effect. Also, the first concave groove has an appropriate depth and is easy to be formed in the manufacturing process of the package structure. The inventor found that if the depth of the first concave groove is too large (for example, greater than 1 mm), the distance between the semiconductor cooling chip and the clamp is too large, reducing the cooling effect of the semiconductor cooling chip. By setting the depth of the first concave groove to 1 mm or less, it is possible to improve the overload resistance of the semiconductor cooling chip and ensure that the semiconductor cooling chip has a good cooling effect. Note that the depth h of the first concave groove may or may not be equal to the wall thickness d of the package structure (see FIG. 2), and those skilled in the art can design according to the actual situation.

[0044] According to the embodiments of the present application, as shown in FIG. 3, the package structure 400 forms the first concave groove 10 together with the first insulating and heat-conducting layer 100 and forms the second concave groove 20 together with the second insulating and heat-conducting layer 200. The depths of the first concave groove 10 and the second concave groove 20 may each independently be 0.2 - 1 mm. Thereby, the overload resistance of the semiconductor cooling chip can be further improved, and by having an appropriate distance between the low-temperature side of the semiconductor cooling assembly and the clamp and an appropriate distance between the high-temperature side of the semiconductor cooling assembly and the radiator, the semiconductor cooling chip can have a good cooling effect. Note that the depth H of the second concave groove (shown in FIG. 8) may or may not be equal to the depth h of the first concave groove. The depth of the second concave groove may or may not be equal to the wall thickness d of the package structure, and those skilled in the art can design according to the actual situation.

[0045] The opening shapes of the first groove 10 and the second groove 20 are not particularly limited, and can be designed by a person skilled in the art according to the actual situation. For example, according to the embodiment of the present application, the opening shapes of the first groove 10 and the second groove 20 may each independently include at least one of a rectangle, a circle, and an ellipse.

[0046] The opening areas of the first groove and the second groove are not particularly limited. For example, the opening area of ​​the first groove 10 is smaller than the area of ​​the first insulating and thermally conductive layer 100 (see FIG. 7) or is equal to the area of ​​the first insulating and thermally conductive layer 100 (see FIGS. 1 and 2). The opening area of ​​the second groove 20 is equal to the area of ​​the second insulating and thermally conductive layer 200 (see FIG. 1 and FIG. 2). area (see FIG. 8) or area (See FIG. 3). Preferably, the opening area of ​​the first groove is equal to the area of ​​the first insulating heat conductive layer, and the opening area of ​​the second groove is equal to the area of ​​the second insulating heat conductive layer, so that the overload resistance of the semiconductor cooling chip can be improved and the semiconductor cooling chip can have a good cooling effect.

[0047] Furthermore, when the opening area of ​​the first groove 10 is smaller than the area of ​​the first insulating and thermally conductive layer 100, the package structure 400 covers a portion of the upper surface of the first insulating and thermally conductive layer 100 (the “upper” side shown in FIG. 7), and the thickness of the portion of the package structure 400 covering the upper surface of the first insulating and thermally conductive layer 100 is the depth h of the first groove 10, and the thickness h of the portion may or may not be equal to the thickness d of the portion of the package structure 400 covering the side wall of the semiconductor cooling assembly (see FIG. 7). Similarly, when the opening area of ​​the second groove 20 is smaller than the area of ​​the second insulating and thermally conductive layer 200, the package structure 400 covers a portion of the underside of the second insulating and thermally conductive layer 200 (the “underside” side shown in FIG. 8 ), and the thickness of the portion of the package structure 400 covering the underside of the second insulating and thermally conductive layer 200 is the depth H of the second groove 20, which may or may not be equal to the thickness d of the portion of the package structure 400 covering the sidewall of the semiconductor cooling assembly (see FIG. 8 ).

[0048] According to the embodiment of the present application, the package structure forms a groove together with the insulating heat conductive layer, which can further improve the uniformity of the assembled thickness of the application side product. As is well known to those skilled in the art, during assembly, it is necessary to apply heat conductive silicone grease to the low temperature side and high temperature side of the semiconductor cooling chip to ensure the heat conductive performance of the product, and the application of heat conductive silicone grease is often done manually. In the case of the conventional semiconductor cooling chip, when the heat conductive silicone grease is applied, the phenomenon of uneven thickness is likely to occur, which affects the heat conductive performance. Since the semiconductor cooling chip of the present application has a groove of a certain depth, when the heat conductive silicone grease is applied, it is only necessary to fill the groove, which effectively improves the application efficiency and the thermal conductivity of the product.

[0049] The specific material for forming the package structure is not particularly limited, and may be any material that can provide protection for the semiconductor cooling assembly and can be easily molded to form the aforementioned structure. For example, according to the embodiment of the present application, the material for forming the package structure 400 may include at least one of polyamide hot melt adhesive, polyolefin hot melt adhesive, and reactive polyurethane hot melt adhesive. The above material has the advantages of insulation, temperature resistance, impact resistance, vibration prevention, moisture proof, waterproof, dustproof, chemical corrosion resistance, etc., has a wide temperature resistance range (-40°C to 150°C), low temperature flexibility, and high temperature creep resistance. The first insulating thermal conductive layer and the second insulating thermal conductive layer can be firmly bonded, so that the formed package structure has excellent performance, and the semiconductor cooling chip can be applied to various harsh manufacturing and use environments. The above material is also suitable for packaging electronic products (i.e., the aforementioned semiconductor cooling assembly) and will not cause internal damage to the electronic products.

[0050] According to an embodiment of the present application, the package structure 400 may be formed by injection molding and cooling solidification. The material forming the package structure can be injection molded under low temperature and low pressure conditions, and the solidification time is short (10 to 50 seconds), the process is simple, and the manufacturing cycle can be significantly shortened. Moreover, the package structure formed by injection molding is hard and not easily broken, which improves the protection effect on the semiconductor cooling assembly.

[0051] The specific constituent materials of the first insulating thermally conductive layer and the second insulating thermally conductive layer are not particularly limited. For example, the first insulating thermally conductive layer 100 and the second insulating thermally conductive layer 200 may each independently include at least one of a ceramic sheet, a glass sheet, an aluminum nitride sheet, and an aluminum sheet having an oxide film.

[0052] According to an embodiment of the present application, the semiconductor layer 300 includes a plurality of thermocouples, each of which includes a P-type semiconductor die and an N-type semiconductor die, and the plurality of thermocouples are connected in series, and the semiconductor cooling chip can achieve a cooling effect after applying a direct current to the thermocouples. The arrangement manner of the semiconductor dies and the manner of realizing the series connection of the thermocouples are not particularly limited, and those skilled in the art can design them based on the conventional semiconductor cooling chips, so the description will be omitted here.

[0053] The solution of the present application will be described below with reference to specific examples, and the following examples are merely for the purpose of illustrating the present application and should not be regarded as limiting the scope of the present application. If no specific techniques or conditions are specified in the examples, they shall be in accordance with the techniques or conditions described in the literature of this field or in accordance with the product specifications. Example 1

[0054] The semiconductor cooling chip includes a semiconductor cooling assembly and a packaging structure, the semiconductor cooling assembly includes a first insulating thermally conductive layer, a second insulating thermally conductive layer arranged on the opposite side of the first thermally conductive layer, and a semiconductor layer located between the first insulating thermally conductive layer and the second insulating thermally conductive layer, the side on which the first insulating thermally conductive layer is installed is the low temperature side, and the side on which the second insulating thermally conductive layer is installed is the high temperature side, and the packaging structure covers a sidewall of the semiconductor cooling assembly, and forms a first groove together with the first insulating thermally conductive layer, and forms a second groove together with the second insulating thermally conductive layer.

[0055] The first insulating and thermally conductive layer and the second insulating and thermally conductive layer are both ceramic sheets, the opening area of ​​the first groove matches the area of ​​the first insulating and thermally conductive layer, and the opening area of ​​the second groove matches the area of ​​the second insulating and thermally conductive layer.

[0056] The package structure is made of polyamide hot melt adhesive, the wall thickness of the package structure is 0.2 mm, and the depth of the first groove and the second groove is both 0.2 mm.

[0057] The manufacturing process of the semiconductor cooling chip is as follows.

[0058] (1) The semiconductor cooling assembly is placed in an aluminum mold.

[0059] (2) The molten polyamide hot melt adhesive is injected into an aluminum mold, the injection temperature is 150°C, and the injection pressure is 2 bar.

[0060] (3) After the injection molding is completed, the heating is stopped and the product is allowed to cool and solidify naturally. The solidification time is 10 seconds.

[0061] (4) The mold is opened and the packaged semiconductor cooling chip is removed. Example 2

[0062] The structure and manufacturing process of the semiconductor cooling chip of this embodiment are basically the same as those of Example 1, except that the wall thickness of the package structure is 0.8 mm, the depths of the first and second grooves are both 0.6 mm, the injection molding temperature is 240°C, the injection molding pressure is 40 bar, and the solidification time is 50 s. Example 3

[0063] The structure and manufacturing process of the semiconductor cooling chip of this embodiment are basically the same as those of the first embodiment, except that the wall thickness of the package structure is 1 mm, and the depths of the first and second grooves are both 1 mm. Example 4

[0064] The structure and manufacturing process of the semiconductor cooling chip of this embodiment are basically the same as those of Example 1, except that the package structure forms a first groove together with only the first insulating thermal conductive layer, and the depth of the first groove is 0.2 mm. Example 5

[0065] The structure and manufacturing process of the semiconductor cooling chip of this embodiment are basically the same as those of the fourth embodiment, except that the depth of the first groove is 0.1 mm. Example 6

[0066] The structure and manufacturing process of the semiconductor cooling chip of this embodiment are basically the same as those of the first embodiment, except that the package structure is made of polyolefin hot melt adhesive and the temperature of injection molding is 180°C. Example 7

[0067] The structure and manufacturing process of the semiconductor cooling chip of this embodiment are basically the same as those of the first embodiment, except that the package structure is formed of reactive polyurethane hot melt adhesive and the injection molding temperature is 180°C. Comparative Example 1

[0068] The semiconductor cooling chip includes a semiconductor cooling assembly and a sealant. The semiconductor cooling assembly includes a first insulating thermally conductive layer, a second insulating thermally conductive layer arranged on the opposite side of the first thermally conductive layer, and a semiconductor layer located between the first insulating thermally conductive layer and the second insulating thermally conductive layer. The side on which the first insulating thermally conductive layer is installed is the low temperature side, and the side on which the second insulating thermally conductive layer is installed is the high temperature side. 704 white silicone rubber is used as the sealant and is installed around the semiconductor cooling assembly. Performance Testing

[0069] 1. An overload resistance test is performed on the semiconductor cooling chips of Examples 1 to 7 and Comparative Example 1, specifically, 10 samples are selected from each Example (for example, 10 samples are selected from Example 1, 10 samples are selected from Example 2, 10 samples are selected from Example 3, 10 samples are selected from Example 4, 10 samples are selected from Example 5, 10 samples are selected from Example 6, and 10 samples are selected from Example 7), and 10 samples are selected from Comparative Example 1, and an overload resistance test is performed on each of the above samples, and the test results are as shown in Table 1. The test standard is SJ-T10135-2010.

[0070] The "maximum pressure value that can be withstood" by the samples of each Example and Comparative Example is the average value of the maximum pressure that can be withstood by the 10 samples in each Example.

[0071] As the semiconductor cooling assemblies in Examples 1 to 7 and Comparative Example 1, the same model of cooling assembly is selected.

[0072] 2. Ten samples were selected from each embodiment, and a pressure of 500 PSI was applied to each sample. The yield of each embodiment and comparative example was calculated. The test results are shown in Table 1.

[0073] 3. The cooling capabilities of the semiconductor cooling chips of Examples 1 to 7 and Comparative Example 1 were tested respectively. The current applied during the test was 3A. The test results are shown in Table 1.

[0074] [Table 1]

[0075] "Maximum pressure that can be withstood" refers to the critical pressure at which cracks occur in the semiconductor cooling chip. "Usage yield at a pressure of 500 PSI" refers to the percentage of samples that do not crack after being subjected to a pressure of 500 PSI out of 10 samples.

[0076] As can be seen from Table 1, compared with the conventional semiconductor cooling chip (i.e., Comparative Example 1), the overload resistance of the semiconductor cooling chip of the present application (i.e., Examples 1 to 7) is significantly improved, the maximum pressure that can be withstood is 1000 PSI or more, the product usage yield is significantly improved, and the cooling effect is good.

[0077] Compared with a semiconductor cooling chip in which the package structure forms a groove only with the low temperature side surface of the semiconductor cooling assembly, the semiconductor cooling chip in which the package structure forms a groove with both the low temperature side surface and the high temperature side surface of the semiconductor cooling assembly has a higher overload resistance capacity (compare Examples 1 to 3 with Example 4).

[0078] In describing this application, the orientations or positional relationships indicated by the terms "upper", "lower", etc. are based on the orientations or positional relationships shown in the drawings and are merely for ease of describing this application, and are not intended to require that this application be configured and operated in a particular orientation, and should not be understood as limiting this application.

[0079] In the description of this specification, a description that refers to the term "one embodiment," "another embodiment," etc. means that the specific feature, structure, material, or characteristic described with reference to the embodiment is included in at least one embodiment of the present application. In this specification, the exemplary expressions of the above terms are not necessarily limited to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be combined in any suitable form in any one or more embodiments or examples. In addition, a person skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, so long as they are not inconsistent with each other. It should be noted that in this specification, the terms "first" and "second" are for illustrative purposes only and should not be understood as indicating or suggesting relative importance or implying the number of technical features shown.

[0080] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are merely illustrative and should not be construed as limiting the present application, and that those skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application. [Explanation of symbols]

[0081] 100 First insulating and thermally conductive layer 200 Second insulating and thermally conductive layer 300 Semiconductor layer 400 Package Structure 10 1st groove 20 Second groove 30 Ceramic Sheet 40 Semiconductor Dies 50 conductor 60 Silicone rubber.

Claims

1. A method for manufacturing a semiconductor cooling chip, comprising: providing a semiconductor cooling assembly including a first insulating and thermally conductive layer, a second insulating and thermally conductive layer, and a semiconductor layer located between the first insulating and thermally conductive layer, the semiconductor layer including a plurality of thermocouples connected in series and electrically connected to electrical leads, the side of the semiconductor cooling assembly on which the first insulating and thermally conductive layer is provided being a low temperature side, and the side of the semiconductor cooling assembly on which the second insulating and thermally conductive layer is provided being a high temperature side; covering a sidewall of the semiconductor cooling assembly with a packaging structure including an adhesive, the adhesive bonding the first insulating and thermally conductive layer and the second insulating and thermally conductive layer, and forming a packaging structure together with the first insulating and thermally conductive layer to form a first groove, allowing the conductive wire to penetrate the packaging structure and extend to the outside of the packaging structure, to obtain the semiconductor cooling chip; The adhesive material includes at least one of a polyamide hot melt adhesive, a polyolefin hot melt adhesive, and a reactive polyurethane hot melt adhesive; the first insulating and thermally conductive layer and the second insulating and thermally conductive layer each independently include at least one of a ceramic sheet, a glass sheet, an aluminum nitride sheet, and an aluminum sheet having an oxide film; An opening area of ​​the first groove corresponds to an area of ​​the first insulating and thermally conductive layer.

2. The method of claim 1 , further comprising forming a second groove in the package structure and the second insulating and thermally conductive layer.

3. The method according to claim 1 or 2, wherein the package structure is formed by injection molding and cooling solidification.

4. The method according to claim 3, wherein the pressure in the injection molding process is 2 to 40 bar and the temperature in the injection molding process is 150 to 240°C.

5. The method according to claim 3 or 4, wherein the cooling and solidifying time is 10 to 50 s.

6. The method according to any one of claims 1 to 5, wherein the wall thickness of the formed packaging structure is between 0.2 and 1 mm.

7. The method according to claim 1 , wherein the first groove has a depth of 0.2 to 1 mm.

8. The method of claim 2 , wherein the first groove and the second groove each have a depth of 0.2 to 1 mm independently.

9. The method described in claim 2, wherein the opening area of ​​the second groove is equal to the area of ​​the second insulating thermally conductive layer.

10. a semiconductor cooling assembly including a first insulating and thermally conductive layer, a second insulating and thermally conductive layer, and a semiconductor layer located between the first insulating and thermally conductive layer, the semiconductor layer including a plurality of thermocouples connected in series and electrically connected to a conductive wire, the side of the semiconductor cooling assembly on which the first insulating and thermally conductive layer is provided being a low temperature side, and the side of the semiconductor cooling assembly on which the second insulating and thermally conductive layer is provided being a high temperature side; a packaging structure covering a sidewall of the semiconductor cooling assembly and forming a first groove together with the first insulating and thermally conductive layer; The package structure includes an adhesive, the adhesive bonding the first insulating and thermally conductive layer and the second insulating and thermally conductive layer; the conductive wire penetrates the package structure and extends to the outside of the package structure; The adhesive material includes at least one of a polyamide hot melt adhesive, a polyolefin hot melt adhesive, and a reactive polyurethane hot melt adhesive; the first insulating and thermally conductive layer and the second insulating and thermally conductive layer each independently include at least one of a ceramic sheet, a glass sheet, an aluminum nitride sheet, and an aluminum sheet having an oxide film; The opening area of ​​the first groove is equal to the area of ​​the first insulating and thermally conductive layer.

11. The semiconductor cooling chip according to claim 10 , wherein the packaging structure and the second insulating and thermally conductive layer form a second groove.

12. The semiconductor cooling chip according to claim 10 or 11, wherein the wall thickness of the packaging structure is 0.2 to 1 mm.

13. The semiconductor cooling chip according to any one of claims 10 to 12, wherein the first groove has a depth of 0.2 to 1 mm.

14. The semiconductor cooling chip according to claim 11, wherein the first groove and the second groove each have a depth of 0.2 to 1 mm independently.

15. The semiconductor cooling chip according to any one of claims 10 to 14, wherein an opening shape of the first groove includes at least one of a rectangle, a circle, and an ellipse.

16. The semiconductor cooling chip according to claim 11 , wherein an opening area of ​​the second groove is equal to an area of ​​the second insulating and thermally conductive layer.

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