Connector and printed circuit board having surface ground plane - Patents.com

Abstract

To reduce generation of unwanted noise and crosstalk between signals in a printed circuit board.SOLUTION: Connector (1300) and printed circuit board combinations include opposing electrical ground structures that increase electrical coupling.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] (Related Applications) This application claims priority to U.S. Provisional Patent Application No. 62 / 736,288, filed September 25, 2018 (the "'288 Application"), the entire disclosure of which is incorporated herein by reference as if fully set forth herein.

[0002] FIELD OF THEINVENTION The present disclosure relates to the field of connectors, and more particularly to connectors and printed circuit board (PCB) and connector combinations, each functioning to conduct data at high data rates. [Background technology]

[0003] This section introduces aspects that may be useful to facilitate a better understanding of the described invention(s). Accordingly, the statements in this section should be read in this light and should not be understood as admissions of what is or is not in the prior art.

[0004] PCBs used in high speed communication applications can be connected using suitable connectors. Typically, many PCBs may be spaced only a few millimeters (mm) apart, and therefore, they are placed closely or densely packed. An even greater challenge arises when, within a given PCB carrying many discrete signals, the PCBs are placed such that the required pitch density may approach or exceed that of differential signal pairs operating within 1-3 mm of each other. It is very difficult to eliminate or substantially reduce the ability of one differential signal pair conducted on the same PCB, and also very tightly tuned, from being inductively or capacitively coupled to another adjacent differential signal pair on the same PCB. In addition to the above challenges, as the speed of the signals conducted by the PCB increases, there is a tendency for unwanted noise, or undesirable coupling, commonly referred to simply as "crosstalk," to increase.

[0005] Furthermore, in existing Connector-to-PCB designs, the signal and ground pin locations of the connector footprint are matched with corresponding receiving structures, such as conductive press-fit pin holes, for each signal and ground location. In addition, conductive ground connection vias may be used within the PCB to electrically connect selected ground designated layers together to establish a robust low impedance ground return. However, these existing designs do not adequately address the problem of unwanted noise coupling. Summary of the Invention

[0006] The inventors describe various exemplary PCB and connector combinations and associated methods that, among other things, reduce crosstalk between signals within a PCB and increase coupling between the connector and the ground structure of the PCB by varying the surface area of ​​the ground frame mounting area relative to the surface area of ​​the PCB's active port area, where the active port area includes the total surface area of ​​the anti-pads and the total surface area of ​​the signal mounting locations on the PCB.

[0007] An embodiment of a PCB may include a top surface for mounting a connector, the top surface having a mounting area having a plurality of signal mounting locations for the connector, a plurality of ground mounting locations for the connector, anti-pads around the plurality of signal mounting locations, and an outer boundary formed between adjacent signal mounting locations of the plurality of signal mounting locations, the mounting area including the plurality of signal mounting locations; and a ground plane covering the top surface within the mounting area, the top surface within the mounting area further containing the ground mounting locations and the signal mounting locations and including anti-pads around the signal mounting locations of the plurality of signal mounting locations, the ground plane covering at least 50% of a total surface area of ​​the mounting area.

[0008] In one embodiment, an outer boundary of the mounting region may be formed between adjacent ground mounting locations of an outermost plurality of ground mounting locations, the mounting area including the plurality of ground mounting locations.

[0009] In an embodiment, (i) the ground mounting location may include a ground via and the signal mounting location may include a signal via; or (ii) the ground mounting location may include a ground surface mount pad and the signal mounting location may include a signal surface mount pad; or (iii) the antipad may include at least one antipad around a pair of signal mounting locations of the plurality of signal mounting locations; or (iv) the antipad may include an antipad around each of the signal mounting locations of the plurality of signal mounting locations.

[0010] In the embodiments described herein, the surface area of ​​the ground plane can cover (i) at least 60% of the total surface area of ​​the mounting area, or (ii) at least 70% of the total surface area of ​​the mounting area, or (iii) at least 80% of the total surface area of ​​the mounting area, or (iv) at least 90% of the total surface area of ​​the mounting area.

[0011] An alternative exemplary PCB may include a top surface for mounting a connector, the top surface having a mounting area having a plurality of signal mounting locations for the connector, a plurality of ground mounting locations for the connector, anti-pads around the plurality of signal mounting locations, and an outer boundary formed between the outermost signal mounting locations, the mounting area including the plurality of signal mounting locations, and a ground plane covering the top surface and the anti-pads within the mounting area excluding the signal vias, the ground plane having a surface area covering at least 50% of the total surface area of ​​the mounting area.

[0012] Such an exemplary PCB may further include an anti-pad including: (i) a ground mounting location including a ground via and a signal mounting location including a signal via; or (ii) a ground mounting location including a ground surface mount pad and a signal mounting location including a signal surface mount pad; or (iii) an anti-pad including at least one anti-pad around a pair of the signal mounting locations of the plurality of signal mounting locations; or (iv) an anti-pad around each of the signal mounting locations of the plurality of signal mounting locations.

[0013] Similar to the previous embodiments, in an alternative PCB, (i) the surface area of ​​the ground plane may cover at least 60% of the total surface area of ​​the mounting area, or (ii) the surface area of ​​the ground plane may cover at least 70% of the total surface area of ​​the mounting area, or (iii) the surface area of ​​the ground plane may cover at least 80% of the total surface area of ​​the mounting area, or (iv) the surface area of ​​the ground plane may cover at least 90% of the total surface area of ​​the mounting area.

[0014] In addition to the PCB of the present invention, the inventors describe a connector of the present invention, including a plurality of wafers configured to form a mounting surface and a mating surface, the mounting surface further configured for mounting to a top surface of a printed circuit board having a ground plane whose surface area may cover at least 50% of the total surface area of ​​an area opposite the mounting region of the mounting surface, the mounting surface may include at least one conductive surface that electrically couples to ground, the connector configured for mounting on the circuit board such that the at least one conductive surface is within 0.3 mm of the ground plane and further configured to operate at a data rate of at least 56 Gbps, the plurality of wafers including a signal transfer wafer, the signal transfer wafer configured to support a plurality of signal terminals, each of the plurality of signal terminals including a tail portion, a contact portion, and a body portion extending between the contact portion and the tail portion, such that (i) the contact portion of the signal terminal is adjacent the mating surface, and (ii) the tail portion of the signal terminal is adjacent the mounting surface, forming a mounting area on the mounting surface.

[0015] Further, in the exemplary connector, (i) the plurality of wafers may include a ground wafer, (ii) the at least one conductive surface electrically coupled to the ground may include a plated edge of the ground wafer, (iii) the ground wafer may include a tail insert, and the at least one conductive surface electrically coupled to the ground may further include a portion of the tail insert positioned along the mounting area, and (iv) the plurality of wafers may include a pair of ground wafers and a pair of signal carrying wafers, the pair of signal carrying wafers positioned adjacent to one another and the ground wafers positioned on either side of the adjacent signal carrying wafer.

[0016] In an embodiment, the ground wafer may include (i) plated plastic, and / or (ii) a tail insert.

[0017] The exemplary connectors described herein and above may further include transverse ground blades for electrically coupling the ground wafer, the transverse ground blades may include tails configured to electrically couple to the ground plane, and the ground wafer may include tail inserts, the transverse ground blades may be interdigitated with the tail inserts.

[0018] In alternative embodiments, the transverse ground blades may extend in a non-perpendicular direction across the ground wafer.

[0019] In addition to the PCBs and connectors of the present invention, we describe methods that correspond to and include the PCBs and connectors of the present invention described above and elsewhere herein.

[0020] Additionally, the inventors describe methods for reducing crosstalk between signals on a PCB. One such method may include forming a PCB having a ground frame mounting area and an active port area, where the active port area includes a total surface area of ​​anti-pads and a total surface area of ​​signal mounting locations on the PCB, and varying the surface area of ​​the ground frame area and varying the active port area to vary the crosstalk between signals at the signal mounting locations.

[0021] More specifically, the exemplary method may further include increasing a surface area of ​​the ground frame region and decreasing an active port area to reduce crosstalk between signals at the signal mounting locations. [Brief description of the drawings]

[0022] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numbers indicate similar elements and in which:

[0023] 1-33 illustrate embodiments of the present invention(s) that reduce unwanted coupling noise and can be used, among other things, to endorse the high data rate capabilities and performance of certain embodiments.

[0024] [Figure 1-5] 1 illustrates an exemplary configuration of a receptacle mounted on an exemplary PCB in accordance with an embodiment of the present invention. [Figure 6] 1 illustrates an exemplary connector including one or more sets of wafers according to an embodiment of the present invention, where each set may include one or more ground and signaling wafers arranged to provide one or more ground-signal-signal-ground configurations or a pattern in which the presence of ground pins can repeat to form a GSSGGSSG pattern or can be represented as a more compact GSSGSSG repeating pattern (where "G" stands for "ground" and "S" stands for "signal"). [Figure 8-11] 1 illustrates the placement of tail inserts, ground blades, ground planes, ground mounting locations, and signal terminal pairs according to an embodiment of the present invention. [Figure 12] 1 illustrates an exemplary PCB with overlapping anti-pads and mounting surface conductive surfaces (e.g., ground wafer edge, transverse ground blades) in accordance with an embodiment of the present invention. [Figure 13] 1 illustrates an exemplary arrangement of PCBs and connectors according to an embodiment of the present invention. Mating connectors with conductive shielding wafers effectively establish a conductive ceiling between the active signal ports and the PCB surface, and a conductive floor between the active signal ports, when the connectors engage at a defined elevation from the PCB surface such that the opposing connector and PCB ground surfaces form a substantially closed aperture / waveguide between the active signal ports, thereby electrically isolating them from one another within the intended operating frequency band. [Figure 14] 1 illustrates an exemplary PCB with overlapping anti-pads and mounting surface conductive surfaces (e.g., ground wafer edge, transverse ground blades) in accordance with an embodiment of the present invention. [Figure 15]1 illustrates a cutaway view of the connector mounted on a PCB showing the engagement of the plug module, connector, and extended anti-pad on the other copper layers of the PCB. [Figure 16-20] 1 shows four different exemplary PCBs and corresponding mounting surfaces, where the surface area of ​​each mounting surface includes a ground plane and an anti-pad, where the surface area of ​​the ground plane covers a percentage of the total surface area of ​​the corresponding mounting area, and the surface area of ​​the anti-pad covers a percentage of the total surface area of ​​the mounting area according to an embodiment of the present invention. [Figure 21-32] 21 shows example graphs of insertion loss, crosstalk, impedance, and return loss for the four example PCBs and corresponding mounting surfaces of FIGS. 16-20. [Diagram 33] 1 also shows an enlarged perspective cross-sectional view of a portion of a mounting surface of a connector mounted on a circuit board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Certain embodiments of the present invention are disclosed below with reference to various drawings and schematics. Both the description and the illustrations have been drafted with the intention of enhancing understanding. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements, and well-known elements that are beneficial or even necessary for commercially successful implementation may not be depicted so as to make the embodiments less ambiguous and more clear.

[0026] Simplicity and clarity in both illustration and description are required to effectively enable a person skilled in the art to make, use, and best practice the present invention in view of what is already known in the art. Those skilled in the art will appreciate that various modifications and changes may be made to the specific embodiments described herein without departing from the spirit and scope of the present invention. Thus, the specification and drawings should be regarded as descriptive and illustrative, rather than restrictive or comprehensive, and all such modifications to the specific embodiments described herein are intended to be included within the scope of the present invention. Furthermore, it should be understood that the following detailed description describes exemplary embodiments and is not intended to be limited to the combination(s) expressly disclosed. Thus, unless otherwise specified, features disclosed herein may be combined together to form additional combinations not otherwise described or shown for purposes of brevity.

[0027] As used herein and in the appended claims, the terms "comprises," "comprising," or any other variation thereof, are intended to refer to a non-exclusive inclusion, such that a process, method, manufacture, or apparatus that includes a list of elements does not include only those elements on the list, but may also include other elements not expressly listed or inherent to such process, method, manufacture, or apparatus. As used herein, the terms "a" or "an" are defined as one or more than one. As used herein, the term "plurality" is defined as two or more than two. As used herein, the term "another" is defined as at least a second or more. Unless otherwise indicated herein, if any, the use of relational terms such as "first" and "second," "top," and "bottom" are used only to distinguish one entity or action from another entity or action, and in so doing do not necessarily require or imply an actual relationship, priority, importance, or order between such entities or actions.

[0028] As used herein, the terms "including" and / or "having" are defined as comprising (i.e., open language). As used herein, the term "coupled" means that at least the electric field energy associated with a current in one conductor is impressed onto another conductor that is not galvanically connected. Stated differently, the word "coupled" is not limited to either a mechanical connection, a galvanic electrical connection, or a magnetic field-mediated electromagnetic interaction, but may include one or more such connections, unless its meaning is limited by the context of a particular description herein.

[0029] It should also be noted that one or more exemplary embodiments may be described as a method. Although a method may be described in an exemplary sequence (i.e., sequentially), it should be understood that such methods may be performed in parallel, jointly, or simultaneously. In addition, the order of each variant step within a method may be permuted. A described method may be terminated when completed, or may include additional steps not described herein, for example, if such steps are known to one of ordinary skill in the art.

[0030] As used herein, the terms "embodiment" or "exemplary" refer to examples falling within the scope of the invention(s).

[0031] The present inventors have discovered a connector and circuit board configuration that, when used in conjunction with one another, can reduce unwanted coupling noise, among other advantages.

[0032] As described further herein, embodiments of the present invention align connector ground structures to capacitively coordinate with similarly aligned ground structures on PCBs that face each other. The coordinating ground structures of the present invention add an additional electrical element - a capacitive ground coupling - to the connector footprint in addition to the galvanic signal and ground connections.

[0033] 1, an exemplary receptacle 500 of a connector mounted on a PCB 100 is shown such that the receptacle 500 is oriented perpendicular to the PCB 100 for receiving a plug module (not shown). Although not specifically shown, it should be understood that the same or similar operating mechanism can be utilized with a vertical connector oriented as a straight connector. In one embodiment, the receptacle 500 may be formed from a housing 502 disposed or positioned within a cage 501, which further functions as a connector 505 (see FIGS. 2 and 3). The cage 501 functions to at least support and control the mating plug module (not shown) and connector, and also functions to provide electromagnetic interference (EMI) protection. The cage 501 also helps maintain mechanical integrity during application operation.

[0034] With reference to FIG. 4, in one embodiment, the connector functions to support terminals including tails 508, contacts 506, and a body therebetween (not shown) that further function to allow a mating plug module to be electrically connected to a PCB (or cable if a bypass design is desired). In the exemplary embodiment of FIG. 4, the tails 508 may be configured as press-fit tails. However, in alternative embodiments, the terminal tails may be configured in various forms other than press-fit to support a desired mounting configuration or arrangement (e.g., surface mount) or interconnection (e.g., cable). In the embodiment of FIG. 4 (and FIG. 5), the receptacle 500 may be press-fit onto the PCB to facilitate assembly. Thus, the terminals of the connector should be aligned with the terminals on the cage. In one embodiment, the cage 501 may include a metal cage. Additionally, the tails 508 may be arranged in a highly repeatable arrangement and may include similar dimensions relative to one another.

[0035] 6 and 7, an exemplary connector may include a set of one or more wafers 620. In one embodiment, the wafer set 620 includes ground wafers 661, 664 and signaling wafers 662, 663 (see FIG. 7) arranged in a ground-signal-signal-ground pattern. A particular application may repeat in a GSSGSSG pattern as shown, or may include additional ground wafers forming a GSSGGSSG repeating pattern (where "G" stands for "ground" and "S" stands for "signal"). In the illustrated embodiment, the signaling wafers 662 and 663 each include an insulating frame (e.g., molded plastic such as liquid crystal polymer (LCP)) that functions to support the signal terminals thereon (each signal terminal has a contact and an associated tail as shown in FIG. 7). In the embodiment shown in FIG. 7, the ground wafers 661 and 664 are formed of a metalized plastic that allows for electrical conductivity and commoning. Moreover, such metallized plastic may be (1) doped to be sufficiently conductive, (2) plated, (3) doped and plated, (4) inked, (5) etched, or (6) some combination of any of the foregoing to function as at least a formed generally conductive surface. In embodiments, in the case of plating, the plated metallized plastic may cover the entire surface area of ​​the ground wafer, or may cover less than the entire surface area of ​​the ground wafer (i.e., selective plating). Thus, in some embodiments, the entire surface of the insulating frame (e.g., molded plastic such as LCP) may be plated to be conductive. Thus, in one embodiment, the ground wafer may first include a stamped / formed conductive plate (possibly including ground contacts and tail features) that is overmolded with plastic and then plated. The contacts and / or tail features may be inserted into the ground wafer as needed, either before or after plating. These conductive tail features function to provide a direct electrical conduction path between the ground wafer and the PCBs that face each other.

[0036] In some embodiments, the metal contact inserts 668 and metal tail inserts 669 may be stitched or inserted into pockets in the ground wafers 661, 664 (shown after stitching in FIG. 7) rather than being formed through a terminal overmolding process (as with the signal carrying wafers 662, 663). This stitching of inserts (whether contacts or tails or both) may be done for all or any of the ground wafers 661, 664. Similar contact and / or tail inserts may be formed for the various signal carrying or power wafers and then stitched to those wafers as desired. Additionally, the tail inserts may be press-fit tail inserts or surface mount tail inserts. In further embodiments, instead of tail inserts, the ground wafers 661, 664 may include plated or metallized conductive plastic tails. Such tails may be formed as part of any molded wafer and may be conductive or may be made conductive (e.g., plated).

[0037] As shown, the exemplary ground wafers 661 and 664 may include a number of raised areas (humps) 680, pegs 681a, and recesses 681b for sandwiching and mating the signal transfer wafers 662, 663. In some embodiments, the pegs 681a and recesses 681b of one ground wafer may form or be arranged as an interference fit with the opposing sandwiched ground wafer. Additionally, in some embodiments, each raised area may be filled to substantially fill the gap of the sandwiched signal transfer wafer pair. Also, depending on the embodiment, some or all of the recesses 681b of the ground wafer may instead be formed as holes in the ground wafer to receive the pegs 681a of the opposing ground wafer. Thus, it should be understood that the arrangement of the pegs 681a and recesses 681b shown in FIG. 7 is merely one example and that many variations are possible.

[0038] In one embodiment, it may be desirable for some or all of the raised areas (bumps) 680, pegs 681a, and / or recesses 681b to be metallized (i.e., include metallized elements) to enable conduction and commonality between the ground wafers 661, 664.

[0039] 33, an exemplary enlarged perspective view and cross-sectional view of an exemplary mounting area of ​​an exemplary connector showing mounting of the connector to a PCB according to some embodiments of the present invention are shown. More specifically, a portion of the top surface of the PCB including ground plane 101 and anti-pads such as anti-pad 102 are shown in FIG. 33. Also shown are signal mounting locations 103 and ground mounting locations 104 for the connector. In the illustrated embodiment, signal mounting location 103 includes signal via 103 and ground mounting location 104 includes ground via 104. In other embodiments, the signal mounting location may include a signal surface mount pad and the ground mounting location may include a ground surface mount pad when the PCB is mated with a surface mount connector. Also, although anti-pads 102 are shown around each of two signal mounting locations, in other embodiments the anti-pads 102 may be bonded together or may instead be a single anti-pad around the two (or possibly more) signal mounting locations. In an exemplary embodiment, the surface area of ​​the ground plane 101 is depicted as covering somewhat more than 50% of the total surface area of ​​the mounting area shown in FIG. 33. The mounting area may be defined as the smallest area that includes all of the signal mounting locations. It is desirable for the surface area of ​​the ground plane to cover more than 50%, 60%, 70%, 80% or even 90% of the total surface area of ​​the mounting area. It is desirable for the surface area of ​​the ground plane to cover as much of the total surface area of ​​the mounting area as possible, unless other top surface features are required, such as, for example, larger anti-pads or additional vias.

[0040] 33, a cross-sectional view of the mounting area of ​​the connector is shown with a portion of the signal terminals shown. In particular, a portion of the tail portion 675 of the signal terminal is shown. In this embodiment, the tail portion 675 includes a press-fit tail portion. In other embodiments, the tail portion may instead be configured to surface mount to a PCB. Also shown are portions of the connector's ground wafers and tail inserts (such as ground wafer 671 with its tail insert 679), and portions of the transverse ground blades 677. In one embodiment, the transverse ground blades 677 may be positioned or configured to electrically connect across all row-aligned ground wafers 671, for example, positioned substantially perpendicular to the blades 677 (i.e., such that the geometric plane containing the blades 677 "crosses" the geometric plane containing the wafers 671). However, it should be understood that the ground blades need not be perpendicular to the ground wafers, but rather extend laterally across them, as desired. Further, depending on the embodiment, the transverse ground blades 677 may be configured to interdigitate with the tail inserts 679 or fit into slots formed in the ground wafer 671, or both, to electrically connect to the ground wafers that they cross. (See, e.g., FIGS. 8-11, where FIG. 10 shows the underside or mounting side of the connector and FIG. 11 shows an enlarged view of a portion of FIG. 10). Both the transverse ground blades 677 and the tail inserts 679 may also be electrically coupled to the ground plane 101 through the ground mounting locations 104. In the illustrated embodiment, multiple transverse ground blades (e.g., the transverse ground blades 677) are positioned between the rows of signal terminal tail pairs 675.

[0041] The ground wafer 671 may be formed of a metalized plastic that allows for electrical conductivity and commoning. As previously mentioned, the metalized plastic may take a variety of forms. The ground wafer 671 may be plated all over its molded plastic frame, including its edges that face the mounting area. The face of the connector that faces the mounting area of ​​the connector includes a number of conductive surfaces that are electrically coupled to ground, and the plated edges of the ground wafer are significant among these conductive surfaces. Portions of the tail insert and transverse (or lateral) ground blades positioned along the face of the mounting area may also include conductive surfaces that are electrically coupled to ground. However, as a matter of surface area, at least in the illustrated embodiment, the plated edges of the ground wafer 671 are more significant than the edges of the ground blades or the edges of the tail insert.

[0042] 12 and 14, an exemplary configuration is shown in which the conductive surface of the PCB with anti-pads 1202 and the mounting area are plane-over-plane with one another. Figure 12 shows the edge 1210 of the face of the mounting ground wafer positioned along the mounting surface, and a portion of the tail insert (within the ground wafer) 1211 positioned along the mounting surface, while Figure 14 also shows a portion of the transverse ground blades 1220 positioned along the face of the mounting area.

[0043] 13, there is shown a typical configuration or arrangement of a combination connector 1300 mounted to a PCB 1301. As shown, the surface of the connector 1300 is not flush (i.e., in contact) with the surface of the PCB 1301, so there is an aperture / waveguide region 1302 between the surface of the PCB 1301 and an electrically coupled ground structure on the surface of the connector 1300 closest to the PCB 1301. In an embodiment of the invention, it is desirable for this aperture / waveguide region 1302 to be as small as possible to reduce undesirable noise.

[0044] More specifically, unwanted noise can be a significant degradation factor limiting operating margins and functional channel lengths when the connector operates in high speeds from 56 Gbps-PAM4 to 112 Gbps-PAM4 and non-modulated applications such as 56 Gbps-NRZ.

[0045] With this in mind, the inventors provide exemplary embodiments herein in which the connector is mountably combined with the PCB. In one such embodiment described in FIG. 33, the connector may be configured or arranged for mounting such that one or more of the conductive surfaces of the face of the mounting area may be nominally within 0.3 mm of the surface of the ground plane 101 of the PCB, as previously described. Thus, the underside of the ground wafer 671 (hidden from view) may be within 0.3 mm of the surface of the portion of the ground plane 101 of the PCB directly below it. In alternative embodiments, the conductive surfaces of the face of the mounting area are desirably within 0.15 mm or even closer to the surface of the ground plane 101.

[0046] It should be appreciated that when constructed or arranged using the dimensions described in the paragraphs above, the surfaces of the connector and PCB combination discussed in this invention may function to increase the electrical coupling of their electrical grounds to an extent that is improved over existing configurations. Moreover, rather than describing the same improvement in electrical coupling in terms of mechanical dimensions, it should be appreciated that such improvement may also be described by indicating that the proximity between the surface of the inventive ground plane of the PCB and the inventive conductive surface of the mounting surface of one or more connectors preferably does not exceed 1 / 15 wavelength fraction of the wavelength of the highest intended operating frequency within the transition region between the surface of the PCB and the conductive surface of the mounting surface of the connector.

[0047] It is also believed that the inventive connector-PCB combination, including a configuration or arrangement in which the surface of the PCB ground plane and the conductive surface of the face of the connector mounting area are in close proximity to one another (e.g., 0.3 mm or less), provides an improved and enhanced capacitive coupling over existing configurations. Such enhanced capacitive coupling allows a substantially equipotential planar surface to be achieved such that a more effective RF ground coupling is established and maintained between the surface of the PCB and the connector facing one another, thereby further providing significantly improved noise reduction. It is further believed that the enhanced capacitive coupling provided by the inventive connector / PCB combination functions to form an electrical shunt between the surface of the PCB ground plane and the conductive surface of the face of the connector mounting area. This shunt capacitance is believed to be substantially parallel to the direct galvanic conduction of the multiple pressed-in ground pins. It is noted that the presence of ground currents in the signal return path is not necessarily limited to the ground pins. Across the conductor plane of the shielding wafer, a time-varying differential voltage can support a "localized" displacement current difference that is not effectively transferred to the surface of the PCB, allowing a potential difference between the conductive wafer of the connector and the ground plane of the PCB. Having realized this, the inventors provide an embodiment in which the opposing PCB and conductive connector surfaces are in substantial proximity to one another to support a parallel plate capacitance between the opposing PCB and conductive connector surfaces, which in turn provides a capacitive coupling path for coupling displacement currents from the conductive wafer to the ground plane surface of the PCB. This capacitive coupling path serves to keep the voltage difference between the connector and the PCB to a minimum, and therefore substantially equipotential.

[0048] 15, there is shown a cutaway of a connector 1500 mounted on a PCB 1501 showing the engagement of the plug module, connector, and extended anti-pads on other copper layers of the PCB. On the PCB surface, these anti-pads contain the active signal mounting locations / ports, thereby forming the active port areas. If these active ports extend vertically below the surface of the PCB, they are effectively dielectric filled but copper free, and these active ports become active voids bounded by the copper portion of the PCB ground frame. These active voids can be managed to maintain high speed electrical performance through the desired breakout signal layers.

[0049] 16-32, connectors and various exemplary PCB layouts are shown according to embodiments discovered by the inventors using simulations. More specifically, FIGS. 16-19 show four different exemplary PCBs, labeled 1-4, and corresponding simulated mounting areas, where the surface area of ​​each mounting area includes a ground plane with an antipad and a surface area with a combined antipad surface area. More specifically, the surface area of ​​the ground plane and the combined antipad can be varied such that the surface area of ​​the ground plane and the combined antipad in each mounting area 1-4 are different. Thus, each mounting area 1-4 has a different percentage of ground plane coverage, as shown in Table 1 below. Stated differently, the surface area of ​​the ground plane, expressed as a first percentage of the total possible surface area of ​​each mounting area, increases across PCBs 1-4, while the surface area of ​​the combined antipad, expressed as a second percentage of the total surface area of ​​each mounting area, decreases. Note that the mounting areas of PCBs 1-4 include different antipad shapes and sizes corresponding to different antipad surface areas.

[0050] [Table 1]

[0051] It should be understood that the values ​​in Table 1 are exemplary. Additionally, the exemplary ground frame utilization percentages are calculated after excluding areas dedicated to active signal ports (see discussion below). The ground frame utilization corresponds to the amount of area dedicated to the surface ground plane area compared to the maximum area within the specified ground frame boundary.

[0052] FIG. 20 shows all four of the exemplary different PCB board mounting areas of CBS1-4 side by side. Referring to PCB4 in FIG. 20, an exemplary surface area of ​​ground frame mounting area 4000 is shown, with antipads 4001a-n plus signal mounting location areas 4002a-n. The antipads and signal mounting location surface areas combined together form an "active port area" that is energized by signal energy. In other words, the exemplary surface area of ​​the antipads 4001a-n (where "n" indicates the last antipad) and the exemplary surface area of ​​the signal mounting locations 4002a-n (where "n" indicates the last signal mounting location) combined, where the total surface area of ​​the antipads 4001a-n and the total surface area of ​​the signal mounting locations 4002a-n form the active port area. One of the objectives of the present invention is to prevent coupling from signals in one active port area to signals in another active port area.

[0053] It should be appreciated that the "first" percentage of the total surface area of ​​each ground frame mounting area as described herein may be calculated by subtracting the surface area of ​​the active port area from the total surface area of ​​the ground frame mounting area 4000. Thus, as the first percentage in each PCB 1-4 increases, the second percentage, represented as the active port area (4001a-n+4002a-n) in each PCB 1-4, decreases. Furthermore, as the utilization of the ground frame increases progressively, crosstalk decreases progressively.

[0054] 21-32 show exemplary graphs of insertion loss, crosstalk, impedance, and return loss for each of the four exemplary PCBs of FIGS. 16-20 and corresponding mounting surfaces based on simulations completed by the inventors. As is evident from the graphs of FIGS. 21-32, the PCBs numbered 3 and 4 include a larger ground plane surface area as a percentage of the total surface area of ​​the individual mounting areas than the PCBs numbered 1 and 2, providing reduced crosstalk as compared to the PCBs numbered 1 and 2. Thus, as the surface area of ​​the ground plane of the present invention increases as a percentage of the total surface area of ​​the individual mounting areas, and the total surface area of ​​the antipads plus the signal mounting locations (i.e., active port area) decreases as a percentage of the total surface area of ​​the individual mounting areas, undesirable crosstalk is reduced. The inventors further note that while crosstalk decreases progressively with increasing ground frame utilization, signal line impedance may not be optimally matched with the use of the maximally reduced antipad area. Thus, the exemplary anti-pad design shown in PCB3 (shown in FIG. 20) shows improved impedance matching performance over the anti-pad design shown in PCB4 (see FIGS. 27-29). Thus, by varying the surface area of ​​the anti-pad and the ground frame utilization, the inventors have provided an inventive approach to achieve a performance trade-off distinction, i.e., reduced noise coupling, while balancing the operational performance of the ground-coupled anti-pad for improved impedance matching. In this manner, good impedance matching and reduced noise can be balanced simultaneously to achieve overall performance. A further advantage of the inventive approach described herein is that it provides the ability to effectively balance both aspects of reduced noise coupling and impedance matching, optimizing the connector and associated PCB interface to provide an overall improved signal-to-noise ratio transfer and impedance matching performance. Thus, it can be seen that the anti-pad design illustrated in the exemplary PCB3 shown in FIG. 20 provides good impedance matching while at the same time providing a very good level of noise suppression.

[0055] Although benefits, advantages, and solutions have been described above with respect to particular embodiments of the present invention, it is to be understood that such benefits, advantages, and solutions, and any element or elements that cause or may cause such benefits, advantages, or solutions to be more pronounced, are not to be construed as critical, necessary, or as an essential feature or element of any or all claims appended to or resulting from this disclosure.

Claims

1. A connector, a plurality of wafers configured to form a mounting surface and a mating surface, the mounting surface further configured for mounting to an upper surface of a printed circuit board having a ground plane, a surface area of ​​the ground plane covering a predetermined percentage of a total surface area corresponding to a mounting area on the mounting surface, the mounting surface including at least one conductive surface electrically coupling to a ground, the at least one conductive surface including a plated edge of a ground wafer, an edge of a ground blade, or an edge of a tail insert, the connector configured for mounting on the printed circuit board such that the at least one conductive surface is within a predetermined distance of the ground plane, and further configured to operate at least at a predetermined data rate; a connector comprising: the plurality of wafers including a signal transmission wafer configured to support a plurality of signal terminals, each of the plurality of signal terminals including a tail portion, a contact portion, and a body portion extending between the contact portion and the tail portion, such that (i) the contact portions of the signal terminals are adjacent to the mating surface, and (ii) the tail portions of the signal terminals are adjacent to the mounting surface, forming the mounting area.

2. The connector of claim 1 , wherein the plurality of wafers includes a ground wafer.

3. 3. The connector of claim 2, wherein the at least one conductive surface electrically coupled to ground comprises a plated edge of the ground wafer.

4. the ground wafer includes a tail insert; The connector of claim 3 , wherein the at least one conductive surface electrically coupled to ground further comprises a portion of the tail insert positioned along the mounting area.

5. 4. The connector of claim 3, wherein the plurality of wafers includes a pair of ground wafers and a pair of signal carrying wafers positioned adjacent to one another and the ground wafers positioned on either side of the adjacent signal carrying wafers.

6. The connector of claim 3 , wherein the ground wafer comprises plated plastic.

7. The connector of claim 6 , wherein the ground wafer includes a tail insert.

8. 4. The connector of claim 3, further comprising transverse ground blades electrically coupling said ground wafers.

9. The connector of claim 8 , wherein the transverse ground blades include tails configured to electrically couple to the ground plane.

10. The connector of claim 9 , wherein the ground wafer includes a tail insert, and the transverse ground blades interdigitate with the tail insert.

11. The connector of claim 8 , wherein the transverse ground blades extend non-perpendicularly across the ground wafer.

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