Continuous-Time Linear Equalization (CTLE) adaptive algorithm enabling baud-rate clock data recovery (CDR) locked to the center of the eye

Abstract

An apparatus and related method relate to adapting a continuous-time linear equalization circuit with a minimum mean square error baud-rate clock and a data recovery circuit to lock onto or near the center of an eye diagram. In an illustrative example, the circuit may include an inter-symbol interference (ISI) detector configured to receive data samples and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voting circuit configured to generate votes corresponding to the average output and a predetermined threshold, and an integrator and code generator configured to generate a code signal corresponding to the generated votes. The introduction of the moving average filter and voting circuit provides a faster method for locking onto or near the center of an eye diagram.

Description

[Technical field]

[0001] Various embodiments relate generally to electronic circuits, and more particularly to clock data recovery (CDR) circuits in receivers. [Background technology]

[0002] A clock data recovery (CDR) circuit is an important block in a receiver system for high-speed serial communication. The CDR circuit can generate the correct sampling clock phase for data recovery. The quality of a high-speed serial communication link can be sensitive to the sampling clock phase, especially in the presence of jitter and noise.

[0003] In a receiver having a phase interpolator that determines the clock phase for sampling the incoming data, a CDR circuit can be used to identify whether the clock phase currently being used is optimal for capturing the incoming data. The CDR circuit can provide dynamic phase adjustment of the phase interpolator. The CDR circuit can operate to move the position of the clock phase toward the center of the data eye. The further the current clock phase is from the center of the data eye, the longer it takes the CDR circuit to lock onto the correct clock phase. Long lock times can lead to data loss.

[0004] One type of existing CDR circuit is an edge-sampled CDR circuit. An edge-sampled CDR circuit may oversample an analog input waveform to generate a correct data sampling dock and recover the transmitted data. An edge-sampled CDR circuit may assume the data to be sampled as near the center between the zero crossings. The resulting oversampled system may consume more clocking power than a system that operates at the symbol rate (also called the baud rate). Furthermore, as the channel loss profile changes, the analog waveform to be sampled may not always be symmetrical. Therefore, maintaining the data sampling dock at the center between the zero crossings may be suboptimal. Summary of the Invention

[0005] The apparatus and associated method relate to adapting a continuous-time linear equalization (CTLE) circuit with a minimum mean square error baud rate clock and a data recovery circuit to lock to the center or near the center of an eye diagram. In an illustrative example, the circuit may include an inter-symbol interference (ISI) detector configured to receive data samples and error samples, a summing circuit coupled to an output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voting circuit configured to generate a vote corresponding to the average output and a predetermined threshold, and an integrator and code generator configured to generate a code signal corresponding to the generated vote. By introducing the moving average filter and the voting circuit, a faster method of locking to the center or near the center of the eye diagram can be obtained.

[0006] Various embodiments may achieve one or more advantages. For example, in some embodiments, the CTLE adaptation may control the precursor and post-cursor inter-symbol interference (ISI) to a relatively small amount, instead of completely zeroing the precursor and post-cursor ISI. In some embodiments, instead of performing the adaptation by considering one bit of data sample at a time, an average of 128 bits of data samples may be calculated. Thus, the CDR adaptation may be performed more quickly. Also, the adaptation may accommodate a small amount of precursor and / or post-cursor ISI. Thus, the CTLE with MMSE baud rate CDR may be able to easily and quickly lock to or near the center of the eye diagram. The adaptation of the CTLE may settle faster. In some embodiments, by placing the lock point at or near the center of the eye diagram, a substantially equal margin may be obtained, and the receiver may be provided with sufficient margin to correctly sample the bits. In some embodiments, a programmable threshold (e.g., a user-defined value) may be received by the voting circuit to obtain different equalization performances. Some embodiments may allow a receiver to accept a small amount of inter-symbol interference (ISI), but still have the small amount of ISI well under control. In some embodiments, the use of CTLE adaptation may eliminate the use of finite-impulse response (FIR), and thus the power consumption of a serializer / deserializer (SerDes) system may be reduced if a small amount of ISI is tolerated.

[0007] In one example, the circuit comprises: (a) an intersymbol interference (ISI) detector configured to receive the data samples and the error samples, (b) a summing circuit configured to receive an output of the ISI detector and generate an adaptive information signal, (c) a moving average filter configured to receive the adaptive information signal from the summing circuit and generate an average output, (d) a voting circuit configured to generate votes in response to the average output and a predetermined threshold, and (e) an integrator and code generator configured to generate an adaptive code signal in response to the generated votes. An intersymbol interference (ISI) detector configured to receive the data samples and the error samples;

[0008] In some embodiments, the ISI detector may be configured to operate according to a truth table of the first post-cursor. In some embodiments, the ISI detector may be configured to operate according to a truth table of the first precursor. In some embodiments, the ISI detector may be configured to operate according to a truth table of the first precursor. In some embodiments, the voting circuit may include a comparator, and the comparator may be configured to generate a zero if the average output is equal to a predetermined threshold. In some embodiments, the comparator may be configured to generate a CTLE adaptation vote of −1, 0, or +1 at each adaptation cycle if the average output is greater than the predetermined threshold. In some embodiments, the accumulator and the code generator may include a register. In some embodiments, the predetermined threshold may range from 3 to 4. In some embodiments, the bit width of the data samples may be 128 bits. In some embodiments, the data samples may be derived from the transmit signal using a data slicer at a baud rate. In some embodiments, the error samples may be derived from the transmit signal using an error slicer at a baud rate.

[0009] In another example, a method includes (a) providing an inter-symbol interference (ISI) detector for receiving data samples and error samples; (b) configuring a summing circuit to receive an output of the ISI detector and generate an adaptive information signal; (c) configuring a moving average filter to receive the adaptive information signal from the summing circuit and generate an average output; (d) configuring a voting circuit to generate votes corresponding to the average output and a predetermined threshold; and (e) providing an integrator and a code generator for generating a code signal corresponding to the generated votes.

[0010] In some embodiments, the ISI detector may be configured to operate according to a truth table of the first post-cursor. In some embodiments, the ISI detector may be configured to operate according to a truth table of the first precursor. In some embodiments, the voting circuit may include a comparator configured to compare the average output with a predetermined threshold, and if the average output is equal to the predetermined threshold, the comparator may be configured to generate a zero. In some embodiments, if the average output is greater than the predetermined threshold, the comparator may be configured to generate a CTLE adaptation vote of -1, 0, or +1 at each adaptation clock cycle. In some embodiments, the accumulator and the code generator may include a register. In some embodiments, the predetermined threshold may range from 3 to 4. In some embodiments, the bit width of the data samples may be 128 bits. In some embodiments, the data samples may be derived from the transmit signal using a data slicer at a baud rate. In some embodiments, the error samples may be derived from the transmit signal using an error slicer at a baud rate.

[0011] The details of various embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. [Brief description of the drawings]

[0012] [Figure 1]FIG. 1 illustrates an example programmable integrated circuit (IC) in which the circuits and processes of the present disclosure may be implemented. [Figure 2A] FIG. 1 illustrates an exemplary communication system. [Figure 2B] FIG. 2 is a block diagram of an exemplary receiver. [Diagram 3] 2 is a block diagram of an example adaptation circuit implemented in a receiver. [Figure 4] 4 is a flow diagram of an exemplary method for implementing the adaptation circuit in FIG. 3. [Figure 5A] FIG. 2 illustrates a simulated eye diagram. [Figure 5B] FIG. 13 shows simulated results of the output of a moving average filter used in an adaptive circuit. [Figure 5C] FIG. 13 is a diagram showing waveforms of the settling behavior of the CTLE in a receiver. [Figure 6] FIG. 1 illustrates an exemplary architecture for a system-on-chip (SOC) type integrated circuit (IC). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Like reference symbols in the various drawings indicate like elements.

[0014] The apparatus and associated method relate to adapting a continuous-time linear equalization (CTLE) circuit with a minimum mean square error (MMSE) baud rate clock and a data recovery (CDR) circuit to lock to the center or near the center of an eye diagram. In an illustrative example, the circuit may include an inter-symbol interference (ISI) detector configured to receive data samples and error samples, a summing circuit coupled to an output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voting circuit configured to generate a vote corresponding to the average output and a predetermined threshold, and an integrator and code generator configured to generate a code signal corresponding to the generated vote. By introducing the moving average filter and the voting circuit, a faster method of locking to the center or near the center of the eye diagram can be obtained.

[0015] For ease of understanding, this document is organized as follows: First, with reference to FIG. 1, an exemplary platform suitable for performing data communications (e.g., an FPGA) is briefly introduced. Second, with reference to FIGS. 2A-4, we move to a description of an exemplary embodiment outlining an adaptation circuit and a method for implementing the adaptation circuit. Then, with reference to FIGS. 5A-5C, we describe exemplary simulation results of the performance of the adaptation circuit. Finally, with reference to FIG. 6, we briefly introduce another exemplary platform suitable for performing data communications and signal conversion (e.g., a system on chip (SOC)).

[0016] 1 shows an example programmable integrated circuit (IC) in which the circuits and processes of the present disclosure may be implemented. The programmable IC 100 includes FPGA logic. The programmable IC 100 may be implemented with a variety of programmable resources and may be referred to as a system on a chip (SOC). Various examples of FPGA logic may include several different types of programmable logic blocks in an array.

[0017] For example, Figure 1 shows a programmable IC 100 that includes a number of different programmable tiles, including a multi-gigabit transceiver (MGT) 101, a configurable logic block (CLB) 102, a block of random access memory (BRAM) 103, an input / output block (IOB) 104, configuration and clocking logic (CONFIG / CLOCKS) 105, a digital signal processing block (DSP) 106, specialized input / output blocks (I / O) 107 (e.g., clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic). The programmable IC 100 includes a dedicated processor block (PROC) 110. The programmable IC 100 may include internal and external reconfiguration ports (not shown).

[0018] In various examples, the serializer / deserializer may be implemented using the MGT 101. The MGT 101 may include various data serializers and data deserializers. The data serializer may include various implementations of a multiplexer. The data deserializer may include various implementations of a demultiplexer.

[0019] In some examples of FPGA logic, each programmable tile includes a programmable interconnect element (INT) 111 with standardized interconnects 124 between corresponding interconnect elements in each adjacent tile. The combined programmable interconnect elements thus implement a programmable interconnect structure for the illustrated FPGA logic. As shown in the example included in FIG. 1, the programmable interconnect element INT 111 includes internal connections 120 between programmable logic elements in the same tile. As shown in the example included in FIG. 1, the programmable interconnect element INT 111 includes inter-INT connections 122 between programmable interconnect elements INT 111 in the same tile.

[0020] For example, the CLB 102 may include a configurable logic element (CLE) 112 that can be programmed to implement user logic in addition to a single programmable interconnect element INT 111. The BRAM 103 may include a BRAM logic element (BRL) 113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a tile may depend on the height of the tile. In the depicted implementation, the BRAM tile has the same height as five CLBs, although other numbers (e.g., four) may be used. The DSP tile 106 may include a DSP logic element (DSPL) 114 and one or more programmable interconnect elements. The IOB 104 may include, for example, two instances of an input / output logic element (IOL) 115 and one instance of a programmable interconnect element INT 111. For example, the actual I / O bond pads that connect to the I / O logic elements 115 may be fabricated using metal layered over the various logic blocks shown, and may not be limited to the area of ​​the input / output logic elements 115.

[0021] In the depicted implementation, columnar regions near the center of the die (shown shaded in FIG. 1) are used for configuration, clocks, and other control logic. Horizontal regions 109 extending from the columns distribute clock and configuration signals across the width of the programmable IC 100. Note that references to "column-like" and "horizontal" regions are relative to a vertical view of the drawing.

[0022] Some programmable ICs utilizing the architecture shown in Figure 1 may include additional logic blocks that break up the normal columnar structure that occupies most of the programmable IC. The additional logic blocks may be programmable blocks and / or dedicated logic. For example, the processor block PROC 110 shown in Figure 1 spans multiple columns of CLBs 102 and BRAMs 103.

[0023] 1 illustrates an exemplary programmable IC architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect / logic implementation are provided merely as examples. For example, in an actual programmable IC, two or more adjacent columns of CLBs 102 may be included wherever a CLB 102 appears to facilitate efficient implementation of user logic.

[0024] High speed digital (HSD) integrated circuits (ICs) may be used in serializer / deserializer (SerDes) systems where a lossy channel may exist between the transmitter and receiver circuits and at high data rates the received data stream may be significantly distorted and require reconstruction (equalization) before use.

[0025] 2A shows an exemplary communication system. In this illustrated example, serial communication system 200 includes a transmitter 202 coupled to a receiver 204 via a transmission medium 206. The transmitter 202 may be part of a serializer-deserializer (SerDes) 208. The receiver 204 may likewise be part of a SerDes 210. The transmission medium 206 may include printed circuit board (PCB) traces, vias, cables, connectors, decoupling capacitors, etc. In some embodiments, the SerDes 208 may be located within an integrated circuit (IC) 212 and the SerDes 210 may be located within an IC 214.

[0026] The transmitter 202 sends serial data onto the transmission medium 206 using a digital baseband modulation technique. Typically, the serial data is divided into symbols. The transmitter 202 converts each symbol into an analog voltage mapped to the symbol. The transmitter 202 couples the analog voltage generated from each symbol to the transmission medium 206. In some embodiments, the transmitter 202 may use a binary non-return-to-zero (NRZ) modulation scheme. In binary NRZ, a symbol is one bit of serial data, and two analog voltages may be used to represent each bit. In some examples, the transmitter 202 may use a multi-level digital baseband modulation technique, such as pulse amplitude modulation (PAM), where a symbol includes multiple bits of serial data, and three or more analog voltages may be used to represent each bit.

[0027] The receiver 204 may include a clock and data recovery (CDR) circuit 216. The receiver 204 receives an analog signal from a transmission medium 206. The transmission medium 206 may degrade the signal quality of the transmitted analog signal. Channel insertion loss is a frequency-dependent degradation in the signal power of an analog signal. High-frequency components of an analog signal may be attenuated more than low-frequency components when the signal passes through a transmission medium. In general, channel insertion loss may increase with increasing frequency. Signal pulse energy of the analog signal may be spread from one symbol period to another symbol period during propagation on the transmission medium 206. The resulting distortion is known as inter-symbol interference (ISI).

[0028] The CDR circuit 216 operates to recover data and clock from the analog signal. The receiver 204 provides the recovered data to a physical coding sublayer (PCS) circuit 218 in the SerDes 210 for decoding and further processing. As shown in FIG. 2A, the transmitter 202 may use a transmitter reference clock 220 and the receiver 204 may use a receiver reference clock 222. In some embodiments, there may be a difference between the transmitter reference clock 220 and the receiver reference clock 222, which may be referred to as a frequency offset between the transmitter reference clock and the receiver reference clock 222. A frequency reference offset may exist when the transmitter reference clock 220 and the receiver reference clock 222 use independent clock sources (e.g., clock sources whose frequencies are nominally the same but not completely the same). In some embodiments, the frequency offset may be fixed (e.g., equal to a constant). In some embodiments, the frequency offset may not be fixed and may be, for example, a periodic function of time.

[0029] 2B shows a block diagram of an exemplary receiver. The receiver 204 includes a continuous time linear equalizer (CTLE) 224. The CTLE 224 is coupled to receive an analog signal from the transmission medium 206. The CTLE 224 may operate as a high-pass filter or a band-pass filter to compensate for the low-pass characteristics of the transmission medium 206. The peak of the frequency response of the CTLE 224 may be adjusted by an adaptation circuit 242.

[0030] The CTLE 224 outputs a first equalized analog signal 226. A decision circuit (e.g., a decision feedback equalizer (DFE)) 230 is coupled to an output of the CTLE 224 and receives the first equalized analog signal 226. The decision circuit 230 may be operable to equalize the first equalized analog signal 226 to compensate for post-cursor ISI. In this illustrated example, the decision circuit 230 also includes a slicer 228. The slicer 228 samples the first equalized analog signal 226 to generate a data sample Dk and an error sample Ek for each symbol k. Each of the slicers 228 may sample its analog input signal using a sampling clock at a baud rate (symbol rate) to generate the data sample and the error sample. The data sample Dk may include an estimated value for the symbol, and the error sample Ek may include an estimated decision error for the symbol. Each data sample Dk and each error sample Ek may contain one or more bits depending on the type of modulation scheme employed (eg, a one-bit sample for binary NRZ, a multi-bit sample for PAM).

[0031] In some embodiments, the receiver 204 may also include a deserializer (not shown) for grouping the data samples Dk and the error samples Ek to generate a deserialized signal to be processed by the CDR circuit 216. The clock manager 232 may be configured to generate a sampling clock signal 233 (e.g., a data sampling clock and / or an error sampling clock used by the slicer 228) from, for example, a sampling clock 237b output by a phase interpolator (PI) 238. Another input of the PI 238 is coupled to an output of a phase-locked loop (PLL) 236. In another example, the functionality of the clock manager 232 may be incorporated into the PI 238. The clock manager 232 may reduce the frequency of the sampling clock 237b provided by the PI 238.

[0032] The CDR circuit 216 is coupled to the output of the slicer 228 to receive the data samples Dk and the error samples Ek. In this illustrated example, the CDR circuit 216 generates a PI code signal 239 corresponding to the received data samples Dk and the error samples Ek. The PI 238 receives a reference clock signal 237a from the PLL 236. The PI 238 may shift the phase of the reference clock signal 237a based on the PI code signal 239 output by the CDR circuit 216. The PI 238 may output the phase-shifted reference clock signal as, for example, a sampling clock signal 237b used by the slicer 228. In some embodiments, the CDR circuit 216 may include a phase detector configured to receive the data samples Dk and the error samples Ek and generate the PI code signal 239. In some embodiments, the slicer 228 may include separate data slicers and error slicers. In some embodiments, the slicer 228 may include, for example, four error slicers.

[0033] The data samples Dk and error samples Ek may also be received by the adaptation circuit 242. In some embodiments, the adaptation circuit 242 may generate a control signal 244 and an adaptation control code 245 for the CTLE 224 to adapt the decision circuit 230 based on the data samples Dk and error samples Ek using known algorithms.

[0034] In this illustrated example, the adaptation circuit 242 includes an inter-symbol interference (ISI) detector 240. The ISI detector 240, coupled to receive the data samples Dk and the error samples Ek, determines whether and in what direction the phase of the data sampling clock signal 233 should be adjusted. The adaptation circuit 242 also generates an adaptation control code 245 for adapting the decision circuit 230. In some embodiments, the CDR circuit 216 may operate according to a minimum mean square error (MMSE) algorithm. In some embodiments, the CDR circuit 216 may operate according to a Mueller-Muller algorithm. An exemplary block diagram of the adaptation circuit 242 is described in detail with reference to FIG. 3.

[0035] In some embodiments, the receiver 204 may also include an automatic gain control (AGC) circuit. The output of the CTLE 224 may be coupled to an input of the AGC circuit. The AGC circuit may be used to control the gain of a high pass filter. The gain of the AGC circuit may also be controlled by the adaptation circuit 242. In some embodiments, the AGC circuit may precede the CTLE circuit 224. In other examples, the receiver 204 may include other types of continuous time filters, with or without amplification. In some embodiments, different algorithms may be used to make the CTLE circuit 224 visible only to the first post-cursor.

[0036] 3 shows a block diagram of an exemplary adaptation circuit implemented in a receiver. In this illustrated example, the adaptation circuit 242 includes an ISI detector 240. The data samples and error samples may be 128 bits. The ISI detector 240 receives the 128-bit data samples Dk (e.g., D(128)) and the 128-bit error samples Ek (e.g., E(128)) and generates a phase detection result signal, which provides a net phase detection result. In this illustrated example, the ISI detection result signal is used to generate a phase detector 234 for incrementing the phase of the sampling clock signal 233 corresponding to the received data samples Dk and error samples Ek. -1 h for decrementing the phase of the sampling clock signal 233. -1 The ISI detector 240 may operate according to a truth table 308 shown in FIG. 3. The truth table 308 may include a first post-cursor h 1 or the first precursor h -1 In this illustrated example, the phase of the sampling clock signal 233 is incremented (e.g., h -1 _inc) or decrement (e.g. h -1 To determine which data sample to add (D_curr_dec), the current data sample D_curr, the next data sample D_next1, and the current error sample E_curr are considered.

[0037] The adaptation circuit 242 includes a summing circuit 310. The summing circuit 310 receives, for example, h -1 Incremental signals 241a and h -1 Receives the decrement signal 241b and inputs it to the moving average filter 320. -1 In this illustrated example, the data samples Dk and error samples Ek may be 128 bits, so the moving average filter 320 filters 128 bits of h at a time. -1 Receive adaptation information and then h -1The moving average filter 320 may generate an average signal 325 of the adaptive information signal 315. Different mathematical algorithms may be used to configure the moving average filter 320 to obtain the average signal 325. In some embodiments, the moving average filter 320 may be a weighted moving average filter. In some embodiments, the moving average filter 320 may be a cumulative moving average filter. In some embodiments, the moving average filter 320 may be an exponential moving average filter. Other weighting systems may also be used to configure the moving average filter 320 to obtain the average signal 325.

[0038] The average signal 325 is received by the voting circuitry 330. The voting circuitry 330 is also configured to receive a predetermined value 335 and generates a voting signal 340 in response to the received average signal 325 and the predetermined value 335. In this illustrated example, the predetermined value 335 may be a programmable threshold indicating an acceptable moving average step size. By introducing a programmable threshold (e.g., a user-defined value), different equalization performance / results can be obtained. In some embodiments, the voting circuitry may include one or more comparators configured to indicate a relationship between the average signal 325 and the predetermined value 335. In some embodiments, the programmable threshold may range from 1 to 10, e.g., 3-4. Furthermore, the window boundaries of the predetermined value may be scaled by considering different design requirements, e.g., the effective number of error slicers and data slicers in the decision circuitry 230 and / or the bus width.

[0039] If the average signal 325 is greater than a predetermined value 335 (e.g., 3), the voting circuit 330 may generate a CTLE adaptation vote of −1, 0, or +1 at each adaptation clock cycle. If the average signal 325 is less than the predetermined value 335, the voting circuit 330 may generate a digital 0. If the average signal 325 is equal to the predetermined value 335, the voting circuit 330 may generate a digital −1. The accumulator and code generator 345 is configured to accumulate the voting signal 340 included in the output of the voting circuit 330, and outputs an adaptation control code signal 245 (e.g., a 32-bit signal) for controlling the DFE adaptation. In some embodiments, the accumulator and code generator 345 may include one or more registers. By introducing the moving average filter 320 and the voting circuit 330, the CTLE adaptation may control the precursor and post-cursor ISI to a relatively small amount instead of completely zeroing the precursor and post-cursor ISI. Also, the adaptation may accommodate a small amount of pre-cursor and / or post-cursor ISI. Thus, the CTLE 224 with the MMSE baud-rate CDR 216 may be able to easily and quickly lock onto or near the center of the eye diagram. Additionally, the adaptation may settle faster.

[0040] Figure 4 is a flow diagram of an exemplary method for implementing the adaptation circuit in Figure 3. A method 400 is described for implementing the adaptation circuit 242 described with reference to Figure 3. The method 400 includes, at 405, providing an inter-symbol interference (ISI) detector (e.g., ISI detector 240) for receiving data samples and error samples, for example, from a decision circuit (e.g., decision circuit 230 including slicer 228). The method 400 also includes, at 410, coupling a summing circuit (e.g., summing circuit 310) to an output of the ISI detector 240.

[0041] The method 400 also includes configuring a moving average filter (e.g., moving average filter 320) to receive the output of the summing circuit 310 and generate an average output (e.g., average signal 325), at 415. The method 400 also includes configuring a voting circuit (e.g., voting circuit 330) to generate a vote (e.g., voting signal 340), at 420, in response to the average output 325 and a predetermined threshold 335. The method 400 also includes providing an integrator and code generator (e.g., integrator and code generator 345), at 425, for generating a code signal in response to the generated vote 340. By introducing the moving average filter 320 and the voting circuit 330, the CTLE adaptation may control the precursor and post-cursor ISI to a relatively small amount, instead of completely zeroing out the precursor and post-cursor ISI. Also, the adaptation may accept a small amount of precursor and / or post-cursor ISI. Therefore, the CTLE 224 with an MMSE baud rate CDR 216 may be able to easily and quickly lock onto or near the center of the eye diagram.

[0042] FIG. 5A shows a simulated eye diagram. The adaptation circuit 242 described with reference to FIG. 3 is implemented in a system model and simulated. The result on the eye diagram with the lock point marked is shown in FIG. 5A. As shown in FIG. 5A, the eye locking (e.g., with MMSE baud rate CDR) is located in the center. By placing the lock point at or near the center of the eye diagram, a substantially equal margin can be obtained and the receiver 204 can be provided with enough margin to correctly sample the bits.

[0043] FIG. 5B shows simulated results of the output of the moving average filter used in the adaptive circuit. In this figure, the output of the moving average filter 320 used in the adaptive circuit 242 is shown. The output of the moving average filter 320 (e.g., average signal 325) is adjusted by the CTLE 224 to a window range of 3 to 4. The average signal 325 is adjusted by a window range of 3 to 4, which may be determined by the user, for example. -1 Vote Filter or h 1 It can be a voting filter. The first post-cursor h 1 and the first precursor h -1 The average signal generated based on is simulated and shown. The receiver may be able to tolerate a small amount of inter-symbol interference (ISI).

[0044] FIG. 5C shows the waveform of the settling behavior of the CTLE in the receiver. The settling behavior of the CTLE 224 in the receiver 204 is simulated. As shown in FIG. 5C, the CTLE control code is settled to a constant value within the control range 0 to 31. By introducing a moving average filter and a voting circuit, a faster way to lock to the center or near the center of the eye diagram can be obtained.

[0045] In this illustrated example, the adaptation circuit 242 is located on the same IC as the receiver 204 and the CTLE 224. In another embodiment, the adaptation circuit 242 may be implemented in a different IC (e.g., another FPGA) to control the equalization.

[0046] In some embodiments, the adaptation circuit 242 may be implemented as a hard block fixed circuit. For example, an application specific integrated circuit (ASIC) may provide the adaptation circuit for generating the adaptive code signal using customized hardware circuitry.

[0047] In some embodiments, some or all of the functionality of the adaptation circuitry 242 may be implemented in a processor configured to execute a set of instructions stored in a data store to control the equalization. For example, the functionality of the voting circuitry 330 may be implemented in a processor. In some embodiments, the processor may be located on the same integrated circuit, which may be an FPGA, with the receiver 204. For example, the adaptation circuitry 242 and the data store may be implemented in a programmable logic block of a system on chip (SOC) or may be implemented in a hard block using fixed circuitry of the SOC, and the receiver 204 may be implemented in another hard block, for example, using fixed circuitry of the SOC.

[0048] 6 shows an example architecture of a system-on-chip (SOC) type integrated circuit (IC). SOC 600 is an example of a programmable IC and an integrated programmable device platform. In the example of FIG. 6, various different subsystems or regions of the illustrated SOC 600 may be implemented on a single die provided in a single integrated package. In other examples, different subsystems may be implemented on multiple interconnected dies provided as a single integrated package.

[0049] In an example, SOC 600 includes multiple regions having circuits with different functionality. In an example, SOC 600 optionally includes a data processing engine (DPE) array 602. SOC 600 includes a programmable logic (PL) region 604 (hereinafter PL region or PL), a processing system (PS) 606, a network on chip (NOC) 608, and one or more hardwired circuit blocks 610. DPE array 602 is implemented as multiple interconnected hardwired programmable processors with interfaces to other regions of SOC 600.

[0050] The PL 604 is a circuit that can be programmed to perform a particular function. As an example, the PL 604 can be implemented as a field programmable gate array type circuit. The PL 604 can include an array of programmable circuit blocks. Examples of programmable circuit blocks in the PL 604 can include, but are not limited to, configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs, and / or UltraRAMs or URAMs), digital signal processing blocks (DSPs), clock managers, and / or delay locked loops (DLLs).

[0051] Each programmable circuit block in PL 604 typically includes both programmable interconnect circuitry and programmable logic circuitry. The programmable interconnect circuitry typically includes a number of interconnect wires of various lengths interconnected by programmable interconnect points (PIPs). Typically, the interconnect wires are configured (e.g., wire-by-wire) to provide connectivity on a bit-by-bit basis (e.g., each wire carries a single bit of information). The programmable logic circuitry implements the logic of a user design using programmable elements that may include, for example, look-up tables, registers, arithmetic logic, etc. The programmable interconnect and programmable logic circuitry may be programmed by loading configuration data into internal configuration memory cells that define how the programmable elements are configured and behave.

[0052] The PS 606 is implemented as a hardwired circuit fabricated as part of the SOC 600. The PS 606 may be implemented as or include any of a variety of different processor types, each capable of executing program code. For example, the PS 606 may be implemented as an individual processor, e.g., a single core capable of executing program code. In another example, the PS 606 may be implemented as a multi-core processor. In yet another example, the PS 606 may include one or more cores, modules, co-processors, interfaces, and / or other resources. The PS 606 may be implemented using any of a variety of different types of architectures. Examples of architectures that may be used to implement the PS 606 include, but are not limited to, an ARM processor architecture, an x86 processor architecture, a GPU architecture, a mobile processor architecture, a DSP architecture, or any other suitable architecture capable of executing computer-readable instructions or program code.

[0053] The NOC 608 includes an interconnection network for sharing data between endpoint circuits in the SOC 600. The endpoint circuits may be located in the DPE array 602, the PL area 604, the PS 606, and / or in the hardwired circuit blocks 610. The NOC 608 may include high-speed data paths with dedicated switching. In one example, the NOC 608 includes horizontal paths, vertical paths, or both horizontal and vertical paths. The arrangement and number of areas shown in FIG. 6 are merely examples. The NOC 608 is an example of a common infrastructure available in the SOC 600 to connect selected components and / or subsystems.

[0054] The NOC 608 provides connectivity to selected ones of the PL 604, the PS 606, and the hardwired circuit blocks 610. The NOC 608 is programmable. In the case of a programmable NOC used with other programmable circuits, the nets to be routed through the NOC 608 are not known until a user circuit design is created for implementation in the SOC 600. The NOC 608 may be programmed by loading configuration data into internal configuration registers that define how elements in the NOC 608, such as switches and interfaces to pass data from switch to switch and between NOC interfaces, are configured and operate.

[0055] The NOC 608 is manufactured as part of the SOC 600 and is not physically modifiable, but may be programmed to establish connectivity between different master and slave circuits of a user circuit design. For example, the NOC 608 may include a number of programmable switches capable of establishing a packet-switched network connecting user-specified master and slave circuits. In this regard, the NOC 608 may accommodate different circuit designs, each having a different combination of master and slave circuits implemented in different locations within the SOC 600 that may be coupled by the NOC 608. The NOC 608 may be programmed to route data, e.g., application data and / or configuration data, between the master and slave circuits of the user circuit design. For example, the NOC 608 may be programmed to couple different user-specified circuits implemented within the PL 604 with the PS 606 and / or the DPE array 602, different hardwired circuit blocks, and / or different circuits and / or systems external to the SOC 600.

[0056] The hardwired circuit blocks 610 may include input / output (I / O) blocks and / or transceivers for sending and receiving signals to and from circuits and / or systems external to the SOC 600, memory controllers, etc. Examples of various I / O blocks may include single-ended I / O and pseudo-differential I / O, as well as high-speed differential clock transceivers. Additionally, the hardwired circuit blocks 610 may be implemented to perform specific functions. Examples of the hardwired circuit blocks 610 include, but are not limited to, encryption engines, digital-to-analog converters, analog-to-digital converters, etc. The hardwired circuit blocks 610 within the SOC 600 may be referred to herein as application-specific blocks, where appropriate.

[0057] In the example of FIG. 6, the PL 604 is shown in two separate regions. In another example, the PL 604 may be implemented as an integrated region of programmable circuitry. In yet another example, the PL 604 may be implemented as three or more distinct regions of programmable circuitry. The particular organization of the PL 604 is not intended to be limiting. In this regard, the SOC 600 includes one or more PL regions 604, a PS 606, and a NOC 608. Optionally, a DPE array 602 may be included.

[0058] In other example implementations, SOC 600 may include two or more DPE arrays 602 located in different regions of the IC. In yet other examples, SOC 600 may be implemented as a multi-die IC, in which case each subsystem may be implemented on a different die. The different dies may be communicatively linked using any of a variety of available multi-die IC technologies, such as stacking the dies side-by-side on an interposer using a stacked die architecture where the IC is implemented as a multi-chip module (MCM), etc. It should be understood that in multi-die IC examples, each die may include a single subsystem, two or more subsystems, one subsystem and a partial subsystem, or any combination thereof.

[0059] A programmable integrated circuit (IC) refers to a type of device that includes programmable logic. One example of a programmable device or IC is a field programmable gate array (FPGA). An FPGA is characterized by including programmable circuit blocks. Examples of programmable circuit blocks include, but are not limited to, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), digital signal processing blocks (DSPs), processors, clock managers, and delay-locked loops (DLLs). Modern programmable ICs have evolved to include programmable logic in combination with one or more other subsystems. For example, some programmable ICs have evolved into systems-on-chips or "SOCs" that include both programmable logic and hardwired processors. Other types of programmable ICs include additional and / or different subsystems.

[0060] Although various embodiments have been described with reference to the figures, other embodiments are possible. For example, in some embodiments, other precursors and / or post-cursors can be used instead of the first precursor and the first post-cursor to generate the input for the moving average filter. For example, the moving average filter and the voting circuit can be extended to any other field using the MMSE algorithm for adaptation.

[0061] Various examples may be implemented using circuitry including various electronic hardware. By way of example and not limitation, the hardware may include transistors, resistors, capacitors, switches, integrated circuits, and / or other devices. In various examples, the circuitry may include analog and / or digital logic, discrete components, traces, and / or memory circuits fabricated on silicon substrates including various integrated circuits (e.g., FPGAs, ASICs). In some embodiments, the circuitry may include pre-programmed instructions and / or software execution executed by a processor. For example, various systems may include both hardware and software.

[0062] Some aspects of the embodiments may be implemented as a computer system. For example, various implementations may include digital and / or analog circuitry, computer hardware, firmware, software, or combinations thereof. The apparatus elements may be implemented in a computer program product tangibly embodied in an information carrier, e.g., a machine-readable storage device, for execution by a fixed hardware processor, and the methods may be executed by a programmable processor executing a program of instructions to perform the functions of the various embodiments by operating on input data to generate output. Some embodiments may be advantageously implemented in one or more computer programs executable on a programmable system including at least one processor coupled to transmit and receive data and instructions to and from a data store, at least one input, and / or at least one output. The data store may include one or more registers, or memory locations, for example, in a memory space. A computer program is a sequence of instructions that can be used directly or indirectly in a computer to perform a particular activity or bring about a particular result. The computer program may be written in any type of programming language, including compiled or interpreted languages, and the computer program may be deployed in any form, such as as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0063] In various embodiments, the computer system may include a non-transitory memory. The memory may be coupled to one or more processors, which may be configured to store computer-readable instructions, including data and processor-executable program instructions. The data and computer-readable instructions may be accessible to the one or more processors. The processor-executable program instructions, when executed by the one or more processors, may cause the one or more processors to perform various operations.

[0064] In various embodiments, the computer system may include an Internet of Things (IoT) device. An IoT device may include an object that is embedded with electronics, software, sensors, actuators, and network connections that allow it to collect and exchange data. An IoT device may be used with wired or wireless devices by transmitting data to another device through an interface. An IoT device may collect useful data and then autonomously stream the data between other devices.

[0065] Several implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, advantageous results may be achieved if the steps of the techniques of the present disclosure are performed in a different order, or if the components of the systems of the present disclosure are combined in a different manner, or if the components are supplemented with other components. Thus, other implementations are within the scope of the appended claims.

Claims

1. an inter-symbol interference (ISI) detector configured to receive data samples (Dk) and error samples (Ek), the ISI detector configured to generate an output comprising an increment signal for incrementing a phase of a sampling clock signal or a decrement signal for decrementing the phase of the sampling clock signal based on the data samples (Dk) and the error samples (Ek); a summing circuit configured to receive the output of the ISI detector and generate an adaptive information signal; a moving average filter configured to receive the adaptive information signal from the summing circuit and generate an average output; a voting circuit configured to generate a vote corresponding to the average output and a predetermined threshold; an integrator and code generator configured to generate an adaptive code signal in response to the generated votes; A circuit comprising:

2. 2. The circuit of claim 1, wherein the ISI detector is configured to operate according to a truth table of at least one of a first precursor or a first post-cursor.

3. 2. The circuit of claim 1, wherein the voting circuit comprises a comparator, the comparator configured to generate a digital -1 if the average output is equal to the predetermined threshold.

4. 4. The circuit of claim 3, wherein the comparator is configured to generate a continuous-time linear equalization (CTLE) adaptation vote of −1, 0, or +1 at each adaptation clock cycle if the average output is greater than the predetermined threshold.

5. The circuit of claim 1 , wherein the accumulator and code generator comprise registers.

6. The circuit of claim 1, wherein the adder circuit generates the adaptive information signal which is the difference between the increment signal and the decrement signal.

7. 2. The circuit of claim 1, wherein the data samples (Dk) are derived from a transmission signal at a baud rate using at least one of a data slicer or an error slicer.

8. providing an inter-symbol interference (ISI) detector for receiving data samples (Dk) and error samples (Ek), the ISI detector configured to generate an output including an increment signal for incrementing a phase of a sampling clock signal or a decrement signal for decrementing the phase of the sampling clock signal based on the data samples (Dk) and the error samples (Ek); configuring a summing circuit to receive the output of the ISI detector and to generate an adaptive information signal; configuring a moving average filter to generate an average output corresponding to said adaptive information signal; configuring a voting circuit to generate a vote responsive to said average output and a predetermined threshold; providing an integrator and a code generator for generating an adaptive code signal in response to said generated votes; A method comprising:

9. The method of claim 8 , wherein the ISI detector is configured to operate according to a truth table of at least one of a first precursor or a first post-cursor.

10. 9. The method of claim 8, wherein the voting circuitry comprises a comparator configured to compare the average output with the predetermined threshold, the comparator configured to generate a digital −1 if the average output is equal to the predetermined threshold.

11. 11. The method of claim 10, wherein the comparator is configured to generate a continuous-time linear equalization (CTLE) adaptation vote of −1, 0, or +1 at each adaptation clock cycle if the average output is greater than the predetermined threshold.

12. The method of claim 8 , wherein the accumulator and code generator comprise registers.

13. The method of claim 8, wherein the summing circuit generates the adaptive information signal which is the difference between the increment signal and the decrement signal.

14. 9. The method according to claim 8, wherein the data samples (Dk) have a bit width of 128 bits.

15. 9. The method of claim 8, wherein the data samples (Dk) are derived from a transmission signal at a baud rate using at least one of a data slicer or an error slicer.

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