Differential link alignment method and system

Abstract

The invention discloses a differential link alignment method and system, and relates to the field of data processing. The method comprises the following steps: under different delay times, judging whether a sampling edge of a clock signal is in a stable region of a differential link based on a training code; if yes, when a latch value obtained based on the sampling edge under the current delay time belongs to a first set, recording the judgment result as a first mark; otherwise, recording the judgment result as a second mark; arranging the first mark and the second mark according to the sequence of the delay time to obtain a mark set; in the mark set, screening out a middle mark of any first interval or second interval; and delaying the clock signal or the differential link based on the delay amount corresponding to the intermediate mark so as to realize data alignment of the differential link. Based on the processing, the sampling edge of the clock signal after data alignment can be prevented from being in the hopping region.

Description

Technical Field

[0001] This invention belongs to the field of data processing, and in particular relates to a method and system for aligning differential links. Background Technology

[0002] A differential link that uses differential signals for data transmission has the following actual waveform: Figure 1 As shown, a signal cycle contains both a stable region and a transition region. For differential links that use an external clock signal for triggering sampling (such as LVDS, Low Voltage Differential Signaling), when the rising or falling edge of the clock signal is in the transition region, it can easily lead to errors in the acquired data. Therefore, during data transmission in a differential link, the sampling point of the clock signal must fall within the stable region of the transmitted data.

[0003] Due to inherent delays in data transmission lines and data receiving terminals, phase deviations between the clock signal and the differential link are easily caused. To correct these phase deviations, a delayed scan is used to train the differential link upon power-up, aligning the clock signal with the differential link's data. Simultaneously, to improve the anti-interference capability of the aligned differential link, the sampling edges of the clock signal need to be aligned to the center of the stable time window.

[0004] However, during link training, when the delay step used to adjust the delay time exceeds the transition region, the transition region is very likely to be undetectable during the delay scan, resulting in the presence of the transition region in the stable time window, which leads to errors in the data alignment results of the differential link. Summary of the Invention

[0005] This application proposes a method and system for aligning differential links to avoid errors in data alignment results when the delay step exceeds the transition region of the differential link.

[0006] To achieve the above objectives, this application proposes the following technical solutions: In a first aspect of this application, a method for aligning differential links is provided, comprising: Under different delay times, the sampling edge of the clock signal is determined based on the training code to determine whether it is in the stable region of the differential link; if so, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag; wherein, the bits in the training code are not completely consistent; the first set includes the values ​​generated after the training code is cyclically shifted. Arrange the first and second flags according to the order of their delay times to obtain the flag set; In the set of flags, select any intermediate flag of either the first interval or the second interval; wherein, the first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags, and the interval between the delay times corresponding to the two endpoints of the first interval does not exceed a single signal cycle of the differential link; the second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags, and the interval between the delay times corresponding to the adjacent first flags on both sides of the second interval is higher than a single signal cycle but lower than two signal cycles. Delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag to achieve data alignment of the differential link.

[0007] Optionally, at different delay times, determining whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code includes: The same training code is input into the differential link at different delay times; Based on the sampling edge of the clock signal, the training code is sampled multiple times at the receiving end of the differential link to obtain multiple latch values; wherein the sampling edge is the upper edge or the lower edge of the clock signal. Determine whether the multiple latch values ​​are consistent; if yes, it indicates that the sampling edge of the clock signal is in the stable region of the differential link; if no, it indicates that the sampling edge of the clock signal is not in the stable region of the differential link.

[0008] Optionally, each delay time is obtained based on a fixed delay step size, and the highest delay time exceeds n signal cycles; where n represents the number of bits in the training code.

[0009] Optionally, if the first set includes only one value generated by cyclic shifting the training code, then the step of selecting the intermediate marker of any first interval or second interval is: Filter out any intermediate marker within an interval consisting of consecutive first markers.

[0010] Optionally, if the first set includes only two values ​​generated by cyclic shifting the training code, then the shift interval between the two values ​​is not less than 1 bit compared to the training code; When the shift interval between two values ​​is 1 bit, the method for selecting the middle flag of any first or second interval is as follows: Filter out any intermediate marker in an interval or a second interval consisting of consecutive first markers; When the shift interval between two values ​​exceeds 1 bit, the intermediate flag for selecting any one of the first or second intervals is: Filter out any intermediate marker of an interval consisting of consecutive first markers.

[0011] Optionally, if the first set includes m values ​​generated by cyclic shifting of the training code, then compared to the training code, among the m values, there are at least two adjacent shifted values ​​with a shift interval of 1 bit, or among the m values, there are at least three adjacent shifted values ​​with a shift interval of not less than 1 bit; where 3≤m≤n-1; Among the m values, if the maximum shift interval between adjacent shift values ​​is 1 bit, the intermediate flag for selecting any one of the first or second intervals is: Filter out the middle marker of any second interval.

[0012] Optionally, before arranging the first and second flags according to their delay times to obtain the flag set, the alignment method further includes: Under different delay times, determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if so, and the latch value obtained based on the sampling edge under the current delay time belongs to the second set, record the judgment result as the first flag; otherwise, record the judgment result as the second flag. The second set includes values ​​generated by cyclically shifting calibration values; the calibration values ​​represent latch values ​​obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

[0013] Optionally, if the second set consists of only one value generated by cyclically shifting the calibration value left by q bits, the maximum delay time exceeds q signal cycles.

[0014] Optionally, if n is even, and the second set includes n / 2 values ​​generated by cyclic shifting of latch values, and the shift interval between adjacent values ​​in the n / 2 values ​​is 1 bit, then the step of selecting any intermediate flag of the first interval or the second interval from the flag set includes: In the set of markers, for all intervals formed by consecutive first or second markers, after removing the first and last markers, filter the middle markers of any remaining interval.

[0015] In a second aspect of this application, an alignment system for differential links is provided, comprising: The flag recording module is used to determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code under different delay times. If it is, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag. The bits in the training code are not completely consistent. The first set includes the values ​​generated after the training code is cyclically shifted. The set generation module is used to arrange the first and second flags according to the order of their delay times to obtain a set of flags; The flag filtering module is used to filter out any intermediate flag in a first interval or a second interval from the flag set. The first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags. The interval between the delay times of the two endpoints in the first interval does not exceed a single signal cycle of the differential link. The second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags. The interval between the delay times of the adjacent first flags on both sides of the second interval is higher than a single signal cycle but lower than two signal cycles. The data alignment module is used to delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag, so as to achieve data alignment of the differential link.

[0016] The beneficial effects of this application are as follows: This application provides a method for aligning a differential link, comprising: determining, based on the training code, whether the sampling edge of the clock signal is in the stable region of the differential link under different delay times; if so, and the latch value obtained based on the sampling edge under the current delay time belongs to a first set, recording the judgment result as a first flag; otherwise, recording the judgment result as a second flag; wherein, the bits in the training code are not completely identical; the first set includes the values ​​generated after cyclic shifting of the training code; arranging the first flag and the second flag according to the order of the delay times to obtain a flag set; In the set of flags, any intermediate flag of the first interval or the second interval is selected; wherein, the first interval consists of consecutive first flags, and the flags adjacent to the outer sides of the first interval are all second flags, and the interval between the two endpoints of the first interval does not exceed a single signal cycle of the differential link; the second interval consists of consecutive second flags, and the flags adjacent to the outer sides of the second interval are all first flags, and the interval between the intervals of the delay times of the adjacent first flags on the outer sides of the second interval is higher than a single signal cycle but lower than two signal cycles; the clock signal or differential link is delayed based on the delay amount corresponding to the intermediate flag to achieve data alignment of the differential link.

[0017] Based on the above processing, the alignment method provided in this application uses two combined judgment methods to obtain the corresponding judgment result for each delay time. Compared with the prior art, this application sets a judgment means for whether the latch value belongs to the first set, which can make the judgment result flags corresponding to the stable regions in two adjacent signal periods different, so that the formed flag set contains at least a first interval and a second interval.

[0018] Meanwhile, based on the constraints of the first interval and the data latching characteristics of the differential link, it can be known that the stable time window corresponding to the first interval falls entirely within the stable region of the differential link, excluding any transition regions. Based on the constraints of the second interval and the data latching characteristics of the differential link, it can be known that although the two ends of the stable time window corresponding to the second interval belong to the transition regions of the differential link, the middle marker located in the center of the second interval can be determined to fall within the stable region. Therefore, by delaying the clock signal based on the delay amount corresponding to the middle marker or completing data alignment via the differential link, it is possible to avoid the sampling edge of the clock signal being in the transition region. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a differential link provided in this application; Figure 2 This is a schematic diagram of data sampling for a differential link provided in this application; Figure 3 This is a schematic diagram of data sampling of a differential link under different delay times provided in this application; Figure 4 This is another data sampling diagram of a differential link provided in this application under different delay times; Figure 5 This is a schematic diagram of a differential link alignment method provided in this application; Figure 6 This is a schematic diagram of another differential link alignment method provided in this application; Figure 7 This is a schematic diagram of the latching results of a differential link under different delay times provided in this application; Figure 8 This is a structural diagram of an alignment system for a differential link provided in this application; Figure 9 This is a structural diagram of an electronic device provided in this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0021] The voltage change process on the two lines transmitting a differential signal requires a certain amount of time, resulting in voltage change regions at both ends and a constant voltage region in the middle within one cycle of the differential signal. These are respectively considered the transition region and the stable region. Figure 1 As shown. Accordingly, by utilizing the rising or falling edge of the clock signal, the signal receiver can stably acquire logic "1" and logic "0" states from the constant voltage region.

[0022] In the field of machine vision, most image sensors use differential links for high-speed data transmission, with data and clock signals transmitted through different channels. Due to factors such as trace delays and process variations, there may be differences in skew between the different data and clock channels at the receiving end of the differential link (i.e., a phase difference exists between them). This causes the sampling edge of the clock signal to be located in the transition region of the differential signal in the differential link, leading to the risk of bit errors in data latching.

[0023] In this application, the differential link refers to a communication link that transmits data based on differential signals, such as LVDS. In the prior art, differential links are used in most cases, such as image sensor data acquisition and long-distance transmission of image data. The voltage levels range from LVDS to sub-LVDS to SLVS, and the interface types vary widely, from the CameraLink interface commonly used in industrial cameras, the MIPI interface commonly used in mobile phones, and the PCIe interface commonly used in computers.

[0024] Before performing effective data latching, the receiver of a differential link typically needs to align the differential link skew of the data channel to avoid the sampling edge of the clock signal being in the transition region of the differential signal in the differential link. This is known as link training.

[0025] A common link training method involves inputting a fixed training pattern into the differential link. The receiving end (e.g., FPGA) adjusts the idelay of the link channel or clock channel and determines whether the data is stable. This process is followed by window scanning, and the idelay window interval from which stable data is obtained after scanning is used as the stable time window. Finally, considering that changes in temperature, voltage, and other factors can cause the stable time window to shift, the idelay of the differential link or clock signal needs to be fixed at the center of the aforementioned stable time window interval. This improves the anti-interference capability of the trained differential link while ensuring stable latch values.

[0026] With the continuous development of signal transmission technology, the transition region width of differential links in existing signal transmission systems is relatively narrow (i.e., the data transition time is shorter). However, the delay time setting at the differential link receiver has certain precision limitations; that is, there is a minimum delay step size for adjusting the delay time. For example... Figure 2 As shown, during the link training process, there are cases where the delay step exceeds the transition region.

[0027] However, when the delay step used to adjust the delay time exceeds the transition region, there may be a problem in scanning the transition region during the steady-state time window scan, resulting in the transition region being included in the steady-state time window scanned using the delay time. Figure 3 , Figure 4 As shown. Specifically, Figure 3 This belongs to the link training method through the delay differential link. delay=1 indicates that the current delay is 1 delay step. The data corresponds to the differential link. bit0, bit1 and bit2 correspond to the numbers of the corresponding bits in the training code. The latch result represents the judgment result under the current delay. In the latch result, 1 corresponds to the flag when the clock signal can stably sample data under the current delay time (i.e., the sampling edge falls in the stable region of the differential link), and 0 corresponds to the flag when the clock signal cannot stably sample data under the current delay time (i.e., the sampling edge falls in the transition region of the differential link). Figure 4 This belongs to the link training method using delayed clock signals. The arrows correspond to the sampling edges of the clock signals at different delay times, and the stable time window is a time window composed of multiple delay times under which stable data can be sampled.

[0028] Therefore, under the aforementioned circumstances, when aligned to the center of the data stability window, the sampling edge of the clock signal is very likely to be in the transition region, causing the differential link training to fail and the data alignment result to be incorrect.

[0029] To avoid the aforementioned errors, this application provides an alignment method for differential links, such as... Figure 5 As shown, the method includes the following steps: S1. Under different delay times, determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if so, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, record the judgment result as the first flag; otherwise, record the judgment result as the second flag.

[0030] The bits in the training code are not completely identical; the first set includes the values ​​generated after cyclic shifting of the training code.

[0031] S2. Arrange the first and second flags according to the order of their delay times to obtain the flag set.

[0032] S3. In the set of markers, select any middle marker of the first interval or the second interval.

[0033] The first interval consists of consecutive first markers, and the adjacent markers on both sides of the outer side of the first interval are all second markers. The interval between the two endpoints of the first interval does not exceed a single signal cycle of the differential link. The second interval consists of consecutive second markers, and the adjacent markers on both sides of the outer side of the second interval are all first markers. The interval between the adjacent first markers on both sides of the outer side of the second interval is higher than a single signal cycle but lower than two signal cycles. S4. Delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag to achieve data alignment of the differential link.

[0034] Based on the above processing, the alignment method provided in this application uses two combined judgment methods to obtain the corresponding judgment result for each delay time. Compared with the prior art, this application sets a judgment means for whether the latch value belongs to the first set, which can make the judgment result flags corresponding to the stable regions in two adjacent signal periods different, so that the formed flag set contains at least a first interval and a second interval.

[0035] Meanwhile, based on the constraints of the first interval and the data latching characteristics of the differential link, it can be known that the stable time window corresponding to the first interval falls entirely within the stable region of the differential link, excluding any transition regions. Based on the constraints of the second interval and the data latching characteristics of the differential link, it can be known that although the two ends of the stable time window corresponding to the second interval belong to the transition regions of the differential link, the middle marker located in the center of the second interval can be determined to fall within the stable region. Therefore, by delaying the clock signal based on the delay amount corresponding to the middle marker or completing data alignment via the differential link, it is possible to avoid the sampling edge of the clock signal being in the transition region.

[0036] Regarding step S1, different delay times can be obtained by successively increasing a fixed delay step size, or by incrementally increasing a non-fixed delay step size to form a delay quantity. That is, the delay time in this application can be expressed as a delay quantity. In practice, to ensure the accuracy of the delay scan results, a fixed delay step size is usually used to form multiple delay times. Furthermore, the maximum value of the delay time in step S1 must exceed n signal periods. Here, the signal period represents the period of a single differential signal in the differential link, which can be calculated from the transmission rate of the differential link.

[0037] The training code is a binary value consisting of multiple bits. For example, a 12-bit training code could be 101110101101, and a 4-bit training code could be 1010. Note that in this application, the bits in the training code are not completely identical; that is, not all bits are 0 or not all bits are 1.

[0038] In step S1, the step of determining whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code under different delay times may include: Step a: Input the same training code into the differential link at different delay times.

[0039] Step b: Based on the sampling edge of the clock signal, the training code is sampled multiple times at the receiving end of the differential link to obtain multiple latch values. The sampling edge is either the upper or lower edge of the clock signal.

[0040] Step c: Determine whether the multiple latch values ​​are consistent; if yes, it means that the sampling edge of the clock signal is in the stable region of the differential link; if no, it means that the sampling edge of the clock signal is not in the stable region of the differential link.

[0041] Taking the training code 101110101101 as an example, with different delay times composed of a fixed delay step, when the delay step is 0, the training code is input from the differential link input terminal. Then, at the differential link receiving terminal, the training code is sampled multiple times continuously based on the clock signal to obtain multiple latch values ​​corresponding to the training code. The number of latch values ​​only needs to be higher than a preset threshold, which can be 1000 or 2000; the specific number is not limited in this application. Afterwards, it is determined whether the multiple latch values ​​are completely identical. If so, it indicates that the clock signal can be sampled stably and is in a stable state. If not, it indicates that the clock signal cannot be sampled stably, and the sampling edge is in the transition region.

[0042] Based on the fundamental concepts of differential link transmission, the clock signal is sampled only once within one signal cycle, yielding a single bit of data. Correspondingly, during the process of obtaining 2000 12-bit latched values ​​at the receiving end, the clock signal's sampling edges are triggered 24000 times.

[0043] Furthermore, for two different delay times, if the clock signals can be stably sampled and each delay time falls within two adjacent signal periods, the difference between the latch value obtained at the later delay time and the latch value obtained at the earlier delay time is a circular left shift of 1 bit. Specifically, taking the aforementioned 12-bit training code as an example, if the stably sampled latch value at the earlier delay time is 101101110101, then the stably sampled latch value at the later delay time is 110110111010. Similarly, this can be extended to: for two different delay times, if the data latch state is stable and the order difference between the signal periods corresponding to the delay times is 'a', then the difference between the latch value obtained at the later delay time and the earlier delay time is a circular left shift of 'a' bits.

[0044] In some embodiments, the first set provided in this application may consist of values ​​generated by cyclically shifting the training code, or it may include other values ​​besides those generated by cyclically shifting the training code. In practice, considering that the latched values ​​in the stable state in this application are all values ​​generated by cyclically shifting the training code, the only difference being that the latched values ​​obtained under different signal period sequences are generated by shifting different bits of the training code, the values ​​generated by cyclically shifting the training code are usually used to form the first set.

[0045] In this application, the first set may include only one value generated by cyclic shifting the training code; or only two values ​​generated by cyclic shifting the training code, wherein the shift interval between the two values ​​is not less than 1 bit compared to the training code; or two values ​​generated by cyclic shifting the training code, wherein the shift interval between the two values ​​is not less than 1 bit compared to the training code; or m values ​​generated by cyclic shifting the training code, wherein, compared to the training code, at least two adjacent shifted values ​​have a shift interval of 1 bit, or at least three adjacent shifted values ​​have a shift interval of not less than 1 bit. Where 3 ≤ m ≤ n-1. Based on the above settings, it can be guaranteed that a first interval or a second interval exists in the flag set obtained in step S2.

[0046] In some embodiments, step S1 may include the following: S101. Under different delay times, determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code. If not, record the judgment result as the second flag; otherwise, proceed to step S102.

[0047] S102. Determine if the latch value obtained based on the sampling edge under the current delay time belongs to the first set. If yes, record the judgment result as the first flag; otherwise, record the judgment result as the second flag.

[0048] Regarding step S1, the determination result represents a flag indicating the data latching state under the current delay time. The first flag and the second flag can be represented by two different numbers or high and low voltage levels. In this application, the number 1 is used to represent the first flag, and the number 0 is used to represent the second flag.

[0049] As can be seen from the aforementioned step S1, compared with the marking of latched state in the prior art, this application adds a judgment on whether the latched value belongs to the first set. Combined with the setting of elements in the aforementioned first set, it can be ensured that the time window corresponding to the first interval in the subsequent flag set does not contain the transition region, and the center of the time window corresponding to the second interval is not in the transition region, thereby avoiding errors in the data alignment results of the differential link.

[0050] For step S2, according to the number of delay steps contained in the delay time, the flags corresponding to each delay time are arranged in ascending order. These flags include a first flag and a second flag.

[0051] For step S3, if the total number of markers in the first or second interval is odd, then the marker at the middle point is directly selected as the middle marker. If the total number of markers in the first or second interval is even, then either of the two middle markers is selected as the middle marker.

[0052] Considering that in the data alignment process of a differential link, it is only necessary to delay the clock signal or the differential link based on a delay time, so that the sampling edge of the delayed clock signal is in a stable region, this application selects any intermediate flag of the first interval or the second interval and uses the delay time corresponding to the intermediate flag for data alignment.

[0053] In some embodiments, if the first set includes only one value generated by cyclic shifting of the training code, then the step of selecting the intermediate marker of any first interval or second interval is: Filter out any intermediate marker within an interval consisting of consecutive first markers.

[0054] Taking the 8-bit training code 10111001 as an example, if the first set only includes one value generated by cyclically shifting the training code, which is 01101110. When the delay step is 0, if the clock signal can be sampled stably, but the latched value is 11011100, which does not belong to the first set, the corresponding judgment result is 0. Increasing the delay time by one delay step and continuing to judge whether the clock signal can be sampled stably and whether the latched value belongs to the first set. As the delay time increases, when the sampling edge of the clock signal is in the stable region of the next signal cycle, it can be known that the clock signal can be sampled stably, the latched value is 01101110, which belongs to the first set, and the corresponding judgment result is 1.

[0055] As the delay step size continues to increase, if the sampling edge of the clock signal is not in the stable region of the next signal cycle, two possibilities arise. The first is that when the sampling edge is in the transition region, the judgment result for the corresponding delay time is 0. The second is that because the delay step size exceeds the transition region, the sampling edge is directly in the stable region of the next signal cycle. Since the latch value is 00110111, which does not belong to the first set, the judgment result for this delay time is 0.

[0056] As can be seen, by setting a judgment step on whether the latch value belongs to the first set, this application utilizes the characteristic of the latch value cyclically shifting under different signal periods, so that even when the clock signal can be sampled stably under adjacent clock periods, the corresponding judgment results are different, ensuring that the time window corresponding to the first interval composed of consecutive 1s is completely in the stable region, that is, the time window does not contain the jumping region.

[0057] It is understandable that for a training code of n bits, when the first set only includes one value generated by cyclic shifting of the training code, the current delay time can correspond to the first flag 1 only if the latch value is the same as one value in the aforementioned first set. The remaining delay times will correspond to the second flag 0. The flag set can be "00000111111100000000……00".

[0058] Since the time window corresponding to consecutive 0s contains multiple signal cycles and has a transition region, while the time window corresponding to consecutive 1s (i.e., the interval composed of consecutive first flags in this application) is only in the stable region of one signal cycle, any intermediate flag in the interval composed of consecutive first flags can be selected for subsequent differential link data alignment.

[0059] As can be seen from the foregoing explanation, by utilizing the step of determining whether a latched value belongs to the first set, this application can distinguish stable regions under different signal periods. To avoid the inclusion of transition regions within the time window corresponding to consecutive 1s, for multiple values ​​generated by cyclic shifting the training code in the first set, the shift interval between adjacent shifted values ​​is set to be at least 1 bit. Taking the 8-bit training code 10111001 as an example, the two values ​​with a shift interval of at least 1 bit can be 01101110 and 10011011. However, 01101110 and 00110111 do not meet the aforementioned requirement.

[0060] For multiple values ​​generated by cyclic shifting of training codes in the first set, when the shift interval between adjacent shift values ​​is 1 bit, the consecutive 0s between two consecutive 1s (the interval composed of consecutive second flags) meet the requirements of the second interval. The two ends of the corresponding time window belong to the transition region, but the middle part is a stable region. Therefore, after data alignment is completed by using the middle flag of consecutive 0s under the current situation, it can also be guaranteed that the delayed sampling edge is not in the transition region.

[0061] In some embodiments, if the first set includes only two values ​​generated by cyclic shifting of the training code, then the shift interval between the two values ​​is not less than 1 bit compared to the training code.

[0062] When the shift interval between two values ​​is 1 bit, the method for selecting the middle flag of any first or second interval is as follows: Filter out any intermediate marker of an interval or a second interval consisting of consecutive first markers. This process corresponds to: selecting the center point of any one of two time windows consisting of consecutive 1s, and the center point of a time window consisting of consecutive 0s between the two consecutive 1s.

[0063] When the shift interval between two values ​​exceeds 1 bit, the intermediate flag for selecting any one of the first or second intervals is: Filter out the middle marker of any interval consisting of consecutive first markers. This process corresponds to selecting the center point of any one of two time windows consisting of consecutive 1s.

[0064] If the first set includes m values ​​generated by cyclic shifting the training code, then compared to the training code, among the m values, there are at least two adjacent shifted values ​​with a shift interval of 1 bit, or among the m values, there are at least three adjacent shifted values ​​with a shift interval of not less than 1 bit. Wherein, 3≤m≤n-1.

[0065] In the m values, if the maximum shift interval between adjacent shift values ​​is 1 bit, it means that in the flag set, the consecutive 0s between two consecutive 1s belong to the second interval. Therefore, the step of filtering out any intermediate flag of the first or second interval is: Filter out the middle marker of any second interval. This process corresponds to selecting the center point of any one of two time windows consisting of consecutive 1s.

[0066] If the total number of bits n in the training code is even, and the first part includes n / 2 values ​​generated by cyclic shifting of latch values, and the shift interval between adjacent values ​​in these n / 2 values ​​is 1 bit, then the step of selecting any intermediate flag of the first interval or the second interval from the flag set includes: In the set of markers, for all intervals formed by consecutive first or second markers, after removing the first and last markers, filter the middle markers of any remaining interval.

[0067] Taking the 12-bit training code 101110101101 as an example, the values ​​obtained by cyclically shifting the training code right by 2 bits (011011101011), 4 bits (110110111010), 6 bits (101101101110), 8 bits (101011011011), 10 bits (111010110110), and 12 bits (101110101101) form the first set. After obtaining the flag set, the first consecutive interval (consecutive 1s or consecutive 0s) and the last consecutive interval are removed from the flag set. Then, the median value of the remaining consecutive 1s or consecutive 0s corresponding to the time window is selected as the delay time of the differential link or clock signal to achieve data alignment.

[0068] In some embodiments, prior to step S2, the alignment method provided in this application further includes step S5, which replaces step S1.

[0069] S5. Under different delay times, determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if so, and the latch value obtained based on the sampling edge under the current delay time belongs to the second set, record the judgment result as the first flag; otherwise, record the judgment result as the second flag. The second set includes values ​​generated by cyclically shifting calibration values; the calibration values ​​represent latch values ​​obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

[0070] Compared to step S1, in step S5, the elements in the second set are obtained by cyclically shifting the latch values ​​obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

[0071] In some embodiments, step S5 provided in this application includes the following: S501. Under different delay times, determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if not, record the judgment result of the current delay time as the second flag; if yes, proceed to step S502. S502. Determine whether the latch value obtained based on the sampling edge under the current delay time belongs to the second set. If yes, record the judgment result as the first flag; otherwise, record the judgment result as the second flag.

[0072] In some embodiments, if the second set includes only a single value generated by cyclically shifting the calibration value left by q bits, then the highest delay time exceeds q signal cycles. Based on the above settings, when the highest delay time exceeds q signal cycles, a first interval (i.e., consecutive 1s with a time window length less than 1 signal cycle) must exist in the flag set obtained in step S2, which can realize the data alignment scheme provided in this application.

[0073] In some embodiments, if n is even, and the second set includes n / 2 values ​​generated by cyclic shifting of latch values, and the shift interval between adjacent values ​​in the n / 2 values ​​is 1 bit, then selecting any intermediate flag of the first interval or the second interval from the flag set includes: In the set of markers, for all intervals formed by consecutive first or second markers, after removing the first and last markers, filter the middle markers of any remaining interval.

[0074] In the image data transmission process, the transmitting end of the differential link is the image sensor, and the receiving end is the FPPGA. The alignment process provided in this application is as follows: Step 1: Configure the sensor in a fixed training code output mode, such as 101110101101 (taking 12-bit as an example). Reset the delay to 0, continuously sample 2000 latch values ​​at the FPGA, and determine whether the 2000 latch values ​​are consistent. If they are, the state is stable at that delay; otherwise, it is not stable. When the data latch is stable, record the window latch result corresponding to the current delay (i.e., the judgment result of this application) as "1" (i.e., the first flag). When the data latch is not stable, record the window latch result corresponding to the current delay as "0" (i.e., the second flag).

[0075] Step 2: If the window latch result record in Step 1 is 1, then the latch value is cyclically shifted by an even number of positions to obtain n / 2 values, which are marked as valid training codes to form the second set. If the window latch result record in (1) is "0", then the valid training code is not marked for the time being.

[0076] Assuming the latch value is 101110101101, then the latch value is circularly shifted right by 2 bits (011011101011), 4 bits (110110111010), 6 bits (101101101110), 8 bits (101011011011), and 10 bits (111010110110). These 6 data points are then marked as valid training codes, forming the second set.

[0077] Step 3: Increase the delay amount configuration by 1 delay step. At this point, determine if the current delay time is in a stable state. When the data latch is stable and a valid training code has been marked, check if the latched data is consistent with the valid training code. If the data is stable and consistent with the valid training code, record the latch result value of this window as "1". Otherwise, record the latch result value of this window as "0". When the data latch is stable and a valid training code has not been marked before, mark the valid training code based on the current latch result.

[0078] Step 4: Repeat steps 2 and 3 until the delay time is configured to its maximum value. Remove the first consecutive 1 and the last consecutive 0 or 1 from the flag set. Select the delay time corresponding to the center value of the remaining consecutive "1" (or consecutive "0") and set it as the delay time of the clock signal or differential link to achieve data alignment of the differential link. That is, after obtaining the window stability condition corresponding to the entire delay range, fix the final delay time to the center value of consecutive "1" (or consecutive "0") to complete the data alignment of the differential link. The actual alignment process is as follows: Figure 6 As shown, the latching results under different delay values ​​are as follows: Figure 7 As shown.

[0079] Based on the above processing, the alignment scheme provided in this application can obtain an accurate stable time window even when the delay time accuracy is greater than the transition region of the differential link, thus avoiding the sampling edge of the clock signal after alignment being in the transition region and improving the reliability of data window scanning.

[0080] In some embodiments, such as Figure 8 As shown, this application also provides an alignment system for differential links, including: The flag recording module 801 is used to determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code under different delay times. If so, and the latch value obtained based on the sampling edge at the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag. The bits in the training code are not completely identical; the first set includes the values ​​generated after cyclic shifting of the training code.

[0081] The set generation module 802 is used to arrange the first and second flags according to the order of their delay times to obtain a set of flags.

[0082] The flag filtering module 803 is used to filter out any intermediate flag of a first interval or a second interval from the flag set; wherein, the first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags, and the interval between the corresponding delay times of the two endpoints in the first interval does not exceed a single signal cycle of the differential link; the second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags, and the interval between the corresponding delay times of the adjacent first flags on both sides of the second interval is higher than a single signal cycle and lower than two signal cycles.

[0083] The data alignment module 804 is used to delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag, so as to achieve data alignment of the differential link.

[0084] This application also provides an electronic device, such as... Figure 9 As shown, it includes a processor 901, a communication interface 902, a memory 903, and a communication bus 904, wherein the processor 901, the communication interface 902, and the memory 903 communicate with each other through the communication bus 904. Memory 903 is used to store computer programs; When the processor 901 executes the program stored in the memory 903, it implements any of the above-mentioned differential link alignment methods.

[0085] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0086] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0087] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0088] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0089] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the alignment method steps of any of the differential links described above.

[0090] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the alignment method steps of the differential link in the above embodiments.

[0091] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for aligning differential links, characterized in that, include: Under different delay times, the sampling edge of the clock signal is determined based on the training code to determine whether it is in the stable region of the differential link; If yes, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag; wherein, the bits in the training code are not completely consistent; the first set includes the values ​​generated after the training code is cyclically shifted; Arrange the first and second flags according to the order of their delay times to obtain the flag set; In the set of flags, select any intermediate flag of either the first interval or the second interval; wherein, the first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags, and the interval between the delay times corresponding to the two endpoints of the first interval does not exceed a single signal cycle of the differential link; the second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags, and the interval between the delay times corresponding to the adjacent first flags on both sides of the second interval is higher than a single signal cycle but lower than two signal cycles. Delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag to achieve data alignment of the differential link.

2. The alignment method according to claim 1, characterized in that, At different delay times, determining whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code includes: The same training code is input into the differential link at different delay times; Based on the sampling edge of the clock signal, the training code is sampled multiple times at the receiving end of the differential link to obtain multiple latch values; wherein the sampling edge is the upper edge or the lower edge of the clock signal. Determine whether the multiple latch values ​​are consistent; if yes, it indicates that the sampling edge of the clock signal is in the stable region of the differential link; if no, it indicates that the sampling edge of the clock signal is not in the stable region of the differential link.

3. The alignment method according to claim 1, characterized in that, Each delay time is obtained based on a fixed delay step size, and the highest delay time exceeds n signal cycles; where n represents the number of bits in the training code.

4. The alignment method according to claim 1, characterized in that, If the first set contains only one value generated by cyclic shifting of the training code, then the step of selecting the middle marker of any first interval or second interval is: Filter out any intermediate marker within an interval consisting of consecutive first markers.

5. The alignment method according to claim 1, characterized in that, If the first set includes only two values ​​generated by cyclic shifting the training code, then the shift interval between the two values ​​is not less than 1 bit compared to the training code; When the shift interval between two values ​​is 1 bit, the method for selecting the middle flag of any first or second interval is as follows: Filter out any intermediate marker in an interval or a second interval consisting of consecutive first markers; When the shift interval between two values ​​exceeds 1 bit, the intermediate flag for selecting any one of the first or second intervals is: Filter out any intermediate marker of an interval consisting of consecutive first markers.

6. The alignment method according to claim 1, characterized in that, If the first set includes m values ​​generated by cyclic shifting of the training code, then compared to the training code, among the m values, there are at least two adjacent shifted values ​​with a shift interval of 1 bit, or among the m values, there are at least three adjacent shifted values ​​with a shift interval of not less than 1 bit; where 3≤m≤n-1; Among the m values, if the maximum shift interval between adjacent shift values ​​is 1 bit, the intermediate flag for selecting any one of the first or second intervals is: Filter out the middle marker of any second interval.

7. The alignment method according to claim 1, characterized in that, Before arranging the first and second flags according to their delay times to obtain the flag set, the alignment method further includes: Under different delay times, determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code; if so, and the latch value obtained based on the sampling edge under the current delay time belongs to the second set, record the judgment result as the first flag; otherwise, record the judgment result as the second flag. The second set includes values ​​generated by cyclically shifting calibration values; the calibration values ​​represent latch values ​​obtained when the sampling edge of the clock signal is first in the stable region of the differential link.

8. The alignment method according to claim 7, characterized in that, If the second set contains only one value generated by cyclically shifting the calibration value left by q bits, then the highest delay time exceeds q signal cycles.

9. The alignment method according to claim 7, characterized in that, If n is even, and the second set includes n / 2 values ​​generated by cyclic shifting the latched values, and the shift interval between adjacent values ​​in these n / 2 values ​​is 1 bit, then selecting any intermediate flag of the first or second interval from the flag set includes: In the set of markers, for all intervals formed by consecutive first or second markers, after removing the first and last markers, filter the middle markers of any remaining interval.

10. An alignment system for differential links, characterized in that, include: The flag recording module is used to determine whether the sampling edge of the clock signal is in the stable region of the differential link based on the training code under different delay times; If yes, and the latch value obtained based on the sampling edge under the current delay time belongs to the first set, the judgment result is recorded as the first flag; otherwise, the judgment result is recorded as the second flag; wherein, the bits in the training code are not completely consistent; the first set includes the values ​​generated after the training code is cyclically shifted; The set generation module is used to arrange the first and second flags according to the order of their delay times to obtain a set of flags; The flag filtering module is used to filter out any intermediate flag in a first interval or a second interval from the flag set. The first interval consists of consecutive first flags, and the flags adjacent to each other on both sides of the first interval are second flags. The interval between the delay times of the two endpoints in the first interval does not exceed a single signal cycle of the differential link. The second interval consists of consecutive second flags, and the flags adjacent to each other on both sides of the second interval are first flags. The interval between the delay times of the adjacent first flags on both sides of the second interval is higher than a single signal cycle but lower than two signal cycles. The data alignment module is used to delay the clock signal or differential link based on the delay amount corresponding to the intermediate flag, so as to achieve data alignment of the differential link.

Images