Processing device, network node, client device, and methods thereof

Abstract

To provide a processing unit generating a second synchronous signal sequence used with a first synchronous signal sequence for synchronization.SOLUTION: A processing unit is configured such that a first circulation shift and a second circulation shift are determined at least on the basis of, a cell ID, at least one of the first circulation shift and the second circulation shift being associated with a first synchronous signal sequence by being determined also on the basis of an index of the first synchronous signal sequence. The processing unit is configured to generate a second synchronous signal sequence on the basis of a sum, with 2 as a modulus, of a first binary sequence cyclically shifted by the amount of the first circulation shift and a second binary sequence cyclically shifted by the amount of the second circulation shift. If two second synchronous signal sequences generated in association with the first synchronous signal sequence are cyclically shifted to each other, the generated two second synchronous signal sequences are non-sequentially shifted to each other.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a processing device, as well as to a network node and a client device comprising such a processing device. Furthermore, the present disclosure also relates to a corresponding method and a computer program product. [Background technology]

[0002] Synchronization is fundamental in most communication systems, for example those based on Long Term Evolution (LTE) or LTE Advanced. To enable client devices to synchronize with the network, at least one transmit-receive point (TRP) in each cell of the network transmits periodic synchronization signals. These synchronization signals are detected by nearby client devices and used by each client device to identify the appropriate cell as the serving cell. Synchronization thus enables a client device to connect to a TRP and track the connection between them for subsequent data communication.

[0003] In the LTE cellular system, the synchronization signal includes a primary synchronization signal (PSS) and a secondary synchronization signal (SSS). The PSS and SSS are each transmitted in each period, i.e., within each 5 ms, with a unique orthogonal frequency division multiplexing (OFDM) code. There are three PSSs and 168 SSSs that are used together to convey 3×168=504 cell identities (IDs). The 168 SSSs are further scrambled by the PSS sequence index and are also scrambled to indicate the first and second half-frame timing. Different PSS and SSS sequence pairs convey different cell IDs and are transmitted by TRPs in different cells. First, the client device obtains rough time and frequency synchronization by detecting the PSS in the time domain, and also detects the index carried in the PSS.

[0004]

number

[0005] The client device then receives the indicator transmitted by the SSS.

[0006]

number

[0007] is obtained by detecting the SSS in the frequency domain. And the cell ID is

[0008]

number

[0009] Specifically, the PSS sequence is constructed based on the Zadoff-Chu (ZC) sequence of length 63 with three different root indices, and the SSS sequence is constructed by splitting two m-sequences of length 31 with separate cyclic shifts m 0 and m 1 These two short m-sequences are constructed by alternating

[0010]

number

[0011] That is, there are 168 SSS sequences associated with each PSS sequence, and the second m sequence is scrambled based on a cyclic shift of the first m sequence. Cell ID N ID is the indicator

[0012]

number

[0013] and indicators

[0014]

number

[0015] , and the circular shift m 0 and m 1 are encoded in the SSS sequence by a unique invertible mapping between

[0016] The 3rd generation partnership project (3GPP) is currently working on defining the New Radio (NR) access technology. It has been agreed that NR synchronization should use 3NR PSS sequences based on m-sequences modulated with pure binary phase-shift keying (BPSK) with three different cyclic shifts. Furthermore, the number of NR SSSs will be about 1000 after scrambling. That is, each PSS sequence will correspond to about 333 SSS sequences. Therefore, 3 NR PSS will provide about 3 × 333 ≒ 1000 cell IDs, which is about twice the number of cell IDs available in LTE.

[0017] Current LTE SSS designs concatenate two short m-sequences and are subject to a high cross-correlation risk since there are many SSS sequence pairs where one of the two short m-sequences has the same cyclic shift. This high cross-correlation risk may lead to a high probability of inaccurate cell ID detection, especially during handover procedures. Summary of the Invention [Means for solving the problem]

[0018] It is an object of embodiments of the present invention to provide a solution that alleviates or overcomes the disadvantages and problems of conventional solutions.

[0019] These and further objects are achieved by the subject matter of the independent claims. Further advantageous implementations of the invention can be found in the dependent claims.

[0020] According to a first aspect of the present invention, the above and other objects are achieved by a processing device for generating a second synchronization signal sequence to be used together with a first synchronization signal sequence for synchronization, comprising: The processing unit performs a first cyclic shift m 0 and the second cyclic shift m 1 at least cell ID N IDand a first cyclic shift m 0 and the second cyclic shift m 1 At least one of the following is an index of the primary synchronization signal sequence:

[0021]

number

[0022] is also determined based on the first synchronization signal sequence, and is associated with the first synchronization signal sequence. The processing unit performs a first cyclic shift m 0 The first binary sequence is cyclically shifted by m 1 a second synchronization signal sequence based on a modulo-2 sum of a first binary sequence and a second binary sequence circularly shifted by a first digit, and if two second synchronization signal sequences generated in association with the first synchronization signal sequence are mutually circularly shifted, then the two generated second synchronization signal sequences are mutually non-sequentially shifted.

[0023] Thus, two second synchronization signal sequences generated in association with a first synchronization signal sequence, which are mutually cyclically shifted, cannot be mutually sequentially shifted. In other words, a first generated second synchronization signal sequence and a second generated second synchronization signal sequence, both associated with one and the same first synchronization signal sequence, where the first generated second synchronization signal sequence may be obtained by cyclically shifting the second generated second synchronization signal sequence and / or the second generated second synchronization signal sequence may be obtained by cyclically shifting the first generated second synchronization signal sequence, are only possible if the first and second generated second synchronization signal sequences are mutually non-sequentially shifted. That is, the first generated second synchronization signal sequence may be obtained only by cyclically shifting the second generated second synchronization signal sequence by more than one step and / or the second generated second synchronization signal sequence may be obtained only by cyclically shifting the first generated second synchronization signal sequence by more than one step.

[0024] The processing device according to the first aspect offers several advantages over conventional solutions: The advantage of the processing device is that the secondary synchronization signal SSS sequence is generated in a simple and efficient manner, such that low complexity and efficient encoding of the cell ID is provided.

[0025] Reducing the cross-correlation between secondary synchronization signal SSS sequences taking into account frequency offsets can be achieved by generating secondary synchronization signal SSS sequences that improve the reliability of secondary synchronization signal SSS sequence detection in client devices, thereby shortening cell search times.

[0026] Also, an efficient and low complexity mapping function can be coded and decoded in a closed form to obtain a sequence index from a cell ID and vice versa by generating and utilizing the secondary synchronization signal SSS sequence. This reduces the complexity of the network node and the client device and provides a fast and efficient method for determining the cell ID. At the client device, the descrambled received signal is efficiently detected, for example by utilizing the fast Walsh-Hadamard transform (FWHT).

[0027] Thus, the described embodiments allow for efficient encoding of the cell ID into the secondary synchronized SSS sequence, thereby ensuring low cross-correlation between the SSS sequences even with large residual frequency offsets, while at the same time allowing for a simplified mapping of the cell ID to the first and second cyclic shift values ​​and vice versa.

[0028] In one implementation of the processing device according to the first aspect, the first and second binary sequences are one in a group, the group being: m-sequence, and m-sequence, where the generated secondary synchronization signal sequence belongs to a set of Gold sequences It consists of:

[0029] An advantage of this implementation is that it ensures low cross-correlation between the generated SSS sequences when the first and second binary sequences utilized to generate the secondary synchronization signal SSS sequence are m-sequences, particularly when they are m-sequences such that the generated secondary synchronization signal SSS sequence belongs to a set of Gold sequences.

[0030] In one implementation of the processing device according to the first aspect, one of the first and second binary sequences utilized to generate the second synchronization signal SSS sequence is the same binary sequence, for example the same pseudo-random maximum length sequence, and is used to generate the one or more first synchronization signal PSS sequences.

[0031] In one implementation of the processing device according to the first aspect, the number of first synchronization signal sequences available for synchronization is one in a group, and the group includes: One primary synchronization signal sequence, Two or more primary synchronization signal sequences, and Three primary synchronization signal sequences, It consists of:

[0032] An advantage of this implementation is that the generation of the synchronization signal is flexible and adaptable to multiple cell IDs. By using one first synchronization signal PSS sequence, the complexity of the first synchronization signal detection can be reduced. By using two or more, e.g., three, first synchronization signal PSS sequences, a subset of the second synchronization signal SSS sequence can be associated with each first synchronization signal PSS sequence. In this way, after a successful detection of the first synchronization signal, only a subset of the second synchronization signal SSS sequence needs to be detected, thereby reducing the complexity of the second synchronization signal SSS detection. Therefore, this implementation is advantageous because it provides a trade-off between the detection complexity of the first synchronization signal and the second synchronization signal.

[0033] In one implementation of the processing device according to the first aspect, the generated second synchronization signal sequence has a length L of 127, where L=127.

[0034] An advantage of this implementation is that secondary synchronization signal (SSS) generation may be available for many currently available and soon to be available wireless systems.

[0035] In one implementation of the processing device according to the first aspect, the processing device is configured to: ID The first cyclic shift m associated with 0 and the second cyclic shift m 1 a processor further configured to determine: First cyclic shift m 0 and the second circular shift m 1 and m are equal 0 =m1 , First cyclic shift m 0 and the second cyclic shift m 1 and are different from each other, m 0 ≠m 1 , First cyclic shift m 0 is the second circular shift m 1 Greater than, m 0 >m 1 , First cyclic shift m 0 is the second circular shift m 1 Less than, m 0 <m 1 , Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, or Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second circular shift m 1 greater than m 0 >m 1 , Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second circular shift m 1 Less than m 0 <m 1 , m 0'=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are associated with different primary synchronization signal sequence indexes, m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are associated with different primary synchronization signal sequence indices, and the first cyclic shift m 0 is the second circular shift m 1 greater than m 0 >m 1 , and m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are associated with different primary synchronization signal sequence indices, and the first cyclic shift m 0 is the second circular shift m 1 Less than m 0 <m 1 , It consists of:

[0036] An advantage of this implementation is that it allows for flexible generation of the secondary synchronization signal SSS sequence, making it robust to large frequency offsets, which is also advantageous since it allows for further encoding of the 5 ms timing and / or adding other information to the secondary synchronization signal SSS sequence.

[0037] In one implementation of the processing device according to the first aspect, the processing device performs a first cyclic shift m 0and the second cyclic shift m 1 of,

[0038]

number

[0039] and further configured to determine: Where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0040]

number

[0041] is the index of the secondary synchronization signal sequence,

[0042]

number

[0043]

number

[0044] is the index of the primary synchronization signal sequence,

[0045]

number

[0046]

number

[0047] is the floor function, mod is the modulus operation.

[0048] The advantage of this implementation form is that robustness against a large frequency offset is guaranteed. Also, all cyclic shifts m of the second binary sequence 1 can be fully utilized. For example, by setting L' = L, when the total number of cell IDs encoded into the second synchronization signal SSS sequence is given, the number of candidate cyclic shifts m of the first binary sequence 0 can be minimized. This is advantageous because detecting the second synchronization signal SSS sequence at the client device can be implemented with such low complexity. In other words, the client device can first descramble the received signal sequence with the minimum number of cyclic shifts of the first binary sequence as a premise, and after descrambling assuming the correct cyclic shift of the first binary sequence, the remaining received signal sequence is only the second binary sequence with a certain unknown cyclic shift, and can be detected by using a low-cost fast Walsh-Hadamard transform FWHT operation.

[0049] In one implementation form of the processing device according to the first aspect, the processing device further configures to determine the first cyclic shift m 0 and the second cyclic shift m 1 as

[0050]

Number

[0051] where g is an integer greater than 1, Here, L' is a positive integer less than or equal to the length L of the second synchronization signal sequence,

[0052]

Number

[0053] is an index of the second synchronization signal sequence,

[0054]

Number

[0055]

number

[0056] is the index of the primary synchronization signal sequence,

[0057]

number

[0058]

number

[0059] is the floor function, mod is the modulus operation.

[0060] The advantage of this implementation is that it ensures robustness against large frequency offsets. This also allows the client device to detect the secondary synchronization signal SSS sequence at low cost based on descrambling and FWHT calculation. Furthermore, this implementation reduces the number of times m 0 <m 1 (or m 0 >m 1 The first circular shift m that satisfies all of the above 0 and the second cyclic shift m 1 This allows for further encoding of the 5 ms timing and / or simply 0 and m 1 By exchanging the values ​​of , it becomes possible to add other information to the secondary synchronization signal SSS sequence, or to create a solution that will not become obsolete if it is deemed useful to increase the number of assumptions in the secondary synchronization signal SSS sequence at a later time.

[0061] In one implementation of the processing device according to the first aspect, the processing device performs a first cyclic shift m 0 and the second cyclic shift m1 is further configured to be determined as

[0062]

Number

[0063] and, where here g is an integer greater than or equal to 1, L' is a positive integer less than or equal to the length L of the second synchronization signal sequence,

[0064]

Number

[0065] is an index of the second synchronization signal sequence,

[0066]

Number

[0067]

Number

[0068] is an index of the first synchronization signal sequence,

[0069]

Number

[0070]

Number

[0071] is the floor function, mod is the remainder operation.

[0072] The advantage of this implementation is that it ensures robustness against large frequency offsets. This also allows the client device to detect the secondary synchronization signal SSS sequence at low cost based on descrambling and FWHT calculation. Furthermore, when g=1, this implementation ensures that m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 It is possible to select a cyclic shift pair (m ′) for each of the two generated secondary synchronization signal SSS sequences, but to associate the corresponding pair of the two generated secondary synchronization signal PSS sequence indices with different primary synchronization signal PSS sequence indices. 0 ,m 1 ) can be selected, potentially allowing more cell IDs to be encoded into the secondary synchronization signal SSS sequence without increasing the SSS sequence length.

[0073] In one implementation of the processing device according to the first aspect, the processing device performs a first cyclic shift m 0 and the second cyclic shift m 1 of,

[0074]

number

[0075] and further configured to determine: Where: g is an integer equal to or greater than 1; L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0076]

number

[0077] is the index of the secondary synchronization signal sequence,

[0078]

number

[0079]

number

[0080] is the index of the primary synchronization signal sequence,

[0081]

number

[0082]

number

[0083] is the floor function, mod is the modulus operation.

[0084] The advantage of this implementation is that it ensures robustness against large frequency offsets. This also allows the client device to detect the secondary synchronization signal SSS sequence at low cost based on descrambling and FWHT calculation. Furthermore, when g=1, this implementation ensures that m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 It is possible to select a cyclic shift pair (m ′) for each of the two generated secondary synchronization signal SSS sequences, but to associate the corresponding pair of the two generated secondary synchronization signal PSS sequence indices with different primary synchronization signal PSS sequence indices. 0 ,m 1) can be selected, which potentially allows more cell IDs to be encoded into the secondary synchronization signal SSS sequence without increasing the SSS sequence length. 0 <m 1 (or m 0 >m 1 The first circular shift m that satisfies all of the above 0 and the second cyclic shift m 1 This allows for further encoding of the 5 ms timing and / or simply 0 and m 1 By exchanging the values ​​of , it becomes possible to add other information to the secondary synchronization signal SSS sequence, or to create a solution that will not become obsolete if it is deemed useful to increase the number of assumptions in the secondary synchronization signal SSS sequence at a later time.

[0085] According to a second aspect of the present invention, the above and other objects are achieved in a network node comprising: A processing device configured to generate a second synchronization signal sequence according to any implementation according to the first aspect or according to the first aspect itself; a transceiver configured to transmit a synchronization signal based on a first synchronization signal sequence and a second synchronization signal sequence; Prepare.

[0086] The network node according to the second aspect offers several advantages over conventional solutions: The advantage of the network node is that it allows for a simple and efficient way of generating secondary synchronisation signal SSS sequences.

[0087] According to a third aspect of the present invention, the above and other objects are achieved in a client device comprising: A processing device configured to generate a second synchronization signal sequence according to any implementation according to the first aspect or according to the first aspect itself; a transceiver configured to receive a second synchronization signal by utilizing the generated second synchronization signal sequence; A first cyclic shift m determined based on the received first synchronization signal and the received second synchronization signal. 0 and the second cyclic shift m 1 Based on cell ID N ID and a processing unit further configured to determine Prepare.

[0088] The client device according to the third aspect offers several advantages over conventional solutions. The advantages of the client device include a simple and efficient way of generating the secondary synchronization signal SSS sequence, a low complexity technique for detecting the secondary synchronization signal SSS sequence, and a low complexity method for determining the first cyclic shift m from the detected secondary synchronization signal SSS sequence. 0 and the second cyclic shift m 1 From cell ID N ID The advantage of this approach is that it allows for a simple and efficient way to decode

[0089] According to a fourth aspect of the present invention, the above and other objects are achieved in a method for determining a second synchronization sequence to be used together with a first synchronization signal sequence for synchronization, the method comprising: First cyclic shift m 0 and the second cyclic shift m 1 at least cell ID N ID determining based on a first cyclic shift m 0 and the second cyclic shift m 1 At least one of the following is an index of the primary synchronization signal sequence:

[0090]

number

[0091] and associating the first synchronization signal sequence with the first synchronization signal sequence by being determined based on First cyclic shift m 0 The first binary sequence is cyclically shifted by m 1and generating a second synchronization signal sequence based on a modulo 2 sum of a first binary sequence and a second binary sequence circularly shifted by a first cyclical shift by a second cyclical shift, where if two second synchronization signal sequences generated in association with the first synchronization signal sequence are circularly shifted versions of each other, then the two generated second synchronization signal sequences are non-sequentially shifted versions of each other.

[0092] In one implementation of the method according to the fourth aspect, the first and second binary sequences are one in a group, the group being: m-sequence, and m-sequence, where the generated secondary synchronization signal sequence belongs to a set of Gold sequences It consists of:

[0093] In one implementation of the method according to the fourth aspect, the number of first synchronization signal sequences available for synchronization is one in a group, the group being: One primary synchronization signal sequence, Two or more primary synchronization signal sequences, and Three primary synchronization signal sequences, It consists of:

[0094] In one implementation of the method according to the fourth aspect, the generated second synchronization signal sequence has a length L of 127, where L=127.

[0095] In one implementation of the method according to the fourth aspect, the method comprises: selecting at least one cell ID N according to one or more of the groups. ID The first cyclic shift m associated with 0 and the second cyclic shift m 1 The method further includes the step of: First cyclic shift m 0 and the second circular shift m 1 and m are equal 0 =m 1 , First cyclic shift m 0 and the second circular shift m 1 and are different from each other, m 0 ≠m1 , First cyclic shift m 0 is the second circular shift m 1 Greater than, m 0 >m 1 , First cyclic shift m 0 is the second circular shift m 1 Less than, m 0 <m 1 , Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, or Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second circular shift m 1 greater than m 0 >m 1 , Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second circular shift m 1 Less than m 0 <m 1 , m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m1 ) and (m 0 ',m 1 ') are associated with different primary synchronization signal sequence indexes, m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are associated with different primary synchronization signal sequence indices, and the first cyclic shift m 0 is the second circular shift m 1 greater than m 0 >m 1 , and m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are associated with different primary synchronization signal sequence indices, and the first cyclic shift m 0 is the second circular shift m 1 Less than m 0 <m 1 , It consists of:

[0096] In one implementation of the method according to the fourth aspect, the method comprises: 0 and the second cyclic shift m 1 of,

[0097]

number

[0098] and determining the Where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0099]

number

[0100] is the index of the secondary synchronization signal sequence,

[0101]

number

[0102]

number

[0103] is the index of the primary synchronization signal sequence,

[0104]

number

[0105]

number

[0106] is the floor function, mod is the modulus operation.

[0107] In one implementation of the method according to the fourth aspect, the method comprises: 0 and the second cyclic shift m 1 of,

[0108]

number

[0109] and determining the Where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0110]

number

[0111] is the index of the secondary synchronization signal sequence,

[0112]

number

[0113]

number

[0114] is the index of the primary synchronization signal sequence,

[0115]

number

[0116]

number

[0117] is the floor function, mod is the modulus operation.

[0118] In one implementation of the method according to the fourth aspect, the method comprises: 0 and the second cyclic shift m 1 of,

[0119]

number

[0120] and determining the Where: g is an integer equal to or greater than 1; L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0121]

number

[0122] is the index of the secondary synchronization signal sequence,

[0123]

number

[0124]

number

[0125] is the index of the primary synchronization signal sequence,

[0126]

number

[0127]

number

[0128] is the floor function, mod is the modulus operation.

[0129] In one implementation of the method according to the fourth aspect, the method comprises: 0 and the second cyclic shift m 1 of,

[0130]

number

[0131] and determining the Where: g is an integer equal to or greater than 1; L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0132]

number

[0133] is the index of the secondary synchronization signal sequence,

[0134]

number

[0135]

number

[0136] is the index of the primary synchronization signal sequence,

[0137]

number

[0138]

number

[0139] is the floor function, mod is the modulus operation.

[0140] The advantages of any method according to the fourth aspect are the same as the advantages of the corresponding processing device of the claim according to the first aspect.

[0141] According to a fifth aspect of the present invention, the above and other objects are achieved by a method for a network node, the method comprising: generating a second synchronization signal sequence according to a method according to a fourth aspect; and transmitting a synchronization signal based on the first synchronization signal sequence and the second synchronization signal sequence.

[0142] The advantages of any method according to the fifth aspect are the same as the advantages of the corresponding network node of the claim according to the second aspect.

[0143] According to a sixth aspect of the present invention, the above and other objects are achieved by a method for a client device, the method comprising: generating a second synchronization signal sequence according to a method according to a fourth aspect; receiving a secondary synchronization signal by utilizing the generated secondary synchronization signal sequence; A first cyclic shift m determined based on the received first synchronization signal and the received second synchronization signal. 0 and the second cyclic shift m 1 Based on cell ID N ID and determining:

[0144] The advantages of any method according to the sixth aspect are the same as the advantages of the corresponding client device of the claim according to the third aspect.

[0145] The present disclosure also relates to a computer program characterized by code means which, when executed by a processing means, causes the processing means to perform any of the methods according to the present disclosure. Furthermore, the present disclosure also relates to a computer program product, comprising a computer readable medium and the computer program as described above, the computer program being contained in the computer readable medium and comprising one or more from the group: Read-Only Memory (ROM), Programmable ROM (PROM), Erasable PROM (EPROM), Flash memory, Electrically EPROM (EEPROM) and Hard Disk.

[0146] Further applications and advantages of the present disclosure will become apparent from the following detailed description.

[0147] The attached drawings are intended to clearly illustrate various embodiments of the present invention.

Brief Description of the Drawings

[0148] [Figure 1] It is a diagram showing a processing device according to an embodiment of the present invention. [Diagram 2] It is a diagram showing a method for a processing device according to an embodiment of the present invention. [Diagram 3] It is a diagram showing a network node according to an embodiment of the present invention. [Figure 4] It is a diagram showing a method for a network node according to an embodiment of the present invention. [Diagram 5] It is a diagram showing a client device according to an embodiment of the present invention. [Figure 6] It is a diagram showing a method for a client device according to an embodiment of the present invention. [Figure 7] It is a diagram showing a wireless system according to an embodiment of the present invention. [Figure 8] It is an explanatory diagram of a determined cyclic shift according to an embodiment of the present invention. [Figure 9] It is another explanatory diagram of a determined cyclic shift according to an embodiment of the present invention. [Figure 10] It is another explanatory diagram of a determined cyclic shift according to an embodiment of the present invention. [Figure 11] It is another explanatory diagram of a determined cyclic shift according to an embodiment of the present invention. [Figure 12] It is another explanatory diagram of a determined cyclic shift according to an embodiment of the present invention. [Figure 13] It is another explanatory diagram of a determined cyclic shift according to an embodiment of the present invention.

Modes for Carrying Out the Invention

[0149] 1 illustrates a processing device 100 according to an embodiment of the present invention. The processing device 100 comprises a processor 102 connected to a memory 104. The processor 102 and the memory 104 are connected to each other by a communication means 106 known in the art. In one embodiment, the processor 102 may be a dedicated processor only for performing the generation of the secondary synchronization signal SSS sequence according to an embodiment of the present invention. In some embodiments, the processor 102 may alternatively be shared with other processors in the network node or client device and perform further processing.

[0150] The processing device 100 is for generating a secondary synchronization signal SSS sequence to be used together with a primary synchronization signal PSS sequence for synchronization, for example by a processor 102, which receives at least a cell ID N ID Based on the first circular shift m 0 and the second cyclic shift m 1 where the first cyclic shift m 0 and the second cyclic shift m 1 At least one of the following is an index of the primary synchronization signal PSS sequence:

[0151]

number

[0152] It is determined based on the primary synchronization signal PSS sequence and is associated with the primary synchronization signal PSS sequence.

[0153] The processing device 100, for example, by the processor 102, performs a first cyclic shift m 0 The first binary sequence is cyclically shifted by m 1and generating a second synchronization signal SSS sequence based on a modulo 2 sum of a first binary sequence and a second binary sequence circularly shifted by a factor of 1, such that if two generated second synchronization signal SSS sequences associated with the first synchronization signal PSS sequence are circularly shifted versions of each other, then the two generated second synchronization signal SSS sequences are non-sequentially shifted versions of each other.

[0154] FIG. 2 shows a flow chart of a corresponding method 200 that may be implemented on a processing device 100 such as that shown in FIG.

[0155] The method 200 performs a first cyclic shift m 0 and the second cyclic shift m 1 at least cell ID N ID where a first cyclic shift m 0 and the second cyclic shift m 1 At least one of the following is an index of the primary synchronization signal PSS sequence:

[0156]

number

[0157] It is determined based on the primary synchronization signal PSS sequence and is associated with the primary synchronization signal PSS sequence.

[0158] The method also includes a first cyclic shift m 0 The first binary sequence is cyclically shifted by m 1 The method includes a second step 204 of generating a second synchronization signal SSS sequence based on a modulo 2 sum of the first synchronization signal PSS sequence and a second binary sequence circularly shifted by 1, such that if two generated second synchronization signal SSS sequences associated with the first synchronization signal PSS sequence are circularly shifted versions of each other, then the two generated second synchronization signal SSS sequences are non-sequentially shifted versions of each other.

[0159] Figure 3 illustrates a network node 300 according to an embodiment of the present invention. In the embodiment shown in Figure 3, the network node 300 comprises a processing unit 100, a transceiver 302 and a memory 304. The processing unit 100 is connected to the transceiver 302 and the memory 304 by communication means 306 as known in the art. Furthermore, the network node 300 comprises an antenna 308 connected to the transceiver 302, meaning that the network node 300 is configured for wireless communication in a wireless communication system.

[0160] The processing unit 100 of the network node 300 is configured for generating a secondary synchronization signal SSS sequence according to any one of the embodiments of the method 200 described herein. The transceiver unit 302 of the network node 300 is configured for transmitting a synchronization signal based on the primary synchronization signal PSS sequence and the secondary synchronization signal SSS sequence.

[0161] Figure 4 shows a flow chart of a corresponding method 400 that may be executed in a network node 300 as shown in Figure 3. The method 400 comprises a first step 402 of generating a secondary synchronization signal SSS sequence according to any one of the embodiments of the method 200 described herein. The method further comprises a second step 404 of transmitting a synchronization signal based on the primary synchronization signal PSS sequence and the secondary synchronization signal SSS sequence.

[0162] Figure 5 illustrates a client device 500 according to an embodiment of the present invention. In the embodiment illustrated in Figure 5, the client device 500 comprises a processing unit 100, a transceiver 502, and a memory 504. The processing unit 100 is connected to the transceiver 502 and the memory 504 by communication means 506 known in the art. Furthermore, the client device 500 comprises an antenna 508 connected to the transceiver 502, which means that the client device 500 is configured for wireless communication in a wireless communication system.

[0163] The processing device 100 of the client device 500 is configured to generate a secondary synchronization signal SSS sequence according to any one of the embodiments described herein. The transceiver 502 of the client device 500 is configured to receive a secondary synchronization signal SSS by utilizing the generated secondary synchronization signal SSS sequence. Furthermore, the processing device 100 is configured to receive a first cyclic shift m determined based on the received primary synchronization signal PSS and the received secondary synchronization signal SSS. 0 and the second cyclic shift m 1 Based on cell ID N ID is configured to determine

[0164] Figure 6 shows a flow chart of a corresponding method 600 that may be performed in a client device 500 as shown in Figure 5. The method 600 comprises a first step 602 of generating a secondary synchronization signal SSS sequence according to any of the embodiments of the method 200 described herein. The method further comprises a second step 604 of receiving a secondary synchronization signal SSS by utilizing the generated secondary synchronization signal SSS sequence. The method also comprises a first cyclic shift m determined based on the received primary synchronization signal PSS and the received secondary synchronization signal SSS. 0 and the second cyclic shift m 1 Based on cell ID N ID A third step 606 is included, determining

[0165] FIG. 7 shows a wireless communication system 700 according to an embodiment. The wireless communication system 700 includes a network node 300 and a client device 500 configured to operate in the wireless communication system 700. Further, the network node 300 and the client device 500 each include a processing device 100. In the wireless communication system 700, a synchronization signal is transmitted by the network node 300 and received by the client device 500. Based on the synchronization signal, the client device 500 synchronizes with the network node 300 and obtains the cell ID of the network node 300 as described in this document. The synchronization signal includes a first synchronization signal PSS sequence and a second synchronization signal SSS sequence, where the second synchronization signal SSS sequence is generated by the processing device 100 in the network node 300. The client device 500 receives the synchronization signal using the second synchronization signal SSS sequence generated by the processing device 100 in the client device 500, for example, for correlation, as described in this document.

[0166] For simplicity, the wireless communication system 700 shown in FIG. 7 includes only one network node 300 and only one client device 500. However, the wireless communication system 700 may include any number of network nodes 300 and any number of client devices 500 without departing from the scope of the present invention.

[0167] The network node 300 may also be referred to as a radio network node, an access network node, an access point, or a base station, e.g., a Radio Base Station (RBS). Certain networks may also be referred to as transmitters, "gNB", "eNB", "eNodeB", "NodeB" or "B node", depending on the technology and terminology used. Radio network nodes may be of various classifications, e.g., macro eNodeB, home eNodeB, or pico base station, based on the transmission power and thus the size of the cell. The radio network node may also be a station (STA). The station (STA) is any device that includes an IEEE 802.11 compliant media access control (MAC) and a physical layer (PHY) interface to the wireless medium (WM). The network node 300 may also be a base station compatible with the fifth generation wireless system.

[0168] The client device 500 here may be referred to as a user device, User Equipment (UE), mobile station, Internet of Things (IoT) device, sensor device, wireless terminal, and / or mobile terminal, and may be capable of wireless communication in a wireless communication system, which may be referred to as a cellular wireless system. Furthermore, the UE may be a wireless-enabled mobile phone, cellular telephone, computer tablet, or laptop. In this context, the UE may be a portable, pocketable, handheld, computer-implemented, or vehicle-mounted mobile device capable of communicating voice and / or data with others, such as other receivers or servers, over a wireless access network. The UE may be a Station (STA), which is any device that includes an IEEE 802.11 compliant Media Access Control (MAC) and a Physical Layer (PHY) interface to the Wireless Medium (WM). Client device 500 may also be configured for communication in fifth generation wireless technologies such as 3GPP related LTE and LTE Advanced, WiMAX and its evolution, and New Radio.

[0169] Furthermore, any method according to the embodiments of the present invention may be implemented in a computer program having code means, which, when executed by a processing means, causes the processing means to perform each step of the method. The computer program may be included in a computer readable medium of a computer program product. The computer readable medium may include substantially any memory, such as a Read-Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable PROM (EPROM), a flash memory, an Electrically Erasable PROM (EEPROM), or a hard disk drive.

[0170] Further, it will be understood by those skilled in the art that the embodiments of the processing device 100, the network node 300 and the client device 500 include the necessary communication capabilities, for example in the form of functions, means, units, elements, etc., to perform the present solution. Other examples of such means, units, elements, functions, etc. are processors, memories, buffers, control logic, encoders, decoders, rate matchers, de-rate matchers, mapping units, multipliers, decision units, selection units, switches, interleavers, de-interleavers, modulators, demodulators, inputs, outputs, antennas, amplifiers, receiving units, transmitting units, DSPs, MSDs, TCM encoders, TCM decoders, feeding units, feeding lines, communication interfaces, communication protocols, etc., suitably arranged together to perform the present solution.

[0171] In particular, the processors of the devices and nodes may comprise one or more instances of a Central Processing Unit (CPU), processing unit, processing circuit, processor, Application Specific Integrated Circuit (ASIC), microprocessor, or other processing logic that may, for example, interpret and execute instructions. Thus, the term "processor" may refer to processing circuitry that includes a plurality of processing circuits, such as some, some, or all of those described above. The processing circuitry may further perform data processing functions for input, output, and processing of data, including data buffering and device control functions, such as call processing control, user interface control, etc.

[0172] According to one embodiment, the first and second binary sequences utilized to generate the secondary synchronization signal SSS sequence are pseudorandom maximal length sequences, or m-sequences.

[0173] According to one embodiment, the first and second binary sequences utilized to generate the secondary synchronization signal SSS sequences are pseudo-random maximal length sequences, i.e. m-sequences, and the generated secondary synchronization signal SSS sequences belong to a set of Gold sequences based on the m-sequences so as to ensure low cross-correlation between the generated SSS sequences. Gold sequences are described in more detail below.

[0174] In one embodiment, one of the first and second binary sequences utilized to generate the secondary synchronization signal SSS sequence is the same binary sequence, e.g., the same pseudo-random maximum length sequence, that is used to generate the one or more primary synchronization signal PSS sequences.

[0175] As described below, in various embodiments, various numbers of primary synchronization signal PSS sequences may be available for the synchronization signal, such as one primary synchronization signal PSS sequence, two or more primary synchronization signal PSS sequences, and three primary synchronization signal PSS sequences. Thus, the generation of secondary synchronization signal SSS sequences described herein may be used with different numbers of primary synchronization signal PSS sequences, making the generation of the synchronization signal flexible and adaptable to multiple cell IDs and / or wireless systems.

[0176] According to one embodiment, as illustrated below, the generated secondary synchronization signal SSS sequence has a length L of 127. L=127, which is suitable for some currently available and soon to be available wireless systems in which the embodiments described herein may be implemented.

[0177] One embodiment of the present invention discloses SSS sequences, d(k), k=0, 1, 2,..., L-1, which are transformed by a cyclic shift m 0 and m 1 can be constructed based on the modulo 2 sum of two binary sequences of length L with different lengths. According to one embodiment, BPSK modulation is used, i.e. d(k)=1-2((s 0 ((k+m 0) mod L)+s 1 ((k+m 1 ) mod L)) mod 2), k=0, 1, 2,…, L-1 (Formula 1)

[0178] The two binary sequences may be chosen, for example, as two m-sequences of the same length L with carefully selected generator polynomials, such that all generated SSS sequences belong to the same set of Gold sequences, which ensures low cross-correlation between the generated SSS sequences.

[0179] For example, the generating polynomials are g 0 (x)=x 7 +x 4 +1 and g 1 (x)=x 7 +x+1. This produces a set of Gold sequences of length L=127, of which n=7 may be chosen as g 0 (x) and g 1 The highest order of (x) is 1, 2, so that the absolute inner product of any two series is 1, 2. (n+1) / 2 -1=15 or 2 (n+1) / 2 +1=17.

[0180] According to an embodiment, one of the first and second binary sequences used to generate the second synchronization signal SSS sequence may be selected as the same binary sequence, for example the same pseudorandom maximum length sequence, and is used to generate the first synchronization signal PSS sequence. In this way, the same binary sequence, for example the same m-sequence, may be used here both for generating the first synchronization signal PSS sequence and for generating one of the first and second binary sequences used to generate the second synchronization signal SSS sequence. For example, both the generated first synchronization signal PSS sequence and the generated second synchronization signal SSS sequence may belong to the same set of Gold sequences, thereby also ensuring low cross-correlation between the generated second synchronization signal SSS sequence and the generated first synchronization signal PSS sequence.

[0181] Cell ID

[0182]

number

[0183] are the series indices of SSS and PSS, i.e.,

[0184]

number

[0185] and

[0186]

number

[0187] The first m of two binary sequences, e.g., two m sequences, is transmitted by 0 and the second m 1 If the PSS is multiple, the first m 0 and the second m 1 At least one of the cyclic shifts depends on the PSS sequence index. Also, if the generated SSS sequences are associated with the same PSS sequence index, it is guaranteed that the cross-correlation is low even with a large residual frequency offset. This is because one SSS sequence cannot be obtained by cyclically shifting another SSS sequence associated with the same PSS index in one step.

[0188] According to one embodiment, m 0 '=m 0 +1 and m 1 '=m 1 The two cyclic shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 In other words, this means that for any two SSS cyclic shift pairs (m 0 ,m1 ) and (m 0 ',m 1 '), m 0 '=m 0 +1 and m 1 '=m 1 +1, at most. This ensures advantageous robustness against large frequency offsets. The cyclic shift pair according to this embodiment may be obtained, for example, by encoding the sequence index conveyed in the PSS, i.e.

[0189]

number

[0190] is a cyclic shift of one of the two binary sequences, for example the first cyclic shift m 0 and the first cyclic shift m 0 It is necessary that any two candidate values ​​of m are separated from each other by more than one (1) cyclic shift step. In this way, sequential cyclic shifts of the first binary sequence are not selected simultaneously. This also means that only non-sequential cyclic shifts of the first binary sequence are selected. The first cyclic shift m 0 is kept here at a minimum so that SSS detection based on low complexity / cost scrambling FWHT is utilized within the client device 500.

[0191] The sequence index conveyed by the SSS, i.e.

[0192]

number

[0193] is the first m 0 and the second m 1 where the second cyclic shift m 1L is allowed to span all or most of its valid values ​​{0, 1, 2, ..., L-1}. Such an SSS design avoids that one SSS sequence can be obtained by cyclically shifting another SSS sequence by one cycle shift step, thereby ensuring robustness against large frequency offsets.

[0194] In addition, the PSS series index

[0195]

number

[0196] The first circular shift m 0 The index of the SSS sequence is encoded as

[0197]

number

[0198] The first circular shift m 0 and the second cyclic shift m 1 The encoding of m can be done in any way. For example, 0 and m 1 may be exchanged in the following formula: 0 Given a value of , the second circular shift m 1 The number of candidate values ​​of is determined by the first circular shift m 0 The various values ​​of may be the same or different.

[0199] According to one implementation of this embodiment, the index of the SSS sequence

[0200]

number

[0201] and PSS series indicators

[0202]

number

[0203] 1st m 0 and the second m 1 The encoding of m into a cyclic shift is obtained as follows: 0 and the second cyclic shift m 1 is determined as follows:

[0204]

number

[0205] where g is the first cyclic shift m 0 L' is a positive integer less than or equal to the length L of the SSS sequence, where L'≦L, which also means that for a given first cyclic shift m 0 The second circular shift m for 1 Here, and in this document,

[0206]

number

[0207] denotes a floor function, and mod denotes a modulus operation. Since g>1, any two SSS sequences (m 0 , m 1 ) and (m 0 ',m 1 The circular shift of 0 '=m 0 +1 and m 1 '=m 1 Satisfy at most one of +1.

[0208] As a non-limiting example, L=127 and

[0209]

number

[0210] It can be said that the implementation of the New Radio synchronization signal in this embodiment may be implemented. For example, g=2,

[0211]

number

[0212] And with L'=112, a total of 336×3=1008 cell IDs are transmitted.

[0213] A schematic and non-limiting description of this example in the present embodiment is given below:

[0214]

number

[0215]

number

[0216] , for L=15, g=2 and L'=8, as shown in Figure 8. Since g=2, m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 There is no m ') in the diagonal direction. This is illustrated in FIG. 8, where all second positions along the diagonal direction are left unused. That is, positions that can be selected (black dots) are separated in the diagonal direction by positions that cannot be selected (white dots). In this document, the diagonal direction associated with the figure is referred to as m 0 =m 1 +c, where c is any integer. Thus, in the illustration of FIG. 8, 0 '=m 0 +1 and m 1'=m 1 +1 and +2 cannot be satisfied at the same time. PSS series indicators

[0217]

number

[0218] is on the y-axis, where m 0 =0 and m 0 = 2 both have the same PSS series index

[0219]

number

[0220] That is, m 0 =0 and m 0 = 2 both have the same PSS series index

[0221]

number

[0222] Accordingly, m 0 = 4 and m 0 =6 are both the same PSS series index

[0223]

number

[0224] It is related to the PSS series index.

[0225]

number

[0226] The first circular shift m of 0 Associations with and SSS index

[0227]

number

[0228] m 0 and m 1 The association of is not constrained to the order shown in Figure 8. Alternatively, any other order is possible.

[0229] Furthermore, cell ID N ID According to an embodiment, the first cyclic shift m 0 and the second cyclic shift m 1 This may be determined based on the first m 0 and the second m 1 From the circular shift value of PSS

[0230]

number

[0231] and SSS

[0232]

number

[0233] This is possible because there exists a simple inverse mapping to the sequence indices, which may be written, for example, as follows:

[0234]

number

[0235]

number

[0236] 1st m 0 and the second m 1Based on the circular shift of

[0237]

number

[0238] and

[0239]

number

[0240] By simply determining the first m 0 and the second m 1 This alleviates the need to implement large tables in the client device to determine the cell ID from a circular shift of

[0241] According to one embodiment, m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of cyclic shifts (m 0 ,m 1 ) and (m 0 ',m 1 That is, there are no two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, and at the same time, the determined cyclic shift pair may satisfy m 0 <m 1 (or m 0 >m 1 is equivalent to always satisfying . This ensures advantageous robustness against large frequency offsets.

[0242] According to one implementation of this embodiment, the PSS

[0243]

number

[0244] The series indicators conveyed by SSS

[0245]

number

[0246] The series index conveyed by the first m 0 and the second m 1 The encoding of the first cyclic shift m 0 and the second cyclic shift m 1 is determined as follows:

[0247]

number

[0248] where g>1 is the first cyclic shift m 0 is the minimum step size between candidate values ​​of m 0 The second circular shift m 1 Since g>1, the maximum number of candidate values ​​of any two SSS sequences, for example, (m 0 , m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1. Also, the generated cyclic shift pair satisfies at most m 0 <m 1 (or m 0 >m 1 ) is always satisfied. If the SSS is transmitted twice every 10 ms, i.e., once in each half-frame, this means that the value m 0 and m 1Advantageously, it would be possible to indicate 5 ms timing using the SSS sequence (e.g. as is done in LTE) by simply replacing , , or this implementation would provide a solution that is future proof for future New Radio releases, e.g. if it is deemed useful to increase the number of assumptions in SSS later.

[0249] As a non-limiting example, assume that L=127 and

[0250]

number

[0251] It can be said that this implementation form may be implemented for the implementation of the New Radio synchronization signal. For example, g=2,

[0252]

number

[0253] And with L'=115, a total of 336×3=1008 cell IDs are transmitted.

[0254] A non-limiting example of this implementation is:

[0255]

number

[0256]

number

[0257] , for L=15, g=2 and L'=8, is presented in Figure 9. In Figure 9, PSS series indicators

[0258]

number

[0259] is on the y-axis, where m 0 =0 and m 0 = 2 both have the same PSS series index

[0260]

number

[0261] That is, m 0 =0 and m 0 = 2 both have the same PSS series index

[0262]

number

[0263] Accordingly, m 0 = 4 and m 0 =6 are both the same PSS series index

[0264]

number

[0265] It is related to the PSS series index.

[0266]

number

[0267] The first circular shift m of 0 and SSS series index

[0268]

number

[0269] 1st m 0 and the second m 19. The association of the cyclic shifts is not restricted to the order shown in FIG. 9, for example, any other order is possible.

[0270] Furthermore, cell ID N ID According to an embodiment, the first cyclic shift m 0 and the second cyclic shift m 1 This may be determined based on the first m 0 and the second m 1 From the circular shift value of PSS

[0271]

number

[0272] and SSS

[0273]

number

[0274] This is possible because there exists a simple inverse mapping to the sequence indices, which may be written, for example, as follows:

[0275]

number

[0276] 1st m 0 and the second m 1 Based on the circular shift of

[0277]

number

[0278] and SSS

[0279]

number

[0280] By simply determining the series indicators, the need to implement a large table in the client device to determine the cell ID from the cyclic shifts of the first m 0 and the second m 1 is alleviated.

[0281] According to one implementation form of the present embodiment, the indicators of the SSS series

[0282] [Number]

[0283] and the indicators of the PSS series

[0284] [Number]

[0285] are encoded into the cyclic shifts of the first m 0 and the second m 1 as follows. That is, the first cyclic shift m 0 and the second cyclic shift m 1 are determined as follows.

[0286] [Number]

[0287] Here, g is the minimum cyclic shift step size between candidate values of the first cyclic shift m 0 , and is an integer greater than 1, g > 1. L' is a positive integer less than or equal to the length L of the SSS series, L' ≤ L, which is also the maximum number of candidate values of the second cyclic shift m 0 for a given first cyclic shift m 1 . Since g > 1, for any two cyclic shift pairs of the SSS series, (m 0 , m 1 ) and (m 0',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 Satisfy at most one of +1.

[0288] As a non-limiting example, L=127 and

[0289]

number

[0290] It can be said that the implementation of the New Radio synchronization signal in this embodiment may be implemented. For example, g=2,

[0291]

number

[0292] And with L'=112, a total of 336×3=1008 cell IDs are transmitted.

[0293] A schematic and non-limiting description of this example in the present embodiment is given below:

[0294]

number

[0295]

number

[0296] , for L=15, g=2 and L'=8, as shown in Fig. 10. Since g=2, m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1This is shown in FIG. 10, where all second positions along the diagonal are left unused. That is, positions that can be selected (black dots) are separated diagonally by positions that cannot be selected (white dots). Thus, in the illustration of FIG. 10, m 0 '=m 0 +1 and m 1 '=m 1 +1 and +2 cannot be satisfied at the same time. PSS series indicators

[0297]

number

[0298] is on the y-axis, where m 0 =0 and m 0 =4 both have the same PSS series index

[0299]

number

[0300] That is, m 0 =0 and m 0 =4 both have the same PSS series index

[0301]

number

[0302] Accordingly, m 0 = 2 and m 0 =6 are both the same PSS series index

[0303]

number

[0304] It is related to the PSS series index.

[0305]

number

[0306] The first circular shift m of 0 Associations with and SSS index

[0307]

number

[0308] m 0 and m 1 The association of cell IDs N is not restricted to the order shown in FIG. 10. Any other order is also possible. ID According to an embodiment, the first cyclic shift m 0 and the second cyclic shift m 1 This may be determined based on the first m 0 and the second m 1 From the circular shift value of PSS

[0309]

number

[0310] and SSS

[0311]

number

[0312] This is possible because there exists a simple inverse mapping to the sequence index, which may be written, for example, as follows:

[0313]

number

[0314] 1st m 0 and the second m1 Based on the circular shift of

[0315]

number

[0316] and SSS

[0317]

number

[0318] By simply determining the series index, the first m 0 and the second m 1 This alleviates the need to implement large tables in the client device to determine the cell ID from a circular shift of

[0319] According to one implementation of this embodiment, the PSS

[0320]

number

[0321] The series indicators conveyed by SSS

[0322]

number

[0323] The series index conveyed by the first m 0 and the second m 1 The encoding of the first cyclic shift m 0 and the second cyclic shift m 1 is determined as follows:

[0324]

number

[0325] where g>1 is the second cyclic shift m 1 is the minimum step size between candidate values ​​of m 0 The second circular shift m 1 Since g>1, the maximum number of candidate values ​​of any two SSS sequences, for example, (m 0 , m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1. Also, the generated / selected cyclic shift pair satisfies m 0 <m 1 (or m 0 >m 1 ) is always satisfied. If the SSS is transmitted twice every 10 ms, i.e., once in each half-frame, this means that the value m 0 and m 1 Advantageously, it would be possible to indicate 5 ms timing using the SSS sequence (as is done in LTE, for example) by simply replacing , , or this implementation would provide a solution that is future proof for future New Radio releases, for example if it is deemed useful to increase the number of assumptions in SSS later.

[0326] As a non-limiting example, L=127 and

[0327]

number

[0328] It can be said that this implementation form may be implemented for the implementation of the New Radio synchronization signal. For example, g=2,

[0329]

number

[0330] And with L'=115, a total of 336×3=1008 cell IDs are transmitted.

[0331] A non-limiting example of this implementation is described below.

[0332]

number

[0333]

number

[0334] , for L=15, g=2 and L'=8, is presented in FIG. 11. In FIG. PSS series indicators

[0335]

number

[0336] is on the y-axis, where m 0 =0 and m 0 =4 both have the same PSS series index

[0337]

number

[0338] That is, m 0 =0 and m 0 =4 both have the same PSS series index

[0339]

number

[0340] Accordingly, m 0 = 2 and m 0 =6 are both the same PSS series index

[0341]

Number

[0342] is associated with. Note that the PSS series index

[0343]

Number

[0344] the first cyclic shift m 0 the association with respect to, and the SSS series index

[0345]

Number

[0346] the first m 0 and the second m 1 the association with respect to the cyclic shift is not restricted in the order of FIG. 11, and for example, any other order is also achievable.

[0347] Furthermore, the cell ID N ID may be determined according to the embodiment based on the first cyclic shift m 0 and the second cyclic shift m 1 This is from the cyclic shift values of the first m 0 and the second m 1 PSS

[0348]

Number

[0349] and SSS

[0350]

Number

[0351] This is possible because there exists a simple inverse mapping to the sequence index, which may be written, for example, as follows:

[0352]

number

[0353] 1st m 0 and the second m 1 Based on the circular shift of

[0354]

number

[0355] and SSS

[0356]

number

[0357] By simply determining the series index, the first m 0 and the second m 1 This alleviates the need to implement large tables in the client device to determine the cell ID from a circular shift of

[0358] According to one embodiment, two cyclic shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') are different PSS series indicators

[0359]

number

[0360] , the two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m0 '=m 0 +1 and m 1 '=m 1 +1. This ensures robustness against large frequency offsets.

[0361] The circular shift pair according to the present embodiment may be obtained, for example, by encoding the sequence index conveyed in the PSS.

[0362]

number

[0363] For example, the first cyclic shift m 0 , i.e., the first cyclic shift m associated with the same primary synchronization signal PSS sequence index 0 Any two candidate values ​​of are separated from each other by more than one (1) cyclic shift step and have different PSS sequence indices.

[0364]

number

[0365] is the first circular shift m 0 It is necessary that the first circular shift m 0 is kept to a minimum so that low-cost / complexity scrambling FWHT based SSS detection is available within the client device 500.

[0366] The series indicators conveyed by SSS, i.e.

[0367]

number

[0368] is two m-sequences m 0 and m 1may be encoded as both a circular shift of m 1 can span all or most of its valid values ​​{0, 1, 2, ..., L-1}. Such an SSS design may lead to one SSS sequence being obtainable by cyclically shifting the other SSS sequence by one cycle shift step. However, according to an embodiment, such an SSS sequence pair may be obtained by using different PSS sequence indices.

[0369]

number

[0370] and will not be co-detected after successful detection of the PSS in the client device 500.

[0371] In addition, the PSS series index

[0372]

number

[0373] The first circular shift m 0 The index of the SSS sequence is encoded as

[0374]

number

[0375] The first circular shift m 0 and the second cyclic shift m 1 The encoding of m as m can be done in any way. 0 and m 1 may be exchanged in the following formula: 0 Given a value of , the second circular shift m 1 The number of candidate values ​​of is determined by the first circular shift m 0 The various values ​​of may be the same or different.

[0376] According to one implementation of this embodiment, the sequence index

[0377]

number

[0378] and

[0379]

number

[0380] , the first m 0 and the second m 1 may be obtained as follows: 0 and the second m 1 The cyclic shift of may be determined as follows:

[0381]

number

[0382] This is a restriction / limitation of the encoding scheme in equations (10) and (11) above, since g is now restricted to the value 1, g=1. According to the implementation, the cyclic shift pair (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 Two SSS sequences that satisfy both ,m + 1 can coexist if they are associated with different PSS indices according to equations (18) and (19). This means that the more efficient value of the cyclic shift pair (m 0 ,m 1 ) may be chosen, advantageously allowing for potentially more cell IDs to be encoded and possibly other information to be added to the SSS sequence without increasing the SSS sequence length.

[0383] As a non-limiting example, for L = 127 and

[0384] [Number]

[0385] it can be said that this implementation form may be used for the implementation of the New Radio synchronization signal of. For example,

[0386] [Number]

[0387] and L' = 112, a total of 336 × 3 = 1008 cell IDs are transmitted.

[0388] The description of this example

[0389] [Number]

[0390] [Number]

[0391] for L = 15 and L' = 8 are given in FIG. 12. In FIG. 12, PSS series index

[0392] [Number]

[0393] is on the y-axis, where m 0 = 0 and m 0 = 2 both have the same PSS series index

[0394] [Number]

[0395] That is, m 0 =0 and m 0 = 2 both have the same PSS series index

[0396]

number

[0397] Accordingly, m 0 = 1 and m 0 =3, both have the same PSS series index

[0398]

number

[0399] It is related to the PSS series index.

[0400]

number

[0401] The first circular shift m of 0 and SSS series index

[0402]

number

[0403] 1st m 0 and the second m 1 The association of the cyclic shifts is not constrained to the order shown in Figure 12.

[0404]

number

[0405] Any two cyclic shift pairs of SSS sequences associated therewith, for example, (m 0 , m 1 ) and (m 0 ', m 1 ') can have any other order as long as at most one of m 0 ' = m 0 + 1 and m 1 ' = m 1 + 1 is satisfied.

[0406] Furthermore, cell ID N ID may, according to an embodiment, be determined based on a first cyclic shift m 0 and a second cyclic shift m 1 . This is possible because there exists a simple inverse mapping from the cyclic shift values of the first m 0 and the second m 1 to the PSS

[0407]

Number

[0408] and SSS

[0409]

Number

[0410] series indices, which may be described, for example, as follows.

[0411]

Number

[0412] This is a limited / restricted inverse mapping in the above equations (12) and (13) for the value 1 of g, where g = 1. Thereby, the first m 0 and the second m 1 ​This alleviates the need to implement a large table in the client device 500 to determine the cell ID from the cyclic shift value of .

[0413] According to one embodiment, two cyclic shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') are different PSS series indicators

[0414]

number

[0415] , the two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, the generated cyclic shift pair is m 0 <m 1 (or m 0 >m 1 ) is always satisfied.

[0416] According to one implementation of this embodiment, the sequence index

[0417]

number

[0418] and

[0419]

number

[0420] , the first m 0 and the second m 1 may be obtained as follows:0 and the second m 1 The cyclic shift of may be determined as follows:

[0421]

number

[0422] This is a restriction / limitation of the encoding scheme in equations (14) and (15) above, since g is now restricted to the value 1, g=1. According to the implementation, the cyclic shift pair (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, are associated with different PSS indices according to equations (22) and (23), and the generated cyclic shift pair is always m 0 <m 1 (or m 0 >m 1 Coexistence is possible when the following two conditions are satisfied: m 0 and m 1 By swapping the values ​​of , it is possible to indicate 5ms timing using the SSS sequence, or to constitute a future-proof solution for future New Radio releases, should it be deemed useful to increase the number of assumptions in SSS at a later date.

[0423] As a non-limiting example, L=127 and

[0424]

number

[0425] It can be said that this implementation form may be used for the implementation of the New Radio synchronization signal. For example,

[0426]

number

[0427] and L′=112, conveying a total of 336×3=1008 cell IDs. A non-limiting illustration of one such implementation is:

[0428]

number

[0429]

number

[0430] , for L=15 and L'=8 are presented in Fig. 13. In Fig. 13, the PSS sequence index

[0431]

number

[0432] is on the y-axis, where m 0 =0 and m 0 =2 both have the same PSS series index

[0433]

number

[0434] That is, m 0 =0 and m 0 =2 both have the same PSS series index

[0435]

number

[0436] Accordingly, m0 = 1 and m 0 =3, both have the same PSS series index

[0437]

number

[0438] It is related to the PSS series index.

[0439]

number

[0440] The first circular shift m of 0 and SSS series index

[0441]

number

[0442] 1st m 0 and the second m 1 The association of the cyclic shifts is not constrained by the order shown in Figure 13.

[0443]

number

[0444] Any two SSS sequence cyclic shift pairs associated with each other, e.g., (m 0 ,m 1 ) and (m 0 ',m 1 ') but m 0 '=m 0 +1 and m 1 '=m 1 +1, and the generated cyclic shift pair is m 0 < m 1 (or m 0 >m 1Any other ordering is feasible, provided that it always satisfies

[0445] Furthermore, cell ID N ID According to an embodiment, the first cyclic shift m 0 and the second cyclic shift m 1 This may be determined based on the first m 0 and the second m 1 From the circular shift value of PSS

[0446]

number

[0447] and SSS

[0448]

number

[0449] This is possible because there exists a simple inverse mapping to the sequence index, which may be written, for example, as follows:

[0450]

number

[0451] This is a restriction / limitation of the inverse mapping in equations (16) and (17) above, since g is now restricted to the value 1, so g=1. This allows the first m 0 and the second m 1 This alleviates the need to implement a large table in the client device 500 to determine the cell ID from the cyclic shift value of .

[0452] As mentioned above, at least one cell ID N ID The first cyclic shift m associated with 0 and the second cyclic shift m 1may be determined according to any number of embodiments described herein and therefore relate to each other in various ways.

[0453] According to some embodiments described herein, such as those described in Figs. 8, 10 and 12, the first m 0 and the second m 1 The cyclic shift of is the first cyclic shift m 0 and the second cyclic shift m 1 are equal, m 0 =m 1 That is, there are available positions diagonally through the origin of the coordinates.

[0454] According to some embodiments described herein, such as those described in Figs. 9, 11 and 13, the first m 0 and the second m 1 The cyclic shift of is the first cyclic shift m 0 and the second circular shift m 1 and are different from each other, and m 0 ≠m 1 and there are no available positions diagonally through the origin of the coordinates.

[0455] According to some embodiments described herein, the first m 0 and the second m 1 The cyclic shift of is the first cyclic shift m 0 is the second circular shift m 1 Larger than m 0 >m 1 That is, there are only usable positions diagonally up through the origin of the coordinates.

[0456] According to some embodiments described herein, such as those described in Figs. 9, 11 and 13, the first m 0 and the second m 1 The cyclic shift of is the first cyclic shift m 0 is the second circular shift m 1 Less than m 0 <m 1That is, there are only usable positions diagonally down through the origin of the coordinates.

[0457] According to some embodiments described herein, such as those described in Figures 8, 9, 10 and 11, the first m 0 and the second m 1 The cyclic shift of is expressed as two pairs of cyclic shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, i.e., there is always an unused position between available positions in the diagonal direction.

[0458] According to some embodiments described herein, the first m 0 and the second m 1 The cyclic shift of is expressed as two pairs of cyclic shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second circular shift m 1 Larger than m 0 >m 1 That is, there will always be unused positions between available positions in the diagonal direction, and there will only be available positions above the diagonal direction through the origin of the coordinates.

[0459] According to some embodiments described herein, such as those described in FIGS. 9 and 11, the first m 0 and the second m 1 The cyclic shift of is expressed as two pairs of cyclic shifts (m 0 ,m 1 ) and (m 0',m 1 ') is m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second circular shift m 1 Smaller, m 0 <m 1 That is, there will always be unused positions between available positions in the diagonal direction, and there will only be available positions diagonally down through the origin of the coordinates.

[0460] According to some embodiments described herein, such as those described in FIGS. 12 and 13, the first m 0 and the second m 1 The circular shift of m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are separate primary synchronization signal PSS sequence coordinates

[0461]

number

[0462] It may be determined to be associated with

[0463] According to some embodiments described herein, the first m 0 and the second m 1 The circular shift of m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are separate primary synchronization signal PSS sequence indexes

[0464]

number

[0465] and the first cyclic shift m 0 is the second circular shift m 1 Larger than m 0 >m 1 That is, there are only available positions diagonally upward through the origin of the coordinate system.

[0466] According to some embodiments described herein, such as those illustrated in FIG. 0 and the second m 1 The circular shift of m 0 '=m 0 +1 and m 1 '=m 1 Two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are separate primary synchronization signal (PSS) sequence indexes

[0467]

number

[0468] and the first cyclic shift m 0 is the second circular shift m 1 Smaller, m 0 <m 1 That is, there are only available positions diagonally down through the origin of the coordinate system.

[0469] Finally, it is to be understood that the invention is not limited to the embodiments described above, but also relates to and includes all embodiments falling within the scope of the appended independent claims. [Explanation of symbols]

[0470] 100 Processing equipment 102 processors 104 Memory 106 Means of communication 200 ways 300 network nodes 302 Transmitter / receiver 304 Memory 306 Means of communication 308 Antenna 400 ways 500 client devices 502 Transmitter / receiver 504 Memory 506 Means of communication 508 Antenna 600 ways 700 Wireless communication system

Claims

1. A processing device, the processing device comprising: PSS series index [0010] generating a primary synchronization signal (PSS) sequence that conveys SSS series indicators [0025] generating a secondary synchronization signal (SSS) sequence carrying a first binary sequence and a second binary sequence, the first binary sequence and the second binary sequence having the same length; [0023] The PSS series index [0030] is the first cyclic shift m of the first binary sequence. 0 and the index of the SSS sequence is [0045] is the first cyclic shift m of the first binary sequence. 0 and a second cyclic shift m of the second binary sequence. 1 is encoded into The processing device according to claim 1,

2. The indicator [0050] The indicator [006] The first cyclic shift m 0 and the second cyclic shift m 1 but, [0070] where g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the SSS sequence, [0080] [0090] is the floor function, mod is the modulus operation, 2. The processing device according to claim 1.

3. The indicator [0089] The indicator ##EQU00011## The first cyclic shift m 0 and the second cyclic shift m 1 but, ##EQU00012## where g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the SSS sequence, ##EQU00013## ##EQU00014## is the floor function, mod is the remainder operation, 2. The processing device according to claim 1.

4. The processing device includes: The first cyclic shift m 0 the first binary sequence circularly shifted by m 1 and a second binary sequence circularly shifted by The first binary sequence and the second binary sequence have the same length L as the SSS sequence.

4. The processing device according to claim 1 .

5. The first binary sequence and the second binary sequence are one in a group, and the group is m-sequence, and m-sequences such that the generated secondary synchronization signal (SSS) sequence belongs to a set of Gold sequences Consists of:

5. A processing device according to any one of claims 1 to 4.

6. one of the first binary sequence and the second binary sequence used to generate the SSS sequence is the same binary sequence used to generate the PSS sequence.

6. The processing device according to claim 1 .

7. The generating polynomial of the first binary sequence is g 0 (x)=x 7 +x 4 +1, and the generating polynomial of the second binary sequence satisfies g 1 (x)=x 7 +x+1 is satisfied.

7. A processing device according to any one of claims 1 to 6.

8. The SSS sequence is ##EQU00015## It is expressed as d(k) which satisfies where k=0, 1, 2, ..., L-1, and L is the length of the SSS sequence; the first binary sequence is denoted as s 0 , the second binary sequence is denoted as s 1 , the first cyclic shift m 0 is a cyclic shift of s 0 , and the second cyclic shift m 1 is a cyclic shift of s 1 ; A processing device according to any one of claims 1 to 7.

9. the length L of the SSS sequence is 127 and L' is 112; 9. A processing device according to any one of claims 1 to 8.

10. 【Fig. 16】 is 3, ##EQU00017## and [0018] is 336, [0019] 10. The processing device according to any one of claims 1 to 9.

11. Cell Identification (ID)N ID , the indicator [0020] and the indicator ##EQU00021## but, [0022] Fulfilling A processing device according to any one of claims 1 to 10.

12. A network node, A processing device according to any one of claims 1 to 10; a transmitter configured to transmit a PSS based on the PSS sequence and an SSS based on the SSS sequence; A network node, characterized by including:

13. 1. A method for wireless communication, comprising: PSS series index [0023] obtaining a primary synchronization signal (PSS) carrying a SSS series indicators ##EQU00024## and obtaining a secondary synchronization signal (SSS) carrying a first binary sequence and a second binary sequence, the SSS sequence of the SSS being based on: Here, the index of the PSS sequence [0025] is the first cyclic shift m of the first binary sequence. 0 and the index of the SSS sequence is encoded into [0026] is the first cyclic shift m of the first binary sequence. 0 and a second cyclic shift m of the second binary sequence. 1 and obtaining a secondary synchronization signal (SSS) encoded by the first binary sequence and the second binary sequence having the same length; The indicator [0027] and the indicator [0028] From cell identification (ID) N ID and obtaining a cell identity (ID) N ID teeth, [0029] Cell identity (ID) N ID and A method comprising:

14. The indicator [0030] The indicator [0031] The first cyclic shift m 0 and the second cyclic shift m 1 but, [0032] where g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the SSS sequence, [Equation 33] [0034] is the floor function, mod is the remainder operation, The method of claim 13.

15. The indicator [Equation 35] The indicator [0036] The first cyclic shift m 0 and the second cyclic shift m 1 but, [Equation 37] where g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the SSS sequence, [Equation 38] [0039] is the floor function, mod is the remainder operation, The method of claim 13.

16. The SSS sequence is a sequence obtained by multiplying the first cyclic shift m 0 the first binary sequence circularly shifted by m 1 and a second binary sequence cyclically shifted by 16. The method according to any one of claims 13 to 15.

17. The first binary sequence and the second binary sequence are one in a group, and the group is m-sequence, and m-sequences such that the generated secondary synchronization signal (SSS) sequence belongs to a set of Gold sequences Consists of:

17. The method according to any one of claims 13 to 16.

18. one of the first binary sequence and the second binary sequence used to generate the SSS sequence is the same binary sequence used to generate the PSS sequence.

18. The method according to any one of claims 13 to 17.

19. The generating polynomial of the first binary sequence is g 0 (x)=x 7 +x 4 +1, and the generating polynomial of the second binary sequence satisfies g 1 (x)=x 7 +x+1 is satisfied.

19. The method according to any one of claims 13 to 18.

20. The first cyclic shift m 0 and the second cyclic shift m 1 generating an SSS sequence based on the candidate values ​​of 20. The method according to any one of claims 13 to 19.

21. After the PSS is successfully detected, By detecting the PSS [0040] and detecting the SSS. [0041] and obtaining the 21. The method according to any one of claims 13 to 20.

22. said detecting said SSS sequence includes a descrambling and fast Walsh-Hadamard transform (FWHT) operation on said SSS. The method of claim 21.

23. said detecting the SSS sequence includes detecting the SSS by cross-correlation with a generated SSS sequence. The method of claim 21.

24. The first cyclic shift m 0 and the second cyclic shift m 1 and determining The first cyclic shift m 0 and the second cyclic shift m 1 According to the above, the indicator [0042] and the indicator [0043] and determining Further comprising:

24. The method according to any one of claims 13 to 23.

25. The received SSS and the first cyclic shift m 0 and descrambling the first cyclic shift m 0 and The second cyclic shift m is calculated by using a fast Walsh-Hadamard transform (FWHT) operation. 1 and Further comprising:

25. The method according to any one of claims 13 to 24.

26. The SSS sequence is [0044] It is expressed as d(k) which satisfies where k=0, 1, 2, ..., L-1, and L is the length of the SSS sequence; the first binary sequence is denoted as s 0 , the second binary sequence is denoted as s 1 , the first cyclic shift m 0 is a cyclic shift of s 0 , and the second cyclic shift m 1 is a cyclic shift of s 1 ; 26. The method according to any one of claims 13 to 25.

27. the length L of the SSS sequence is 127 and L' is 112; 27. The method according to any one of claims 13 to 26.

28. 【Fig. 45】 is 3, [0046] and [0047] is 336, [0048] That is, 28. The method according to any one of claims 13 to 27.

29. Processing device, characterized in that said processing device is configured to execute the method according to any one of claims 13 to 28.

30. A client device, A processing device configured to carry out the method according to any one of claims 13 to 28; a transceiver configured to receive a primary synchronization signal (PSS) and a secondary synchronization signal (SSS); A client device comprising:

31. A computer readable medium containing a computer program which, when executed by a computer, causes the computer to perform the method of any one of claims 13 to 28.

32. A computer program causing a computer to carry out a method according to any one of claims 13 to 28.

33. A communication system comprising a network node according to claim 12 and a client device according to claim 30.

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