Wafer Level Package for Devices

Abstract

According to one exemplary embodiment of the present invention, a wafer-level package (100) for a device is provided, the package (100) including a first substrate (11) and a second substrate (22), an encapsulation structure including a seal ring (40) and a bonding layer (30) between the first substrate (11) and the second substrate (22), and lateral electrical connection lines (50) on the surface of the first substrate (11), the lateral electrical connection lines (50) extending through the seal ring (40) to form electrical connections between a device inside the package (100) and an electrical circuit outside the package (100).

Description

[Technical field]

[0001] The present invention relates to wafer level packages for devices, and more particularly to wafer level packages for Micro-Electro-Mechanical Systems (MEMS). [Background technology]

[0002] Microelectromechanical systems (MEMS) are miniaturized mechanical and electromechanical elements, such as devices and structures, made using microfabrication techniques. MEMS consist of components ranging from 1 to 100 μm in size, with MEMS devices roughly ranging in size from 20 μm to 1 mm.

[0003] MEMS are prone to electrical failure and mechanical damage due to their small size, composition, and the very demanding manufacturing method. Therefore, MEMS devices need to be packaged, for example by sealing the device between two wafers connected by a seal ring. Non-uniform bonding temperature and bonding force used to bond the two wafers together can lead to poor quality MEMS. Melting near the eutectic temperature and non-uniform bonding force can lead to excessive squeezing of the bonding material out of the seal ring area of ​​the MEMS. This can lead to void formation and gap size variation between the wafers. Furthermore, commonly used bonding techniques only offer a small process window, which can lead to bond misalignment. Furthermore, electrical connections are typically formed by difficult and complex structures with pads inside and outside the packaging.

[0004] Therefore, there is a need for improved structures and methods of manufacturing encapsulation structures for wafer packaging. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made to solve the problems in the conventional techniques described above. [Means for solving the problem]

[0006] The invention is defined by the features of the independent claims. Some particular embodiments are defined in the dependent claims.

[0007] According to a first aspect of the present invention, there is provided a wafer level package for a device, the package including a first substrate and a second substrate, an encapsulation structure including a seal ring and a bonding layer between the first substrate and the second substrate, and lateral electrical connection lines on a surface of the first substrate, the lateral electrical connection lines extending through the seal ring to form an electrical connection between a device inside the package and an electrical circuit outside the package. The package includes a plurality of microrings within the seal ring, at least a portion of the material of the bonding layer being disposed between the microrings.

[0008] According to one embodiment of the present invention, the bonding layer is on a surface of the second substrate.

[0009] According to one embodiment of the present invention, the micro-rings are formed by protrusions on the surface of the seal ring.

[0010] According to one embodiment of the present invention, the seal ring comprises a dielectric material.

[0011] According to one embodiment of the present invention, the package includes a microring pattern on a first substrate.

[0012] According to a second aspect of the present invention, there is provided a method of forming a wafer level package for a device, the method comprising the steps of: creating lateral electrical connection lines on a surface of a first substrate, creating a seal ring on a surface of the first substrate and over a portion of the lateral electrical connection lines, creating a first layer of bonding material on a surface of the seal ring, creating a second layer of bonding material on a surface of a second substrate, and bonding the first layer of bonding material to the second layer of bonding material to form a bonding layer, the lateral electrical connection lines extending through the seal ring to form an electrical connection between a device inside the package and an electrical circuit outside the package. The method includes providing a plurality of microrings within the seal ring to confine at least a portion of the material of the bonding layer between the microrings when the material melts during the bonding process.

[0013] According to one embodiment of the present invention, the step of bonding the first bonding material layer to the second bonding material layer is performed by eutectic bonding, transient liquid phase bonding, or glass frit wafer bonding.

[0014] According to one embodiment of the present invention, the wafer level package is for a MEMS device.

[0015] The present invention has several advantages. The present invention provides lateral electrical connection lines that extend through the seal ring to form electrical connections between devices inside the package and electrical circuits outside the package. In addition, the microrings provide a controlled squash of the bonding layer (e.g., molten germanium-aluminum alloy) between the bonding substrates. In addition, the microrings provide a larger process window in bonding substrates, especially eutectic bonding of substrates. The microrings also provide a tight gap that is not affected by temperature and pressure non-uniformities (such as voids) due to the tight microring height. The present invention provides good and uniform bond strength for wafer level packages. The present invention also improves bond quality by reducing slip misalignment between bonding substrates through localized knurling to increase friction. [Brief description of the drawings]

[0016] [Figure 1] 1 illustrates a portion of a seal ring of a wafer level package in accordance with at least some embodiments of the present invention. [Diagram 2] 1 illustrates a portion of a seal ring of a wafer level package for a device in accordance with at least some embodiments of the present invention. [Diagram 3] 1 illustrates a portion of a seal ring of a wafer level package for a device in accordance with at least some embodiments of the present invention. [Figure 4] 1 illustrates a top view of a portion of a seal ring structure in accordance with at least some embodiments of the present invention. [Diagram 5] 1 illustrates a wafer level package for a device in accordance with at least some embodiments of the present invention. [Figure 6A] ~ [Figure 6B] 1 illustrates a method of forming a wafer level package for a device in accordance with at least some embodiments of the present invention. [Figure 7A] ~ [Figure 7C]1 illustrates a cross-sectional view of a microring design in accordance with at least some embodiments of the present invention. [Figure 8] 1 illustrates a top view of a microring structure in accordance with at least some embodiments of the present invention. [Figure 9A] ~ [Figure 9D] 1 illustrates a method for manufacturing a first structure in accordance with at least some embodiments of the present invention. [Figure 10A] ~ [Figure 10B] 4 illustrates a method for manufacturing a second structure in accordance with at least some embodiments of the present invention. [Figure 11A] ~ [Figure 11C] 1 illustrates a method for manufacturing a first structure in accordance with at least some embodiments of the present invention. [Figure 12A] ~ [Figure 12E] 4 illustrates a method for manufacturing a second structure in accordance with at least some embodiments of the present invention. [Figure 13A] ~ [Figure 13C] 1 illustrates a method for manufacturing a first structure in accordance with at least some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In this context, the term "substrate" encompasses wafers, including, for example, MEMS device wafers and cap wafers.

[0018] It is an objective of at least some embodiments of the present invention to provide high quality wafer level packages (especially for Microelectromechanical Systems (MEMS) devices) whose sealing structures provide good electrical connections and tight gap control that are immune to temperature and pressure non-uniformities (such as voids).

[0019] FIG. 1 shows a part of a wafer level package 100 for devices according to some embodiments. The wafer level package 100 for devices includes a first substrate 11 and a second substrate 22, an encapsulation structure including a seal ring 40 and a bonding layer 30 between the first substrate 11 and the second substrate 22, and lateral electrical connection lines 50 and / or dummy lines 51 on the surface of the first substrate 11, where the lateral electrical connection lines 50 extend through the seal ring 40 to form an electrical connection between a device inside the package and an electrical circuit outside the package. In this way, the electrical connection is formed by a simple yet reliable structure. In one embodiment, the lateral electrical connection lines 50 and the dummy lines 51 have the same composition but different patterns and arrangements, as well as the purpose of the structure. The lateral electrical connection lines 50 are intended to provide electrical contact between the device inside the package and the external circuitry outside the package, while the dummy lines 51 are there to provide a uniform surface underneath the seal ring 40 around the lateral electrical connection lines 50 to make it easier to control the thickness of the seal ring 40.

[0020] 1-3 show that the wafer level package 100 for a device includes a bonding layer 30 on a surface of the second substrate 22. The bonding layer 30 enables the first substrate 11 and the second substrate 12 of the wafer level package 100 to be joined by bonding.

[0021] According to some embodiments, the bonding layer 30 includes a eutectic alloy. A eutectic alloy may include two or more metals. Suitable eutectic alloys include, for example, a germanium-aluminum alloy, a gold-tin alloy, a gold-germanium alloy, a gold-silicon alloy, a gold-indium alloy, or a copper-tin alloy.

[0022] According to some other embodiments, bonding layer 30 is an intermetallic bonding layer. The intermetallic bonding layer may include a metal alloy, such as a copper-tin alloy, a gold-indium alloy, or a silver-tin alloy.

[0023] Alternatively, bonding layer 30 may be a glass frit wafer bonding layer. Glass frit bonding has a high tolerance to surface roughness and can capture high topography of the substrate.

[0024] 1-3 show that the package 100 includes multiple (e.g., 2, 3, or more) microrings 33 within the seal ring 40. The microrings confine the bonding layer 30 material (e.g., molten metal) between the microrings by pinch-off effect and control the horizontal squashing of the bonding layer 30 material outside the microrings. The microrings also provide tight gap control by providing tight microring height. The microrings provide a gap that is not affected by temperature and pressure non-uniformities (e.g., voids) by providing uniform flow of bonding material into the gap. The bonding layer may extend over the entire surface of the second substructure (not shown). Additionally, the microrings increase the process window of the bonding. Additionally, the microrings reduce slip misalignment between the first and second substrates by providing localized knurling to increase friction.

[0025] According to some embodiments, the microring 33 is formed by a protrusion on the surface of the seal ring 40. The microring 33 may be formed by a continuous ring spanning the surface of the seal ring 40. Thus, the microring 33 may span the periphery of the cavity.

[0026] 4 shows a top view of a seal ring structure according to some embodiments. The seal ring may have a cross-sectional width of, for example, 40-300 μm (such as 60-100 μm). The lateral electrical connection lines 50 extend through the seal ring 40 to the outside of the wafer level package. The lateral electrical connection lines 50 may have a width of, for example, 5-30 μm (such as 10-20 μm). The lateral electrical connection lines 50 allow electrical connection between devices inside the package and electrical circuitry outside the package.

[0027] 4 further shows that dummy lines 51 are provided within the seal ring. The dummy lines make the surface under the seal ring 40 uniform. The width of the dummy lines 50 may be, for example, 1 to 20 μm (e.g., 2 to 5 μm). The interval between the dummy lines 51 and the interval between the lateral electrical connection lines 50 and the dummy lines 51 may be, for example, 2 to 20 μm (e.g., 3 to 10 μm). The thickness of the lateral electrical connection lines 50 and the dummy lines 51 may be, for example, 0.2 to 5 μm (e.g., 0.5 to 1 μm).

[0028] 3 shows that the package 100 includes a microgroove 34 in the second substrate 22. The microgroove allows for alignment of the microring 33 with respect to the second substrate 22.

[0029] FIG. 5 shows that the package 100 includes a cavity 60 in the second substrate 22 .

[0030] 5 further shows that package 100 includes a getter 61 on the surface of cavity 60. The getter may be used to create and maintain a vacuum. The getter may be a thin film getter. The getter absorbs some or all of the gases (e.g., water vapor, oxygen, carbon monoxide, carbon dioxide, nitrogen, hydrogen, and / or other gases) that may be released into the cavity.

[0031] In one embodiment, the first substrate 11 and the second substrate 22 comprise silicon or ceramic. Silicon is a very reliable substrate material since it is very unlikely to fatigue and can operate for long periods without breaking. In single crystal form, silicon has little hysteresis and therefore little energy dissipation. Suitable ceramic substrates are, for example, silicon nitride, aluminum nitride, titanium nitride, or silicon carbide. Aluminum nitride in the wurtzite structure exhibits pyroelectric and piezoelectric properties, which allows the fabrication of sensors with sensitivity to, for example, normal and shear forces. Titanium nitride has high electrical conductivity and a large elastic modulus.

[0032] According to one embodiment, the lateral electrical connection lines 50 and the dummy lines 51 include metals such as molybdenum, aluminum, or copper that provide good and reliable electrical connections in the lateral electrical connection lines between devices inside the package and electrical circuitry outside the package.

[0033] According to one embodiment, the seal ring 40 comprises a dielectric material, a ceramic material, or a metal covered with an insulating layer. The seal ring may be, for example, silicon dioxide (SiO 2 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), or aluminum oxide (Al 2 O 3 The bonding layer 30 may include copper or nickel coated with a SiO 2 . The silicon dioxide provides a good wetting surface for the bonding layer 30 and good electrical insulation.

[0034] The microring 33 may include or be formed of the same material as the seal ring 40, which may be, for example, silicon dioxide (SiO 2 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 3N 4 ), silicon carbide (SiC), or aluminum oxide (Al 2 O 3 ) coated copper or nickel.

[0035] According to one embodiment, the getter comprises a metal that is susceptible to absorbing gases. For example, the getter may comprise at least one of titanium, aluminum, zirconium, boron, cobalt, calcium, strontium, or thorium.

[0036] According to one embodiment, the package 100 includes a microring pattern 90 on the first substrate 11. The microring pattern 90 is made of, for example, silicon (Si), silicon dioxide (SiO 2 ), metal, or semiconductor material. The microring pattern 90 confines the material of the seal ring 40 (e.g., molten metal) between the microrings by a pinch-off effect. The microring pattern also provides tight gap control by providing a tight height for the microring pattern.

[0037] Alternatively, the dummy lines 51 may form the microring pattern 90 .

[0038] 6A and 6B show that one method of forming a wafer level package 100 for a device includes the steps of forming a lateral electrical connection line 50 (not shown in FIGS. 6A and 6B) on a surface of a first substrate 11, forming a seal ring 40 on a portion of the lateral electrical connection line 50 on the surface of the first substrate 11, forming a first bonding material layer 31 on the surface of the seal ring 40, forming a second bonding material layer 32 on a surface of a second substrate 22, and bonding the first bonding material layer 31 to the second bonding material layer 32 to form a bonding layer 30. The lateral electrical connection line 50 extends through the seal ring 40 to form an electrical connection between a device inside the package 100 and an electrical circuit outside the package 100.

[0039] Depositing each layer of the wafer level package 100 (e.g., the first bonding material layer 31 and the second bonding material layer 32) may be performed by a deposition process. The deposition process may include, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0040] The first bonding material layer 31 and the second bonding material layer 32 may each have a thickness of, for example, 0.3 to 0.8 μm (0.4 to 0.7 μm, etc.) The microring 33 may also have a thickness of, for example, 0.3 to 0.8 μm (0.4 to 0.7 μm, etc.).

[0041] According to some embodiments, bonding of the first bonding material layer 31 to the second bonding material layer 32 is achieved by eutectic bonding. First, the temperature may be increased to a value below the eutectic temperature of the eutectic alloy. Then, the temperature may be held constant for a short period of time to ensure uniform heating of both the first and second substrates. After that, the temperature may be increased to a temperature above the eutectic point. Finally, the structure may be cooled to a temperature below the eutectic temperature.

[0042] Eutectic bonding does not require the use of strong contact forces during bonding. Eutectic bonding is less sensitive to surface flatness irregularities, scratches, and particles than direct wafer bonding methods because the eutectic bonding process occurs entirely in the liquid phase.

[0043] According to some embodiments, eutectic bonding is performed at a temperature 10-20°C above the eutectic temperature of the eutectic alloy. Aluminum-germanium bonding may be performed at, for example, 390°C. Gold-stainless steel bonding may be performed at, for example, 290°C. Gold-silicon bonding may be performed at, for example, 375°C. Gold-germanium bonding may be performed at, for example, 435°C.

[0044] Alternatively, bonding of the first bonding material layer 31 to the second bonding material layer 32 may be achieved by transient liquid phase bonding. Transient liquid phase bonding results in an intermetallic bonding layer. This advanced solder bonding process allows high quality hermetic seals to be formed at lower temperatures than other bonding techniques. Transient liquid phase bonding uses one thin (typically 1-10 μm thick) metal layer that diffuses into the bonding partner during a thermal process to form an intermetallic layer whose remelting temperature is higher than the bonding temperature. The intermetallic bonding layer can be formed at a bonding temperature lower than the bonding temperature of most common eutectic alloys. Thus, the intermetallic bonding layer may be used in applications where low manufacturing temperatures are required.

[0045] Transient liquid phase bonding may be performed similarly to eutectic bonding: first, the temperature may be increased to a value below the bonding temperature. Then, the temperature may be held constant for a short period of time to ensure uniform heating of both the first and second substrates. After that, the temperature may be increased to a temperature above the bonding temperature. Finally, the structure may be cooled to a temperature below the bonding temperature.

[0046] According to some embodiments, the transient liquid phase bonding may be carried out at a temperature of 150-300°C.

[0047] Alternatively, bonding of the first bonding material layer 31 to the second bonding material layer 32 may be achieved by glass frit wafer bonding, which uses a low melting point glass as a bonding intermediate layer. Bonding is achieved by heating the substrates with an applied contact force.

[0048] Bonding may be performed in a bonding chamber in which a controlled vacuum pressure can be created. This vacuum pressure can be, for example, 0.8×10 -5The bonding chamber may be pumped with one or more inert gases, such as argon and nitrogen.

[0049] 9A shows that a seal ring 40 may be deposited on the first substrate 11. The thickness of the seal ring 40 may be, for example, 0.3 to 1 μm (such as 0.4 to 0.6 μm).

[0050] According to some embodiments, the method may include providing a plurality of microrings 33 within the seal ring 40. Providing the microrings within the seal ring may be performed by patterning the seal ring as shown in FIG. 9B. The microrings confine at least a portion of the material of the bonding layer 30 between the microrings 33.

[0051] 7A-7C show cross-sectional views of designs of microrings 33 according to some embodiments. The microrings are provided within a seal ring 40. A first bonding material layer 31 is provided on the seal ring 40 and the microrings 33. The height of the microrings may be, for example, 0.5 μm. The width of the gap between the microrings and the shape of the microrings may be selected according to, for example, the preferred characteristics of the encapsulation structure or process parameters.

[0052] 8 shows a top view of the structure of a microring 33 according to some embodiments. A plurality of (e.g., two) microrings 33 may be provided in the seal ring 40. The width of the microring may be, for example, 0.5 to 15 μm.

[0053] According to some embodiments, the method may include a step of depositing an oxide layer. The oxide layer may be deposited, for example, on the first substrate 11, the second substrate 22, the first bonding material layer 31, the second bonding material layer 32, the seal ring 40, and the lateral electrical connection lines 50. The oxide layer may be grown by thermal oxidation, where a layer is exposed to oxygen and / or steam, and a thin surface layer grows on the layer. The oxide layer of the first substrate 11 and the second substrate 22 (typically of silicon) may be formed of silicon dioxide (SiO 2 The oxide layer protects the layers of the wafer level package from oxidation.

[0054] 9B, 9D, and 10B show that, according to some embodiments, the method includes patterning the seal ring 40, the oxide layer, the first material layer 31, and / or the second material layer 32. The patterning may be performed to remove some areas from each layer of the wafer level package. The patterning may be performed by lithography, e-beam lithography, ion beam lithography, ion track technology, x-ray lithography, or diamond patterning.

[0055] According to some embodiments, the method includes removing the oxide layer before bonding the first bonding material layer 31 to the second bonding material layer 32. Removal of the oxide layer may be performed, for example, by plasma cleaning, wet chemical etching, or dry chemical etching.

[0056] 12D shows that, according to some embodiments, the method includes forming a cavity 60 in the second substrate 22. The cavity may be formed, for example, by silicon wet etching or silicon dry etching.

[0057] According to some embodiments, the method includes forming a getter 61 over the cavity 60 in the second substrate 22. The getter 61 may be formed by a getter deposition process. The deposition of the getter may be performed by using, for example, sputtering, resistance evaporation, electron beam evaporation, or other suitable deposition techniques.

[0058] Next, a method for forming an encapsulation structure for wafer packaging for devices will be discussed in more detail with the aid of exemplary embodiments.

[0059] 9A-9D show a method for manufacturing a first structure 10 according to some embodiments. First, the surface of the first substrate 11 may be provided with lateral electrical connection lines 50 and dummy lines 51 (not shown). Then, as shown in FIG. 9A, the seal ring 40 may be deposited on the lateral electrical connection lines 50 and the dummy lines 51. The seal ring 40 may be patterned as shown in FIG. 9B. Then, a first bonding material layer 31 may be deposited on the seal ring as shown in FIG. 9C. Finally, the seal ring layer and the first bonding material layer may be patterned as shown in FIG. 9D.

[0060] 10A and 10B illustrate a method for manufacturing a second structure 20, according to some embodiments. First, as shown in FIG 10A, a second bonding material layer 32 is deposited on a second substrate 22. Then, as shown in FIG 10B, the second bonding material layer is patterned.

[0061] 11A-11B show a method for manufacturing a first structure 10 according to some embodiments of the present invention. First, as shown in FIG. 11A, an oxide layer 80 (e.g., silicon oxide (SiO 2 Next, the lateral electrical connection lines 50 and the dummy lines 51 are provided on the oxide layer (FIG. 11B). Thereafter, in order to prevent the lateral electrical connection lines 50 and the dummy lines 51 from being oxidized, a metal or metal oxide layer 80 (e.g., aluminum or aluminum oxide (Al 2 O3 11C, a metal or metal oxide layer 80 (e.g., aluminum or aluminum oxide (Al) layer) may be deposited on the first bonding material layer 31. A metal or metal oxide layer 80 (e.g., aluminum or aluminum oxide (Al) layer) may be deposited on the first bonding material layer 31. 2 O 3 ) layer) may be deposited.

[0062] 12A-12E show a method for manufacturing the second structure 20 according to some embodiments. First, an alignment mark 70 may be generated on the back side of the second substrate 22 and chip numbering may be performed (FIG. 12A). Then, a second bonding material layer 32 may be provided on the second substrate 22, and the first bonding material layer may be patterned as shown in FIG. 12B. Then, an oxide layer 80 may be deposited on the first bonding material layer 31. The oxide layer 80 may be patterned (FIG. 12C). The oxide layer 80 may be removed, which may be done, for example, by plasma cleaning before bonding, wet chemical etching, or dry chemical etching. Furthermore, a cavity 60 may be formed in the second substrate 22, which may be done by silicon wet etching or silicon dry etching (FIG. 12D). Finally, optionally, a getter 61 may be deposited on the surface of the cavity 60, as shown in FIG. 12E.

[0063] 13A-13C show a method for manufacturing a first structure 10 according to some embodiments of the present invention. First, the surface of the first substrate 11 may be provided with lateral electrical connection lines 50 and, optionally, dummy lines 51 (not shown). Next, as shown in FIG. 13A, a microring pattern 90 is created on the first substrate 11. After that, a seal ring 40 is deposited on the microring pattern 90 and on the surface of the first substrate 11 and on a part of the lateral electrical connection lines 50 (FIG. 13B). The seal ring 40 reproduces the shape of the microring pattern 90. Finally, a first bonding material layer 31 may be deposited on the seal ring as shown in FIG. 13C.

[0064] Alternatively, the dummy lines 51 may form the microring pattern 90 .

[0065] According to some embodiments, the encapsulation structure may be directed to MEMS devices, although the encapsulation structure may also be used in other devices, such as automotive devices (e.g., lidar components and tire pressure sensors), RF components (e.g., switches, filters, inductors, and antennas), passive photonic devices (e.g., silicon waveguides and modulators, microspectrometer components, and plasmonic devices).

[0066] According to at least some embodiments, the mechanical bond is formed solely by bonding layer 30 such that microring 33 does not participate in the formation of the mechanical bond.

[0067] It is to be understood that the disclosed embodiments of the invention are not limited to the particular structures, process steps, or materials disclosed herein, but extend to equivalents thereof as would be recognized by one of ordinary skill in the art. It is also to be understood that the terminology used herein is used only for the purpose of describing particular embodiments, and is not intended to be limiting.

[0068] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0069] As used herein, a number of items, structural elements, compositional elements, and / or materials may be present in common lists for convenience. However, these lists should be construed as if each element of the list were individually identified as a separate and unique element. Thus, the individual elements of such lists should be construed as de facto equivalents of any other elements of the same list solely based on their presence in a common grouping, unless otherwise indicated. Furthermore, various embodiments and examples of the invention may be referenced herein in conjunction with alternatives with respect to their various components. It should be understood that such embodiments, examples, and alternatives should not be construed as de facto equivalents of each other, but should be considered as separate and independent manifestations of the invention.

[0070] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the above description, various specific details are set forth, such as examples of lengths, widths, shapes, etc., to provide a thorough understanding of embodiments of the present invention. However, one of ordinary skill in the art will recognize that the present invention may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the present invention.

[0071] While the above-described embodiments illustrate the principles of the present invention in one or more specific applications, it will be apparent to those skilled in the art that various changes in form, usage, and details of the embodiments may be made without the exercise of the inventive faculty and without departing from the principles and concepts of the present invention. Accordingly, the present invention is not intended to be limited except as by the claims that follow.

[0072] In this document, the verbs "to comprise" and "to include" are used as open limitations that do not exclude or require the presence of unrecited features. Features recited in the dependent claims may be freely combined with each other, unless expressly stated otherwise. Furthermore, it is to be understood that the use of "a" or "an", i.e. the singular, does not exclude a plurality throughout this document.

[0073] Reference List 10 First Structure 11 First substrate 20 Second Structure 22 Second board 30 Bonding Layer 31 First bonding material layer 32 Second bonding material layer 33 Micro Ring 34 Microgroove 40 Seal Ring 50 Lateral electrical connection line 51 Dummy Track 60 Cavity 61 Getta 70 Alignment Mark 80 Oxide layer 90 Micro Ring Pattern 100 Wafer Level Package

Claims

1. A wafer level package (100) for a device, comprising: A first substrate (11) and a second substrate (22); a sealing structure including a seal ring (40) and a bonding layer (30) between the first substrate (11) and the second substrate (22); a lateral electrical connection line (50) on a surface of the first substrate (11), the lateral electrical connection line (50) extending through the seal ring (40) to form an electrical connection between the device inside the package (100) and an electrical circuit outside the package (100); Including, The seal ring (40) includes a plurality of microrings (33), and at least a portion of the material of the bonding layer (30) is disposed between the microrings (33). Package (100).

2. The wafer level package (100) of claim 1, wherein the bonding layer (30) is on a surface of the second substrate (22).

3. The wafer level package (100) of any one of claims 1 to 2, wherein the microring (33) is formed by a protrusion on a surface of the seal ring (40).

4. The wafer level package (100) of any one of claims 1 to 3, wherein the seal ring (40) comprises a dielectric material.

5. The wafer level package (100) of any one of claims 1 to 4, wherein the package (100) comprises a cavity (60) in the second substrate (22).

6. The wafer level package (100) of claim 5, wherein the package (100) includes a getter (61) on a surface of the cavity (60).

7. The wafer level package (100) of any one of claims 1 to 6, wherein the package (100) comprises a microring pattern (90) on the first substrate (11).

8. The wafer level package (100) of any one of claims 1 to 7, wherein the package (100) is for a MEMS device.

9. A method of forming a wafer level package (100) for a device, comprising: - making lateral electrical connection lines (50) on a surface of a first substrate (11); creating a seal ring (40) on a surface of the first substrate (11) and on a portion of the lateral electrical connection line (50); forming a first bonding material layer (31) on a surface of the seal ring (40); creating a second layer of bonding material (32) on a surface of the second substrate (22); bonding the first bonding material layer (31) to the second bonding material layer (32) to form a bonding layer (30); Including, the lateral electrical connection traces (50) extend through the seal ring (40) to form electrical connections between the device inside the package (100) and electrical circuitry outside the package (100); providing a plurality of microrings (33) within the seal ring (40) thereby confining at least a portion of the material of the bonding layer (30) between the microrings (33), method.

10. The method of claim 9, wherein the microrings (33) are formed by protrusions on a surface of the seal ring (40).

11. The method of any one of claims 9 to 10, wherein the seal ring (40) comprises a dielectric material.

12. The method according to any one of claims 9 to 11, comprising the step of depositing an oxide layer on the first bonding material layer (31) and on the second bonding material layer (32).

13. 13. The method of claim 11 or 12, comprising the step of patterning the seal ring (40), the oxide layer, the first material layer (31) and / or the second material layer (32).

14. The method according to any one of claims 9 to 13, comprising the steps of forming a cavity (60) in the second substrate (22) and forming a getter (61) on a surface of the cavity (60) by a getter deposition process.

15. The method according to any one of claims 9 to 14, wherein the step of bonding the first bonding material layer (31) to the second bonding material layer (32) is performed by eutectic bonding, transient liquid phase bonding, or glass frit wafer bonding.

16. The method of claim 15, wherein the eutectic bonding is performed at a temperature 10-20° C. above the eutectic temperature of the eutectic alloy.

17. The method of claim 15, wherein the transient liquid phase bonding is carried out at a temperature of 150 to 300°C.

18. The method according to any one of claims 9 to 17, comprising the step of providing a microring pattern (90) on the first substrate (11).

19. The method of any one of claims 9 to 18, wherein the wafer level package (100) is for a MEMS device.

Images