Photoelectric conversion device, apparatus, substrate

Abstract

To suppress the propagation of a potential variation in a signal line to another circuit.SOLUTION: A photoelectric conversion device includes a photoelectric conversion unit, a first transistor that receives a charge in the photoelectric conversion unit in a gate, a second transistor connected to the gate, a signal line to which a signal is output from the first transistor, a third transistor provided in an electric route between the signal line and the first transistor, a first potential line that supplies a potential to turn off the second transistor, a second potential line that supplies a potential, which is common to the potential to turn off the second transistor and is to turn off the third transistor, and an isolator connected to the first potential line and the second potential line.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a photoelectric conversion device, an apparatus, and a substrate.

Background Art

[0002] A photoelectric conversion device including pixels having a photoelectric conversion section is known. Patent Document 1 describes that a control signal for turning off a plurality of transistors included in a pixel is generated by a common voltage generation circuit (negative voltage generation circuit 19).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a common voltage is used in generating a signal for turning off a plurality of transistors, potential fluctuations of a signal line are propagated to another circuit through the common voltage. As a result, the accuracy of a signal output from the photoelectric conversion device is degraded.

[0005] In the technology according to the present disclosure, propagation of potential fluctuations of a signal line to another circuit is suppressed.

Means for Solving the Problems

[0006] One aspect of the present disclosure includes a photoelectric conversion unit, a first transistor that receives the charge of the photoelectric conversion unit at its gate, a second transistor connected to the gate, a signal line from which a signal is output from the first transistor, a third transistor provided in an electrical path between the signal line and the first transistor, a first potential line that supplies a potential for turning off the second transistor, a second potential line that is at the same potential as the potential for turning off the second transistor and supplies a potential for turning off the third transistor, and an isolator connected to the first potential line and the second potential line , a potential supply unit, wherein the first potential line is connected to the potential supply unit, and the second potential line is connected to the potential supply unit via the isolator. A photoelectric conversion device characterized by the above. Further, another aspect of the present disclosure includes a photoelectric conversion unit, a first transistor that receives the charge of the photoelectric conversion unit at its gate, a second transistor connected to the gate, a signal line from which a signal is output from the first transistor, a third transistor provided in an electrical path between the signal line and the first transistor, a first potential line that supplies a potential for turning off the second transistor, a second potential line that is at the same potential as the potential for turning off the second transistor and supplies a potential for turning off the third transistor, an isolator connected to the first potential line and the second potential line, a plurality of pixels each having the photoelectric conversion unit, the first transistor, the second transistor, and the third transistor and arranged over a plurality of rows, a plurality of vertical scanning circuits that scan the plurality of rows of pixels row by row, a plurality of the first potential lines, a plurality of the second potential lines, and a plurality of the isolators, wherein at least one of the plurality of first potential lines, at least one of the plurality of second potential lines, and at least one of the plurality of isolators are correspondingly arranged for each of the plurality of vertical scanning circuits. A photoelectric conversion device characterized by this. 。

Advantages of the Invention

[0007] According to the technology of the present disclosure, it is possible to suppress the propagation of potential fluctuations of the signal line to another circuit.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0009] Hereinafter, each embodiment will be described with reference to the drawings.

[0010] In each of the embodiments described below, as an example of a photoelectric conversion device, an imaging device will be mainly described. However, each embodiment is not limited to the imaging device and is also applicable to other examples of the photoelectric conversion device. For example, there are a distance measuring device (a device for distance measurement using focus detection or TOF (Time Of Flight)), a photometric device (a device for measuring the incident light amount), and the like.

[0011] Note that the conductivity type of the transistor described in the embodiments below is an example and is not limited to only the conductivity type described in the embodiments. With respect to the conductivity type described in the embodiments, the conductivity type can be appropriately changed, and along with this change, the potentials of the gate, source, and drain of the transistor are appropriately changed.

[0012] For example, for a transistor that operates as a switch, the low level and high level of the potential supplied to the gate may be reversed with respect to the description in the embodiments along with the change in the conductivity type. Also, the conductivity type of the semiconductor region described in the embodiments below is an example and is not limited to only the conductivity type described in the embodiments. With respect to the conductivity type described in the embodiments, the conductivity type can be appropriately changed, and along with this change, the potential of the semiconductor region is appropriately changed.

[0013] (Embodiment 1) FIG. 1, FIG. 2, and FIG. 3 are schematic diagrams of an imaging device, which is a photoelectric conversion device according to Embodiment 1, and FIG. 4 is a timing chart.

[0014] FIG. 1 is a diagram showing the configuration of an imaging device. The imaging device has a pixel array 110 in which a plurality of pixels 100 are arranged in a plurality of rows and columns. The imaging device includes a vertical scanning circuit 120 that scans the pixel array 110 row by row. The imaging device also includes a signal line 130, a current source 140, and an isolator (resistive element) 150. Further, the imaging device includes a signal processing circuit 160 and a negative voltage supply circuit (potential supply unit) 170. A first potential line 152 is connected to the negative voltage supply circuit 170. The negative voltage supply circuit 170 only needs to have at least a function of supplying a negative voltage, and may further have a function of generating a negative voltage. For example, the negative voltage may be generated outside the photoelectric conversion device, and the negative voltage supply circuit 170 may be a circuit that buffers the negative voltage supplied from the outside. A second potential line 154 is connected to the first potential line 152 via the isolator 150. The first potential line 152 and the second potential line 154 are connected to the vertical scanning circuit 120. As will be described later, the first potential line 152 is a wiring that supplies the potential VTX L of a signal for turning off the transfer transistor. The second potential line 154 is a wiring that supplies the potential VSELL of a signal for turning off the selection transistor described later. The potentials VTX L and VSELL are the same potential.

[0015] The vertical scanning circuit 120 is connected to the pixels 100 of the pixel array 110 via control lines provided row by row. Control lines 102 - n, 103 - n, and 104 - n are arranged for the pixels 100 in the n-th row (n is a natural number). The control line 102 - n transmits the signal SEL(n). The control line 103 - n transmits the signal RES(n). The control line 104 - n transmits the signal TX(n).

[0016] The imaging device can be a non - stacked type imaging device in which all the configurations shown in FIG. 1 are housed in one substrate (typically a semiconductor substrate, but may be a substrate different from the semiconductor substrate such as a glass substrate). Note that, as in Example 2 described later, a stacked type imaging device in which a plurality of substrates (typically semiconductor substrates, but may be substrates different from the semiconductor substrate such as glass substrates) are stacked may also be used.

[0017] Figure 2 shows an example of the configuration of pixel 100. Pixel 100 includes a photodiode 400 which is an example of a photoelectric conversion unit, a transfer transistor 410, a floating diffusion (hereinafter referred to as FD) 420, a source follower transistor 430, and a selection transistor 440. The transfer transistor 410 transfers the charge generated by the photoelectric conversion in the photodiode 400 to the FD 420. The source follower transistor 430 outputs a signal based on the potential of the FD 420 to the selection transistor 440. The selection transistor 440 outputs the signal output from the source follower transistor 430 to the signal line 130.

[0018] The gate of the reset transistor 455 is connected to the control line 103-n. The gate of the transfer transistor 410 is connected to the control line 104-n. The gate of the selection transistor 440 is connected to the control line 102-n.

[0019] The anode of the photodiode 400 is connected to the GND node 450. Also, the source follower transistor 430 and the reset transistor 455 are connected to the power supply node 460. The transistors included in pixel 100 are described here as N-type transistors. In this case, a power supply voltage of typically 1 to 6V is input to the power supply node 460. The GND node 450 can be set to the ground potential, but is not limited to this potential and can also be set to a negative potential. Note that the transistors included in pixel 100 may be P-type transistors. In this case, the magnitude relationship between the potentials of the power supply node 460 and the GND node 450 may be reversed.

[0020] The source follower transistor 430 is an example of a first transistor that receives the signal charge of the photodiode 400 at its gate. The transfer transistor 410 is a transistor provided in the electrical path between the photodiode 400 and the source follower transistor 430. Also, it is an example of a second transistor connected to the gate of the source follower transistor 430. The selection transistor 440 is an example of a third transistor provided in the electrical path between the source follower transistor 430 and the signal line 130.

[0021] Figure 3 shows an example of a unit circuit for one row of the vertical scanning circuit 120. The unit circuit for one row of the vertical scanning circuit 120 has buffers 121 and 122. The potential VTXL and the potential VTXH are supplied to the gate of the transfer transistor 410 via the buffer 121 and the control line 104-n. The potential VTXL is the low level of the gate of the transfer transistor 410, and the potential VTXH is the high level of the gate of the transfer transistor 410. The transistors of the pixel 100 are N-type. Therefore, the transistor is off when a low-level signal is applied to the gate, and the transistor is on when a high-level signal is applied to the gate.

[0022] The potential VSELL and the potential VDDH are supplied to the gate of the selection transistor 440 via the buffer 122 and the control line 102-n. The potential VSELL is the low level of the gate of the selection transistor 440, and the potential VDDH is the high level of the gate of the selection transistor 440.

[0023] In FIG. 1, when all of the signals TX(1) to TX(n) are at a low level, the potential VTXL is supplied to the transfer transistors 410 of all the pixels 100 in the pixel array 110 via the vertical scanning circuit 120. The potential VTXL is connected to the negative voltage supply circuit 170. Also, when all of the signals SEL(1) to SEL(n) are at a low level, the potential VSELL is supplied to the selection transistors 440 of all the pixels 100 in the pixel array 110 via the vertical scanning circuit 120. The first potential line 154 and the second potential line 152 that supply the potential VSELL and the potential VTXL to the vertical scanning circuit 120 are connected via the isolator 150.

[0024] Details will be described later with reference to FIG. 4. The potential fluctuation of the signal line 130 propagates to the control line 102-n through the capacitive coupling between the signal line 130 and the gate of the selection transistor 440. The potential fluctuation of this control line 102-n propagates to the first potential line 154 that transmits the potential VSELL. If the isolator 150 is not provided, the potential fluctuation of the first potential line 154 propagates to the second potential line 152. As a result, the potential of the potential VTXL fluctuates. The potential fluctuation of this potential VTXL propagates to the control line 104-n. As a result, due to the capacitive coupling between the control line 104-n and the FD420, it propagates to the FD420 of the pixel 100 in which the transfer transistor 410 to which the potential VTXL is applied is in the off state. As a result, the accuracy of the signal output by the pixel 100 decreases. That is, the potential fluctuation of the signal line 130 causes a potential fluctuation of the FD420 of the pixel 100 in which the transfer transistor 410 is in the off state, and reduces the accuracy of the signal of the pixel 100. In the present disclosure, an isolator 150 is provided in the electrical path between the first potential line 154 and the second potential line 152. Thereby, it is made difficult to cause a potential fluctuation of the FD420 of the pixel 100 in which the transfer transistor 410 is in the off state due to the potential fluctuation of the signal line 130. Thereby, it is possible to suppress a decrease in the accuracy of the signal of the pixel 100.

[0025] In FIG. 2, the signal charges generated by the photodiode 400 are transferred to the FD 420 when the transfer transistor 410 is turned on. The transferred signal charges are converted into a signal voltage by the parasitic capacitance associated with the FD 420. Then, the signal voltage is output to the signal line 130 via the source follower transistor 430 and the selection transistor 440. The source follower transistor 430, together with the current source 140 in FIG. 1, constitutes a source follower circuit. By this source follower circuit, the signal voltage of the FD 420 is buffered in the source follower circuit and output to the signal line 130. Then, it is further read out to the subsequent stage by the signal processing circuit 160.

[0026] The operation will be further described with reference to the timing chart of FIG. 4. FIG. 4 shows, as an example, the operations related to the pixels 100 in three rows, namely the first row, the second row, and the third row. In FIG. 4, the signals SEL(1) to (3) are respectively input to the gates of the selection transistors 440 of the pixels 100 in rows 1 to 3 in FIG. 1. The signals RES(1) to (3) are respectively input to the gates of the reset transistors 455 of the pixels 100 in rows 1 to 3 in FIG. 1. Similarly, the signals TX(1) to (3) are respectively input to the gates of the transfer transistors 410 of the pixels 100 in rows 1 to 3 in FIG. 1. The potential of the signal line 130 indicates the potential of the signal line 130 in the column where signals are sequentially output from the pixels 100 where light is incident. The potential of the first potential line 152 is shown by comparing the case where the isolator 150 is provided and the comparative example where the isolator 150 is not provided.

[0027] At time t0, the signal RES(1) is at a high level, and the potential of the FD 420 of the pixel 100 in the first row is reset.

[0028] At time t1, the signal SEL(1) becomes a high level, and the pixel 100 in the first row is selected. On the other hand, since the signals SEL(2) and (3) are at a low level, the pixels 100 in the second and third rows are in a non-selected state.

[0029] At time t2, the signal RES(1) becomes low level, and the reset of FD420 of the pixel 100 in the first row is released.

[0030] During the period from time t3 to t4, the signal TX(1) becomes high level and is output to the signal line 130 via the selection transistor 440 to which the signal SEL(1) is input. Therefore, the potential of the signal line 130 decreases during the period from time t3 to t4. Also, during this period from time t3 to t4, the signals SEL(2) and (3) which are at low level ideally do not fluctuate. However, actually, all the control lines 102-n of non-selected rows including the signals SEL(2) and (3) are capacitively coupled from the signal line 130. As a result, a current flows through the control lines 102-n and the potential of the control lines 102-n fluctuates. This potential fluctuation of the control lines 102-n of non-selected rows propagates to the second potential line 154. At this time, the potential fluctuations of the control lines 102-n of each non-selected row are summed up and propagated to the second potential line 154. When the isolator 150 is not provided, the potential fluctuation of this second potential line 154 causes the potential of the first power supply line 152 to fluctuate. This potential fluctuation of the first power supply line 152 causes a fluctuation in the potential VTXL and fluctuates the potential of the control lines 104-n. This potential fluctuation of the control lines 104-n fluctuates the potential of the FD420 of the selected row due to the capacitive coupling between the control lines 104-n and the FD420. As a result, the signal accuracy output from the pixel 100 of the selected row decreases. When an image is generated using the signal output from the photoelectric conversion device, the image quality deteriorates.

[0031] At time t5, the signal RES(1) becomes high level, and the charge of FD420 of the pixel 100 in the first row is reset. At time t5, the potential of the signal line 130 rises and returns to the voltage before the potential decrease.

[0032] Also, at the same time t5, the signal SEL(2) becomes high level and the pixel 100 in the second row is selected. On the other hand, at time t5, the signal SEL(1) becomes low level, and the signal SEL(3) continues to be at low level. Therefore, the pixels 100 in the first and third rows are in a non-selected state.

[0033] At time t6, the signal RES(2) becomes low level, and the reset of FD420 of the pixel 100 in the second row is released.

[0034] During the period from time t7 to t8, the signal TX(2) becomes high level and is output to the signal line 130 via the selection transistor 440 to which the signal SEL(2) is input. As a result, the potential of the signal line 130 decreases. Also during this period from time t7 to t8, the same fluctuations as in the period from time t3 to t4 occur in the signals SEL(1) and (3) of the non-selected rows. Therefore, potential fluctuations occur in the FD420 of the selected row.

[0035] Similarly, after time t9, the pixel 100 in the third row is selected, the pixels 100 in the first and second rows are in the non-selected state, and when TX(3) becomes high level during the period from time t11 to t12, the potential of the signal line 130 decreases. Then, the same fluctuations as in the periods t3 to t4 and t7 to t8 occur in the signals SEL(1) and (2) of the non-selected rows. Therefore, potential fluctuations occur in the FD420 of the selected row.

[0036] After the fourth row, in any n-th row, potential fluctuations occur in the FD420 of the selected row due to potential fluctuations in the control line 102 - n of the non-selected row. As shown in FIG. 4, when the isolator 150 is not provided, the potential fluctuation of the potential VTXL of the first potential line 152 is large. In this embodiment, an isolator 150 is provided between the first potential line 152 and the second potential line 154. Thereby, the propagation of potential fluctuations from the second potential line 154 to the first potential line 152 can be suppressed. Thereby, the fluctuation of the signal VTXL is suppressed. Therefore, the potential fluctuation of the FD420 of the selected row can be suppressed.

[0037] Note that if the resistance value of the isolator 150 is too small, the effect of suppressing the potential fluctuation of the first potential line 152 will be small. On the other hand, if the resistance value of the isolator 150 is too large, although the potential fluctuation of the first potential line 152 can be suppressed, the current supply to the second potential line 154 will be suppressed. As a result, the fluctuation of the potential VSELL will increase. Therefore, it is preferable that the suitable resistance value of the isolator 150 is in the range of 10 Ω or more and 1000 Ω or less. In particular, setting it in the range of 60 Ω or more and 150 Ω or less is preferable in that it can achieve both high-voltage supply from the first potential line 152 to the second potential line 154 and high-dimensional suppression of the propagation of potential fluctuations. Also, when creating a resistance of 10 Ω or more with the parasitic resistance of the wiring, the wiring area becomes large, resulting in restrictions on the wiring layout. For this reason, it is preferable to use a resistance element provided with polysilicon or a diffusion resistance provided with a diffusion region in which impurities are diffused in a semiconductor substrate as the isolator 150.

[0038] Note that the pixel structure described in this embodiment is not limited to the form of FIG. 2. For example, it can also be applied to the pixels having a global shutter function described in FIG. 11. The pixel 100 described in FIG. 11 includes a shutter transistor 490 and a holding capacitor 480 (holding portion) between the transfer transistor 410 and the photodiode 400. A signal GS is applied from the vertical scanning circuit 120 to the gate of this shutter transistor 490. The signal GS changes to a high level and a low level simultaneously for all the pixels 100 in the entire row of the pixel array 110. Therefore, when the signal GS changes to a high level, signal charges are transferred from the photodiodes 400 of all the pixels 100 in the pixel array 110 to the corresponding holding capacitors 480. That is, a global shutter operation can be performed. This has the global shutter function. In this form, the transfer transistor 410 is connected to the holding capacitor 480, which is a holding portion for holding the charge of the photodiode 400, and the gate of the source follower transistor. Also, in this form, it can be said that the transfer transistor 410 is connected to the photodiode. Further, in this form, the voltage (which may be a negative voltage) at which the shutter transistor 490 is turned off and applied to the gate of the shutter transistor 490 may be generated from a potential line connected via an isolator to the second potential line 154. Further, a transistor for discharging charge may be further connected to the photodiode with respect to the configuration described in FIG. 11. The voltage (which may be a negative voltage) at which the charge discharging transistor is turned off and applied to the gate of this charge discharging transistor may be generated from a potential line connected via an isolator to the second potential line 154.

[0039] Further, for the pixel configuration of FIG. 2 or the pixel configuration of FIG. 11, a transistor for changing the capacitance value connected to FD420 may be provided. When this transistor is turned on, an additional capacitance is connected to FD420. This additional capacitance may use the capacitance of the channel portion of the transistor, or a capacitance element (MIM capacitance, MOS capacitance, etc.) may be provided separately from the transistor. Thereby, the charge-voltage conversion coefficient for converting signal charges into voltage can be reduced by the combined capacitance of FD420 and the additional capacitance. The voltage (which may be a negative voltage) for turning off the transistor, applied to the gate of the transistor for changing this capacitance value, may be generated from a potential line connected via an isolator to the second potential line 154. Also in this form, the same effects as those of the present embodiment can be obtained.

[0040] Also in pixel 100, the point that the potential fluctuation of signal line 130 causes the potential fluctuation of FD420 of the pixel 100 in the selected row is the same. Therefore, by providing isolator 150, a decrease in the signal accuracy of the pixel 100 in the selected row can be suppressed.

[0041] In addition, in this embodiment, an example in which one pixel 100 includes one photodiode 400 has been described, but the present invention is not limited to this example. One pixel 100 may include a plurality of photodiodes. In this case, by adopting a configuration in which a plurality of photodiodes are provided for one microlens, it is possible to perform focus detection (distance measurement) by the image plane phase difference method. Further, when a plurality of photodiodes are provided, the charges of the plurality of photodiodes may be input to one FD420. In this case, a plurality of transfer transistors are arranged so as to correspond to each of the plurality of photodiodes, but there is one reset transistor and one source follower transistor. As another example, a plurality of FD420s may be provided in one pixel, and the charges of some of the plurality of photodiodes may be input to some FDs, and the charges of other photodiodes may be input to other FDs. In this case, a plurality of reset transistors and source follower transistors are arranged in one pixel 100. Note that the number of selection transistors may be changed according to the number of photodiodes, or may be changed according to the number of signal lines 130 arranged corresponding to one column of pixels 100. For example, when two signal lines 130 are provided for one column of pixels, the pixel 100 may be provided with a plurality of selection transistors 440 for one source follower transistor 430. One of the plurality of selection transistors 440 is connected to one of the two signal lines 130, and another selection transistor is connected to the other signal line 130. Thereby, it becomes possible to appropriately switch the signal line output from the pixel 100 according to the operation mode of the imaging device.

[0042] In addition, in this embodiment, a resistance element is used as an example of the isolator, but the present invention is not limited to this example. In this embodiment, a common potential is supplied from the first potential line 152 to the second potential line 154 by voltage supply via the isolator 150. A negative voltage supply circuit 170 may supply a potential to the second potential line 154 without passing through the first potential line 152. In this case, a capacitance element may be used as the isolator.

[0043] Also, in this embodiment, an example where the potentials VTXL and VSELL are negative potentials has been described, but the present invention is not limited to this example, and they may be a ground potential or a positive potential. Also, although an example where the potentials VTXL and VSELL are the same potential has been shown, depending on the operation of the photoelectric conversion device and the resistance value of the isolator 160, they may not be exactly the same potential. Even including such cases, the potentials VTXL and VSELL can be treated as a common potential.

[0044] (Embodiment 2) This embodiment will be described centering on the differences from Embodiment 1.

[0045] FIGS. 5 and 6 show schematic diagrams of the imaging device according to Embodiment 2. Hereinafter, the description will center on the differences from Embodiment 1.

[0046] This embodiment relates to an imaging device in which a plurality of substrates are stacked.

[0047] In FIG. 5, the pixel array 110 is disposed on the first substrate 200.

[0048] In FIG. 6, on the second substrate 300, a vertical scanning circuit 120, an isolator 150, a power supply pad 180 to which VTXL is input, and a power supply pad 190 to which a signal VSELL is input are arranged. In this embodiment, six isolators 150, power supply pads 180, and power supply pads 190 are arranged respectively. The isolator 150 is arranged between the vertical scanning circuit 120 and the power supply pads 180 and 190. A negative voltage supply circuit 170 is connected to the outside of the second substrate 300 via the power supply pad 180. As another example, the negative voltage supply circuit 170 may be arranged on the second substrate 300. A bypass capacitor 310 is connected between the power supply pad 180 and a ground potential node (hereinafter sometimes referred to as GND). A bypass capacitor 320 is connected between the power supply pad 190 and GND. The first substrate 200 and the second substrate 300 are bonded together so that the signals SEL(1) to SEL(n), RES(1) to RES(n), and TX(1) to TX(n) of the pixel array 110 and the vertical scanning circuit 120 are connected. The first substrate 200 and the second substrate 300 are bonded together such that the first substrate 200 is on top and the second substrate 300 is at the bottom when viewed from the light incident surface. These first and second substrates are electrically connected. This electrical connection can be achieved by a TSV (Through Silicon Via) structure. As another connection method, an insulating film and a conductive member provided in a groove of the insulating film may be provided on the bonding surfaces of the first substrate and the second substrate respectively, and a hybrid bonding may be used to bond the insulating films and the conductive members to each other. Note that the electrical connection of a plurality of substrates is not limited to these forms, and microbumps may be used, and various connection methods may be adopted. Here, the potential VTXL is input from the outside of the imaging device via six power supply pads 180. Further, a bypass capacitor 310 is arranged between the power supply pad 180 and GND. Thereby, compared with the case where there is one power supply pad 180 or the case where the bypass capacitor 310 is not provided, the fluctuation of the potential VTXL can be further suppressed.In addition, by inputting the potential VSELL through six isolators 150, it is possible to make the VSELL potential uniform within the second substrate 300 and suppress image quality degradation compared to the case of a single location. Furthermore, by arranging a bypass capacitor 320 between the power supply pad 190 and GND, it is also possible to suppress fluctuations in the potential VSELL due to the arrangement of the isolators 150.

[0049] Note that in this embodiment, a configuration in which two substrates are stacked is shown, but the number of substrates is not limited to this, and a form in which more substrates are stacked may also be used.

[0050] (Embodiment 3) Regarding this embodiment, the description will focus on the differences from Embodiment 1.

[0051] In Embodiment 1, potential fluctuations of FD originating from the control line connected to the gate of the transfer transistor were suppressed. In this embodiment, potential fluctuations of FD originating from the control line connected to the gate of the reset transistor are suppressed.

[0052] FIGS. 7 and 8 show schematic diagrams of the imaging device according to Embodiment 3. FIG. 7 is the same as FIG. 1 except that the potential VTXL in FIG. 1 has become the potential VPRESL. The potential VRESL is a low-level potential applied to the gate of the reset transistor 455 shown in FIG. 1. The potential VRESL is supplied to the gate of the reset transistor 455 to be set off via the vertical scanning circuit 120 and the control line 103-n. The negative voltage supply circuit 170 supplies the potential VRESL to the vertical scanning circuit 120 via the third potential line 153. The potential VRESL is the same potential as the potential VSELL.

[0053] FIG. 8 shows an example of a unit circuit for one row of the vertical scanning circuit 120, similar to FIG. 3. The unit circuit for one row of the vertical scanning circuit 120 has buffers 122 and 123. The configuration of buffer 122 is the same as that in FIG. 3. The potential VRESL and the potential VRESH are connected to the gate of the reset transistor 455 via buffer 123. The potential VRESL is a low-level potential supplied to the gate of the reset transistor. Also, the potential VRESH is a high-level potential supplied to the gate of the reset transistor 455.

[0054] In FIG. 7, the control line 103-n is connected to the third potential line 153 (another example of the first potential line) via the vertical scanning circuit 120. Also, the third potential line 153 is connected to the negative voltage supply circuit 170. Further, the control line 102-n is connected to the second potential line 154 via the vertical scanning circuit 120. The second potential line 154 and the third potential line 153 are connected via the isolator 150. Thereby, it is possible to suppress the propagation of potential fluctuations of the signal line 130, the control line 102-n, and the second potential line 154 to the third potential line 153. If the isolator 150 is not provided, the potential fluctuation of the third potential line 153 propagates to the control line 103-n. Then, due to the capacitive coupling between the control line 103-n and the FD420, potential fluctuations occur in the FD420 of the pixels 100 in the selected row. On the other hand, by providing the isolator 150, it is possible to suppress the potential fluctuations of the FD420 of the pixels 100 in the selected row via the control line 103-n. Thereby, it is possible to suppress a decrease in the accuracy of the signal output from the pixels 100 in the selected row.

[0055] Also, this embodiment can be combined with Embodiment 1. That is, as shown in FIG. 1, the second potential line 154 and the first potential line 152 are connected via an isolator. Then, as shown in FIG. 8, the second potential line 154 and the third potential line 153 are connected via another isolator. That is, with respect to the second potential line 154, the first potential line 152 and the third potential line 153 can each be connected via an isolator. This form can obtain both the effects of Embodiment 1 and the effects of this embodiment, and can further suppress the decrease in the signal accuracy of the pixels 100 in the selection row.

[0056] (Embodiment 4) Regarding this embodiment, the description will focus on the differences from Embodiment 1.

[0057] FIGS. 9 and 10 show schematic diagrams of the imaging device according to Embodiment 4. FIG. 9 shows an example of another configuration of the pixel 100. The difference between FIG. 9 and FIG. 2 is that the GND node 450 of the photodiode 400 has become the node 470. FIG. 10 shows the same part as FIG. 1, but is different from FIG. 1 in that the node 470 from the pixel 100 is connected to the negative voltage supply circuit 170. By connecting the node 470 to the negative voltage supply circuit 170, the reference potential of the pixel becomes a negative potential. The potential VSELL is connected to the node 470 via the isolator 150.

[0058] Thereby, even if the potentials of the power supply potential 460 and the potential VTXH are lowered, it is possible to suppress the deterioration of the transfer characteristics of the transfer transistor 410. Also, since it becomes possible to lower the potentials of the power supply potential 460 and the potential VTXH, the power consumption can be reduced. Further, by providing the isolator 150, it is possible to suppress the fluctuation caused by the second potential line 154, which is the origin of the potential fluctuation of the signal line 130, from propagating to the node 470. Thereby, it is possible to suppress the potential fluctuation of the FD420 due to the capacitive coupling between the node 470 and the FD420.

[0059] Furthermore, similar to Example 1, the potential VSELL may be connected to the potential VTXL via the isolator 150. Thereby, it becomes possible to obtain the effects of Example 1 as well. It is also possible to combine with Examples 2 and 3.

[0060] The pixel 100 shown in FIG. 2 is an example and is not limited thereto. Also, although an example in which one signal line 130 is provided in one pixel column is shown, it is not limited thereto. Four, eight, twelve, etc. may be used. The signal processing circuit 160 may include a gain amplifier and an ADC.

[0061] (Example 5) This example is applicable to any of Examples 1 to 4. FIG. 12(a) is a schematic diagram for explaining a device 9191 including the semiconductor device 930 of the present embodiment. The device 9191 including the semiconductor device 930 will be described in detail. As described above, the semiconductor device 930 can include, in addition to the semiconductor device 910 having the semiconductor layer 10, a package 920 that houses the semiconductor device 910. The package 920 can include a substrate to which the semiconductor device 910 is fixed and a lid such as glass facing the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the substrate and a terminal provided on the semiconductor device 910.

[0062] The device 9191 can include at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0063] The processing device 960 processes the signals output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for constituting an AFE (Analog Front End) or DFE (Digital Front End). The display device 970 is an EL display device or a liquid crystal display device that displays the information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores the information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0064] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. In the device 9191, the signals output from the semiconductor device 930 are displayed on the display device 970 or transmitted externally by a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960 separately from the storage circuit and the arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signals output from the semiconductor device 930.

[0065] Also, the device 9191 is suitable for electronic devices such as an information terminal having a photographing function (e.g., a smartphone or a wearable terminal) or a camera (e.g., a single-lens reflex camera, a compact camera, a video camera, a surveillance camera). The mechanical device 990 in the camera can drive the components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for anti-vibration operations.

[0066] Also, the device 9191 can be a transportation device such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation device can be used as a moving device. The device 9191 as a transportation device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (operation) by means of a photographing function. The processing device 960 for assisting and / or automating driving (operation) can perform processing for operating the mechanical device 990 as a moving device based on the information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analysis device such as an electron microscope, an office device such as a copying machine, or an industrial device such as a robot.

[0067] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. The increase in value here includes at least any one of addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental load, cost reduction, miniaturization, and weight reduction.

[0068] Therefore, if the semiconductor device 930 according to the present embodiment is used in the device 9191, the value of the device can also be improved. For example, when the semiconductor device 930 is mounted on a transportation device and excellent performance can be obtained when photographing the outside of the transportation device or measuring the external environment. Therefore, in manufacturing and selling the transportation device, deciding to mount the semiconductor device according to the present embodiment on the transportation device is advantageous for improving the performance of the transportation device itself. In particular, the semiconductor device 930 is suitable for a transportation device that performs driving support and / or autonomous driving of the transportation device using the information obtained by the semiconductor device.

[0069] The above-described embodiments can be appropriately modified without departing from the technical idea. The disclosure of this specification includes not only what is described in this specification but also all matters that can be grasped from this specification and the drawings attached hereto. Also, the disclosure of this specification includes the complementary set of the concepts described in this specification. That is, if this specification describes, for example, that "A is larger than B," even if the description that "A is not larger than B" is omitted, it can be said that this specification discloses that "A is not larger than B." This is because when the description that "A is larger than B" is given, it is premised that the case where "A is not larger than B" is considered.

[0070] [Modification Embodiment] The present invention is not limited to the above embodiments and can be variously modified.

[0071] For example, an example in which a part of the configuration of one of the embodiments is added to another embodiment or an example in which a part of the configuration of another embodiment is replaced is also included in the embodiments of the present invention.

[0072] Note that the above examples are merely specific examples for implementing the present invention, and the technical scope of the present invention should not be construed as being limited thereby. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features.

Description of Reference Numerals

[0073] 100 pixels 110 pixel array 150 isolator 152 first potential line 154 second potential line 400 photodiode (photoelectric conversion unit) 410 transfer transistor 420 floating diffusion 430 source follower transistor 440 selection transistor 455 reset transistor

Claims

1. A photoelectric conversion unit, a first transistor that receives the charge of the photoelectric conversion unit at its gate, a second transistor connected to the gate, a signal line from which a signal is output from the first transistor, a third transistor provided in the electrical path between the signal line and the first transistor, a first potential line that supplies a potential for turning off the second transistor, a second potential line that has the same potential as the potential for turning off the second transistor and supplies a potential for turning off the third transistor, an isolator connected to the first potential line and the second potential line, and a potential supply unit, and the first potential line is connected to the potential supply unit, and the second potential line is connected to the potential supply unit via the isolator, characterized in that it is a photoelectric conversion device.

2. A plurality of pixels each having the photoelectric conversion unit, the first transistor, the second transistor, and the third transistor, arranged over a plurality of rows, and a vertical scanning circuit that scans the plurality of rows of pixels row by row, wherein the first potential line and the second potential line are connected to the vertical scanning circuit, characterized in that it is the photoelectric conversion device according to Claim 1.

3. A photoelectric conversion unit, a first transistor that receives the charge of the photoelectric conversion unit at its gate, a second transistor connected to the gate, a signal line from which a signal is output from the first transistor, a third transistor provided in the electrical path between the signal line and the first transistor, a first potential line that supplies a potential for turning off the second transistor, a second potential line that has the same potential as the potential for turning off the second transistor and supplies a potential for turning off the third transistor, an isolator connected to the first potential line and the second potential line, a plurality of pixels each having the photoelectric conversion unit, the first transistor, the second transistor, and the third transistor, arranged over a plurality of rows, a plurality of vertical scanning circuits that scan the plurality of rows of pixels row by row, a plurality of the first potential lines, a plurality of the second potential lines, and a plurality of the isolators, wherein at least one of the plurality of first potential lines, at least one of the plurality of second potential lines, and at least one of the plurality of isolators are correspondingly arranged for each of the plurality of vertical scanning circuits, characterized in that it is a photoelectric conversion device.

4. The photoelectric conversion device according to claim 3, characterized in that a plurality of the isolators are connected to one of the plurality of first potential lines and one of the plurality of second potential lines.

5. comprising a plurality of pads to which the first potential line is connected, The photoelectric conversion device according to claim 3 or 4, characterized in that each of the plurality of isolators is provided corresponding to one of the plurality of pads.

6. The photoelectric conversion device according to any one of claims 1 to 5, characterized in that the isolator is a resistance element.

7. The photoelectric conversion device according to claim 6, characterized in that the resistance value of the resistance element is 10 Ω or more.

8. The photoelectric conversion device according to claim 6 or 7, characterized in that the resistance value of the resistance element is 1000 Ω or less.

9. The photoelectric conversion device according to any one of claims 6 to 8, characterized in that the resistance value of the resistance element is 60 Ω or more and 150 Ω or less.

10. The photoelectric conversion device according to any one of claims 6 to 9, characterized in that the resistance element contains polysilicon.

11. The photoelectric conversion device according to any one of claims 6 to 9, characterized in that the resistance element includes a diffusion region in which impurities are diffused into the substrate.

12. The photoelectric conversion device according to any one of claims 1 to 11, characterized in that the common potential is a negative voltage.

13. The photoelectric conversion device according to any one of claims 1 to 12, characterized in that the second transistor is connected to the photoelectric conversion unit.

14. The photoelectric conversion device according to any one of claims 1 to 12, characterized in that the second transistor is connected to a holding unit that holds the charge of the photoelectric conversion unit.

15. The photoelectric conversion device according to any one of claims 1 to 12, characterized in that the second transistor is a reset transistor that is connected to a power supply voltage and resets the charge of the gate.

16. The photoelectric conversion device according to any one of claims 1 to 12, characterized in that the second transistor is a transistor that switches the capacitance value of a capacitor connected to the gate.

17. A device comprising the photoelectric conversion device according to any one of claims 1 to 16, an optical device corresponding to the photoelectric conversion device, a control device for controlling the photoelectric conversion device, A processing device that processes the signal output from the photoelectric conversion device, A display device that displays the information obtained by the photoelectric conversion device, A storage device that stores the information obtained by the photoelectric conversion device, and A device, characterized by further comprising at least one of a mechanical device that operates based on the information obtained by the photoelectric conversion device.

18. A photoelectric conversion unit, A first transistor that receives the charge of the photoelectric conversion unit at the gate, A second transistor connected to the gate, A signal line from which a signal is output from the first transistor, A substrate for laminating on a substrate on which a third transistor provided in an electrical path between the signal line and the first transistor is arranged, A first potential line that supplies a potential for turning off the second transistor, A second potential line that is a potential common to the potential for turning off the second transistor and supplies a potential for turning off the third transistor, An isolator connected to the first potential line and the second potential line, and A substrate, characterized in that a potential is supplied from a potential supply unit to the first potential line, and the second potential line is supplied with a potential from the potential supply unit via the isolator.

19. A photoelectric conversion unit, A first transistor that receives the charge of the photoelectric conversion unit at the gate, A second transistor connected to the gate, A signal line from which a signal is output from the first transistor, A third transistor provided in an electrical path between the signal line and the first transistor, A first potential line that supplies a potential for turning off the second transistor, A second potential line that is a potential common to the potential for turning off the second transistor and supplies a potential for turning off the third transistor, An isolator connected to the first potential line and the second potential line, A plurality of pixels each having the photoelectric conversion unit, the first transistor, the second transistor, and the third transistor, arranged over a plurality of rows, A plurality of vertical scanning circuits that scan the plurality of rows of pixels row by row, A plurality of the first potential lines, a plurality of the second potential lines, and a plurality of the isolators, and A substrate, characterized in that at least one of the plurality of first potential lines, at least one of the plurality of second potential lines, and at least one of the plurality of isolators are correspondingly arranged for each of the plurality of vertical scanning circuits.

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