Indicating device

Abstract

Provided is a display device suitable for high-gradation display. A display device having, in each pixel, two drive transistors and a light emission device, wherein the two drive transistors and the light emission device are connected in series. One transistor is a p-channel type, and the other transistor is an n-channel type, the transistors being driven alternately. Due to this configuration, it is possible to suppress fluctuation in voltage between gate and source when performing high-gradation display. Moreover, a transistor having a metal oxide in a channel formation region is used as the n-channel transistor, whereby it is possible to increase display characteristics of low-gradation display.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification or the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, an operation method thereof, or a manufacturing method thereof.

[0003] Note that in this specification or the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may include a semiconductor device.

Background Art

[0004] Techniques for constructing a transistor using a metal oxide formed on a substrate have attracted attention. For example, techniques for using a transistor using zinc oxide or an In-Ga-Zn-based oxide as a switching element of a pixel of a display device are disclosed in Patent Document 1 and Patent Document 2.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a display device using a light-emitting device such as an organic EL element, a driving transistor is connected to one electrode of the light-emitting device, and the luminance of the light-emitting device is controlled by the current flowing through the driving transistor.

[0007] When an n-channel type transistor is used as the driving transistor, the source of the driving transistor and the anode of the light-emitting device are connected. Here, the cathode potential (common potential) of the light-emitting device may show fluctuations or position dependence under the influence of factors such as the resistance of the electrode in the case of high gradation display (high luminance display). The fluctuation of the cathode potential changes the Vgs (gate-source voltage) of the n-channel type transistor. Therefore, a deviation may occur between the input image data and the luminance of the light-emitting device.

[0008] On the other hand, when a p-channel type transistor is used as the driving transistor, a configuration can be adopted to avoid the above problems. However, a transistor using general silicon in the channel formation region has a high off-current and insufficient transfer characteristics at a low level potential (low gradation). Also, considering current magnitude control, saturation characteristics, etc., there is a problem of low layout freedom, such as the need to increase the channel length.

[0009] Therefore, one of the objectives of one aspect of the present invention is to provide a display device suitable for wide gradation display. Or, one of the objectives is to provide a display device having excellent display characteristics.

[0010] Or, one of the objectives is to provide a display device with low power consumption. Or, one of the objectives is to provide a highly reliable display device. Or, one of the objectives is to provide a novel display device, etc. Or, one of the objectives is to provide an operation method of the above display device. Or, one of the objectives is to provide a novel semiconductor device, etc.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0012] One aspect of the present invention relates to a display device suitable for wide gamut display.

[0013] One aspect of the present invention is a display device having a first transistor, a second transistor, and a light-emitting device in a pixel, wherein one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, the other of the source or drain of the second transistor is electrically connected to the anode of the light-emitting device, the first transistor is a p-channel type, and the second transistor is an n-channel type.

[0014] The first transistor has silicon in the channel formation region, the second transistor has a metal oxide in the channel formation region, and the metal oxide preferably has In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0015] The pixel further has a third transistor, a fourth transistor, and a fifth transistor, wherein one of the source or drain of the third transistor is electrically connected to the gate of the first transistor, one of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor, and one of the source or drain of the fifth transistor can be electrically connected to the other of the source or drain of the second transistor.

[0016] The third transistor, the fourth transistor, and the fifth transistor have a metal oxide in the channel formation region, and the metal oxide preferably contains In, Zn, and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0017] The display device further includes a first circuit that outputs a first data potential and a second data potential. One of the first data potential and the second data potential is equal to the input potential to the first circuit, and the other is a potential obtained by binarizing the input potential. One of the first data potential and the second data potential is input to the gate of the first transistor via the third transistor, and the other can be input to the gate of the second transistor via the fourth transistor.

[0018] The first circuit includes a CMOS inverter circuit having a p-channel transistor with silicon in the channel formation region and an n-channel transistor with a metal oxide in the channel formation region, and the metal oxide can contain In, Zn, and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

Advantages of the Invention

[0019] By using one aspect of the present invention, a display device suitable for wide gradation display can be provided. Alternatively, a display device having excellent display characteristics can be provided.

[0020] Alternatively, a display device with low power consumption can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device or the like can be provided. Alternatively, a method of operating the above display device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

Brief Description of the Drawings

[0021] FIG. 1 is a diagram for explaining a pixel circuit. FIGS. 2A and 2B are diagrams for explaining a conventional pixel circuit. FIG. 3A is a diagram for explaining a signal generation circuit. FIG. 3B is a diagram for explaining a buffer circuit. FIG. 4A is a diagram for explaining the output potential of a source driver. FIG. 4B is a diagram for explaining the output potential of a buffer circuit. FIG. 5 is a diagram for explaining the operations of a signal generation circuit and a pixel circuit. FIG. 6 is a diagram for explaining the operations of a signal generation circuit and a pixel circuit. FIG. 7 is a diagram for explaining a display device. FIGS. 8A to 8C are diagrams for explaining a display device. FIGS. 9A and 9B are diagrams for explaining a touch panel. FIG. 10 is a diagram for explaining a display device. FIGS. 11A to 11C are diagrams for explaining a transistor. FIGS. 12A to 12C are diagrams for explaining a transistor. FIGS. 13A and 13B are diagrams for explaining a transistor. FIGS. 14A to 14F are diagrams for explaining an electronic device.

DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and the repeated description thereof may be omitted. Note that the hatching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings.

[0023] Even if an element is illustrated as a single element on a circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, transistors that operate as switches may be connected in series or in parallel. Also, there are cases where a capacitor is divided and arranged at a plurality of positions.

[0024] In addition, a single conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in this specification, a plurality of names may be used for the same element. Also, even if it is illustrated on a circuit diagram that elements are directly connected to each other, actually, the elements may be connected via one or a plurality of conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0025] (Embodiment 1) In this embodiment, a display device which is one aspect of the present invention will be described with reference to the drawings.

[0026] One aspect of the present invention is a display device having two transistors having the function of driving transistors for pixels and one light-emitting device (also referred to as a light-emitting element). The two transistors and the light-emitting device are connected in series. When one transistor is operated as a driving transistor, the other transistor is operated as a switch.

[0027] The two transistors are a combination of a p-channel type transistor and an n-channel type transistor. The p-channel type transistor functions as a driving transistor during high gradation (high brightness) display. At this time, the n-channel type transistor is in a low-resistance conduction state. Also, the n-channel type transistor functions as a driving transistor during low gradation (low brightness) display. At this time, the p-channel type transistor is in a low-resistance conduction state. By adopting such a configuration, it is possible to suppress fluctuations in the gate-source voltage (Vgs) during high gradation display.

[0028] In addition, by using a transistor (hereinafter referred to as an OS transistor) having a metal oxide in the channel formation region in an n-channel type transistor, the display characteristics of low gradation display can be improved. The OS transistor has a characteristic of extremely low off-current.

[0029] The switching of the drive transistor can be performed according to a binary signal potential input to the pixel. The binary signal potential is generated by a signal generation circuit provided between the source driver and the pixel. In the signal generation circuit, two signal potentials, namely, a data potential input from the source driver and a potential obtained by binarizing the data potential, are output to the pixel. The binary signal potential can be used as a gate potential for conducting a transistor operating as a switch with low resistance.

[0030] FIG. 1 is a circuit diagram of a pixel included in a display device according to an aspect of the present invention. The pixel 10 includes a transistor 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a capacitor 106, a capacitor 107, and a light-emitting device 108. Note that a configuration without the transistor 105 is also possible.

[0031] One of the source or drain of the transistor 101 is electrically connected to one electrode of the capacitor 106 and the gate of the transistor 103. One of the source or drain of the transistor 102 is electrically connected to one electrode of the capacitor 107 and the gate of the transistor 104. One of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104. The other of the source or drain of the transistor 103 is electrically connected to the other electrode of the capacitor 106. The other electrode of the transistor 104 is electrically connected to the anode of the light-emitting device 108, the other electrode of the capacitor 107, and one of the source or drain of the transistor 105.

[0032] The other of the source or drain of transistor 101 is electrically connected to wiring 121. The other of the source or drain of transistor 102 is electrically connected to wiring 122. The other of the source or drain of transistor 103 is electrically connected to wiring 123. The other of the source or drain of transistor 105 is electrically connected to wiring 124. The cathode of light-emitting device 108 is electrically connected to wiring 129. The gates of transistor 101 and transistor 102 are electrically connected to wiring 125. The gate of transistor 105 is electrically connected to wiring 126.

[0033] Wiring 121 and wiring 122 are source lines that connect pixel 10 to signal generation circuit 40 and source driver 20 described later. Wiring 123 and wiring 129 are power lines, and wiring 123 can be a high-potential power line and wiring 129 can be a low-potential power line. Wiring 124 is a wiring that supplies a reset potential (for example, a low potential). Wiring 125 and wiring 126 are gate lines that control the operation of the transistors connected thereto.

[0034] Here, transistor 101, transistor 102, and transistor 105 function as switches. Transistor 103 and transistor 104 function as driving transistors or switches for light-emitting device 108. Transistor 103 is a p-channel type transistor, and transistor 104 is an n-channel type transistor. Capacitors 106 and 107 function as holding capacitors. Note that in FIG. 1, transistor 101, transistor 102, and transistor 105 are illustrated as n-channel type transistors, but they may be p-channel type transistors.

[0035] FIG. 2A is an example of a conventional pixel circuit and includes three n-channel type transistors (transistors 302, 304, 305), capacitor 307, and light-emitting device 308.

[0036] Transistor 304 is a driving transistor, and a data potential is supplied to the gate of transistor 304 via transistor 302. At this time, a reset potential is supplied to the source of transistor 304 via transistor 305. That is, since the gate potential can be supplied in a state where the source potential of transistor 304 is stable, Vgs becomes an ideal value.

[0037] On the other hand, the display device has a plurality of light-emitting devices, and their cathodes are connected to a common electrode COM. Here, when a translucent conductive film (for example, indium tin oxide, etc.) having a higher resistance than metal is used for the common electrode COM, a voltage drop may occur in the common electrode COM when a large current flows during high-tone (high-brightness) display. Since the light-emitting device also operates as a constant-voltage element during light emission, when the potential of the common electrode COM (the potential of the cathode) changes, the potential of the anode also changes.

[0038] Ideally, Vgs is maintained by capacitor 307 which is a holding capacitor, but due to the influence of parasitic capacitance Cp added to the gate of transistor 304, the change amount of the gate potential of transistor 304 becomes smaller than the change amount of the source potential (the potential of the anode). That is, since Vgs becomes smaller, there is a problem that a desired luminance cannot be obtained.

[0039] FIG. 2B is another example of a conventional pixel circuit, and includes two p-channel transistors (transistor 301, transistor 303), capacitor 306, and light-emitting device 309.

[0040] Transistor 303 is a driving transistor, and a data potential is supplied to the gate of transistor 303 via transistor 301. Here, since the source of transistor 303 is electrically connected to a power supply line 323 that can use a low-resistance metal wiring or the like, the source potential is always stable, and Vgs becomes an ideal value.

[0041] However, p-channel transistors are generally formed of transistors having silicon in the channel formation region (hereinafter referred to as Si transistors). Since Si transistors have a relatively high off-current, the transfer characteristics of low-level potentials are poor. Therefore, there is a problem that sufficient gradation cannot be obtained in low gradation (low brightness) display.

[0042] In addition, when using Si transistors in a pixel circuit, there is also a problem of low layout freedom, such as the need to increase the channel length in consideration of current magnitude control, saturation characteristics, etc.

[0043] One aspect of the present invention is a display device suitable for wide gradation display that can compensate for the disadvantages of the above-described conventional circuits and Si transistors.

[0044] In the display device of one aspect of the present invention, when performing high gradation display, transistor 103 (a p-channel Si transistor) is used as a driving transistor. When performing low gradation (low brightness) display, transistor 104 (an n-channel OS transistor) is used as a driving transistor. Further, for transistor 101, transistor 102, and transistor 105, either an Si transistor or an OS transistor may be used.

[0045] With such a configuration, it is possible to suppress the change in Vgs that occurs in high gradation display when using an n-channel transistor as a driving transistor, and improve the display quality of high gradation.

[0046] In addition, since control is performed with a relatively large current in high gradation display, it is not necessary to increase the channel length to suppress the current. That is, since a transistor with a short channel length can be used, the layout freedom increases. Further, even if an Si transistor with a relatively high off-current is used, it does not affect the display.

[0047] For the channel formation region of the Si transistor, amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used. When providing a transistor on an insulating surface such as on a glass substrate and the transistor is a p-channel type, it is preferable to use polycrystalline silicon.

[0048] High-quality polycrystalline silicon can be easily obtained by using a laser crystallization process or the like, and a transistor with high mobility can be formed even for a p-channel type. Also, high-quality polycrystalline silicon can be obtained by a solid-phase growth method in which a metal catalyst such as nickel or palladium is added to amorphous silicon and heated. Further, laser irradiation may be performed on the polycrystalline silicon formed by the solid-phase growth method using a metal catalyst to further improve the crystallinity. Since the metal catalyst remains in the polycrystalline silicon and deteriorates the electrical characteristics of the transistor, it is preferable to provide a region doped with phosphorus or a rare gas or the like outside the channel formation region and capture the metal catalyst in the region.

[0049] In low gradation display, an n-channel type transistor is used as the driving transistor. In a display with many low gradation parts, since the current flowing through the entire pixel of the display device is relatively small, the voltage drop of the common electrode connected to the cathode of the light-emitting device hardly occurs. That is, the influence of the change in Vgs described above can be ignored. Also, as the n-channel type transistor, it is preferable to use an OS transistor.

[0050] Since the OS transistor has a large energy gap of the semiconductor layer, it can exhibit an extremely low off-current characteristic of several yA / μm (current value per 1 μm channel width). Therefore, since the transmission characteristic of a lower level potential is improved compared to using an Si transistor as the driving transistor, the display quality of low gradation can be enhanced.

[0051] Also, it is preferable to use OS transistors for transistors 101 and 102 as well. Due to the low off-current characteristics of the OS transistors, the potential of the gates of the driving transistors (transistors 103 and 104) can be held for a long time. Therefore, even if the frame frequency is decreased, the image can be held. For example, in the case of displaying a moving image, the first frame frequency (e.g., 60 Hz or more) is set, and in the case of displaying a still image, the display device can be made to consume less power by switching to a second frame frequency (e.g., about 1 to 10 Hz) lower than the first frame frequency.

[0052] Note that in order to obtain the effect of one aspect of the present invention, not limited to the above-described configuration, all the transistors included in the pixel may be formed of Si transistors. Alternatively, all the transistors included in the pixel may be formed of OS transistors.

[0053] As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium or the like can be used, and for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS is suitable for transistors and the like that value reliability because the atoms constituting the crystal are stable. In addition, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors and the like that perform high-speed driving.

[0054] The OS transistor has characteristics different from those of Si transistors, such as no occurrence of impact ionization, avalanche breakdown, and short-channel effect, and a highly reliable circuit can be formed. Also, variations in electrical characteristics due to non-uniformity of crystallinity, which are problems in Si transistors, are less likely to occur in OS transistors.

[0055] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can typically be formed by a sputtering method. Alternatively, it may be formed using an ALD (Atomic Layer Deposition) method.

[0056] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn-based oxide by the sputtering method preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0057] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, still more preferably 1×10 10 / cm 3 or less, and an oxide semiconductor with a carrier density of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low defect level density and stable characteristics.

[0058] In addition to these, depending on the semiconductor characteristics and electrical characteristics (such as field-effect mobility and threshold voltage) of the transistors required, those with an appropriate composition may be used. Further, in order to obtain the semiconductor characteristics of the required transistors, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate values.

[0059] In an oxide semiconductor constituting a semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and it becomes n-type. For this reason, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0060] In addition, when an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. For this reason, the concentration of the alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0061] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and it easily becomes n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. For this reason, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably set to 5×10 18 atoms / cm 3 or less.

[0062] In addition, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, it may react with oxygen that binds to metal atoms to form water, and thus oxygen vacancies may be formed in the oxide semiconductor. When the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may have normally-on characteristics. Furthermore, defects with hydrogen incorporated into oxygen vacancies may function as donors, and electrons as carriers may be generated. Also, a part of hydrogen may bind to oxygen that binds to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0063] Defects with hydrogen incorporated into oxygen vacancies may function as donors in the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, defects may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may sometimes be paraphrased as "donor concentration".

[0064] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0065] Further, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0066] The oxide semiconductor film with an amorphous structure, for example, has a disordered atomic arrangement and no crystal component. Or, the oxide film with an amorphous structure, for example, has a completely amorphous structure and no crystal part.

[0067] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-described regions.

[0068] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0069] CAC-OS is, for example, a configuration of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Hereinafter, in the oxide semiconductor, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0070] Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may also be included.

[0071] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO.) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0).), and gallium oxide (hereinafter, GaO X3 (Let X3 be a real number greater than 0).), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).), etc., and when the materials are separated, it becomes a mosaic shape, and the mosaic-shaped InO X1 , or In X2 Zn Y2 O Z2 is in a configuration uniformly distributed in the film (hereinafter, also referred to as a cloud shape).

[0072] That is, CAC-OS is a composite oxide semiconductor having a configuration in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 , or InO X1 are mixed. In this specification, for example, when the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region, it is said that the first region has a higher In concentration than the second region.

[0073] Note that IGZO is a common name and may refer to a single compound of In, Ga, Zn, and O. As a representative example, InGaO 3 (ZnO) m1 (where m1 is a natural number), or In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number), and crystalline compounds represented thereby can be mentioned.

[0074] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

[0075] On the other hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which, in a material composition containing In, Ga, Zn, and O, a region observed as nanoparticles mainly composed of Ga in part and a region observed as nanoparticles mainly composed of In in part are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0076] Note that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga is not included.

[0077] Note that there may be cases where no clear boundary can be observed between the region where GaO X3 is the main component and the region where In X2 Zn Y2 O Z2 , or InO X1 is the main component.

[0078] In addition, when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are included instead of gallium, CAC-OS refers to a structure in which regions observed as nanoparticles mainly composed of the metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern, respectively.

[0079] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by the sputtering method, any one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used as the film-forming gas. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable to set the flow rate ratio of oxygen gas to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0080] CAC-OS has the characteristic that no distinct peak is observed when measured using an out-of-plane method θ / 2θ scan, which is one of the X-ray diffraction (XRD) measurement methods. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0081] Also, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0082] Also, for example, in CAC-OS in In-Ga-Zn oxide, regions where GaO X3 is the main component and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are unevenly distributed and mixed, and it can be confirmed that they have a structure.

[0083] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed and has properties different from those of an IGZO compound. That is, CAC-OS has regions where components such as GaO X3 are the main component and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component, and they are phase-separated from each other, and the regions with each element as the main component have a mosaic-like structure.

[0084] Here, regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are regions with higher conductivity compared to regions where components such as GaO X3 are the main component. That is, when carriers flow through regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component, conductivity as an oxide semiconductor is exhibited. Therefore, when regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are distributed in a cloud-like manner in the oxide semiconductor, high field-effect mobility (μ) can be realized.

[0085] On the other hand, regions where components such as GaO X3 are the main component are In X2 Zn Y2 O Z2 , or InOX1 is a region with higher insulation compared to the region where it is the main component. That is, the region where X3 such as is the main component is distributed in the oxide semiconductor, suppressing the leakage current and enabling a good switching operation.

[0086] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by X3 such as and the conductivity caused by X2 In Y2 Zn Z2 O X1 or InO on act complementarily to achieve a high on-current (I

[0087] Also, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0088] In high-tone display, when transistor 103 is used as a driving transistor, transistor 104 becomes a resistor. Therefore, a gate potential for making transistor 104 in a low-resistance conduction state (on state of the switch) is supplied to transistor 104. Also, in low-tone display, when transistor 104 is used as a driving transistor, transistor 103 becomes a resistor. Therefore, a gate potential for making transistor 103 in a low-resistance conduction state (on state of the switch) is supplied to transistor 103.

[0089] In this way, the pixel 10 is supplied with a data potential for display and a potential for switching. In one aspect of the present invention, a potential for switching can be generated based on the data potential supplied from the source driver using a signal generation circuit.

[0090] FIG. 3A is a diagram for explaining a signal generation circuit 40 electrically connected between the source driver 20 and the pixel 10. The signal generation circuit 40 has a circuit 40a and a circuit 40b.

[0091] Circuit 40a outputs the generated signal potential to wiring 121. That is, circuit 40a is a circuit for generating a signal potential for controlling transistor 103. Further, circuit 40b outputs the generated signal potential to wiring 122. That is, circuit 40b is a circuit for generating a signal potential for controlling transistor 104.

[0092] Circuit 40a includes buffer circuit 41a and selection circuit 45a. Buffer circuit 41a can be configured such that, for example, CMOS inverter circuits 42 as shown in FIG. 3B are connected in series in an even number of stages. CMOS inverter circuit 42 can be configured to include p-channel transistor 43p and n-channel transistor 43n. Note that in FIG. 3B, a configuration in which two CMOS inverter circuits 42 are connected in series is shown, but an even number of four or more stages may be used.

[0093] Selection circuit 45a includes inverter circuit 46a, transistor 47a, and transistor 48a. The output terminal of source driver 20 is electrically connected to one of the source or drain of transistor 47a and the input terminal of buffer circuit 41a. The output terminal of buffer circuit 41a is electrically connected to the gate of transistor 47a, one of the source or drain of transistor 48a, and the input terminal of inverter circuit 46a. The output terminal of inverter circuit 46b is electrically connected to the gate of transistor 48a. The other of the source or drain of transistor 47a and the other of the source or drain of transistor 48a are electrically connected to wiring 121.

[0094] Circuit 40b includes buffer circuit 41b and selection circuit 45b. Buffer circuit 41b can have the same configuration as buffer circuit 41a.

[0095] The selection circuit 45b includes an inverter circuit 46b, a transistor 47b, and a transistor 48b. The output terminal of the source driver 20 is electrically connected to one of the source or drain of the transistor 48b and the input terminal of the buffer circuit 41b. The output terminal of the buffer circuit 41b is electrically connected to the gate of the transistor 47b, one of the source or drain of the transistor 47b, and the input terminal of the inverter circuit 46b. The output terminal of the inverter circuit 46b is electrically connected to the gate of the transistor 48b. The other of the source or drain of the transistor 47b and the other of the source or drain of the transistor 48b are electrically connected to the wiring 122.

[0096] The signal generation circuit 40 can be formed of Si transistors. Alternatively, the p-channel transistors included in the signal generation circuit 40 may be formed of Si transistors, and the n-channel transistors may be formed of OS transistors. When the transistor 104 used in the pixel 10 is an OS transistor, by using OS transistors for the n-channel transistors of the signal generation circuit 40, the step of forming n-channel transistors with Si transistors becomes unnecessary, and the manufacturing cost can be reduced.

[0097] The potential input to the signal generation circuit 40 is the data potential output by the source driver 20, and the buffer circuits 41a and 41b have the function of binarizing the data potential. Therefore, the data potential and the potential obtained by binarizing the data potential are input to the selection circuits 45a and 45b. At this time, Table 1 shows the signal potentials output by the signal generation circuit 40 (selection circuits 45a and 45b).

[0098]

Table 1

[0099] If the output potential of the selection circuit 45a and the output potential of the selection circuit 45b with respect to the input potential of the signal generation circuit 40 are the same as those in Table 1, a circuit other than the configuration shown in FIG. 3A may be used as the signal generation circuit 40.

[0100] Here, “DataH” and “DataL” are data potentials (image data). FIG. 4A is a diagram showing the relationship between the display gradation and the output potential of the source driver 20. The output potential on the low gradation side is “DataL”, and the output potential on the high gradation side is “DataH”. In FIG. 4A, the boundary between the two is set to a gradation near the center, but the low gradation side or the high gradation side rather than the said gradation may be set as the boundary between the two.

[0101] “DataL” is the data potential input to the gate of the transistor 104 which is an n-channel type transistor. Therefore, the gradation and the output potential are in a proportional relationship, and the higher the gradation, the larger the output potential. “DataH” is the data potential input to the gate of the transistor 103 which is a p-channel type transistor. Therefore, the gradation and the output potential are in an inverse proportional relationship, and the higher the gradation, the smaller the output potential.

[0102] “DataH” output from the selection circuit 45a and “DataL” output from the selection circuit 45b are potentials equivalent to the output potential of the source driver 20.

[0103] Also, “H” is a binary high-level potential, and “L” is a binary low-level potential. FIG. 4B is a diagram showing the output characteristics of the buffer circuit 41a or the buffer circuit 41b. The input data is the data potential output by the source driver 20. When the above-mentioned “DataL” is input, the potential “L” binarized by the operation of the two-stage inverter is output. When “DataH” is input, the potential “H” binarized by the operation of the two-stage inverter is output.

[0104] The potential "L" output from the selection circuit 45a and the potential "H" output from the selection circuit 45b are the potentials obtained by binarizing the data potential output by the source driver 20 using the buffer circuit 41a or the buffer circuit 41b. Note that the magnitude relationship of "DataH", "DataL", "H", and "L" is "L" ≤ "DataL" < "DataH" ≤ "H".

[0105] FIG. 5 is a diagram showing the operations of the signal generation circuit 40 and the pixel 10 when the data potential output by the source driver 20 is "DataH" (high gradation). As shown in Table 1, when the data potential "DataH" is input from the source driver 20 to the signal generation circuit 40, the signal generation circuit 40 outputs the data potential "DataH" to the wiring 121 and outputs the potential "H" to the wiring 122.

[0106] The data potential "DataH" is input to the gate of the transistor 103 via the transistor 101, and the transistor 103 conducts a current corresponding to the data potential "DataH". The potential "H" is input to the gate of the transistor 104 via the transistor 102. At this time, since the transistor 104 is an n-channel transistor, it is in a low-resistance conduction state.

[0107] That is, the transistor 103 serves as a driving transistor for the light-emitting device 108, and the transistor 104 operates as a switch.

[0108] Here, since the transistor 104 does not operate as a driving transistor, the potential of the anode of the light-emitting device 108 changes in high-gradation display, and even if Vgs changes, it does not affect the display. Therefore, the display quality during high-gradation display can be improved.

[0109] FIG. 6 is a diagram showing the operations of the signal generation circuit 40 and the pixel 10 when the data potential output from the source driver 20 is “DataL” (low gradation). As shown in Table 1, when the data potential “DataL” is input from the source driver 20 to the signal generation circuit 40, the signal generation circuit 40 outputs a potential “L” to the wiring 121 and outputs the data potential “DataL” to the wiring 122.

[0110] The potential “L” is input to the gate of the transistor 103 via the transistor 101. At this time, since the transistor 103 is a p-channel type transistor, it is in a low-resistance conduction state. The data potential “DataL” is input to the gate of the transistor 104 via the transistor 102, and the transistor 104 flows a current corresponding to the data potential “DataL”.

[0111] That is, the transistor 103 operates as a switch, and the transistor 104 operates as a driving transistor of the light-emitting device 108.

[0112] Here, by using an OS transistor with a low off-current for the transistor 104, the gradation property in low gradation display can be enhanced. That is, in the display device according to one aspect of the present invention, the display quality can be enhanced from low gradation to high gradation.

[0113] FIG. 7 is a diagram for explaining a display device according to one aspect of the present invention. The display device includes a pixel array 11, a source driver 20, a gate driver 30, and a signal generation circuit 40. The pixel array 11 includes pixels 10 arranged in a column direction and a row direction. The pixel 10 is provided with the two driving transistors described in the present embodiment. Note that the wirings are simply illustrated, and wirings are provided that are connected to the elements included in the pixel 10 according to one aspect of the present invention described above.

[0114] For the source driver 20 and the gate driver 30, a sequential circuit such as a shift register can be used.

[0115] Note that the source driver 20 and the gate driver 30 can use a method of externally attaching an IC chip by a COF (chip on film) method, a COG (chip on glass) method, a TCP (tape carrier package) method, or the like. Alternatively, it may be formed on the same substrate as the pixel array 11 using transistors manufactured using a process common to the pixel array 11.

[0116] The gate driver 30 shows an example of being arranged on one side of the pixel array 11, but two gate drivers may be arranged to face each other via the pixel array 11 to divide the driving lines.

[0117] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0118] (Embodiment 2) In this embodiment, a configuration example of a display device using a light-emitting device will be described. Note that, in this embodiment, descriptions of the elements, operations, and functions of the display device described in Embodiment 1 are omitted.

[0119] The pixel 10 and the signal generation circuit 40 described in Embodiment 1 can be applied to the display device described in this embodiment. Note that the scanning line driving circuit described below corresponds to the gate driver, and the signal line driving circuit corresponds to the source driver.

[0120] FIGS. 8A to 8C are diagrams showing the configuration of a display device to which one aspect of the present invention can be applied.

[0121] In FIG. 8A, a sealing material 4005 is provided so as to surround a display portion 215 provided on a first substrate 4001, and the display portion 215 is sealed by the sealing material 4005 and a second substrate 4006.

[0122] In FIG. 8A, the scanning line driving circuit 221a, the signal line driving circuit 231a, the signal line driving circuit 232a, and the common line driving circuit 241a each have a plurality of integrated circuits 4042 provided on a printed circuit board 4041. The integrated circuit 4042 is formed of a single crystal semiconductor or a polycrystalline semiconductor. The common line driving circuit 241a has a function of supplying a specified potential to wirings 123, 124, 129, etc. shown in Embodiment 1.

[0123] Various signals and potentials supplied to the scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal line driving circuit 232a are supplied via an FPC (Flexible printed circuit) 4018.

[0124] The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have a function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0125] Note that the connection method of the integrated circuit 4042 is not particularly limited, and a wire bonding method, a COF method, a COG method, a TCP method, etc. can be used.

[0126] FIG. 8B shows an example in which the integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a are mounted by the COG method. Also, a part or all of the driving circuit can be integrally formed on the same substrate as the display unit 215 to form a system on panel.

[0127] In FIG. 8B, an example in which the scanning line driving circuit 221a and the common line driving circuit 241a are formed on the same substrate as the display unit 215 is shown. By forming the driving circuit simultaneously with the pixel circuit in the display unit 215, the number of components can be reduced. Therefore, productivity can be improved.

[0128] Also, in FIG. 8B, a sealing material 4005 is provided so as to surround a display unit 215 provided on a first substrate 4001, a scanning line driving circuit 221a, and a common line driving circuit 241a. A second substrate 4006 is provided on the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a. Therefore, the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a are sealed together with the display device by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0129] Also, in FIG. 8B, an example is shown in which a signal line driving circuit 231a and a signal line driving circuit 232a are separately formed and mounted on a first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. Further, as shown in FIG. 8C, the signal line driving circuit 231a and the signal line driving circuit 232a may be formed on the same substrate as the display unit 215.

[0130] Further, the display device may include a panel in a state where the display device is sealed, and a module in a state where an IC or the like including a controller is mounted on the panel.

[0131] Also, the display unit and the scanning line driving circuit provided on the first substrate have a plurality of transistors. As the transistor, the Si transistor or the OS transistor shown in Embodiment 1 can be applied.

[0132] The structures of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. All the transistors included in the peripheral driving circuit may have the same structure, or may have two or more types of transistor structures. Similarly, all the transistors included in the pixel circuit may have the same structure, or may have two or more types of transistor structures.

[0133] Further, an input device 4200 can be provided on the second substrate 4006. The configuration in which the input device 4200 is provided in the display device shown in FIGS. 8A to 8C can function as a touch panel.

[0134] There is no limitation on the detection device (also referred to as a sensor element) included in the touch panel according to one aspect of the present invention. Various sensors capable of detecting the proximity or contact of a detected object such as a finger or a stylus can be applied as the detection device.

[0135] As the sensor method, for example, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure sensitive method can be used.

[0136] In the present embodiment, a touch panel having a capacitance type detection device will be described as an example.

[0137] As the capacitance method, there are a surface capacitance method, a projected capacitance method, etc. Further, as the projected capacitance method, there are a self-capacitance method, a mutual-capacitance method, etc. Using the mutual-capacitance method is preferable because simultaneous multi-point detection is possible.

[0138] The touch panel according to one aspect of the present invention can adopt various configurations, such as a configuration in which a separately manufactured display device and a detection device are bonded together, and a configuration in which electrodes constituting the detection device are provided on one or both of the substrate supporting the display device and the counter substrate.

[0139] FIGS. 9A and 9B show an example of a touch panel. FIG. 9A is a perspective view of the touch panel 4210. FIG. 9B is a schematic perspective view of the input device 4200. For clarity, only representative components are shown.

[0140] The touch panel 4210 has a configuration in which a separately manufactured display device and a detection device are bonded together.

[0141] The touch panel 4210 has an input device 4200 and a display device, and these are provided in an overlapping manner.

[0142] The input device 4200 has a substrate 4263, electrodes 4227, 4228, a plurality of wirings 4237, 4238, and 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or 4239. Also, the electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b is electrically connected to each of the plurality of wirings 4237 and 4238. An IC 4273b can be provided on the FPC 4272b.

[0143] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, in addition to a capacitive touch sensor, an optical touch sensor using a photoelectric conversion element may be applied.

[0144] FIG. 10 is a cross-sectional view of the portion indicated by the chain line N1-N2 in FIG. 8B. FIG. 10 is an example of a display device using a light-emitting device as a display device. The display device has an electrode 4015, and the electrode 4015 is electrically connected via an anisotropic conductive layer 4019 to the terminal of the FPC 4018. Also, in FIG. 10, the electrode 4015 is electrically connected to the wiring 4014 at the openings formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0145] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed from the same conductive layer as the source electrodes and drain electrodes of the transistors 4010 and 4011.

[0146] In addition, the display unit 215 and the scanning line driving circuit 221a provided on the first substrate 4001 have a plurality of transistors, and the transistors 4010 included in the display unit 215 and the transistors 4011 included in the scanning line driving circuit 221a are exemplified. In FIG. 10, bottom gate type transistors are exemplified as the transistors 4010 and 4011, but top gate type transistors may also be used.

[0147] An insulating layer 4112 is provided on the transistors 4010 and 4011. In addition, a partition wall 4510 is formed on the insulating layer 4112.

[0148] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030, and to form the side surface of the opening to be an inclined surface formed with a continuous curvature.

[0149] In addition, the transistors 4010 and 4011 are provided on the insulating layer 4102. The transistors 4010 and 4011 also have an electrode 4017 formed on the insulating layer 4111. The electrode 4017 can function as a back gate electrode.

[0150] In addition, the display device has a capacitor 4020. An example is shown in which the capacitor 4020 has an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, an insulating layer 4103, and an electrode formed in the same process as the source electrode and the drain electrode. The configuration of the capacitor 4020 is not limited to this, and it may be formed of other conductive layers and insulating layers.

[0151] In addition, the display device has an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer that hardly transmits impurity elements is used. By sandwiching the semiconductor layer of the transistor with the insulating layer 4111 and the insulating layer 4104, intrusion of impurities from the outside can be prevented.

[0152] The transistor 4010 provided in the display unit 215 is electrically connected to the display device. As the display device, a light-emitting device can be used. As the light-emitting device, for example, an EL device utilizing electroluminescence can be applied. The EL device has a layer containing a light-emitting compound (also referred to as an "EL layer") between a pair of electrodes. When a potential difference greater than the threshold voltage of the EL device is generated between the pair of electrodes, holes are injected from the anode side into the EL layer, and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting compound contained in the EL layer emits light.

[0153] As the EL device, for example, an organic EL device or an inorganic EL device can be used. Note that an LED (including a micro LED) using a compound semiconductor as a light-emitting material is also one type of EL element, and an LED can also be used.

[0154] In addition to the light-emitting compound, the EL layer may have a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, a substance with high electron injection property, or a bipolar substance (a substance with high electron transport property and high hole transport property).

[0155] The EL layer can be formed by methods such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, etc.

[0156] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their element structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission using a donor level and an acceptor level. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission using inner-shell electron transition of metal ions. Here, an organic EL device is used for explanation as the light-emitting device.

[0157] For the light-emitting device, at least one of a pair of electrodes may be transparent in order to extract light. Then, a transistor and a light-emitting device are formed on a substrate, and there are a top emission structure for extracting light from the surface opposite to the substrate, a bottom emission structure for extracting light from the surface on the substrate side, and a dual emission structure for extracting light from both surfaces. Any light-emitting device with any emission structure can be applied.

[0158] Also, if necessary, optical members (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided.

[0159] Examples of materials that can be used as the light-shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing a solid solution of multiple metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. Also, a laminated film of a film containing the material of the colored layer can be used for the light-shielding layer. For example, a laminated structure of a film containing the material used for a colored layer that transmits light of a certain color and a film containing the material used for a colored layer that transmits light of another color can be used. It is preferable to share the materials of the colored layer and the light-shielding layer because the device can be shared and the process can be simplified.

[0160] Examples of materials that can be used for the colored layer include metal materials, resin materials, and resin materials containing pigments or dyes. The light-shielding layer and the colored layer can be formed, for example, using an inkjet method.

[0161] The light-emitting device 4513, which is a display device, is electrically connected to the transistor 4010 provided in the display unit 215. The structure of the light-emitting device 4513 is a laminated structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, but is not limited to this structure. The structure of the light-emitting device 4513 can be appropriately changed according to the direction of light extracted from the light-emitting device 4513 and so on.

[0162] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers stacked on each other.

[0163] The emission color of the light-emitting device 4513 can be white, red, green, blue, cyan, magenta, yellow, etc. depending on the material constituting the light-emitting layer 4511.

[0164] As a method for realizing color display, there are a method of combining a light-emitting device 4513 having a white emission color with a coloring layer, and a method of providing light-emitting devices 4513 having different emission colors for each pixel. The former method has higher productivity than the latter method. On the other hand, in the latter method, since it is necessary to separately produce the light-emitting layer 4511 for each pixel, the productivity is inferior to the former method. However, in the latter method, an emission color with higher color purity can be obtained than in the former method. In addition to the latter method, the color purity can be further enhanced by imparting a microcavity structure to the light-emitting device 4513.

[0165] Note that the light-emitting layer 4511 may contain an inorganic compound such as quantum dots. For example, by using quantum dots in the light-emitting layer, it can also function as a light-emitting material.

[0166] A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting device 4513. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), etc. can be formed. Further, a filling material 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. In this way, it is preferable to package (encase) with a highly airtight and low outgassing protective film (laminated film, ultraviolet curable resin film, etc.) or cover material so as not to be exposed to the outside air.

[0167] As the filling material 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), an acrylic resin, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. Further, the filling material 4514 may contain a desiccant.

[0168] As the sealing material 4005, a glass material such as glass frit, a curable resin that cures at room temperature such as a two-component mixed resin, a resin material such as a photocurable resin or a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.

[0169] Further, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light emitting surface of the light emitting device. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and can reduce reflection can be performed.

[0170] Further, by forming the light emitting device into a microcavity structure, light with high color purity can be extracted. Further, by combining the microcavity structure and the color filter, reflection can be reduced and the visibility of the display image can be improved.

[0171] In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display device, the light transmittance and reflectivity may be selected according to the direction of the light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

[0172] The first electrode layer 4030 and the second electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide.

[0173] Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or their alloys, or their metal nitrides.

[0174] Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or their derivatives composed of two or more of aniline, pyrrole, and thiophene can be mentioned.

[0175] Further, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0176] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0177] (Embodiment 3) In this embodiment, an example of a transistor that can be used in place of each transistor shown in the above embodiment will be described with reference to the drawings.

[0178] The display device according to one aspect of the present invention can be manufactured using various types of transistors such as bottom-gate type transistors or top-gate type transistors. Therefore, according to the existing manufacturing line, the material of the semiconductor layer and the transistor structure to be used can be easily replaced.

[0179] 〔Bottom-gate type transistor〕 FIG. 11A is a cross-sectional view in the channel length direction of a channel protection type transistor 810 which is a kind of bottom-gate type transistor. In FIG. 11A, the transistor 810 is formed on a substrate 771. Further, the transistor 810 has an electrode 746 on the substrate 771 via an insulating layer 772. Further, the transistor 810 has a semiconductor layer 742 on the electrode 746 via an insulating layer 726. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

[0180] Further, the transistor 810 has an insulating layer 741 on the channel formation region of the semiconductor layer 742. Further, in contact with a part of the semiconductor layer 742, the transistor 810 has an electrode 744a and an electrode 744b on the insulating layer 726. The electrode 744a can function as one of a source electrode or a drain electrode. The electrode 744b can function as the other of a source electrode or a drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741.

[0181] The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 741 on the channel formation region, it is possible to prevent the exposure of the semiconductor layer 742 that occurs when the electrodes 744a and 744b are formed. Therefore, it is possible to prevent the channel formation region of the semiconductor layer 742 from being etched when the electrodes 744a and 744b are formed.

[0182] Further, the transistor 810 has an insulating layer 728 on the electrodes 744a, 744b and the insulating layer 741, and has an insulating layer 729 on the insulating layer 728.

[0183] When an oxide semiconductor is used for the semiconductor layer 742, it is preferable to use a material capable of depriving at least a portion of the semiconductor layer 742 in contact with the electrodes 744a and 744b of oxygen and causing oxygen deficiency. The region where oxygen deficiency occurs in the semiconductor layer 742 has an increased carrier concentration, and the region becomes n-type, becoming an n-type region (n + -type region). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, examples of the material capable of depriving the semiconductor layer 742 of oxygen and causing oxygen deficiency include tungsten, titanium, and the like.

[0184] By forming source and drain regions in the semiconductor layer 742, the contact resistance between the electrodes 744a and 744b and the semiconductor layer 742 can be reduced. Thus, electrical characteristics of the transistor, such as field-effect mobility and threshold voltage, can be made good.

[0185] When a semiconductor such as silicon is used for the semiconductor layer 742, it is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of the transistor.

[0186] The insulating layer 729 is preferably formed using a material having a function of preventing or reducing the diffusion of impurities from the outside into the transistor. Note that the insulating layer 729 can be omitted as necessary.

[0187] An electrode 723 that can function as a back gate electrode is provided over the insulating layer 729. The electrode 723 can be formed by the same material and method as the electrode 746. Note that a configuration without providing the electrode 723 may also be used.

[0188] Generally, the back gate electrode is formed of a conductive layer and is arranged so as to sandwich the channel formation region of the semiconductor layer between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be a ground potential (GND potential) or an arbitrary potential. Further, by changing the potential of the back gate electrode independently without linking it to the potential of the gate electrode, the threshold voltage of the transistor can be changed.

[0189] Both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each function as a gate insulating layer. Note that the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

[0190] When one of the electrode 746 or the electrode 723 is referred to as the "gate electrode", the other is referred to as the "back gate electrode". For example, in the transistor 810, when the electrode 723 is referred to as the "gate electrode", the electrode 746 is referred to as the "back gate electrode". Further, when the electrode 723 is used as the "gate electrode", the transistor 810 can be considered as a type of top gate transistor. Also, in some cases, one of the electrode 746 and the electrode 723 is referred to as the "first gate electrode" and the other is referred to as the "second gate electrode".

[0191] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, and further by setting the electrode 746 and the electrode 723 to the same potential, the region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction, so that the amount of carrier movement increases. As a result, the on-current of the transistor 810 increases and the field-effect mobility becomes higher.

[0192] Therefore, the transistor 810 is a transistor having a large on-current with respect to the occupied area. That is, the occupied area of the transistor 810 can be reduced with respect to the required on-current.

[0193] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed (particularly, an electric field shielding function against static electricity and the like). Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced.

[0194] Further, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, it is possible to prevent light deterioration of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor.

[0195] FIG. 11B is a cross-sectional view of a channel protection type transistor 820 having a configuration different from that of FIG. 11A in the channel length direction. The transistor 820 has substantially the same structure as the transistor 810, but is different in that the insulating layer 741 covers the end portion of the semiconductor layer 742. Also, in an opening formed by selectively removing a part of the insulating layer 741 overlapping with the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a are electrically connected. Also, in another opening formed by selectively removing a part of the insulating layer 741 overlapping with the semiconductor layer 742, the semiconductor layer 742 and the electrode 744b are electrically connected. The region of the insulating layer 741 overlapping with the channel formation region can function as a channel protection layer.

[0196] By providing the insulating layer 741, it is possible to prevent the exposure of the semiconductor layer 742 that occurs when the electrodes 744a and 744b are formed. Therefore, it is possible to prevent thinning of the semiconductor layer 742 when the electrodes 744a and 744b are formed.

[0197] In addition, the distance between the electrode 744a and the electrode 746, and the distance between the electrode 744b and the electrode 746 are longer in the transistor 820 than in the transistor 810. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced.

[0198] FIG. 11C is a cross-sectional view of the channel length direction of a channel etching type transistor 825 which is one of the bottom gate type transistors. The transistor 825 forms the electrodes 744a and 744b without using the insulating layer 741. Therefore, a part of the semiconductor layer 742 exposed during the formation of the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be increased.

[0199] 〔Top Gate Type Transistor〕 The transistor 842 illustrated in FIG. 12A is one of the top gate type transistors. The electrodes 744a and 744b are electrically connected to the semiconductor layer 742 at the openings formed in the insulating layer 728 and the insulating layer 729.

[0200] Also, by removing a part of the insulating layer 726 that does not overlap with the electrode 746 and introducing impurities into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, an impurity region can be formed self-alignedly in the semiconductor layer 742. The transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region where impurities are introduced through the insulating layer 726 of the semiconductor layer 742 is smaller than the impurity concentration in the region where impurities are introduced without passing through the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that overlaps with the insulating layer 726 and does not overlap with the electrode 746.

[0201] Further, the transistor 842 has an electrode 723 formed on the substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 via the insulating layer 772. The electrode 723 can function as a back gate electrode. Note that a configuration without providing the electrode 723 may be employed.

[0202] Also, as in the transistor 844 shown in FIG. 12B, all of the insulating layer 726 in a region not overlapping with the electrode 746 may be removed. Further, as in the transistor 846 shown in FIG. 12C, the insulating layer 726 may be left.

[0203] FIG. 13A shows a cross-sectional view of the transistor 810 in the channel width direction, and FIG. 13B shows a cross-sectional view of the transistor 842 in the channel width direction.

[0204] In the structures shown in FIGS. 13A and 13B, the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode are the same. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0205] The length of each of the gate electrode and the back gate electrode in the channel width direction is longer than the length of the semiconductor layer 742 in the channel width direction, and the entire semiconductor layer 742 in the channel width direction is covered with the gate electrode or the back gate electrode with each insulating layer interposed therebetween.

[0206] With this configuration, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the back gate electrode.

[0207] In this way, the device structure of a transistor that electrically surrounds the semiconductor layer 742 in which a channel formation region is formed by the electric fields of the gate electrode and the back gate electrode can be called a Surrounded channel (S-channel) structure.

[0208] By adopting an S-channel structure, an electric field for inducing a channel by one or both of the gate electrode and the back gate electrode can be effectively applied to the semiconductor layer 742, thereby improving the current driving ability of the transistor and enabling high on-current characteristics. Further, since the on-current can be increased, the transistor can be miniaturized. Also, by adopting an S-channel structure, the mechanical strength of the transistor can be enhanced.

[0209] Note that the gate electrode and the back gate electrode may not be connected and different potentials may be supplied to each of them. For example, by supplying a constant potential to the back gate electrode, the threshold voltage of the transistor can be controlled.

[0210] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and examples.

[0211] (Embodiment 4) As electronic devices that can use the display device according to one aspect of the present invention, there can be mentioned display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS. 14A to 14F.

[0212] FIG. 14A shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom lever 968, a lens 969, and the like. The display device according to one aspect of the present invention can be used for the display unit 965.

[0213] FIG. 14B is a mobile data terminal, which includes a housing 911, a display unit 912, a speaker 913, operation buttons 914, a camera 919, etc. Information can be input and output by the touch panel function of the display unit 912. The display device according to one aspect of the present invention can be used for the display unit 912.

[0214] FIG. 14C is a mobile phone, which includes a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone is provided with a touch sensor on the display unit 952. Any operation such as making a call or inputting characters can be performed by touching the display unit 952 with a finger or a stylus. Further, the housing 951 and the display unit 952 are flexible and can be bent and used as shown in the figure. The display device according to one aspect of the present invention can be used for the display unit 952.

[0215] FIG. 14D is a drive recorder, which includes a housing 931, a display unit 932, operation buttons 933, a microphone 934, a lens 935, mounting parts 936, etc. By fixing it to the front window of an automobile via the mounting parts 936, the scenery in front during driving can be recorded. The recorded image can be shown on the display unit 932. The display device according to one aspect of the present invention can be applied to the display unit 932.

[0216] FIG. 14E is a television, which includes a housing 971, a display unit 973, operation buttons 974, a speaker 975, a communication connection terminal 976, a light sensor 977, etc. A touch sensor is provided on the display unit 973, and input operations can also be performed. The display device according to one aspect of the present invention can be used for the display unit 973.

[0217] FIG. 14F is a digital signage, which has a large display unit 922. For the digital signage, for example, a large display unit 922 is attached to the side surface of a pillar 921. The display device according to one aspect of the present invention can be used for the display unit 922.

[0218] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

Explanation of Signs

[0219] 10: Pixel, 11: Pixel array, 20: Source driver, 30: Gate driver, 40: Signal generation circuit, 40a: Circuit, 40b: Circuit, 41a: Buffer circuit, 41b: Buffer circuit, 42: CMOS inverter circuit, 43n: n-channel transistor, 43p: p-channel transistor, 45a: Selection circuit, 45b: Selection circuit, 46a: Inverter circuit, 46b: Inverter circuit, 47a: Transistor, 47b: Transistor, 48a: Transistor, 48b: Transistor, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Capacitor, 107: Capacitor, 108: Light-emitting device, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 129: Wiring, 215: Display unit, 221a: Scanning line driving circuit, 231a: Signal line driving circuit, 232a: Signal line driving circuit, 241a: Common line driving circuit, 301: Transistor, 302: Transistor, 303: Transistor, 304: Transistor, 305: Transistor, 306: Capacitor, 307: Capacitor, 308: Light-emitting device, 309: Light-emitting device, 323: Power supply line, 723: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 771: Substrate, 772: Insulating layer, 810: Transistor, 820: Transistor, 825: Transistor, 842: Transistor, 844: Transistor, 846: Transistor, 911: Housing, 912: Display unit, 913: Speaker, 914: Operation button, 919: Camera, 921: Column, 922: Display unit, 931: Housing, 932: Display unit, 933: Operation button, 934: Microphone, 935: Lens, 936: Component, 951: Housing, 952: Display unit, 953: Operation button, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display unit, 966: Operation key, 967: Speaker, 968: Zoom lever, 969: Lens, 971: Housing, 973: Display unit, 974: Operation button, 975: Speaker, 976: Communication connection terminal, 977: Optical sensor, 4001: Substrate, 4005: Sealing material, 4006: Substrate,4010: Transistor, 4011: Transistor, 4014: Wiring, 4015: Electrode, 4017: Electrode, 4018: FPC, 4019: Anisotropic Conductive Layer, 4020: Capacitor, 4021: Electrode, 4030: Electrode Layer, 4031: Electrode Layer, 4041: Printed Circuit Board, 4042: Integrated Circuit, 4102: Insulating Layer, 4103: Insulating Layer, 4104: Insulating Layer, 4110: Insulating Layer, 4111: Insulating Layer, 4112: Insulating Layer, 4200: Input Device, 4210: Touch Panel, 4227: Electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC, 4273b: IC, 4510: Partition Wall, 4511: Light Emitting Layer, 4513: Light Emitting Device, 4514: Filling Material

Claims

1. A display device having, in a pixel, first to fifth transistors, first to fourth wirings, a first gate line, a second gate line, and a light-emitting device, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to the first wiring serving as a power supply line; the other of the source and the drain of the second transistor is electrically connected to an anode of the light-emitting device; a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor; the first transistor is a p-channel type; the second transistor is an n-channel type; the other of the source or the drain of the third transistor is electrically connected to the second wiring serving as a first signal line, and a gate of the third transistor is electrically connected to the first gate line; the other of the source or the drain of the fourth transistor is electrically connected to the third wiring serving as a second signal line, and a gate of the fourth transistor is electrically connected to the first gate line; one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring having a function of supplying a first potential; a gate of the fifth transistor is electrically connected to the second gate line.

2. The display device according to claim 1, wherein the first transistor has silicon in a channel formation region; the second transistor has a metal oxide in a channel formation region; the metal oxide has In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

3. The display device according to claim 1 or 2, wherein each of the third transistor, the fourth transistor, and the fifth transistor has a metal oxide in a channel formation region. The display device having the metal oxide includes In, Zn, and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

4. In any one of Claims 1 to 3, having a first circuit, the first circuit has a function of outputting a first data potential and a second data potential, one of the first data potential or the second data potential is equivalent to the input potential to the first circuit, the other of the first data potential or the second data potential is a potential obtained by binarizing the input potential, one of the first data potential or the second data potential is input to the gate of the first transistor via the third transistor, the other of the first data potential or the second data potential is input to the gate of the second transistor via the fourth transistor.

5. In Claim 4, the first circuit has a CMOS inverter circuit having a p-channel transistor having silicon in the channel formation region and an n-channel transistor having a metal oxide in the channel formation region, the metal oxide includes In, Zn, and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

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