Adjustment of Voltage Set Point in Pulse RF Signal for Adjustable Edge Shear System

Abstract

1. A method for adjusting a voltage set point for a multi-state pulsed RF signal in a plasma processing system, the method including: applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first multi-state pulsed RF signal; applying RF power from a second generator to an edge electrode surrounding the ESC and disposed below an edge ring surrounding the ESC, wherein the RF power from the second generator defines a second multi-state pulsed RF signal having a first state and a second state, wherein for each state of the second multi-state pulsed RF signal, the second generator automatically introduces a phase adjustment to substantially match the phase to a corresponding state of the first multi-state pulsed RF signal; and adjusting a voltage set point for the second state of the second multi-state pulsed RF signal to adjust the phase adjustment to a target phase adjustment setting.

Description

Technical Field

[0001] The present disclosure relates to the fabrication of semiconductor devices.

Background Art

[0002] In the manufacture of semiconductor devices on a semiconductor wafer, a plasma etching process is often used. In the plasma etching process, a semiconductor wafer including the semiconductor device being manufactured is exposed to a plasma generated within a plasma processing volume. The plasma interacts with the materials on the semiconductor wafer, whereby the materials are removed from the semiconductor wafer and / or the materials are changed so that they can then be removed from the semiconductor wafer. The plasma can be generated using a specific reaction gas, and the reaction gas causes the components of the plasma to interact with the materials to be removed / modified from the semiconductor wafer and does not significantly interact with other materials on the wafer that should not be removed / modified. The plasma is generated using a high-frequency signal that energizes a specific reaction gas. These high-frequency signals are transmitted through the plasma processing volume containing the reaction gas while the semiconductor wafer is exposed to the plasma processing volume. The transmission path of the high-frequency signal through the plasma processing volume can affect the form in which the plasma is generated within the plasma processing volume. For example, in the region of the plasma processing volume where more high-frequency signal power is transmitted, more energy may be imparted to the reaction gas, thereby causing spatial non-uniformity of plasma characteristics across the plasma processing volume. The spatial non-uniformity of plasma characteristics can appear, among other plasma characteristics, as spatial non-uniformity of ion density, ion energy, and / or reactive component density. The spatial non-uniformity of plasma characteristics can, accordingly, cause spatial non-uniformity of plasma processing results on the semiconductor wafer. Therefore, the form in which the high-frequency signal is transmitted through the plasma processing volume can affect the uniformity of plasma processing results on the semiconductor wafer. The present disclosure arises in this situation.

SUMMARY OF THE INVENTION

[0003] Broadly speaking, embodiments of the present disclosure provide a method and system for adjusting the voltage setpoint of a secondary state of a pulsed RF signal in an adjustable edge sheath (TES) system, where the edge electrode is powered independently and separately from the main electrode of the electrostatic chuck (ESC).

[0004] In some implementations, a method for adjusting a voltage setpoint for a multi-state pulsed RF signal in a plasma processing system is provided. The method includes applying RF power from a first generator to an ESC, where the RF power from the first generator defines a first multi-state pulsed RF signal, and applying RF power from a second generator to an edge electrode disposed below an edge ring surrounding the ESC and surrounding the ESC, where the RF power from the second generator defines a second multi-state pulsed RF signal having a first state and a second state, and for each state of the second multi-state pulsed RF signal, the second generator automatically introduces a phase adjustment to substantially align the phase with the corresponding state of the first multi-state pulsed RF signal, and adjusting the voltage setpoint for the second state of the second multi-state pulsed RF signal to adjust the phase adjustment to a target phase adjustment setting.

[0005] In some implementations, the target phase adjustment setting is captured via a user interface.

[0006] In some implementations, the target phase adjustment setting is calculated based on a model.

[0007] In some implementations, the target phase adjustment setting defines a predetermined amount of phase adjustment used when the phase of the RF power from the second generator is adjusted.

[0008] In some implementations, adjusting the voltage setpoint to adjust the phase adjustment includes performing a stepwise adjustment of the voltage setpoint until the phase adjustment reaches the target phase adjustment setting.

[0009] In some embodiments, the stepwise adjustment is based on a specific voltage set point associated with the first state of the second multi-state pulse RF signal.

[0010] In some embodiments, when the phase adjustment reaches the target phase adjustment setting or when the phase adjustment is within a predetermined range of the target phase adjustment setting, the phase adjustment is adjusted to the target phase adjustment setting.

[0011] In some embodiments, by adjusting the voltage set point to adjust the phase adjustment to the target phase adjustment setting, the voltage set point is located in the middle portion of the allowable range of the voltage set point.

[0012] In some embodiments, the target phase adjustment setting that facilitates the voltage set point being located in the middle portion of the allowable range of the voltage set point remains substantially the same with respect to changes in the capacitance of the matching circuit through which the RF power from the second generator is applied to the edge electrode.

[0013] In some embodiments, the change in the capacitance of the matching circuit responds to a change in the voltage set point of the first state of the second multi-state pulse RF signal.

[0014] In some embodiments, the change in the voltage set point of the first state is generated based on the usage amount of the edge ring.

[0015] In some embodiments, the usage amount of the edge ring is defined as the amount of time of RF exposure of the edge ring.

[0016] In some embodiments, a method for adjusting a voltage set point for a multi-state pulsed RF signal in a plasma processing system is provided. The method includes applying RF power from a first generator to an ESC, where the RF power from the first generator defines a first pulsed RF signal having a first state and a second state, and applying RF power from a second generator to an edge electrode disposed below an edge ring surrounding the ESC and surrounding the ESC, where the RF power from the second generator defines a second pulsed RF signal having a first state and a second state, and the second generator automatically introduces a first phase adjustment that substantially aligns the phase of the first state of the second pulsed RF signal with the first state of the first pulsed RF signal, and the second generator automatically introduces a second phase adjustment that substantially aligns the phase of the second state of the second pulsed RF signal with the second state of the first pulsed RF signal, and the second phase adjustment is adjusted to a target phase adjustment setting, and in response to detecting a change in the second phase adjustment away from the target phase adjustment setting, adjusting a voltage set point for the second state of the second pulsed RF signal to return the second phase adjustment to the target phase adjustment setting.

[0017] In some embodiments, the target phase adjustment setting is captured via a user interface.

[0018] In some embodiments, the target phase adjustment setting is calculated based on a model.

[0019] In some embodiments, the target phase adjustment setting defines a predetermined amount of phase adjustment used when the phase of the second state of the second pulsed RF signal is adjusted.

[0020] In some embodiments, adjusting the voltage set point to return the second phase adjustment includes performing a stepwise adjustment to the voltage set point until the second phase adjustment reaches the target phase adjustment setting.

[0021] In some embodiments, the stepwise adjustment is based on a specific voltage set point associated with the first state.

[0022] In some embodiments, when the second phase adjustment reaches the target phase adjustment setting or when the second phase adjustment is within a predetermined range of the target phase adjustment setting, the second phase adjustment is reset to the target phase adjustment setting.

[0023] In some embodiments, by adjusting the voltage setpoint to reset the second phase adjustment to the target phase adjustment setting, the voltage setpoint is positioned in the middle portion of the allowable range of the voltage setpoint.

[0024] In some embodiments, the target phase adjustment setting that facilitates the voltage setpoint being positioned in the middle portion of the allowable range of the voltage setpoint remains substantially the same with respect to changes in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode.

[0025] In some embodiments, the change in the capacitance of the matching circuit responds to the change in the voltage setpoint of the first state of the second pulsed RF signal.

[0026] In some embodiments, the change in the voltage setpoint of the first state of the second pulsed RF signal occurs based on the usage amount of the edge ring.

[0027] In some embodiments, the usage amount of the edge ring is defined as the amount of time of RF exposure of the edge ring.

Brief Description of the Drawings

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[0038] The following description sets forth numerous specific details in order to provide an understanding of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that some or all of these specific details may not be necessary to practice the present disclosure. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0039] In a plasma etching system for semiconductor wafers, spatial variations in etching results across the entire semiconductor wafer can be characterized by radial etching uniformity and azimuthal etching uniformity. Radial etching uniformity can be characterized by variations in etching rate as a function of radial position on the semiconductor wafer, extending outward from the center of the semiconductor wafer to the edge of the semiconductor wafer at a given azimuthal position on the semiconductor wafer. And azimuthal etching uniformity can be characterized by variations in etching rate as a function of azimuthal position on the semiconductor wafer around the center of the semiconductor wafer at a given radial position on the semiconductor wafer. In some plasma processing systems, such as the systems described herein, the semiconductor wafer is disposed on an electrode, and a high-frequency signal is radiated from the electrode to generate a plasma within a plasma generation region above the semiconductor wafer, and the plasma has controlled characteristics to cause a defined etching process on the semiconductor wafer.

[0040] Advances in two-state RF pulse application enable high aspect ratio etching by improving the relationship between process margin and etch selectivity, profile bow, critical dimension (CD), and etch rate uniformity. In the current two-state RF pulse nomenclature, "state 1" (or "S1") represents a state of high bias and source power, e.g., 1 kW, with ion energy above 3 keV and operating at a pressure below 30 mTorr to obtain a narrow IADF. The other state in the pulse, referred to as "state 0" (or "S0"), represents a deposition step with low bias and source power, e.g., less than 1 kW, and ion energy less than 100 eV. State 0 mainly provides passivation due to different mechanisms such as direct ion deposition and ion-activated neutral deposition. A typical pulse repetition rate for operating this two-state RF pulse regime is about 100 Hz to 2 kHz.

[0041] To date, current state-of-the-art dielectric etch processes rely on the implementation of one or two RF regimes supported by on / off RF pulse application or level-level RF pulse application to combine the benefits of high vertical etch rate and sufficient sidewall passivation.

[0042] However, according to embodiments of the present disclosure, additional regimes can independently recover or add more margin in the process. Embodiments based on such regimes can incorporate suitable intermediate states based on the implementation of a multi-state RF pulse application scheme that overcomes the basic process development limits and barriers in existing etching technologies. The intermediate state is based on the selective trimming of the mask neck polymer in a low ion energy state to facilitate a more aggressive high energy state (on / high state) and a passivation state (off / low state) that is more prone to polymer formation. Introducing such a low ion energy state by source power only serves to control the neck / mask shape. Combining this approach with on-off pulse application instead of level-by-level pulse application causes more polymer deposition on top of the mask, passivates the top of the mask, and controls the mask etching rate. This approach fundamentally enables breaking the trade-off between the mask neck / process margin and the selectivity ratio.

[0043] The pulsed RF cycle can be characterized as a three-level pulsed RF using three different states of RF. In some embodiments, S1 is configured to supply high source power and high bias power. This results in high aspect ratio (HAR) etching but also results in sputtering of the mask and the formation of a neck. S0 is configured as a low / off state where the applied source power or bias power is low / absent. S0 causes more neutral deposition on top to protect the mask. In some embodiments, S0 is configured to provide direct ion deposition and ion-assisted neutral deposition.

[0044] In some embodiments, the intermediate state S2 (state 2) is configured as a state of only (substantially) source power (e.g., 60 MHz, high frequency) using low source power and very low or zero (or substantially zero) bias power. S2 causes dissociation and helps to open the neck by etching, whatever neck is formed. Therefore, state S2 is configured to open the neck.

[0045] In summary, according to embodiments of the present disclosure, S1 uses high energy ions that form a neck, S2 opens the neck, and S0 provides passivation. The resulting feature has an open neck and further has more masks due to increased passivation. This poses a trade-off problem between the neck and selectivity.

[0046] In contrast, in a level-by-level RF pulse application regime where only S1 and S0 are activated, there may be not only extremely large passivation but also necks, which tend to cause clogging. However, with three-level RF pulse application using S1, S0, and S2, an open neck and passivation are provided, thereby breaking the trade-off between selectivity and cap margin. Generally speaking, state S0 provides selectivity, while state S2 improves the cap margin.

[0047] Generally speaking, in some embodiments, the frequency of the bias power is less than about 10 MHz. In some embodiments, the frequency of the bias power is about 400 kHz.

[0048] In some embodiments, the frequency of the source power is greater than about 10 MHz. In some embodiments, the frequency of the source power is greater than about 20 MHz. In some embodiments, the frequency of the source power is about 60 MHz.

[0049] The above-described states S1, S0, and S2 have been discussed with respect to the RF power applied to the main electrode of the ESC. However, in a plasma processing system implementing an adjustable edge sheath (TES) system, bias RF power is independently supplied to an edge electrode surrounding the ESC, thereby enabling control of the plasma sheath and plasma characteristics in the edge region of the wafer. The RF power applied to the edge electrode is synchronized with the main electrode, and thus, although the corresponding states S1, S0, and S2 are also included, the attributes of these states in the TES RF signal are controlled independently of the main bias RF signal.

[0050] FIG. 1 shows a vertical cross-sectional view of a portion of a plasma processing system 100 for use in semiconductor chip manufacturing according to some embodiments. The plasma processing system 100 includes an electrode 109, which is formed of aluminum in some embodiments. A ceramic layer 110 is formed on the upper surface of the electrode 109. The ceramic layer 110 is configured to receive and support the wafer W while a plasma processing operation is being performed on the wafer W. In some implementations, the ceramic layer 110, the electrode 109, and associated components define an electrostatic chuck (ESC).

[0051] A first high-frequency signal generator 147 (e.g., about 60 MHz) and a second high-frequency signal generator 149 (e.g., about 400 kHz) supply high-frequency power to the electrode 109 via an impedance matching system 143. By applying high-frequency power to the gas species introduced into the process space on the wafer, a plasma 180 for wafer processing, e.g., for etching, is generated.

[0052] An edge ring 167 surrounds the ceramic layer 110 and is configured to facilitate the extension of the plasma sheath radially outward beyond the outer peripheral edge of the wafer W, thereby improving the process results near the periphery of the wafer W.

[0053] The adjustable edge sheath (TES) system is implemented to include a TES electrode 415 disposed (embedded) within a bonding ring 161. A TES high-frequency signal generator 403 supplies high-frequency power to the TES electrode 415 via a TES impedance matching system 401. The TES system can control the characteristics of the plasma 180 near the outer periphery edge of the wafer W, such as, for example, controlling the plasma sheath, plasma density, and the characteristics of ion attraction or repulsion. Generally speaking, by applying high-frequency power to the TES electrode 415, the TES system enables the adjustment of the plasma at the edge of the wafer and improves the radial uniformity.

[0054] For a given process recipe, the parameters of the process recipe are set, and these parameters include the parameters of the TES system that provide radial uniformity. For example, in the illustrated embodiment, for an edge ring 167 having an initial thickness J1, for a state S1 at a first voltage V1, high-frequency power is supplied by the TES high-frequency signal generator 403, which is configured such that at the edge or peripheral region of the wafer W, above the upper surface of the wafer W, the plasma sheath shown at S1 is adjusted to have a height H1.

[0055] However, during plasma processing, the edge ring 167 is partially consumed or worn away, and thus, as the RF time and process cycles accumulate, the thickness of the edge ring 167 gradually decreases. Thus, for example, during several hours of RF time, the thickness of the edge ring 167 may decrease from thickness J1 to thickness J2. With the voltage V1 for state S1 applied during processing, as the thickness of the edge ring 167 decreases, the level of the plasma sheath also decreases. For example, when the thickness of the edge ring 167 wears to thickness J2, the plasma sheath drops to the level shown at S2, thereby decreasing the height to H2 above the upper surface of the wafer W at the wafer edge.

[0056] This decrease in the thickness of the edge ring and the resulting change in the plasma sheath level at the wafer edge lead to radial non-uniformity at the edge. For example, differences in etching rates (non-uniformity in etching rate and etching depth) between the edge and the central part of the wafer, and inclination of the feature profile at the edge (non-uniformity in the etching direction) may occur.

[0057] Therefore, in order to counteract the influence of edge ring wear / consumption and maintain the level of the plasma sheath despite the loss of edge ring thickness, the voltage applied to the TES electrode 415 for state S1 can be increased to a second voltage V2. In the illustrated embodiment, for state S1, a voltage V2 (greater than voltage V1) is applied by the TES high-frequency signal generator 403, and when the thickness of the edge sheath decreases to thickness J2, the plasma sheath recovers to that indicated by reference S1. That is, even when the thickness of the edge ring 167 decreases, in the TES system, by applying an increased voltage for state S1, the level of the plasma sheath is maintained.

[0058] However, increasing the voltage applied to the TES electrode 415 in state S1 changes the impedance of the system and causes an increase in the reflection of high-frequency power in state S1. To minimize the high-frequency power reflected in state S1, the capacitance setting in the TES impedance matching system 401 can be adjusted as discussed in more detail below.

[0059] Note that the TES high-frequency signal generator 403 is configured to automatically adjust the phase of the generated high-frequency signal to match the phase of the state S1 of the high-frequency signal (e.g., at 400 kHz) generated by the high-frequency signal generator 149. Thus, when the voltage of state S1 applied to the TES electrode 415 increases, the TES high-frequency signal generator 401 is automatically adjusted to maintain phase alignment with the state S1 of the high-frequency signal from the high-frequency signal generator 149. By adjusting the capacitance setting in the TES impedance matching system to minimize the reflection of high-frequency power, it has been found that the (automatically occurring) phase adjustment by the TES high-frequency signal generator 403 results in substantially returning to the original amount of phase adjustment with respect to the original voltage (the first voltage of state S1 before being increased to compensate for edge ring wear). Therefore, the capacitance setting in the TES impedance matching system can be optimized using the amount of phase adjustment for state S1.

[0060] FIG. 2 shows a vertical cross-sectional view of a plasma processing system 100 for use in semiconductor chip manufacturing according to some embodiments. The system 100 includes a chamber 101 formed by a wall 101A, an upper member 101B, and a bottom member 101C. The wall 101A, the upper member 101B, and the bottom member 101C collectively form an inner region 103 within the chamber 101. The bottom member 101C includes an exhaust port 105 to which exhaust gas from the plasma processing operation is directed. In some embodiments, during operation, a suction force is applied at the exhaust port 105 by a turbo pump or other vacuum device, etc., to draw process exhaust gas out of the inner region 103 of the chamber 101. In some embodiments, the chamber 101 is formed of aluminum. However, in various embodiments, the chamber 101 can be formed of basically any material that provides sufficient mechanical strength and acceptable thermal performance, and any material that is chemically compatible with other materials with which the chamber interfaces and to which the chamber is exposed during the plasma processing operation within the chamber 101, for example, among others, stainless steel, etc. At least one wall 101A of the chamber 101 includes a door 107 through which a semiconductor wafer W is transferred into and out of the chamber 101. In some embodiments, the door 107 is configured as a slit valve door.

[0061] In some embodiments, semiconductor wafer W is a semiconductor wafer undergoing fabrication processes. For ease of discussion, semiconductor wafer W will hereinafter be referred to as wafer W. However, it should be understood that in various embodiments, wafer W can basically be any type of substrate that undergoes a plasma-based manufacturing process. For example, in some embodiments, wafer W referred to herein can be a substrate formed of silicon, sapphire, GaN, GaAs, or SiC, or other substrate materials, and can include glass panels / substrates, metal foils, metal sheets, polymer materials, etc. Also, in various embodiments, wafer W referred to herein can have a different shape, form, and / or size. For example, in some embodiments, wafer W referred to herein can correspond to a circular semiconductor wafer on which integrated circuit devices are fabricated. In various embodiments, circular wafer W can have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or another size. Also, in some embodiments, wafer W referred to herein can correspond to a non-circular substrate, such as, among other shapes, a rectangular substrate for a flat panel display.

[0062] Plasma processing system 100 includes an electrode 109 disposed on an equipment plate 111. In some embodiments, electrode 109 and equipment plate 111 are formed of aluminum. However, in other embodiments, electrode 109 and equipment plate 111 can be formed of another conductive material having sufficient mechanical strength and compatible thermal and chemical performance characteristics. A ceramic layer 110 is formed on the upper surface of electrode 109. In some embodiments, the ceramic layer has a vertical thickness of about 1.25 millimeters (mm) as measured perpendicular to the upper surface of electrode 109. However, in other embodiments, ceramic layer 110 can have a vertical thickness greater than or less than 1.25 mm. Ceramic layer 110 is configured to receive and support wafer W during the plasma processing operation on wafer W. In some embodiments, the upper surface of electrode 190 and the outer peripheral side surface of electrode 109, which are located radially outside of ceramic layer 110, are covered with a ceramic spray coat.

[0063] Ceramic layer 110 includes a configuration of one or more clamp electrodes 112 for generating an electrostatic force to hold wafer W on the upper surface of ceramic layer 110. In some embodiments, ceramic layer 110 includes a configuration of two clamp electrodes 112 that operate in a bipolar form to supply a clamping force to wafer W. Clamp electrodes 112 are connected to a direct current (DC) supply 117, which generates a controlled clamping voltage to hold wafer W against the upper surface of ceramic layer 110. Electric wires 119A, 119B are connected between DC supply 117 and equipment plate 111. Electric wires / conductors are routed through equipment plate 111 and electrode 109 to electrically connect electric wires 119A, 119B to clamp electrodes 112. DC supply 117 is connected to control system 120 through one or more signal conductors 121.

[0064] The electrode 109 also includes the configuration of a temperature control fluid channel 123 through which a temperature control fluid flows to control the temperature of the electrode 109, thereby controlling the temperature of the wafer W. The temperature control fluid channel 123 is pipe-connected (fluid-connected) to ports on the equipment plate 111. A temperature control fluid supply and return line are connected to these ports on the equipment plate 111 and to the temperature control fluid circulation system 125 as indicated by the arrow 126. The temperature control fluid circulation system 125 includes, among other devices, a temperature control fluid supply, a temperature control fluid pump, and a heat exchanger to supply a controlled flow of temperature control fluid through the electrode 109 to obtain and maintain a specified wafer W temperature. The temperature control fluid circulation system 125 is connected to the control system 120 through one or more signal conductors 127. In various embodiments, various types of temperature control fluids such as water or a cooling liquid / gas can be used. Also, in some embodiments, the temperature control fluid channel 123 is configured to enable spatially varying control of the temperature of the wafer W, for example, two-dimensional (x and y) control across the entire wafer W.

[0065] The ceramic layer 110 also includes a configuration of a backside gas supply port (not shown) that is fluidly connected to a corresponding backside gas supply channel within the electrode 109. The backside gas supply channel within the electrode 109 is routed through the electrode 109 to the interface between the electrode 109 and the equipment plate 111. One or more backside gas supply lines are connected to ports on the equipment plate 111 and to the backside gas supply system 129, as indicated by the arrow 130. The equipment plate 111 is configured to supply backside gas from one or more backside gas supply lines to the backside gas supply channel within the electrode 109. The backside gas supply system 129 includes, among other devices, a backside gas supply section, a mass flow controller, and a flow control valve to provide a controlled flow of backside gas through the configuration of the backside gas supply port within the ceramic layer 110. In some embodiments, the backside gas supply system 129 also includes one or more components for controlling the temperature of the backside gas. In some embodiments, the backside gas is helium. Also, in some embodiments, the backside gas supply system 129 can be used to supply clean dry air (CDA) to the configuration of the backside gas supply port within the ceramic layer 110. The backside gas supply system 129 is connected to the control system 120 through one or more signal conductors 131.

[0066] The three lift pins 132 extend through the equipment plate 111, the electrode 109, and the ceramic layer 110, resulting in the vertical movement of the wafer W relative to the upper surface of the ceramic layer 110. In some embodiments, the vertical movement of the lift pins 132 is controlled by corresponding electromechanical and / or air-lifting devices 133 connected to the equipment plate 111. The three lifting devices 133 are connected to the control system 120 through one or more signal conductors 134. In some embodiments, the three lift pins 132 are arranged to have substantially equal azimuthal angular intervals around the vertical centerline of the electrode 109 / ceramic layer 110, extending at right angles to the upper surface of the ceramic layer 110. It should be understood that the lift pins 132 are lifted to accommodate the wafer W into the chamber 101 and to remove the wafer W from the chamber 101. Also, during the processing of the wafer W, the lift pins 132 are lowered to enable the wafer W to be placed on the upper surface of the ceramic layer 110.

[0067] Also, in various embodiments, one or more of the electrode 109, the equipment plate 111, the ceramic layer 110, the clamp electrode 112, the lift pin 132, or any other component basically associated therewith can be equipped to include one or more sensors, for example, sensors for temperature measurement, voltage measurement, and current measurement among others. Any sensor disposed within the electrode 109, the equipment plate 111, the ceramic layer 110, the clamp electrode 112, the lift pin 132, or any other component basically associated therewith is connected to the control system 120 via an electric wire, an optical fiber, or through a wireless connection.

[0068] The equipment plate 111 is provided within the opening of the ceramic support 113 and is supported by the ceramic support 113. The ceramic support 113 is disposed on the support surface 114 of the cantilever arm assembly 115. In some embodiments, the ceramic support 113 has a substantially annular shape, whereby the ceramic support 113 substantially surrounds the radially outer periphery of the equipment plate 111 while also providing a support surface 116 on which the bottom outer peripheral surface of the equipment plate 111 is placed. The cantilever arm assembly 115 extends through the wall 101A of the chamber 101. In some embodiments, a sealing mechanism 135 is provided within the wall 101A of the chamber 101 where the cantilever arm assembly 115 is located to provide sealing of the inner region 103 of the chamber 101 while also enabling the cantilever arm assembly 115 to move upward and downward in the z - direction in a controlled manner.

[0069] The cantilever arm assembly 115 has an opening region 118 through which various devices, wires, cables, and tubes are passed to support the operation of the system 100. The opening region 118 within the cantilever arm assembly is exposed to the ambient atmospheric conditions outside the chamber 101, such as air composition, temperature, pressure, and relative humidity. Also, a high - frequency signal supply rod 137 is disposed inside the cantilever arm assembly 115. More specifically, the high - frequency signal supply rod 137 is disposed inside the conductive tube 139, whereby the high - frequency signal supply rod 137 is spaced from the inner wall of the tube 139. The sizes of the high - frequency signal supply rod 137 and the tube 139 can vary. The region inside the tube 139 between the inner wall of the tube 139 and the high - frequency signal supply rod 137 is occupied by air along the entire length of the tube 139. In some embodiments, the outer diameter (D rod ) of the high - frequency signal supply rod 137 and the inner diameter (D tube ) of the tube 139 are set to satisfy the relationship ln(D tube / D rod )≧e 1 .

[0070] In some embodiments, the high-frequency signal supply rod 137 is placed substantially centrally within the tube 139, such that there is a substantially uniform radial thickness of air between the high-frequency signal supply rod 137 and the inner wall of the tube 139 along the length of the tube 139. However, in some embodiments, the high-frequency signal supply rod 137 is not placed centrally within the tube 139, but rather an air gap exists within the tube 139 at any location between the high-frequency signal supply rod 137 and the inner wall of the tube 139 along the length of the tube 139. The delivery end of the high-frequency signal supply rod 137 is electrically and physically connected to the lower end of the high-frequency signal supply shaft 141. In some embodiments, the delivery end of the high-frequency signal supply rod 137 is bolted to the lower end of the high-frequency signal supply shaft 141. The upper end of the high-frequency signal supply shaft 141 is electrically and physically connected to the bottom of the equipment plate 111. In some embodiments, the upper end of the high-frequency signal supply shaft 141 is bolted to the bottom of the equipment plate 111. In some embodiments, both the high-frequency signal supply rod 137 and the high-frequency signal supply shaft 141 are formed of copper. In some embodiments, the high-frequency signal supply rod 137 is formed of copper, or aluminum, or anodized aluminum. In some embodiments, the high-frequency signal supply shaft 141 is formed of copper, or aluminum, or anodized aluminum. In other embodiments, the high-frequency signal supply rod 137 and / or the high-frequency signal supply shaft 141 are formed of another conductive material that transmits high-frequency electrical signals. In some embodiments, the high-frequency signal supply rod 137 and / or the high-frequency signal supply shaft 141 are coated with a conductive material (e.g., silver or another conductive material) that transmits high-frequency electrical signals. Also, in some embodiments, the high-frequency signal supply rod 137 is a solid rod. However, in other embodiments, the high-frequency signal supply rod 137 is a tube. It should be understood that the region 140 surrounding the connection between the high-frequency signal supply rod 137 and the high-frequency signal supply shaft 141 is occupied by air.

[0071] The supply end of the high-frequency signal supply rod 137 is electrically and physically connected to the impedance matching system 143. The impedance matching system 143 is connected to the first high-frequency signal generator 147 and the second high-frequency signal generator 149. The impedance matching system 143 is also connected to the control system 120 through one or more signal conductors 144. The first high-frequency signal generator 147 is also connected to the control system 120 through one or more signal conductors 148. The second high-frequency signal generator 149 is also connected to the control system 120 through one or more signal conductors 150. The impedance matching system 143 includes a configuration of inductors and capacitors that are dimensioned and connected to provide impedance matching such that high-frequency power can be transmitted along the high-frequency signal supply rod 137, along the high-frequency signal supply shaft 141, through the equipment plate 111, through the electrode 109, and into the plasma processing region 182 above the ceramic layer 110. In some embodiments, the first high-frequency signal generator 147 is a high-frequency signal generator with a high frequency, and the second high-frequency signal generator 149 is a high-frequency signal generator with a low frequency. In some embodiments, the first high-frequency signal generator 147 generates a high-frequency signal in the range from about 50 megahertz (MHz) to about 70 MHz, or in the range from about 54 MHz to about 63 MHz, or about 60 MHz. In some embodiments, the first high-frequency signal generator 147 supplies high-frequency power in the range from about 5 kilowatts (kW) to about 25 kW, or in the range from about 10 kW to about 20 kW, or in the range from about 15 kW to about 20 kW, or about 10 kW, or about 16 kW. In some embodiments, the second high-frequency signal generator 149 generates a high-frequency signal in the range from about 50 kilohertz (kHz) to about 500 kHz, or in the range from about 330 kHz to 440 kHz, or about 400 kHz. In some embodiments, the second high-frequency signal generator 149 supplies high-frequency power in the range from about 15 kW to about 100 kW, or in the range from about 30 kW to about 50 kW, or about 34 kW, or about 50 kW.In an exemplary embodiment, the first high-frequency signal generator 147 is set to generate a high-frequency signal having a frequency of about 60 MHz, and the second high-frequency signal generator 149 is set to generate a high-frequency signal having a frequency of about 400 kHz.

[0072] The coupling ring 161 is configured and arranged to extend around the outer periphery in the radial direction of the electrode 109. In some embodiments, the coupling ring 161 is formed of a ceramic material. The quartz ring 163 is configured and arranged to extend around the outer peripheries in the radial direction of both the coupling ring 161 and the ceramic support 113. In some embodiments, when the quartz ring 163 is disposed around both the coupling ring 161 and the ceramic support 113, the coupling ring 161 and the quartz ring 163 are configured to have substantially aligned upper surfaces. Also, in some embodiments, the substantially aligned upper surfaces of the coupling ring 161 and the quartz ring 163 are substantially aligned with the upper surface of the electrode 109, and the upper surface is located outside the radial peripheral portion of the ceramic layer 110. Further, in some embodiments, the cover ring 165 is configured and arranged to extend around the outer periphery in the radial direction of the upper surface of the quartz ring 163. In some embodiments, the cover ring 165 is formed of quartz. In some embodiments, the cover ring 165 is configured to extend vertically above the upper surface of the quartz ring 163. Thus, the cover ring 165 provides a peripheral boundary within which the edge ring 167 is disposed.

[0073] The edge ring 167 is configured to facilitate the radial outward extension of the plasma sheath beyond the outer periphery of the wafer W, thereby improving the process results near the periphery of the wafer W. In various embodiments, the edge ring 167 is formed of a conductive material, among other materials, such as crystalline silicon, polycrystalline silicon (polysilicon), boron-doped single-crystalline silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, silicon carbide or a silicon carbide layer on an aluminum oxide layer, or a silicon alloy, or a combination thereof. It should be understood that the edge ring 167 is formed as an annular shape structure, for example, a ring shape structure. The edge ring 167 can perform many functions, including shielding the components below the edge ring 167 from being damaged by the ions of the plasma 180 formed within the plasma processing region 182. Further, the edge ring 167 improves the uniformity of the plasma 180 in and along the outer peripheral region of the wafer W.

[0074] The fixed outer support flange 169 is attached to the cantilever arm assembly 115. The fixed outer support flange 169 is configured to extend around the outer vertical side surface of the ceramic support 113, around the outer vertical side surface of the quartz ring 163, and around the lower outer vertical side surface of the cover ring 165. The fixed outer support flange 169 has an annular shape surrounding the assembly of the ceramic support 113, the quartz ring 163, and the cover ring 165. The fixed outer support flange 169 has an L-shaped vertical cross-section including a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the fixed outer support flange 169 has an inner vertical surface that is disposed in contact with the outer vertical side surface of the ceramic support 113, in contact with the outer vertical side surface of the quartz ring 163, and in contact with the lower outer vertical side surface of the cover ring 165. In some embodiments, the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 extends over the entire outer vertical side surface of the ceramic support 113, over the entire outer vertical side surface of the quartz ring 163, and over the lower outer vertical side surface of the cover ring 165. In some embodiments, the cover ring 165 extends radially outwardly on the upper surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169. And, in some embodiments, the upper outer vertical side surface of the cover ring 165 (located above the upper surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169) is substantially vertically aligned with the outer vertical surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169. The horizontal portion of the L-shaped cross-section of the fixed outer support flange 169 is placed on and fixed to the support surface 114 of the cantilever arm assembly 115. The fixed outer support flange 169 is formed of a conductive material. In some embodiments, the fixed outer support flange 169 is formed of aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange 169 can be formed of another conductive material such as copper or stainless steel. In some embodiments, the horizontal portion of the L-shaped cross-section of the fixed outer support flange 169 is bolted to the support surface 114 of the cantilever arm assembly 115.

[0075] The articulating outer support flange 171 is configured and arranged to extend around the outer vertical surface 169D of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 and around the upper outer vertical side surface of the covering 165. The articulating outer support flange 171 has an annular shape surrounding both the vertical portion of the L-shaped vertical cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering 165. The articulating outer support flange 171 has an L-shaped vertical cross-section including a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the articulating outer support flange 171 has an inner vertical surface, and the inner vertical surface is close to and spaced from both the outer vertical side surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering 165. Thus, the articulating outer support flange 171 is movable in the vertical direction (z-direction) along both the vertical portion of the L-shaped vertical cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering 165. The articulating outer support flange 171 is formed of a conductive material. In some embodiments, the articulating outer support flange 171 is formed of aluminum or anodized aluminum. However, in other embodiments, the articulating outer support flange 171 can be formed of another conductive material such as copper or stainless steel.

[0076] A plurality of conductive straps 173 are connected between the articulating outer support flange 171 and the fixed outer support flange 169 around the outer circumferences in the radial direction of both the articulating outer support flange 171 and the fixed outer support flange 169. In an exemplary embodiment, the conductive strap 173 is shown to have an "outward-facing" configuration in that the conductive strap 173 bends outwardly away from the fixed outer support flange 169. In some embodiments, the conductive strap 173 is formed of stainless steel. However, in other embodiments, the conductive strap 173 can be formed of another conductive material, for example, among others, aluminum or copper.

[0077] In some embodiments, 48 conductive straps 173 are substantially evenly distributed around the radial outer periphery of the articulating outer support flange 171 and the fixed outer support flange 169. However, it should be understood that in different embodiments, the number of conductive straps 173 can be varied. In some embodiments, the number of conductive straps 173 is in the range of from about 24 to about 80, or in the range of from about 36 to about 60, or in the range of from about 40 to about 56. In some embodiments, the number of conductive straps 173 is less than 24. In some embodiments, the number of conductive straps 173 is more than 80. Since the number of conductive straps 173 affects the ground return path of the high-frequency signal around the outer periphery of the plasma treatment region 182, the number of conductive straps 173 can affect the uniformity of the process results across the entire wafer W. Also, in different embodiments, the size of the conductive straps 173 can be varied.

[0078] In some embodiments, the conductive strap 173 is connected to the fixed outer support flange 169 by a clamping force applied by fixing the clamping ring 175 to the upper surface of the horizontal portion of the L-shaped cross-section of the fixed outer support flange 169. In some embodiments, the clamping ring 175 is bolted to the fixed outer support flange 169. In some embodiments, the bolts for fixing the clamping ring 175 to the fixed outer support flange 169 are disposed at locations between the conductive straps 173. However, in some embodiments, one or more bolts for fixing the clamping ring 175 to the fixed outer support flange 169 can be arranged to extend through the conductive straps 173. In some embodiments, the clamping ring 175 is formed of the same material as the fixed outer support flange 169. However, in other embodiments, the clamping ring 175 and the fixed outer support flange 169 can be formed of different materials.

[0079] In some embodiments, the conductive strap 173 is connected to the articulating outer support flange 171 by a clamping force applied by fixing the clamping ring 177 to the bottom surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange 171. Alternatively, in some embodiments, the first end portion of each of the plurality of conductive straps 173 is connected by the clamping ring 177 to the upper surface of the horizontal portion of the articulating outer support flange 171. In some embodiments, the clamping ring 177 is bolted to the articulating outer support flange 171. In some embodiments, the bolts fixing the clamping ring 177 to the articulating outer support flange 171 are located at locations between the conductive straps 173. However, in some embodiments, one or more bolts fixing the clamping ring 177 to the articulating outer support flange 171 can be arranged to extend through the conductive strap 173. In some embodiments, the clamping ring 177 is formed of the same material as the articulating outer support flange 171. However, in other embodiments, the clamping ring 177 and the articulating outer support flange 171 can be formed of different materials.

[0080] The set of support rods 201 is disposed around the cantilever arm assembly 115 and extends vertically through the horizontal portion 169B of the L-shaped cross-section of the fixed outer support flange 169. The upper end of the support rod 201 is configured to engage the bottom surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange 171. In some embodiments, the lower end of each support rod 201 engages a resistance mechanism 203. The resistance mechanism 203 is configured to provide an upward force that resists downward movement of the support rod 201 while allowing some downward movement of the support rod 201. In some embodiments, the resistance mechanism 203 includes a spring and provides an upward force to the corresponding support rod 201. In some embodiments, the resistance mechanism 203 includes a material having a sufficient spring constant, such as a spring and / or rubber, and provides an upward force to the corresponding support rod 201. It should be understood that as the articulating outer support flange 171 moves downward and engages the set of support rods 201, the set of support rods 201 and the corresponding resistance mechanism 203 provide an upward force to the articulating outer support flange 171. In some embodiments, the set of support rods 201 includes three support rods 201 and the corresponding resistance mechanism 203. In some embodiments, the support rods 201 are arranged to have substantially equal azimuthal angular intervals with respect to the vertical centerline of the electrode 109. However, in some embodiments, the support rods 201 are arranged to have unequal azimuthal angular intervals with respect to the vertical centerline of the electrode 109. Also, in some embodiments, more than three support rods 201 and corresponding resistance mechanisms 203 are provided to support the articulating outer support flange 171.

[0081] Referring again to FIG. 2, the plasma processing system 100 further includes a C-shroud member 185 disposed above the electrode 109. The C-shroud member 185 is configured to interface with the articulating outer support flange 171. Specifically, a seal 179 is disposed on the upper surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange 171, such that when the articulating outer support flange 171 moves upwardly towards the C-shroud member 185, the C-shroud member 185 engages the seal 179. In some embodiments, the seal 179 is conductive to assist in establishing conductivity between the C-shroud member 185 and the articulating outer support flange 171. In some embodiments, the C-shroud member 185 is formed of polysilicon. However, in other embodiments, the C-shroud member 185 is formed of another type of conductive material that is chemically compatible with the processes formed in the plasma processing region 182 and has sufficient mechanical strength.

[0082] The C-shroud extends around the plasma processing region 182 and is configured to provide a radially extending portion of the plasma processing region 182 volume into a region defined within the C-shroud member 185. The C-shroud member 185 includes a lower wall 185A, an outer vertical wall 185B, and an upper wall 185C. In some embodiments, the outer vertical wall 185B and the upper wall 185C of the C-shroud member 185 are solid, non-perforated members, and the lower wall 185A of the C-shroud member 185 includes a plurality of vents 186 through which process gas flows out from within the plasma processing region 182. In some embodiments, a throttle member 196 is disposed below the vents 186 of the C-shroud member 185 to control the flow of process gas through the vents 186. More specifically, in some embodiments, the throttle member 196 is configured to move vertically up and down perpendicular to the z-direction with respect to the C-shroud member 185 to control the flow of process gas through the vents 186. In some embodiments, the throttle member 196 is configured to engage and / or enter the vents 186.

[0083] The upper wall 185C of the C shroud member 185 is configured to support the upper electrodes 187A / 187B. In some embodiments, the upper electrodes 187A / 187B include an inner upper electrode 187A and an outer upper electrode 187B. Instead, in some embodiments, the inner upper electrode 187A exists and the outer upper electrode 187B does not exist, and the inner upper electrode 187A extends radially to cover the location that would be occupied by the outer upper electrode 187B. In some embodiments, the inner upper electrode 187A is formed of single crystal silicon and the outer upper electrode 187B is formed of polysilicon. However, in other embodiments, the inner upper electrode 187A and the outer upper electrode 187B can be formed of other materials that are structurally, chemically, electrically, and mechanically compatible with the processes carried out within the plasma processing region 182. The inner upper electrode 187A includes a plurality of through ports 197 defined as holes that extend through the entire vertical thickness of the inner upper electrode 187A. The through ports 197 are distributed across the inner upper electrode 187A with respect to the x-y plane to supply a flow of process gas from the plenum region 188 above the upper electrodes 187A / 187B to the plasma processing region 182 below the upper electrodes 187A / 187B.

[0084] It should be understood that the distribution of the through-ports 197 across the entire inner upper electrode 187A can be configured in different forms in different embodiments. For example, the total number of through-ports 197 within the inner upper electrode 187A and / or the spatial distribution of the through-ports 197 within the inner upper electrode 187A can vary between different embodiments. Also, the diameter of the through-ports 197 can vary between different embodiments. Generally, it is of interest to reduce the diameter of the through-ports 197 to a size small enough to prevent the plasma 180 from entering the through-ports 197 from the plasma processing region 182. In some embodiments, as the diameter of the through-ports 197 is reduced, the total number of through-ports 197 within the inner upper electrode 187A is increased such that the defined overall flow rate of the process gas flowing from the process gas plenum region 188 through the inner upper electrode 187A to the plasma processing region 182 is maintained. Also, in some embodiments, the upper electrodes 187A / 187B are electrically connected to a reference ground potential. However, in other embodiments, the inner upper electrode 187A and / or the outer upper electrode 187B are electrically connected to a corresponding direct current (DC) power supply or a corresponding high frequency power supply via a corresponding impedance matching circuit.

[0085] The plenum region 188 is defined by the upper element 189. One or more gas supply ports 192 are formed through the chamber 101 and the upper element 189 such that they are in fluid communication with the plenum region 188. The one or more gas supply ports 192 are fluidly connected (pipingly connected) to the process gas supply system 191. The process gas supply system 191 includes, among other devices, one or more process gas supplies, one or more mass flow controllers, and one or more flow control valves to supply a regulated flow of one or more process gases to the plenum region 188 through the one or more gas supply ports 192, as indicated by the arrow 193. In some embodiments, the process gas supply system 191 also includes one or more components for controlling the temperature of the process gas. The process gas supply system 191 is connected to the control system 120 through one or more signal conductors 194.

[0086] The processing gap (g1) is defined as the vertical (z-direction) distance measured between the upper surface of the ceramic layer 110 and the bottom surface of the inner upper electrode 187A. The size of the processing gap (g1) can be adjusted by moving the cantilever arm assembly 115 in the vertical direction (z-direction). As the cantilever arm assembly 115 moves upward, the articulated outer support flange 171 eventually engages the lower wall 185A of the C-shroud member 185, and at that point, as the cantilever arm assembly 115 continues to move upward, the articulated outer support flange 171 moves along the fixed outer support flange 169, which continues until a set of support rods 201 engages the articulated outer support flange 171 and a prescribed processing gap (g1) size is achieved. Then, to remove the wafer W from the chamber, the cantilever arm assembly 115 is moved downward until the articulated outer support flange 171 moves away from the lower wall 185A of the C-shroud member 185 to reverse this movement. In various embodiments, the size of the processing gap (g1) during plasma processing of the wafer W is controlled in a range up to about 10 centimeters, or up to about 8 centimeters, or up to about 5 centimeters. It should be understood that FIG. 2 shows the system 100 in a closed configuration with the wafer W on the ceramic layer 110 in a position for plasma processing.

[0087] During plasma processing operations within the plasma processing system 100, one or more process gases are supplied to the plasma processing region 182 via the process gas supply system 191, the plenum region 188, and the through-port 197 within the inner upper electrode 187A. Also, a high-frequency signal is transmitted to the plasma processing region 182 via the first and second high-frequency signal generators 147, 149, the impedance matching system 143, the high-frequency signal supply rod 137, the high-frequency signal supply shaft 141, the facility plate 111, the electrode 109, and through the ceramic layer 110. The high-frequency signal converts the process gas within the plasma processing region 182 into plasma 180. The ions and / or reactive components of the plasma interact with one or more materials on the wafer W to change the composition and / or shape of a specific material on the wafer W. The exhaust gas from the plasma processing region 182 is affected by the suction force applied at the exhaust port 105 and flows through the vent 186 within the C shroud member 185, through the inner region 103 within the chamber 101, and to the exhaust port 105 as indicated by the arrow 195.

[0088] In various embodiments, the electrode 109 can be configured to have different diameters. However, in some embodiments, the diameter of the electrode 109 is extended to increase the surface area of the electrode 109 on which the edge ring 167 is placed. In some embodiments, a conductive gel 226 is disposed between the bottom of the edge ring 167 and the top of the electrode 109 and / or between the bottom of the edge ring 167 and the top of the coupling ring 161. In these embodiments, the increased diameter of the electrode 109 results in an increase in the surface area on which the conductive gel is disposed between the edge ring 167 and the electrode 109.

[0089] It should be understood that the combination of the articulating outer support flange 171, the conductive strap 173, and the fixed outer support flange 169 is at electrically ground reference potential, and together they form a ground return path for the high-frequency signal transmitted from the electrode 109 through the ceramic layer 110 into the plasma processing region 182. The azimuthal uniformity of this ground return path around the outer periphery of the electrode 109 can affect the uniformity of the process results on the wafer W. For example, in some embodiments, the uniformity of the etching rate across the wafer W can be affected by the azimuthal uniformity of the ground return path around the outer periphery of the electrode 109. For this purpose, it should be understood that the number, configuration, and arrangement of the conductive straps 173 around the outer periphery of the electrode 109 can affect the uniformity of the process results across the wafer W.

[0090] Referring again to FIG. 2, the adjustable edge sheath (TES) system is implemented to include a TES electrode 415 disposed (embedded) within the coupling ring 161. The TES system also includes a plurality of TES high-frequency signal supply pins 413 that are physically and electrically connected to the TES electrode 415. Each TES high-frequency signal supply pin 413 extends through a corresponding insulator feed-through member 421 configured to electrically isolate the TES high-frequency signal supply pin 413 from the surrounding structure, such as the ceramic support 113 and the cantilever arm assembly 115 structure. In some embodiments, O-rings 417 and 419 are disposed to ensure that the region inside the insulator feed-through member 421 is not exposed to any material / gas present within the plasma processing region 182. In some embodiments, the TES high-frequency signal supply pins 413 are formed of, among other things, copper, or aluminum, or anodized aluminum.

[0091] The TES high-frequency signal supply pin 413 extends into the opening region 118 inside the cantilever arm assembly 115, and each of the TES high-frequency signal supply pins 413 is electrically connected to the TES high-frequency signal supply conductor 409 through the corresponding TES high-frequency signal filter 411. In some embodiments, three TES high-frequency signal supply pins 413 are arranged to be physically and electrically connected to the TES electrode 415 at azimuthal locations that are substantially equally spaced around the center line of the electrode 109. However, it should be understood that other embodiments can have more than three TES high-frequency signal supply pins 413 that are physically and electrically connected to the TES electrode 415. Also, some embodiments can have either one or two TES high-frequency signal supply pins 413 that are physically and electrically connected to the TES electrode 415. Each TES high-frequency signal supply pin 413 is electrically connected to the corresponding TES high-frequency signal filter 411, and each TES high-frequency signal filter 411 is electrically connected to the TES high-frequency signal supply conductor 409. In some embodiments, each TES high-frequency signal filter 411 is configured as an inductor. For example, in some embodiments, each TES high-frequency signal filter 411 is configured as a coiled conductor, such as a metal coil wound around a dielectric core structure. In various embodiments, the metal coil can be formed, among other things, of a solid copper rod, a copper tube, an aluminum rod, or an aluminum tube. Also, in some embodiments, each TES high-frequency signal filter 411 can be configured as a combination of inductive and capacitive structures. In order to improve the uniformity of the plasma treatment results across the entire wafer W, each of the TES high-frequency signal filters 411 has substantially the same configuration.

[0092] In some embodiments, the TES high-frequency signal supply conductor 409 is formed as a ring-shaped (annular-shaped) structure so as to extend around the opening region 118 inside the cantilever arm assembly 115, enabling a physical and electrical connection between the azimuthally distributed TES high-frequency signal filter 411 and the TES high-frequency signal supply conductor 409. In some embodiments, the TES high-frequency signal supply conductor 409 is formed as a solid (non-tubular) structure. Alternatively, in some embodiments, the TES high-frequency signal supply conductor 409 is formed as a tubular structure. In some embodiments, the TES high-frequency signal supply conductor 409 is formed of, among other things, copper, or aluminum, or anodized aluminum.

[0093] The TES high-frequency signal supply conductor 409 is electrically connected to the TES high-frequency supply cable 407. Also, the capacitor 408 is connected between the TES high-frequency signal supply conductor 409 and the reference ground potential, for example, the structure of the cantilever arm assembly 115. More specifically, the capacitor 408 has a first end that is electrically connected to both the TES high-frequency supply cable 407 and the TES high-frequency signal supply conductor 409, and the capacitor 408 has a second end that is electrically connected to the reference ground potential. In some embodiments, the capacitor 408 is a variable capacitor. In some embodiments, the capacitor 408 is a fixed capacitor. In some embodiments, the capacitor 408 is set to have a capacitance in the range extending from about 10 picofarads to about 100 picofarads. The TES high-frequency supply cable 407 is connected to the TES impedance matching system 401. The TES impedance matching system 401 is connected to the TES high-frequency signal generator 403. The high-frequency signal generated by the TES high-frequency signal generator 403 is transmitted through the TES impedance matching system 401 to the TES high-frequency supply cable 407, then to the TES high-frequency signal supply conductor 409, then through the TES high-frequency signal filter 411 to the corresponding TES high-frequency signal supply pin 413, and then to the TES electrode 415 within the coupling ring 161. In some embodiments, the TES high-frequency signal generator 403 is configured and operated to generate a high-frequency signal within a frequency range extending from about 50 kilohertz to about 27 MHz. In some embodiments, the TES high-frequency signal generator 403 supplies high-frequency power within a range extending from about 50 watts to about 10 kilowatts. The TES high-frequency signal generator 403 is also connected to the control system 120 through one or more signal conductors 405.

[0094] The TES impedance matching system 401 is dimensioned and connected to provide impedance matching so that high-frequency power can be transmitted from the TES high-frequency signal generator 403, along the TES high-frequency supply cable 407, along the TES high-frequency signal supply conductor 409, through the TES high-frequency signal filter 411, through the corresponding TES high-frequency signal supply pin 413, to the TES electrode 415 within the coupling ring 161, and into the plasma processing region 182 above the edge ring 167. FIG. 3 shows an exemplary schematic circuit diagram of the TES impedance matching system 401 according to some embodiments. The TES impedance matching system 401 includes an input line 321 that is electrically connected to the TES high-frequency signal generator 403. The TES input line 321 is electrically connected to the input terminal of a first inductor 322. The output terminal of the first inductor 322 is electrically connected to an internal node 328. A second inductor 324 has an input terminal that is electrically connected to the internal node 328. The output terminal of the second inductor 324 is electrically connected to a second internal node 329. A first capacitor 326 has an input terminal that is electrically connected to the second internal node 329. The output terminal of the first capacitor 326 is electrically connected to the input terminal of a third inductor 327. The output terminal of the third inductor 327 is electrically connected to the TES high-frequency supply cable 407. Also, a second capacitor 323 has an input terminal that is electrically connected to the first internal node 328. The second capacitor 323 has an output terminal that is electrically connected to a reference ground potential. In some embodiments, the second capacitor 323 is a variable capacitor. Also, a third capacitor 325 has an input terminal that is electrically connected to the second internal node 329. The third capacitor 325 has an output terminal that is electrically connected to a reference ground potential. It should be understood that the electrical configuration of the TES impedance matching system 401 shown in FIG. 3 is provided by way of example. In other embodiments, the TES impedance matching system 401 can have an inductor and / or capacitor configuration different from the example shown in FIG. 3.The TES impedance matching system 401 is also connected to the control system 120 through one or more signal conductors 404.

[0095] By transmitting high-frequency signals / power through the TES electrodes 415 disposed (embedded) within the coupling ring 161, the TES system can control the characteristics of the plasma 180 near the outer peripheral edge of the wafer W. For example, in some embodiments, by operating the TES system to control the shape of the plasma 180 sheath and / or by controlling the size (either increasing or decreasing the sheath thickness), the characteristics of the plasma 180 sheath near the edge ring 167 are controlled. Also, in some embodiments, by controlling the shape of the plasma 180 sheath near the edge ring 167, various characteristics of the bulk plasma 180 above the wafer W can be controlled. Also, in some embodiments, the TES system is operated to control the density of the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to increase or decrease the density of the plasma 180 near the edge ring 167. Also, in some embodiments, the TES system is operated to control the bias voltage present in the edge ring 167, and then the bias voltage controls / influences the movement of ions and other charged components in the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to control the bias voltage present in the edge ring 167 to attract more ions from the plasma 180 towards the edge of the wafer W. And, in some embodiments, the TES system is operated to control the bias voltage present in the edge ring 167 to repel ions from the plasma 180 away from the edge of the wafer W. It should be understood that the TES system can be operated to perform various different functions, among others the functions described above, either separately or in combination.

[0096] In some embodiments, the coupling ring 161 is formed of a dielectric material, such as, among others, quartz, or ceramic, or alumina (Al 2 O 3 ), or a polymer.

[0097] The bottom surface of the edge ring 167 is coupled to the top surface of the coupling ring 161 via a layer of a gel having thermal and electrical conductivity, and has a portion that serves as a heat sink for the edge ring 167 with respect to the coupling ring 161. Also, the bottom surface of the edge ring 167 has another portion that is coupled to the top surface of the electrode 109 via a layer of a gel having thermal and electrical conductivity. Examples of gels having thermal and electrical conductivity include, among others, polyimide, polyketone, polyether ketone, polyether sulfone, polyethylene terephthalate, fluorinated ethylene propylene copolymer, cellulose, triacetate, and silicone. In some embodiments, the gel having thermal and electrical conductivity is formed as a double-sided tape. In some embodiments, the edge ring 167 has an inner diameter dimensioned to be close to the outer diameter of the ceramic layer 110.

[0098] In various embodiments, the TES electrode 415 is formed of a conductive material, such as, among others, platinum, steel, aluminum, or copper. During operation, capacitive coupling occurs between the TES electrode 415 and the edge ring 167, and as a result, the edge ring 167 is powered and affects the processing of the wafer W near the outer periphery of the wafer W.

[0099] FIG. 4 conceptually shows the components of the TES high-frequency signal generator 403 according to an implementation of the present disclosure. FIG. 5 is a graph showing various states of the (multi-state / pulse) TES high-frequency signal generated by the TES high-frequency signal generator 403 and applied to the TES electrode according to an implementation of the present disclosure. Referring to both FIGS. 4 and 5, various states of the (multi-state / pulse) TES high-frequency (RF) signal and the corresponding operations of the TES high-frequency signal generator 403 for realizing the various states are described herein.

[0100] FIG. 5 shows the relationship between the voltage set point and time for the TES RF signal generated by the TES RF signal generator 403 according to an implementation of the present disclosure. As shown, the TES RF signal is defined to have a three-state pulse RF cycle, and the states S1, S0, and S2 are periodically repeated in order. In the illustrated implementation, state S0 precedes state S2, but in other implementations, these orders are reversed, for example, state S2 precedes state S0. As shown, each state has a voltage set point that defines the target voltage realized by the TES RF signal generator 403 for that state.

[0101] For the state S1 of the TES RF signal, the voltage set point is Vs1, which in some implementations is configured to provide high aspect ratio etching. For the state S0 of the TES RF signal, the voltage set point is Vs0, which in some implementations is configured to cause passivation. For the state S2 of the TES RF signal, the voltage set point is Vs2, which in some implementations is configured to promote dissociation and neck opening in the feature.

[0102] As can be seen from the figure, the voltage setpoints for states S0 and S2 are lower than the voltage setpoint for state S1. Therefore, to efficiently implement the three-state pulse TES RF signal, the TES RF signal generator 403 uses a single power amplifier 431 to control the RF output power to implement the voltage setpoint for state S1 (Vs1), and utilizes drive actuators 433 and 435 to selectively attenuate the RF output to implement the voltage setpoints for states S0 and S2 (Vs0 and Vs2). The output level of the power amplifier 431 is adjusted to generate an RF signal according to the voltage setpoint for S1, which is Vs1. In some embodiments, the RF signal from the power amplifier 431 further includes additional voltage states that are lower than Vs1 but not too low to implement the desired voltage setpoints Vs0 and Vs2. For the TES RF signal, to fully generate state S0, the drive actuator 433 is configured to selectively attenuate the relevant portion of the power amplifier's signal by an attenuation amount D1 to implement the voltage setpoint Vs0 for S0. Similarly, to fully generate state S2, the drive actuator 435 is configured to selectively attenuate the relevant portion of the power amplifier's signal by an attenuation amount D2 to implement the voltage setpoint Vs2 for S2. Thus, according to embodiments of the present disclosure, the voltage levels for states S0 and S2 are implemented by attenuating the output of the power amplifier as needed to implement the voltage setpoints Vs0 and Vs2.

[0103] The voltages of the respective states are related as described above, but the phases of the respective states can be independently controlled according to the embodiments of the present disclosure. Generally speaking, it is optimal to align the phases of the respective states of the pulsed TES RF signal with the phases of the corresponding states of the pulsed RF signal applied to the electrode 109 by the RF signal generator 149. That is, the phase of the state S1 of the TES RF signal (generated by the RF signal generator 403) is adjusted to be aligned with the phase of the state S1 of the bias RF signal (generated by the RF signal generator 149), the phase of the state S0 of the TES RF signal (generated by the RF signal generator 403) is adjusted to be aligned with the phase of the state S0 of the bias RF signal (generated by the RF signal generator 149), and the phase of the state S2 of the TES RF signal (generated by the RF signal generator 403) is adjusted to be aligned with the phase of the state S2 of the bias RF signal (generated by the RF signal generator 149).

[0104] According to an embodiment of the present disclosure, the TES high-frequency signal generator 403 is configured to automatically and independently adjust the phases of the various states of the generated TES high-frequency signal to be aligned with the phases of the corresponding states of the high-frequency signal generated by the high-frequency signal generator 149. To achieve this, the TES RF signal generator 403 includes a phase actuator 437 for state S1, a phase actuator 439 for state S0, and a phase actuator 441 for state S2. The phase actuator 437 applies a phase adjustment PA1 to automatically adjust the phase of the state S1 in the TES RF signal to be aligned with the corresponding state S1 in the RF signal generated by the high-frequency signal generator 149 for the electrode 109. The phase actuator 439 applies a phase adjustment PA2 to automatically adjust the phase of the state S0 in the TES RF signal to be aligned with the corresponding state S0 in the RF signal generated by the high-frequency signal generator 149 for the electrode 109. The phase actuator 441 applies a phase adjustment PA3 to automatically adjust the phase of the state S2 in the TES RF signal to be aligned with the corresponding state S2 in the RF signal generated by the high-frequency signal generator 149 for the electrode 109.

[0105] In some embodiments, the voltage setpoint of state S1 applied to the TES electrode 415 is increased to compensate for the wear of the edge ring 167 according to the accumulation of the RF time. Accordingly, the TES RF signal generator 403 is then automatically adjusted to maintain the phase alignment of the RF signal from the RF signal generator 149 with state S1. As described, the phase adjustment (automatically occurring) by the TES RF signal generator 403, by adjusting the capacitance setting in the TES impedance matching system 401 that minimizes the reflection of the RF power in state S1, results in substantially returning to its original phase adjustment amount with respect to the original voltage (the first voltage of state S1 before being increased to compensate for edge ring wear). Therefore, the capacitance setting of the variable capacitor 323 in the TES impedance matching system 401 can be optimized using the phase adjustment amount for state S1.

[0106] However, according to an embodiment of the present disclosure, the capacitance setting in the TES impedance matching system 401 sets the capacitance C1 that is applied to all of the states S1, S0, and S2 of the pulsed TES RF signal. As further discussed below, such a change in the capacitance setting of the TES impedance matching system also affects the relationship between the voltage setpoints for states S0 and S2 and the allowable ranges of the voltage setpoints for these states. Accordingly, it is desirable to optimize the voltage setpoints for states S0 and S2 in response to the change in the capacitance setting.

[0107] FIG. 6 is a graph conceptually showing the allowable range of the voltage setpoint for state S0 or S2 according to an implementation of the present disclosure. More specifically, the allowable voltage setpoint range is shown by a vertical bar as a function of the capacitor tap position of the variable capacitor 323 in the TES impedance matching system 401. Generally speaking, as the voltage setpoint of state S1 changes, the capacitor tap position, for example, also changes accordingly so as to minimize the reflected power from state S1. However, as described above, states S0 and S2 are dependent on the voltage of state S1 in that the voltages of states S0 and S2 are realized by the drive actuator attenuating the output of the power amplifier. This is set by the TES RF signal generator when controlling the voltage setpoint of state S1. The range of the expected voltage setpoints for states S0 and S2 is determined by the voltage of state S1 and the ability of the drive actuator to attenuate the output of the power amplifier. The maximum value or upper limit of the voltage setpoint for S0 / S2 is determined by the voltage setpoint of state S1. This is because the output of the power amplifier used to control state S1 to its fully non-attenuated amount is the maximum output expected for states S0 / S2. The minimum value or lower limit of the voltage setpoint for S0 / S2 is determined by the amount of attenuation possible by the drive actuator of the TES RF signal generator 403. Therefore, the range of the allowable voltage set values is bounded by the output required to control state S1 and the amount by which the drive actuator can attenuate the output of the power amplifier.

[0108] As described above, for example, when the voltage setpoint of state S1 is increased to compensate for wear of the edge ring, the capacitor tap position of the variable capacitor 323 in the TES impedance matching system 401 is adjusted to minimize the reflected power. Accordingly, as shown in FIG. 6, since the voltage setpoint of state S1 changes according to the wear of the edge ring, the allowable range of the voltage setpoint for states S0 / S2 changes with the change in the capacitor tap position.

[0109] However, such a shift in the acceptable range of the voltage setpoint presents the problem of how to adjust the voltage setpoints for states S0 and S2. For example, if the voltage setpoint for state S1 changes and the capacitor tap position also changes, the acceptable range of the voltage setpoint for state S0 changes, which may result in the existing voltage setpoint for state S0 no longer being within the acceptable range, and as a result, the system may not be able to achieve the existing voltage setpoint for state S0. A similar change may occur in the acceptable range of the voltage setpoint for state S2, and again, it may result in the existing voltage setpoint for state S2 no longer being within the acceptable range, and as a result, the system may not be able to achieve the existing voltage setpoint for state S2. In addition, for either state S0 or S2, even if the existing voltage setpoint is still within the acceptable range, it may be at the edge of the range of acceptable values, and as a result, the degree of freedom to adjust the voltage setpoint to optimize a given recipe as needed is limited.

[0110] For example, continuing to refer to FIG. 6, the existing voltage setpoint for S0 / S2 is V1. When the capacitor tap position is at P5, the voltage setpoint V1 is approximately in the middle of the acceptable range 600 of acceptable voltage setpoints. This provides some tolerance for adjusting the voltage setpoint up or down if required for recipe optimization.

[0111] However, if the voltage setpoint for state S1 is increased, and as a result, the capacitor tap position changes to P4, the acceptable range of the voltage setpoint for state S0 / S2 changes to acceptable range 602, which is, roughly speaking, an increase from the previous acceptable range 600. At this stage, the existing voltage setpoint V1 for S0 / S2 is still within acceptable range 602. However, V1 is now near the bottom of the current acceptable range 602, and as a result, the degree of freedom to further reduce the voltage setpoint if necessary is very limited. This can be a problem for recipe development because the user may try to adjust the voltage setpoint in such a way and may notice that it is not possible to do so.

[0112] If the voltage setpoint for state S1 is further increased, such that the capacitor tap position then changes to P3, the allowable range for the voltage setpoint for states S0 / S2 changes to allowable range 604, which, generally speaking, is an increase from the previous allowable range 602. This presents an unsatisfactory scenario in that the existing S0 / S2 voltage setpoint V1 is now outside of the current allowable range 604 of the voltage setpoint. In other words, when the capacitor tap position is at P3, the system cannot achieve the existing setpoint V1. In such a scenario, as a non-limiting example, the system may generate an error indicating that the voltage setpoint is outside of the allowable range.

[0113] Accordingly, as the voltage setpoint for state S1 changes and the capacitor tap position changes, it is desirable to adjust the voltage setpoint for states S0 / S2. For example, when the capacitor tap position changes to P4, it is desirable to change the S0 / S2 voltage setpoint to V2 such that the S0 / S2 voltage setpoint is maintained approximately in the middle or near the middle of allowable range 602. Similarly, when the capacitor tap position changes to P3, it is desirable to change the S0 / S2 voltage setpoint to V3 such that the S0 / S2 voltage setpoint is maintained approximately in the middle or middle portion of, or near, allowable range 604.

[0114] Over the entire range of capacitor tap settings, the voltage setpoint for states S0 / S2, which is approximately in the middle of the tolerance range for any given capacitor tap setting, has been unexpectedly found to result in approximately constant or the same phase adjustment amount (automatically set by the TES RF signal generator 403 for states S0 / S2) over the entire range of capacitor tap settings. In other words, if the capacitor tap setting is changed in response to a change in the voltage setpoint for state S1, and the resulting phase adjustment amount is approximately the same as the one that existed before changing the capacitor tap setting, the voltage setpoint for states S0 / S2 will be approximately in the middle of the (new) tolerance range. Therefore, when the capacitor tap setting changes, a target phase adjustment amount can be defined and used to determine the appropriate voltage setpoint for states S0 / S2. In this specification, states S0 and S2 are alternatively referred to, and thus it should be understood that the target phase adjustment amount for state S0 can be the same as or different from the target phase adjustment amount for state S2.

[0115] Figure 7 is a graph conceptually showing the relationship between the phase adjustment for states S0 / S2 and the voltage setpoint for states S0 / S2 according to an implementation of the present disclosure. In the illustrated implementation, curve 700 shows the phase adjustment for a given capacitor tap position as described above as a function of the voltage setpoint for states S0 / S2. The tolerance range 602 of the voltage setpoint is indicated by the width of curve 700 along the horizontal axis representing the voltage setting value.

[0116] Point 706 along curve 700 represents the maximum voltage setpoint Vmax as determined by the voltage of state S1 as described above. Position 702 along curve 700 represents the minimum voltage setpoint Vmin, which may be based on the amount of power attenuation possible by the drive actuator of the TES RF signal generator 403. The allowed voltage setpoint range 602 also corresponds to the phase adjustment range 710. As shown, when the voltage setpoint is adjusted to Vc corresponding to point 704 along curve 700, which is approximately in the center or middle of the allowed voltage setpoint range 602, the phase adjustment amount is PA TThis is an unexpected result. However, when the voltage setpoint is adjusted to approximately the middle of the allowable range of the voltage setpoint, this phase adjustment amount PA T was found to be approximately the same for all capacitor tap settings.

[0117] Therefore, PA T defines a target phase adjustment amount that can be used to automatically adjust the voltage setpoint for states S0 / S2 so as to stay approximately in the middle of the allowable range of the voltage setpoint. In response to the change in the voltage setpoint of state S1 and the accompanying change in the capacitor tap setting, the phase adjustment amount for states S0 / S2 is adjusted until it reaches the target phase adjustment amount or falls within a predetermined range of the target phase adjustment amount (for example, within x degrees of PA T ). As described above, states S0 and S2 may have the same or different target phase adjustment amounts, each configured to allow the corresponding voltage setpoint to stay approximately in the middle of the allowable range.

[0118] In some embodiments, a target phase adjustment range 708 is defined, and the voltage setpoint for states S0 / S2 is adjusted until the phase adjustment amount for states S0 / S2 falls within the target phase adjustment range. It will be understood that the target phase adjustment range is configured such that the corresponding voltage setpoint range (phase adjustment resulting in falling within the target phase adjustment range) is approximately in the middle of the allowable voltage setpoint range. It will be understood that states S0 and S2 may potentially have the same or different target phase adjustment ranges.

[0119] Figure 8 conceptually shows a method of maintaining a voltage setpoint within a schematic intermediate range of acceptable voltage setpoints for a state of a pulsed RF signal, according to an implementation of the present disclosure. In method operation 801, a target phase adjustment range (or amount) is determined for a given state of the pulsed RF signal. The target phase adjustment range is configured such that it is the range of phase adjustment amounts obtained when the voltage setpoint for a given state is within the intermediate / central range of acceptable voltage setpoints. As described above, the phase adjustment is automatically performed by the TES RF signal generator to minimize the phase difference / delta in the state where the (main) RF signal is applied to electrode 109 for a given state. Thus, when the voltage setpoint changes, the phase adjustment also automatically changes to minimize the phase difference. Thus, the range of acceptable voltage setpoints corresponds to the range of phase adjustment, in which case it was unexpectedly discovered that the target phase adjustment range / amount resulting from the voltage setpoint in the middle of that acceptable range is substantially constant or the same for different capacitance settings in the TES impedance matching system 401.

[0120] In method operation 803, the amount of phase adjustment automatically determined by the TES RF signal generator is monitored for a given state, such as state S0 or state S2. In method operation 805, it is determined whether the amount of phase adjustment is within the target phase adjustment range. If so, the method returns to method operation 803 for continued monitoring of the amount of phase adjustment.

[0121] If not, in method operation 807, the voltage setpoint for a given state, such as state S0 or state S2, is adjusted. The method then returns to method operations 803 and 805 to continue monitoring the amount of phase adjustment and again determine whether the amount of phase adjustment is within the target phase adjustment range. It will be understood that when the amount of phase adjustment is within the target phase adjustment range, the voltage setpoint will fall within the approximate intermediate / central range of acceptable voltage setpoints for the current situation.

[0122] FIG. 9 is a graph conceptually showing changes in voltage set points for various states of a pulsed RF signal according to an implementation of the present disclosure. Voltage set points for states S1, S0, and S2 are shown as a function of the accumulated RF time of the edge ring. Curve 901 shows the voltage set point for state S1. As can be seen from the figure, as the RF time accumulates, the voltage set point for state S1 is periodically increased to compensate for the wear of the edge ring and maintain the plasma sheath height and characteristics in the edge region.

[0123] According to the method of the present disclosure, the voltage set points for state S2 (shown by curve 903) and state S0 (shown by curve 905) are also incremented in a stepwise manner in coordination with the stepwise change in the voltage set point of state S1. As discussed, the voltage set points for states S0 and S2 are adjusted to maintain a target phase adjustment amount or range for each state.

[0124] In some implementations, the target phase adjustment amount or range can be specified via a user interface. For example, there can be a default target phase adjustment amount or range (e.g., 160 - 180 degrees in some implementations), which can be adjusted by the user in predetermined increments (e.g., 1 - 10 degree increments in some implementations) and within a predetermined range (e.g., 120 - 220 degrees in some implementations).

[0125] For a given recipe, there can be a target phase adjustment for each state of the pulsed RF signal for each recipe step. Further, the target phase adjustment can be editable via a user interface, e.g., via a recipe editor of the user interface. There can be a default value for the target phase adjustment provided when a new recipe step is constructed. For example, there can be a model (based on empirical data) that predicts what the target phase adjustment should be for each recipe step. When constructing each recipe step, the user can have the option to use this model or the user can enter their own values.

[0126] It will be understood that any of the methods described in this disclosure can be implemented to operate automatically by the control system 120. In some embodiments, as discussed, the capacitor tap position can be automatically optimized to minimize the reflected power of the TES system.

[0127] FIG. 10 shows an exemplary schematic diagram of the control system 120 of FIG. 2 according to some embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling a semiconductor manufacturing process implemented in the plasma processing system 100. In various embodiments, the control system 120 includes a processor 1401, a memory hardware unit (HU) 1403 (e.g., memory), an input HU 1405, an output HU 1407, an input / output (I / O) interface 1409, an I / O interface 1411, a network interface controller (NIC) 1413, and a data communication bus 1415. The processor 1401, the memory HU 1403, the input HU 1405, the output HU 1407, the I / O interface 1409, the I / O interface 1411, and the NIC 1413 are in a data communication state with each other via the data communication bus 1415. The input HU 1405 is configured to receive data communication from a plurality of external devices. Examples of the input HU 1405 include a data collection system, a data collection card, and the like. The output HU 1407 is configured to transmit data to a plurality of external devices. An example of the output HU 1407 is a device controller. Examples of the NIC 1413 include a network interface card, a network adapter, and the like. Each of the I / O interfaces 1409 and 1411 is defined to provide compatibility between various hardware units coupled to the I / O interface. For example, the I / O interface 1409 can be defined to convert a signal received from the input HU 1405 into a form, amplitude, and / or speed compatible with the data communication bus 1415. Also, the I / O interface 1407 can be defined to convert a signal received from the data communication bus 1415 into a form, amplitude, and / or speed compatible with the output HU 1407.Although various operations described herein are described as being performed by the processor 1401 of the control system 120, it should be understood that in some embodiments, the various operations can be performed by multiple processors of the control system 120 and / or by multiple processors of multiple computing systems in data communication with the control system 120.

[0128] In some embodiments, the control system 120 is used to control devices in various wafer fabrication systems based at least in part on sensed values. For example, the control system 120 may control one or more of the valve 1417, the filter heater 1419, the wafer support structure heater 1421, the pump 1423, and other devices 1425 based on the sensed values and other control parameters. The valve 1417 can include valves associated with the control of the backside gas supply system 129, the process gas supply system 191, and the temperature control fluid circulation system 125. The control system 120 receives the sensed values from, for example, a pressure manometer 1427, a flow meter 1429, a temperature sensor 1431, and / or other sensors 1433, such as a voltage sensor, a current sensor, etc. The control system 120 may also be used to control the processing conditions within the plasma processing system 100 during the performance of plasma processing operations on the wafer W. For example, the control system 120 can control the type and amount of process gas supplied from the process gas supply system 191 to the plasma processing region 182. Also, the control system 120 can control the operation of the first high-frequency signal generator 147, the second high-frequency signal generator 149, the impedance matching system 143, the TES high-frequency signal generator 403, and the TES impedance matching system 401. Also, the control system 120 can control the operation of the DC supply 117 for the clamp electrode 112. The control system 120 can also control the operation of the lifting device 133 for the lift pin 132 and the operation of the door 107. The control system 120 also controls the operation of the backside gas supply system 129 and the temperature control fluid circulation system 125. The control system 120 also controls the vertical movement of the cantilever arm assembly 115. The control system 120 also controls the operation of the throttle member 196 and the pump that controls suction at the exhaust port 105. The control system 120 also controls the operation of the hold-down control mechanism 913 of the hold-down rod 911 of the TES system 1000. The control system 120 also receives an input from the temperature probe of the TES system 1000.It should be understood that the control system 120 is equipped to programmatically control and / or manually control any function within the plasma processing system 100.

[0129] In some embodiments, the control system 120 is configured to execute a computer program that includes a set of instructions for controlling process timing, process gas delivery system temperature and pressure differential, valve position, process gas mixing, process gas flow rate, backside cooling gas flow rate, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power level, RF frequency, RF pulsing, impedance matching system 143 settings, single - arm assembly position, bias power, and other parameters of a particular process. In some embodiments, other computer programs stored in a memory device associated with the control system 120 may be used. In some embodiments, there is a user interface associated with the control system 120. The user interface includes a display 1435 (e.g., a display screen and / or graphical software display of device and / or process conditions) and user input devices 1437 such as a pointing device, keyboard, touch screen, microphone, etc.

[0130] Software for instructing the operation of control system 120 may be designed or configured in many different forms. To execute various wafer manufacturing processes in a process sequence, a computer program for instructing the operation of control system 120 can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. The compiled object code or script is executed by processor 1401 to perform the tasks identified in the program. Control system 120 can be programmed to control various process control parameters related to process conditions, such as, among other things, filter pressure difference, process gas composition and flow rate, backside cooling gas composition and flow rate, temperature, pressure, plasma conditions such as RF power level and RF frequency, bias voltage, cooling gas / fluid pressure, and chamber wall temperature. Examples of sensors that may be monitored during the wafer manufacturing process include, but are not limited to, mass flow control modules, pressure sensors such as pressure manometer 1427, and temperature sensor 1431. Appropriate programmed feedback and control algorithms can be used with the data from these sensors to control / regulate one or more process control parameters to maintain desired process conditions.

[0131] In some embodiments, control system 120 is part of a broader manufacturing control system. Such manufacturing control systems can include semiconductor processing equipment including processing tools, chambers, and / or wafer processing platforms, and / or specific processing components such as wafer pedestals, gas flow systems. These manufacturing control systems may be incorporated into electronics for controlling operations before, during, and after wafer processing. Control system 120 may control various components or subcomponents of the manufacturing control system. Control system 120 may be programmed to control any of the processes disclosed herein, including supply of process gases, supply of backside cooling gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and operation settings, tools and other transfer tools connected to or interfacing with a particular system, and / or wafer transfer in and out of load locks, according to wafer processing requirements.

[0132] Broadly speaking, control system 120 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that performs functions such as receiving instructions, issuing instructions, controlling operations, enabling wafer processing operations, enabling endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to control system 120 in the form of various individual settings (or program files) that may define process parameters for performing a particular process on a wafer within system 100. In some embodiments, the process parameters may be part of a recipe defined by a process engineer to implement one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0133] In some implementations, the control system 120 may be part of or coupled to a computer that is incorporated in or coupled to the plasma processing system 100, or network-connected to the system 100 in another form, or a combination thereof. For example, the control system 120 may be within all or part of a “cloud” of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system 100, monitor the current progress of a manufacturing operation, investigate the history of past manufacturing operations, investigate trends or performance metrics from multiple manufacturing operations, change the parameters of the current process, and set up processing steps for continuing the current process or starting a new process. In some embodiments, a remote computer (e.g., a server) may provide a process recipe to the system 100 via a network that may include a local network or the Internet.

[0134] The remote computer may include a user interface that enables the input or programming of parameters and / or settings, which are then communicated from the remote computer to the system 100. In some embodiments, the control system 120 receives, in data format, instructions that specify parameters for each processing step carried out during one or more operations. It should be understood that the parameters may be specific to the type of process being carried out within the plasma processing system 100. Thus, as described above, the control system 120 may be distributed by comprising, for example, one or more individual controllers that are networked together and aimed at a common purpose such as the processes and controls described herein. An example of such a distributed controller for such a purpose may be one or more integrated circuits on the plasma processing system 100 that are in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of the remote computer), and these are combined to control the processes carried out in the plasma processing system 100.

[0135] Although not necessarily limiting, exemplary systems that the control system 120 can interface with include a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacture of semiconductor wafers. As described above, depending on the process steps implemented by the tool, the control system 120 can communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or a tool used in material transport for loading and unloading wafer containers between tool positions and / or load ports within a semiconductor manufacturing facility.

[0136] The embodiments described herein may also be implemented in conjunction with various computer system configurations including, for example, a hand-held hardware unit, a microprocessor system, a microprocessor-based or programmable consumer electronics, a minicomputer, a mainframe computer, and the like. The embodiments described herein may also be implemented in conjunction with a distributed computing environment where tasks are performed by a remote processing hardware unit linked through a network. It should be understood that the embodiments described herein, particularly those associated with the control system 120, can utilize various computer-implemented operations involving data stored on a computer system. These operations are operations that require physical manipulation of physical quantities. Any operations described herein that form part of the embodiments are useful mechanical operations. The embodiments also relate to hardware units or devices for performing these operations. The device may be specially constructed for a specific computer. When defined as a dedicated computer, the computer can also execute other processes, program executions, or routines that are not part of the dedicated purpose while being capable of operating for the dedicated purpose. In some embodiments, the operations may be processed by a general-purpose computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained through a network. When data is obtained through a network, the data may be processed by other computers on the network, such as a cloud of computing resources.

[0137] The various embodiments described herein can be realized via process control instructions instantiated as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit capable of storing data that can later be read by a computer system. Examples of non-transitory computer-readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. The non-transitory computer-readable medium can include computer-readable tangible media distributed across a computer system coupled to a network so that the computer-readable code is stored and executed in a distributed fashion.

[0138] The foregoing disclosure includes some details for clarity of understanding, but it will be apparent that certain changes and modifications can be made within the scope of the appended claims. For example, it should be understood that one or more features from any of the embodiments disclosed herein may be combined with one or more features of any of the embodiments disclosed herein. Accordingly, this embodiment should be regarded as illustrative rather than restrictive, and the scope of the claims should not be limited to the details described herein, but may be modified within the scope of the described embodiments and the scope of equivalents. The present disclosure includes the following application examples. [Application Example 1] A method for adjusting a voltage set point for a multi-state pulse RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first multi-state pulse RF signal; applying RF power from a second generator to an edge electrode disposed below an edge ring surrounding the ESC and surrounding the ESC, wherein the RF power from the second generator defines a second multi-state pulse RF signal having a first state and a second state, and for each state of the second multi-state pulse RF signal, the second generator automatically introduces a phase adjustment for substantially aligning the phase with a corresponding state of the first multi-state pulse RF signal; adjusting a voltage set point for the second state of the second multi-state pulse RF signal to adjust the phase adjustment to a target phase adjustment setting. [Application Example 2] The method according to Application Example 1, wherein the target phase adjustment setting is captured via a user interface. [Application Example 3] The method according to Application Example 1, wherein the target phase adjustment setting is calculated based on a model. [Application Example 4] The method according to Application Example 1, wherein the target phase adjustment setting defines a predetermined phase adjustment amount used when the phase of the RF power from the second generator is adjusted. [Application Example 5] The method according to Application Example 1, wherein adjusting the voltage set point to adjust the phase adjustment includes performing a stepwise adjustment on the voltage set point until the phase adjustment reaches the target phase adjustment setting. [Application Example 6] The method according to Application Example 5, wherein the stepwise adjustment is based on a specific voltage set point associated with the first state of the second multi-state pulse RF signal. [Application Example 7] The method according to Application Example 1, wherein when the phase adjustment reaches the target phase adjustment setting, or when the phase adjustment is within a predetermined range from the target phase adjustment setting, the phase adjustment is adjusted to the target phase adjustment setting. [Application Example 8] A method according to Application Example 1, wherein the voltage setpoint is adjusted to adjust the phase adjustment to the target phase adjustment setting, and the voltage setpoint is located in the middle part of the allowable range of the voltage setpoint. [Application Example 9] A method according to Application Example 6, wherein the target phase adjustment setting that facilitates the voltage setpoint being located in the middle part of the allowable range of the voltage setpoint remains substantially the same with respect to a change in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode. [Application Example 10] A method according to Application Example 9, wherein the change in the capacitance of the matching circuit responds to a change in the voltage setpoint of the first state of the second multi-state pulse RF signal. [Application Example 11] A method according to Application Example 10, wherein the change in the voltage setpoint of the first state occurs based on the usage amount of the edge ring. [Application Example 12] A method according to Application Example 11, wherein the usage amount of the edge ring is defined as the amount of time of RF exposure of the edge ring. [Application Example 13] A method for adjusting a voltage setpoint for a multi-state pulse RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first pulse RF signal having a first state and a second state; applying RF power from a second generator to an edge electrode disposed below an edge ring surrounding the ESC and surrounding the ESC, wherein the RF power from the second generator defines a second pulse RF signal having a first state and a second state, the second generator automatically introducing a first phase adjustment that substantially aligns the phase of the first state of the second pulse RF signal with the first state of the first pulse RF signal, the second generator automatically introducing a second phase adjustment that substantially aligns the phase of the second state of the second pulse RF signal with the second state of the first pulse RF signal, and the second phase adjustment is adjusted to a target phase adjustment setting. In response to detecting a change in the second phase adjustment away from the target phase adjustment setting, adjusting a voltage set point for the second state of the second pulsed RF signal to return the second phase adjustment to the target phase adjustment setting, a method comprising. [Application Example 14] The method according to Application Example 13, wherein the target phase adjustment setting is captured via a user interface. [Application Example 15] The method according to Application Example 13, wherein the target phase adjustment setting is calculated based on a model. [Application Example 16] The method according to Application Example 13, wherein the target phase adjustment setting defines a predetermined amount of phase adjustment used when the phase of the second state of the second pulsed RF signal is adjusted. [Application Example 17] The method according to Application Example 13, wherein adjusting the voltage set point to return the second phase adjustment comprises performing a stepwise adjustment on the voltage set point until the second phase adjustment reaches the target phase adjustment setting. [Application Example 18] The method according to Application Example 17, wherein the stepwise adjustment is based on a specific voltage set point associated with the first state. [Application Example 19] The method according to Application Example 13, wherein when the second phase adjustment reaches the target phase adjustment setting, or when the second phase adjustment is within a predetermined range of the target phase adjustment setting, the second phase adjustment is returned to the target phase adjustment setting. [Application Example 20] The method according to Application Example 13, wherein by adjusting the voltage set point to return the second phase adjustment to the target phase adjustment setting, the voltage set point is located in the middle portion of the allowable range of the voltage set point. [Application Example 21] The method according to Application Example 20, wherein the target phase adjustment setting that facilitates the voltage set point being located in the middle portion of the allowable range of the voltage set point remains substantially the same with respect to a change in the capacitance of a matching circuit through which the RF power from the second generator passes when applied to the edge electrode. [Application Example 22] The method according to Application Example 21, wherein the change in the capacitance of the matching circuit responds to a change in the voltage set point of the first state of the second pulsed RF signal. [Application Example 23] The method according to Application Example 22, wherein the change in the voltage set point of the first state of the second pulsed RF signal occurs based on the usage amount of the edge ring. [Application Example 24] The method according to Application Example 23, wherein the usage amount of the edge ring is defined as the amount of time of RF exposure of the edge ring.

Claims

1. A method for adjusting a voltage set point for a multi-state pulse RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first multi-state pulse RF signal; applying RF power from a second generator to an edge electrode disposed below an edge ring surrounding the ESC and surrounding the ESC, wherein the RF power from the second generator defines a second multi-state pulse RF signal having a first state, a second state, and a third state, and for each state of the second multi-state pulse RF signal, the second generator automatically introduces a phase adjustment for substantially aligning the phase with a corresponding state of the first multi-state pulse RF signal; adjusting a voltage set point for the second state of the second multi-state pulse RF signal to adjust the phase adjustment to a target phase adjustment setting; wherein the voltages corresponding to the first state, the second state, and the third state are each greater than zero, the voltage corresponding to the first state is greater than the voltage corresponding to the second state, and the voltage corresponding to the second state is greater than the voltage corresponding to the third state.

2. The method of claim 1, wherein the target phase adjustment setting is captured via a user interface.

3. The method of claim 1, wherein the target phase adjustment setting is calculated based on a model.

4. The method of claim 1, wherein the target phase adjustment setting defines a predetermined amount of phase adjustment used when the phase of the RF power from the second generator is adjusted.

5. The method of claim 1, wherein adjusting the voltage set point to adjust the phase adjustment includes performing a stepwise adjustment on the voltage set point until the phase adjustment reaches the target phase adjustment setting.

6. The method of claim 5, wherein the stepwise adjustment is based on a specific voltage set point associated with the first state of the second multi-state pulse RF signal.

7. The method according to claim 1, wherein when the phase adjustment reaches the target phase adjustment setting, or when the phase adjustment is within a predetermined range from the target phase adjustment setting, the phase adjustment is adjusted to the target phase adjustment setting.

8. The method according to claim 1, wherein by adjusting the voltage setpoint to adjust the phase adjustment to the target phase adjustment setting, the voltage setpoint is located in the middle part of the allowable range of the voltage setpoint.

9. The method according to claim 8, wherein the target phase adjustment setting that facilitates the voltage setpoint being located in the middle part of the allowable range of the voltage setpoint remains substantially the same with respect to a change in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode.

10. The method according to claim 9, wherein the change in the capacitance of the matching circuit responds to a change in the voltage setpoint of the first state of the second multi-state pulsed RF signal.

11. The method according to claim 10, wherein the change in the voltage setpoint of the first state occurs based on the usage amount of the edge ring.

12. The method according to claim 11, wherein the usage amount of the edge ring is defined as the amount of time of RF exposure of the edge ring.

13. A method of adjusting a voltage setpoint for a multi-state pulsed RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first pulsed RF signal having a first state and a second state. Applying RF power from a second generator to an edge electrode disposed below an edge ring surrounding the ESC and surrounding the ESC, wherein the RF power from the second generator defines a second pulsed RF signal having a first state, a second state, and a third state, and the second generator automatically introduces a first phase adjustment that substantially aligns the phase of the first state of the second pulsed RF signal with the first state of the first pulsed RF signal, and the second generator automatically introduces a second phase adjustment that substantially aligns the phase of the second state of the second pulsed RF signal with the second state of the first pulsed RF signal, and the second phase adjustment is adjusted to a target phase adjustment setting, and in response to detecting a change in the second phase adjustment away from the target phase adjustment setting, adjusting a voltage setpoint for the second state of the second pulsed RF signal to return the second phase adjustment to the target phase adjustment setting, and the voltages corresponding to the first state, the second state, and the third state are each greater than zero, the voltage corresponding to the first state is greater than the voltage corresponding to the second state, and the voltage corresponding to the second state is greater than the voltage corresponding to the third state, method.

14. The method according to claim 13, wherein the target phase adjustment setting is captured via a user interface.

15. The method according to claim 13, wherein the target phase adjustment setting is calculated based on a model.

16. The method according to claim 13, wherein the target phase adjustment setting defines a predetermined phase adjustment amount used when the phase of the second state of the second pulsed RF signal is adjusted.

17. The method according to claim 13, wherein adjusting the voltage setpoint to return the second phase adjustment includes performing a stepwise adjustment on the voltage setpoint until the second phase adjustment reaches the target phase adjustment setting.

18. The method according to claim 17, wherein the stepwise adjustment is based on a specific voltage setpoint associated with the first state.

19. The method according to claim 13, wherein when the second phase adjustment reaches the target phase adjustment setting, or when the second phase adjustment is within a predetermined range of the target phase adjustment setting, the second phase adjustment is returned to the target phase adjustment setting.

20. The method according to claim 13, wherein by adjusting the voltage set point to return the second phase adjustment to the target phase adjustment setting, the voltage set point is located in the middle portion of the allowable range of the voltage set point.

21. The method according to claim 20, wherein the target phase adjustment setting that facilitates the voltage set point being located in the middle portion of the allowable range of the voltage set point remains substantially the same with respect to a change in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode.

22. The method according to claim 21, wherein the change in the capacitance of the matching circuit responds to a change in the voltage set point of the first state of the second pulsed RF signal.

23. The method according to claim 22, wherein the change in the voltage set point of the first state of the second pulsed RF signal is generated based on the usage amount of the edge ring.

24. The method according to claim 23, wherein the usage amount of the edge ring is defined as the amount of time of RF exposure of the edge ring.

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