Semiconductor device

Abstract

To provide a semiconductor device applicable to various usage aspects.SOLUTION: A semiconductor device 100 includes: a semiconductor package 110 including an n-type normally OFF transistor 10 and a normally-on transistor 20; a plurality of second terminals 102 provided on the semiconductor package 110, the second terminals being electrically connected to the n-type normally OFF transistor 10 or the normally-on transistor 20 and being lined up in a first direction; a fourth terminal 104 provided on the semiconductor package 110 and electrically connected to the n-type normally OFF transistor 10; and a fifth terminal 105 provided on the semiconductor package 110 and electrically connected to the normally-on transistor 20.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Group III nitrides, such as GaN (gallium nitride)-based semiconductors, are expected as materials for next-generation power semiconductor devices. GaN-based semiconductors have a larger bandgap compared to Si (silicon). Therefore, GaN-based semiconductor devices can realize power semiconductor devices that are smaller and have higher breakdown voltages compared to Si (silicon) semiconductor devices. Also, since the parasitic capacitance can be reduced thereby, power semiconductor devices with high-speed driving can be realized.

[0003] In GaN-based transistors, generally, a HEMT (High Electron Mobility Transistor) structure using a two-dimensional electron gas (2DEG) as carriers is applied. A normal HEMT is a normally-on transistor that conducts even without applying a voltage to the gate. In GaN-based transistors, there is a problem that it is difficult to realize a normally-off transistor that does not conduct unless a voltage is applied to the gate.

[0004] In power supply circuits and the like that handle large power of several hundred V to 1 kV, a normally-off operation is required with emphasis on safety. Therefore, a circuit configuration has been proposed to realize a normally-off operation by performing a cascode connection in which a normally-on GaN-based transistor and a normally-off Si transistor are connected.

[0005] In addition, in the case of a circuit configuration where the main circuit current flowing between the drain and source and the drive current flowing between the gate and source share the source inductance, due to the electromotive force generated in the source inductance with the time change of the main circuit current, the drive current is also modulated. As a result, problems such as delays such as a decrease in the rise speed and fall speed of the power semiconductor device, and ringing in which the drain current and source voltage change drastically with time have occurred. Therefore, a circuit configuration using a Kelvin connection in which the main circuit current and the gate drive current do not share the source inductance has been proposed.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor device applicable to various usage modes.

Means for Solving the Problems

[0008] The semiconductor device according to the embodiment includes a semiconductor package having a normally-off transistor and a normally-on transistor cascode-connected to the normally-off transistor, and is provided in the semiconductor package, electrically connected to the normally-off transistor, and arranged in parallel in the first direction respectively and passed by a virtual straight line a plurality of second terminals, a fourth terminal provided in the semiconductor package and electrically connected to the normally-off transistor, and a fifth terminal provided in the semiconductor package and electrically connected to the normally-on transistor arranged in the first direction respectively, and a plurality of them passed by a virtual straight line and includes a fifth terminal.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members may be denoted by the same reference numerals. Also, the description of members etc. once described may be omitted as appropriate.

[0011] In addition, in this specification, the semiconductor device refers to a power module in which a plurality of elements such as discrete semiconductors are combined, or an intelligent power module in which a drive circuit for driving these elements and a self-protection function are incorporated into a plurality of elements such as discrete semiconductors, or the entire system including a power module and an intelligent power module.

[0012] In addition, in this specification, the "GaN-based semiconductor" is a general term for semiconductors including GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and intermediate compositions thereof.

[0013] (First Embodiment) The semiconductor device of the embodiment includes an n-type channel normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a Zener diode having a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode, a semiconductor package including a semiconductor package, a first terminal provided in the semiconductor package and electrically connected to the first electrode, a plurality of second terminals provided in the semiconductor package and electrically connected to the first electrode and arranged in the first direction, a third terminal provided in the semiconductor package and electrically connected to the fourth electrode, a plurality of fourth terminals provided in the semiconductor package and electrically connected to the first control electrode and arranged in the first direction, and a plurality of fifth terminals provided in the semiconductor package and electrically connected to the second control electrode and arranged in the first direction

[0014] FIG. 1 is a schematic diagram of a power conversion system 900 according to the present embodiment

[0015] The power conversion system 900 includes a power conversion device 800 and a motor 810

[0016] The power conversion device 800 includes transistors 600a, 600b, 600c, 600d, 600e, and 600f, a DC power supply 300, a converter 400, and a smoothing capacitor 500. As will be described later, the transistors 600a, 600b, 600c, 600d, 600e, and 600f may include a plurality of transistors and other elements

[0017] The DC power supply 300 outputs a DC voltage. The converter 400 is a DC-DC converter that converts the DC voltage output by the DC power supply 300 into another DC voltage. The smoothing capacitor 500 smoothes the voltage output by the converter 400

[0018] Each of transistors 600a, 600b, 600c, 600d, 600e, and 600f has a semiconductor device 100 described later. By transistors 600a, 600b, 600c, 600d, 600e, and 600f, the DC voltage smoothed by smoothing capacitor 500 is converted into AC.

[0019] For example, transistor 600a has a first transistor electrode 602 and a second transistor electrode 604. Also, transistor 600b has a third transistor electrode 606 and a fourth transistor electrode 608. Transistors 600a and 600b are electrically connected to each other by electrically connecting the first transistor electrode 602 and the fourth transistor electrode 608.

[0020] Similarly, transistors 600c and 600d and transistors 600e and 600f are electrically connected to each other, respectively.

[0021] Motor 810 has coils 810u, 810v, and 810w. One ends of coils 810u, 810w, and 810v are electrically connected to each other at neutral point 820. The other end of coil 810u is electrically connected between transistors 600a and 600b. The other end of coil 810v is electrically connected between transistors 600c and 600d. Also, the other end of coil 810w is electrically connected between transistors 600e and 600f.

[0022] Note that the ground in the power conversion device 800 of this embodiment may be electrically connected, for example, between a plurality of provided smoothing capacitors 500. Also, for example, the ground in the power conversion device 800 may be electrically connected to a wire in which transistors 600b, 600d, and 600f are electrically connected to each other.

[0023] FIG. 2 is a circuit diagram of the semiconductor device 100 of the present embodiment. The semiconductor device 100 of the present embodiment is, for example, a power module with a rated voltage of 600V or 1200V.

[0024] The semiconductor device 100 includes an n-type normally-off transistor 10, a normally-on transistor 20, a first diode 40, a Zener diode 80, a first terminal 101, a second terminal 102, a third terminal 103, a fourth terminal 104, a fifth terminal 105, and a semiconductor package 110.

[0025] The n-type normally-off transistor 10 has a first electrode 11, a second electrode 12, and a first control electrode 13.

[0026] The n-type normally-off transistor 10 is a transistor in which no drain current flows when no voltage is input to the gate. The n-type normally-off transistor 10 is, for example, an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a Si (silicon) semiconductor. For example, the first electrode 11 is a source electrode, the second electrode 12 is a drain electrode, and the first control electrode 13 is a gate electrode. The n-type normally-off transistor 10 also has a body diode (parasitic diode) 14 having an anode 15 and a cathode 16. The breakdown voltage of the n-type normally-off transistor 10 is, for example, 10V or more and 50V or less.

[0027] The normally-on transistor 20 has a third electrode 21, a fourth electrode 22, and a second control electrode 23. The third electrode 21 is electrically connected to the second electrode 12.

[0028] The normally-on transistor 20 is a transistor in which a drain current flows even when no voltage is input to the gate. The normally-on transistor 20 is, for example, a HEMT (High Electron Mobility Transistor) using a GaN-based semiconductor. For example, the third electrode 21 is a source electrode, the fourth electrode 22 is a drain electrode, and the second control electrode 23 is a gate electrode.

[0029] The breakdown voltage of the normally-on transistor 20 is higher than that of the n-type normally-off transistor 10. The breakdown voltage of the normally-on transistor 20 is, for example, 40V or more and 3500V or less.

[0030] The semiconductor device 100 of the present embodiment realizes a normally-off operation by electrically connecting the n-type normally-off transistor 10 and the normally-on transistor 20 in series. For example, when the semiconductor device 100 is used for the transistor 600b (FIG. 1), the third transistor electrode 606 is electrically connected to the first electrode 11, and the fourth transistor electrode 608 is electrically connected to the fourth electrode 22.

[0031] The first diode 40 has a first anode 41 and a first cathode 42. The first anode 41 is electrically connected to the second control electrode 23. The first cathode 42 is electrically connected to the third electrode 21. The first diode 40 is preferably a Schottky barrier diode with a fast response speed. Note that the first diode 40 can also be preferably used even if it is a PN junction diode. The use of the first diode 40 will be described in the seventh usage mode of the semiconductor device 100 of the embodiment, which will be described later.

[0032] The Zener diode 80 has a second anode 81 and a second cathode 82. The second anode 81 is electrically connected to the first electrode 11. Also, the second cathode 82 is electrically connected to the second electrode 12. In other words, the Zener diode 80 is connected in parallel to the n-type normally-off transistor 10. When an overvoltage due to a surge or the like occurs at the connection part between the n-type normally-off transistor 10 and the normally-on transistor 20, when the overvoltage reaches the Zener voltage, charges are released to the Zener diode 80. Therefore, an increase in the voltage at the connection part is suppressed, and an increase in the leakage current of the gate insulating film of the normally-on transistor 20 and a breakdown of the gate insulating film are suppressed.

[0033] The n-type normally-off transistor 10, the normally-on transistor 20, the first diode 40, and the Zener diode 80 are provided in the semiconductor package 110. In other words, the semiconductor package 110 has the n-type normally-off transistor 10, the normally-on transistor 20, the first diode 40, and the Zener diode 80.

[0034] The first terminal 101 is provided on the semiconductor package 110 and is electrically connected to the first electrode 11. The first terminal 101 is used, for example, as the source terminal of the semiconductor device 100.

[0035] The second terminal 102 is provided on the semiconductor package 110 and is electrically connected to the first electrode 11. The second terminal 102 is used, for example, as a terminal for performing a Kelvin connection to the semiconductor device 100.

[0036] The third terminal 103 is provided on the semiconductor package 110 and is electrically connected to the fourth electrode 22. The third terminal 103 is used, for example, as the drain terminal of the semiconductor device 100.

[0037] The fourth terminal 104 is provided on the semiconductor package 110 and is electrically connected to the first control electrode 13. The fourth terminal 104 is used, for example, to input a gate signal to the n-type normally-off transistor 10.

[0038] The fifth terminal 105 is provided on the semiconductor package 110 and is electrically connected to the second control electrode 23. The fifth terminal 105 is used, for example, to input a gate signal to the normally-on transistor 20.

[0039] FIG. 3 is a schematic top view of the semiconductor device 100 of the present embodiment.

[0040] FIG. 3(a) is a schematic top view of the semiconductor device 100 of the present embodiment. FIG. 3(b) is an example of a part of the schematic top view of the semiconductor device 100 of the present embodiment.

[0041] The n-type normally-off transistor 10 is, for example, a vertical Si-MOSFET, and the first electrode 11 and the first control electrode 13 are provided on the upper surface. The first electrode 11 is electrically connected to the first terminal 101 via, for example, a bonding wire 116. Also, the first electrode 11 is electrically connected to the second terminal 102 via, for example, a bonding wire 122. The second electrode 12 is provided on the lower surface of the n-type normally-off transistor 10 (not shown). The second electrode 12 is electrically connected to a metal plate 112, for example, plated with nickel, palladium, gold, etc. on Cu (copper). The first control electrode 13 is electrically connected to the fourth terminal 104 via a bonding wire 124.

[0042] The second anode 81 of the Zener diode 80 is provided on the upper surface of the Zener diode 80. The second anode 81 is electrically connected to the first terminal 101 via, for example, a bonding wire 114. That is, the second anode 81 is electrically connected to the first electrode 11 via, for example, a bonding wire 114, the first terminal 101, and a bonding wire 116. Also, a second cathode 82 is provided on the lower surface of the Zener diode 80 (not shown). The second cathode 82 is electrically connected to, for example, a plate 112. And the second cathode 82 is electrically connected to the second electrode 12 via, for example, the plate 112.

[0043] The third electrode 21, the fourth electrode 22, and the second control electrode 23 of the normally-on transistor 20 are provided on the upper surface of the normally-on transistor 20. The third electrode 21 is connected to the plate 112 via, for example, a bonding wire 126. That is, the third electrode 21 is electrically connected to the second electrode 12 via, for example, a bonding wire 126 and the plate 112. The fourth electrode 22 is electrically connected to the third terminal 103 via, for example, a bonding wire 128. The second control electrode 23 is electrically connected to the fifth terminal 105 via, for example, a bonding wire 118.

[0044] The first anode 41 of the first diode 40 is provided on the upper surface of the first diode 40. The first anode 41 is electrically connected to the fifth terminal 105 via, for example, a bonding wire 120. That is, the first anode 41 is electrically connected to the second control electrode 23 via a bonding wire 120, the fifth terminal 105, and a bonding wire 118. Also, a first cathode 42 is provided on the lower surface of the first diode 40 (not shown). The first cathode 42 is electrically connected to the third electrode 21 via the plate 112 and a bonding wire 126.

[0045] Note that the material and number of bonding wires used in the semiconductor device 100 of the present embodiment are not particularly limited. Further, not limited to bonding wires, as shown in FIG. 21, connection by a metal plate may be used.

[0046] The semiconductor device 100 has a plurality of second terminals 102a, 102b, and 102c as the second terminal 102. The plurality of second terminals 102a, 102b, and 102c are electrically connected to each other by a terminal 102d.

[0047] Further, the semiconductor device 100 has a plurality of fifth terminals 105a, 105b, and 105c as the fifth terminal. The fifth terminals 105a, 105b, and 105c are electrically connected to each other by a terminal 105d.

[0048] Similarly, the semiconductor device 100 has a plurality of first terminals 101a, 101b, 101c,..., 101q that are electrically connected to each other as the first terminal 101. Note that the first terminals 101a, 101b, 101c,..., 101q do not have to be separated. Further, the semiconductor device 100 has a plurality of third terminals 103a, 103b, 103c,..., 103q that are electrically connected to each other as the third terminal 103. Note that the semiconductor device 100 may further have terminals 106a, 106b, 106c,..., 106k as the terminal 106 and terminals 107a, 107b, 107c, and 107d as the terminal 107, which are other terminals.

[0049] Note that the third terminals 103a, 103b, 103c,..., 103q do not have to be separated as shown in FIG. 20. The same applies to the second terminal 102, the fifth terminal 105, the first terminal 101, the terminal 106, and the terminal 107.

[0050] For example, as shown in FIG. 3(b), the plurality of second terminals 102a, 102b, and 102c are each passed through by a virtual straight line l 1 Thereby. Further, the plurality of fifth terminals 105a, 105b, and 105c are each passed through by a virtual straight line l1 It is passed by. In other words, the plurality of second terminals 102a, 102b, and 102c are arranged in the first direction. Also, the plurality of fifth terminals 105a, 105b, and 105c are arranged in the first direction. Here, the first direction is, for example, the direction in which the first terminal 101 and the third terminal 103 face each other.

[0051] Note that the virtual straight line l 1 is not actually described or provided in the semiconductor device 100.

[0052] Also, it is preferable that the plurality of second terminals 102a, 102b, and 102c and the plurality of fifth terminals 105a, 105b, and 105c are provided at the end of the semiconductor package 110.

[0053] Also, it is preferable that none of the first terminal 101, the third terminal 103, and the fourth terminal 104 are provided between the plurality of second terminals 102a, 102b, and 102c and the plurality of fifth terminals 105a, 105b, and 105c. In other words, it is preferable that the plurality of second terminals 102a, 102b, and 102c and the plurality of fifth terminals 105a, 105b, and 105c are provided adjacent to each other without any of the first terminal 101, the third terminal 103, and the fourth terminal 104 intervening therebetween.

[0054] Also, it is preferable that the fourth terminal 104 is provided at the end of the semiconductor package 110.

[0055] Also, it is preferable that none of the first terminal 101, the third terminal 103, and the fourth terminal 105 are provided between the plurality of second terminals 102a, 102b, and 102c and the fourth terminal 104. In other words, it is preferable that the plurality of second terminals 102a, 102b, and 102c and the fourth terminal 104 are provided adjacent to each other without any of the first terminal 101, the third terminal 103, and the fifth terminal 105 intervening therebetween.

[0056] Note that, in the semiconductor device 100 of the present embodiment, the number of the plurality of second terminals 102a, 102b, and 102c is three, but it is not limited to three. Also, in the semiconductor device 100 of the present embodiment, the number of the plurality of fifth terminals 105a, 105b, and 105c is three, but it is not limited to three.

[0057] FIG. 4 is a circuit diagram showing a first usage mode of the semiconductor device 100 of the present embodiment. The chip resistor 150a as the chip resistor 150 has a sixth terminal 152a as the sixth terminal 152 and a seventh terminal 154a as the seventh terminal 154. And the sixth terminal 152a is electrically connected to the second terminal 102, and the seventh terminal 154a is electrically connected to the fifth terminal 105. The chip resistor 150a is, for example, a 0603 type chip resistor with a long side of 0.6 mm and a short side of 0.3 mm.

[0058] FIG. 5 is a schematic top view showing a first usage mode of the semiconductor device 100 of the present embodiment. The sixth terminal 152a is electrically connected to the second terminal 102a as the second terminal 102 via the metal plate 142. Also, the seventh terminal 154a is electrically connected to the fifth terminal 105c via the metal plate 140.

[0059] FIG. 6 is a schematic top view showing a second usage mode of the semiconductor device 100 of the present embodiment. The chip resistor 150b as the chip resistor 150 has a sixth terminal 152b as the sixth terminal 152 and a seventh terminal 154b as the seventh terminal 154. And the sixth terminal 152b is electrically connected to the second terminal 102a as the second terminal 102, and the seventh terminal 154b is electrically connected to the fifth terminal 105b as the fifth terminal 105. The chip resistor 150b is, for example, a 1005 type chip resistor with a long side of 1.0 mm and a short side of 0.5 mm.

[0060] FIG. 7 is a schematic top view showing a third usage mode of the semiconductor device 100 of the present embodiment. The chip resistor 150c as the chip resistor 150 has a sixth terminal 152c as the sixth terminal 152 and a seventh terminal 154c as the seventh terminal 154. And the sixth terminal 152c is electrically connected to the second terminal 102b as the second terminal 102, and the seventh terminal 154c is electrically connected to the fifth terminal 105b as the fifth terminal 105. The chip resistor 150c is, for example, a 1608 type chip resistor with a long side of 1.6 mm and a short side of 0.8 mm.

[0061] FIG. 8 is a circuit diagram showing a fourth usage mode of the semiconductor device 100 of the present embodiment. The chip ferrite bead 156 has a sixth terminal 152 and a seventh terminal 154. And the sixth terminal 152 is electrically connected to the second terminal 102, and the seventh terminal 154 is electrically connected to the fifth terminal 105.

[0062] FIG. 9 is a schematic top view showing a fourth usage mode of the semiconductor device 100 of the present embodiment. The sixth terminal 152 is electrically connected to the second terminal 102b as the second terminal 102 via the metal plate 142. Also, the seventh terminal 154 is electrically connected to the fifth terminal 105b as the fifth terminal 105 via the metal plate 140.

[0063] FIG. 10 is a circuit diagram showing a fifth usage mode of the semiconductor device 100 of the present embodiment. The third cathode 164 of the first chip diode 160 is electrically connected to the second terminal 102. The third anode 162 of the first chip diode 160 is electrically connected to the fifth terminal 105.

[0064] Further, the sixth terminal 152 of the chip resistor 150a is electrically connected to the second terminal 102. The fourth cathode 174 of the second chip diode 170 is electrically connected to the fifth terminal 105. The fourth anode 172 of the second chip diode 170 is electrically connected to the seventh terminal 154. As a result, an electric circuit in which the second chip diode 170 and the chip resistor 150a are electrically connected is electrically connected in parallel to the first chip diode 160.

[0065] When a suddenly large current flows from the side of the fifth terminal 105 to the side of the second terminal 102, the large current applied to the first chip diode 160 flows. On the other hand, when a suddenly large current flows from the side of the second terminal 102 to the side of the fifth terminal 105, the large current applied to the second chip diode 170 flows, but the current is limited by the chip resistor 150a. Thereby, a suddenly large current flowing when the n-type normally-off transistor 10 and the normally-on transistor 20 provided in the semiconductor package 110 change from off to on is suppressed, and an increase in noise is suppressed.

[0066] In addition, although the embodiment using the chip resistor 150a is described in FIG. 10, a chip ferrite bead 156 may be used instead of the chip resistor 150a.

[0067] FIG. 11 is a schematic top view showing a fifth usage mode of the semiconductor device 100 of the present embodiment. The metal plate 146 is electrically connected to the second terminal 102c. The sixth terminal 152 and the third cathode 164 are electrically connected to the metal plate 146. The metal plate 144 is electrically connected to the fifth terminal 105a. The third anode 162 and the fourth cathode 174 are electrically connected to the metal plate 144. The seventh terminal 154 and the fourth anode 172 are connected by the metal plate 148.

[0068] FIG. 12 is a schematic top view showing a sixth usage mode of the semiconductor device 100 according to the present embodiment. The second terminal 102 and the fifth terminal 105 are electrically connected by a wiring 180. A mode of connection using the wiring 180 as in the present usage mode may be employed. Note that the second terminal 102 may be any of the second terminals 102a, 102b, and 102c. Also, the fifth terminal 105 may be any of the fifth terminals 105a, 105b, and 105c.

[0069] FIG. 13 is a circuit diagram showing a seventh usage mode of the semiconductor device 100 according to the present embodiment.

[0070] The capacitor 85 has an eighth terminal 86 and a ninth terminal 87. The eighth terminal 86 is electrically connected to the fifth terminal.

[0071] The resistor 75 has a tenth terminal 76 and an eleventh terminal 77. The tenth terminal 76 is electrically connected to the fourth terminal 104.

[0072] The second diode 70 has a fifth anode 71 and a fifth cathode 72. The fifth anode 71 is electrically connected to the eleventh terminal 77. The fifth cathode 72 is electrically connected to the fourth terminal 104 and the tenth terminal 76. The second diode 70 is provided electrically in parallel with the resistor 75.

[0073] The third diode 90 has a third anode 91 and a third cathode 92. The third anode 91 is electrically connected to the fifth terminal 105 and the eighth terminal 86. The third cathode 92 is electrically connected to the ninth terminal 87, the fifth anode 71, and the eleventh terminal 77. The third diode 90 is provided electrically in parallel with the capacitor 85.

[0074] The second diode 70 and the third diode 90 are preferably Schottky barrier diodes with a high response speed. Note that the second diode 70 and the third diode 90 may be PN junction diodes and can be preferably used.

[0075] The capacitor 85 is preferably a ceramic capacitor because of its excellent frequency characteristics. However, as the capacitor 85, other film capacitors, aluminum electrolytic capacitors, tantalum electrolytic capacitors, etc. can also be preferably used.

[0076] The gate resistor 94 has a terminal 93 and a terminal 95. The terminal 93 is connected to the third cathode 92, the ninth terminal 87, the fifth anode 71, and the eleventh terminal 77.

[0077] The signal source 98 outputs a signal such as a square wave, for example.

[0078] The gate drive circuit 96 is connected to the terminal 95. And the gate drive circuit 96 outputs a signal for driving the n-type normally-off transistor 10 and the normally-on transistor 20 based on the signal output from the signal source 98. Incidentally, the ground of the gate drive circuit 96 is connected to the second terminal 102.

[0079] The gate drive circuit 96 is an IC in which a plurality of elements are integrated on one chip, or an electronic circuit board on which a plurality of electronic components are arranged.

[0080] Next, an example of the operation of the seventh usage mode of the semiconductor device 100 of the present embodiment will be described.

[0081] For example, consider the case of outputting a square wave that reciprocates between 0V and V g_on using the signal source 98 and the gate drive circuit 96.

[0082] FIG. 14 is a schematic diagram showing an example of V g_on . FIG. 14(a) shows that the output voltage of the gate drive circuit 96 is 0V output during the time t 1 and V output during the time t 2 g_on ​This shows the case of a square wave that repeats between and. FIG. 14(b) shows that the output voltage of the first gate drive circuit 96a is the voltage V output during time t 1 and the voltage V output during time t 1 and the sum of V and the square wave that repeats between and. In the case of FIG. 14(b), V 2 = V 1 + V 2 (V g_on = |V 1 | + |V 2 (V g_on = |V 1 | + |V 2 |)). FIG. 14(c) shows the case where a negative voltage is output during time t 1 . In the case of FIG. 14(c), V g_on = |V 2 | - |V 1 |. Thus, the output voltage of the gate drive circuit 96 is a voltage that changes with time. And, for example, the maximum voltage among the output voltages of the gate drive circuit 96 is V g_on . Note that in FIG. 14, t 1 = t 2 is shown for illustration, but t 1 and t 2 may be different. Also, the way the output voltage of the gate drive circuit 96 changes with time is not limited to that shown in FIG. 14. Also, V g_on can be easily measured using a commercially available oscilloscope or the like. Also, V g_on is the voltage measured with reference to the voltage of the first terminal 101 or the first electrode 11. Here, "with reference to the voltage" means, for example, "setting the voltage to 0V".

[0083] When V g_on is output from the gate drive circuit 96, current flows from the capacitor 85 through the first diode 40. Between the second control electrode 23 and the third electrode 21, there is the forward voltage V FA voltage corresponding to this is input. As a result, the normally-on transistor 20 turns on. On the other hand, when 0V is output from the gate drive circuit 96, a current flows in the reverse direction from the parasitic capacitance C (not shown) of the normally-on transistor 20 to the capacitor 85 via gs . A negative voltage (V F - V g_on ) corresponding to the difference between V F and V g_on is input between the second control electrode 23 and the third electrode 21. If the negative voltage (V F - V g_on ) is lower than the threshold voltage of the normally-on transistor 20, it is possible to turn off the normally-on transistor 20. gs Also, if V g_on is higher than the threshold voltage of the n-type normally-off transistor 10, it is possible to turn on the n-type normally-off transistor 10 when V g_on is output from the gate drive circuit 96. F g_on F g_on F g_on

[0084] g_on g_on

[0085] Here, when the semiconductor device 100 transitions from off to on, it is desirable that the n-type normally-off transistor 10 turns on before the normally-on transistor 20. If the normally-on transistor 20 turns on first, a high voltage is applied to the connection portion between the second electrode 12 and the third electrode 21, so the characteristics of the n-type normally-off transistor 10 with low breakdown voltage may deteriorate.

[0086] In the semiconductor device 100 of the present embodiment, when the semiconductor device 100 transitions from the off state to the on state, the current output from the gate drive circuit 96 flows through the second diode 70. Therefore, the charging of the first control electrode 13 is not affected by the resistance 75. Accordingly, the first control electrode 13 can be charged promptly. Thus, when the semiconductor device 100 transitions from the off state to the on state, it is possible to surely turn on the n-type normally-off transistor 10 before the normally-on transistor 20. As a result, the reliability of the semiconductor device is improved. ​​​​​​​​​

[0087] Also, by providing the resistor 75, the turn-off timing of the n-type normally-off transistor 10 can be delayed by a desired time from the turn-off timing of the normally-on transistor 20. Further, depending on the characteristics of the second diode 70, the resistance value of the resistor 75, and the design of the square wave shape, it is possible to operate while keeping the n-type normally-off transistor 10 in the on state.

[0088] Note that consider the case where 0V is output by the signal source 98 and the gate drive circuit 96, and the n-type normally-off transistor 10 and the normally-on transistor 20 are off. When a high voltage is applied to the fourth electrode 22, the voltage of the third electrode 21 increases. At this time, there is a possibility that the off state of the normally-on transistor 20 cannot be maintained. Therefore, the third diode 90 is provided to short-circuit the gate drive circuit 96 and the second control electrode 23 so that the off state of the normally-on transistor 20 is maintained.

[0089] Note that in the above, the electrical connection via the metal plates 140, 142, 144, and 146 is described. However, the electrical connection of the second terminal 102 and the fifth terminal 105 in the semiconductor device 100 of the embodiment may be an electrical connection that does not pass through the metal plates 140, 142, 144, and 146.

[0090] Next, the operation and effects of the semiconductor device 100 of the embodiment will be described.

[0091] FIG. 15 is a circuit diagram of a semiconductor device 1000 which is a comparative form of the embodiment. In the semiconductor device 1000, the second terminal 102, the fifth terminal 105, the first diode 40, and the Zener diode 80 are not provided. Also, the second control electrode 23 and the first electrode 11 are electrically connected via the wiring 1002. For example, a signal source and a gate drive circuit are connected to the first control electrode 13 via the fourth terminal 104 to input a signal for controlling the n-type normally-off transistor 10. The voltage input to the second control electrode 23 is determined by the difference between the voltage of the second electrode 12 and the voltage of the first electrode 11, that is, the drain-source voltage Vds of the n-type normally-off transistor 10. Thereby, it is possible to control both the n-type normally-off transistor 10 and the normally-on transistor 20.

[0092] Here, when dV / dt, which is the time change of the voltage accompanying switching, occurs in an unintended form, suppression may be required. As a method of controlling dV / dt, for example, a method of selecting a resistor having an appropriate resistance value and connecting the first electrode 11 and the second control electrode 23 with such a resistor can be considered. However, the resistance value of the resistor connecting the first electrode 11 and the second control electrode 23 varies depending on the specifications of the power conversion system 900 in which the semiconductor device 1000 is used. Therefore, it is difficult to appropriately select the resistance value of the resistor connecting the first electrode 11 and the second control electrode 23 without actually using the semiconductor device 1000 in the power conversion system 900 and conducting trial and error. However, since the connection between the first electrode 11 and the second control electrode 23 is performed within the semiconductor package 110, there is a problem that it is not possible to easily select a resistor and connect the resistor.

[0093] Also, when power is switched, a signal having a high frequency is generated, so it is preferable to connect the first electrode 11 and the second control electrode 23 with a short wiring length. However, the sizes of chip resistors and chip ferrite beads, which are preferably used as resistors, may have different sizes depending on the resistance value of the resistor. Therefore, the connection has a wiring length that varies greatly depending on the resistance value, and there are cases where dV / dt cannot be controlled well and parasitic oscillation occurs.

[0094] Also, for example, when the semiconductor device 100 is used in the seventh usage mode, as described above, the reliability of the semiconductor device 100 is improved. However, depending on the specifications of the power conversion system 900, there may be cases where other usage modes are appropriate. Therefore, there has been a demand for a semiconductor device that can be easily used in various usage modes.

[0095] Therefore, in the semiconductor device 100 of the embodiment, a plurality of second terminals 102 and a plurality of fifth terminals 105 passed through by the virtual straight line l 1 are provided. In other words, since a plurality of second terminals 102 and a plurality of fifth terminals 105 arranged in the first direction are provided, in any of the first usage mode shown in FIGS. 4 and 5, the second usage mode shown in FIG. 6, the third usage mode shown in FIG. 7, the fourth usage mode shown in FIGS. 8 and 9, and the fifth usage mode shown in FIGS. 10 and 11, according to the specifications of the power conversion system 900 and the sizes of chip resistors, chip ferrite beads, etc. used, a plurality of second terminals 102 and a plurality of fifth terminals 105 can be appropriately selected, and connections such as resistors can be made with a short wiring length. Therefore, control of dV / dt can be easily performed.

[0096] Also, depending on the specifications of the power conversion system 900, the semiconductor device 100 can be used in the sixth usage mode shown in FIG. 12. The sixth usage mode can be regarded as the connection between the second control electrode 23 and the first electrode 11 by the wiring 1002 of the semiconductor device 1000 serving as a comparative form being performed outside the semiconductor package 110 using the wiring 180.

[0097] Furthermore, depending on the specifications of the power conversion system 900, the semiconductor device 100 can be used in the seventh usage mode shown in FIG. 13.

[0098] In this way, the semiconductor device 100 can be appropriately used according to the specifications of the power conversion system 900. Therefore, it becomes possible to provide a semiconductor device applicable to various usage modes.

[0099] FIG. 16 is a graph for explaining the operation and effect of the semiconductor device 100 of the embodiment. FIG. 16(a) is a graph showing the time change when the resistance of the chip resistor 150 is changed with respect to the current flowing through the n-type normally-off transistor 10 and the normally-on transistor 20 when the semiconductor device 100 of the embodiment is used in the first usage mode. FIG. 16(b) is a graph showing the time change of the voltage between the first electrode 11 and the fourth electrode 22 when the resistance of the chip resistor 150 is changed when the semiconductor device 100 of the embodiment is used in the first usage mode. FIG. 16(c) is a graph showing the time change when the resistance of the chip resistor 150 is changed with respect to the product of the current flowing through the n-type normally-off transistor 10 and the normally-on transistor 20 and the voltage between the first electrode 11 and the fourth electrode 22 when the semiconductor device 100 of the embodiment is used in the first usage mode. As shown in FIG. 16(a), when the resistance value of the chip resistor 150 is small, the oscillation of the current does not easily decay even after a long time, and the amplitude of the oscillation is large. When the resistance value of the chip resistor 150 is large, the oscillation of the current decays in a short time, and the amplitude of the oscillation is small. As shown in FIG. 16(b), when the resistance of the chip resistor 150 is large, it tends to take a longer time for the voltage to drop from 400V to 0V. When the resistance of the chip resistor 150 is small, it tends to take a shorter time for the voltage to drop from 400V to 0V, and the control of dV / dt can be easily performed. As shown in FIG. 16(c), when the resistance value of the chip resistor 150 is larger, the product of the above-described current and voltage tends to be smaller. In the semiconductor device 100 of the embodiment, it is possible to appropriately select the resistance value of the chip resistor 150 according to the specifications of the power conversion system 900 and perform the operation in each preferable mode.

[0100] Incidentally, it is preferable that the plurality of second terminals 102 and the plurality of fifth terminals 105 are provided at the end of the semiconductor package 110. Further, it is preferable that none of the first terminal 101, the third terminal 103, and the fourth terminal 104 is provided between the plurality of second terminals 102 and the plurality of fifth terminals 105. This is to minimize the connection of components such as the chip resistor 150.

[0101] Further, it is preferable that the fourth terminal 104 is provided at the end of the semiconductor package 110. Further, it is preferable that none of the first terminal 101, the third terminal 103, and the fifth terminal 105 is provided between the plurality of second terminals 102a, 102b, and 102c and the fourth terminal 104. This is to reduce the parasitic inductance generated by the wiring.

[0102] Further, it is preferable that the fifth terminal 105 is provided at the end of the semiconductor package 110. Further, it is preferable that none of the first terminal 101, the third terminal 103, and the fourth terminal 104 is provided between the plurality of second terminals 102a, 102b, and 102c and the fifth terminal 105. This is to reduce the parasitic inductance generated by the wiring.

[0103] According to the semiconductor device 100 of the present embodiment, it is possible to provide a semiconductor device applicable to various usage modes.

[0104] (Second Embodiment) The semiconductor device of this embodiment includes an n-type normally-off transistor having a first electrode, a second electrode, and a first control electrode; a third electrode electrically connected to the second electrode; a fourth electrode; a normally-on transistor having a second control electrode; a first anode electrically connected to the second control electrode; a first diode having a first cathode electrically connected to the first electrode; a second anode electrically connected to the first electrode; a Zener diode having a second cathode electrically connected to the second electrode; a semiconductor package including these components; a first terminal provided in the semiconductor package and electrically connected to the first electrode; a plurality of second terminals provided in the semiconductor package, electrically connected to the first electrode, and arranged in the first direction; a third terminal provided in the semiconductor package and electrically connected to the fourth electrode; a fourth terminal provided in the semiconductor package and electrically connected to the first control electrode; and a plurality of fifth terminals provided in the semiconductor package, electrically connected to the second control electrode, and arranged in the first direction. Here, the description of the content overlapping with the first embodiment is omitted.

[0105] FIG. 17 is a circuit diagram of the semiconductor device 200 of this embodiment. The semiconductor device 200 is different from the semiconductor device 100 of the first embodiment in that the first cathode 42 of the first diode 40 is electrically connected to the first electrode 11. Since the plurality of second terminals 102 are electrically connected to the first electrode 11, the first cathode 42 is electrically connected to the plurality of second terminals 102.

[0106] Also in the semiconductor device 200 of this embodiment, it is possible to provide a semiconductor device applicable to various usage modes.

[0107] (Third Embodiment) The semiconductor device of this embodiment includes a p-type channel normally-off transistor (hereinafter referred to as a p-type normally-off transistor) having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a semiconductor package having the above, a first terminal provided in the semiconductor package and electrically connected to the first electrode, a second terminal provided in the semiconductor package, electrically connected to the second electrode or the third electrode, and arranged in a first direction, a third terminal provided in the semiconductor package and electrically connected to the fourth electrode, a fourth terminal provided in the semiconductor package, electrically connected to the first control electrode and arranged in the first direction, and a fifth terminal provided in the semiconductor package, electrically connected to the second control electrode and arranged in the first direction respectively. Here, the description of the content overlapping with the first and second embodiments is omitted.

[0108] FIG. 18 is a circuit diagram of the semiconductor device 210 of this embodiment. In the semiconductor device 210, a p-type normally-off transistor 30 is used instead of the n-type normally-off transistor 10. The p-type normally-off transistor 30 has a first electrode 31, a second electrode 32, and a first control electrode 33. The p-type normally-off transistor 30 is a transistor in which no drain current flows when no voltage is input to the gate. The p-type normally-off transistor 30 is, for example, a p-type channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a Si (silicon) semiconductor. For example, the first electrode 31 is a drain electrode, the second electrode 32 is a source electrode, and the first control electrode 33 is a gate electrode. Further, the p-type normally-off transistor 30 has a body diode (parasitic diode) 34 having an anode 35 and a cathode 36. The breakdown voltage of the p-type normally-off transistor 30 is, for example, 10V or more and 50V or less.

[0109] Also, the point that the second terminal 102 is electrically connected to the second electrode 32 (or the third electrode 21) is different from the semiconductor device 100 of the first embodiment. This is because in the case of an n-type normally-off transistor, control is performed by the voltage between the first electrode 11, which is the source electrode, and the first control electrode 13, while in the case of a p-type normally-off transistor, control is performed by the voltage between the second electrode 32, which is the source electrode, and the first control electrode 33. Therefore, the second terminal 102 is electrically connected to the second electrode 32.

[0110] FIG. 19 is a schematic top view of the semiconductor device 210 of the present embodiment.

[0111] For example, a metal plate 112 plated with nickel, palladium, gold, etc. on Cu (copper) is electrically connected to the first terminal 101. On the plate 112, a normally-on transistor 20, a p-type normally-off transistor 30, and a first diode 40 are provided.

[0112] The normally-on transistor 20 has a second control electrode 23a and a second control electrode 23b as the second control electrode 23. The second control electrode 23a is electrically connected to the fifth terminal 105 by, for example, a bonding wire 118. The third electrode 21 is electrically connected to the second terminal 102 by, for example, a bonding wire 120.

[0113] The p-type normally-off transistor 30 has a second electrode 32 and a second control electrode 33 on the upper surface, and a first electrode 31 (not shown) on the lower surface. The second electrode 32 is electrically connected to the third electrode 21 by, for example, a bonding wire 126. The second control electrode 33 is electrically connected to the fourth terminal 104 by, for example, a bonding wire 124. The first electrode 31 is electrically connected to the plate 112 and the first terminal 101.

[0114] A Zener diode 80 is provided on the second terminal 102. The second anode 81 of the Zener diode 80 is provided on the upper surface of the Zener diode 80 and is electrically connected to the plate 112 and the first terminal 101 by, for example, a bonding wire 130. The second cathode 82 of the Zener diode 80 is provided on the lower surface of the Zener diode 80 and is electrically connected to the second terminal 102 and the second electrode 32.

[0115] The first anode 41 of the first diode 40 is provided on the upper surface of the first diode 40. The second control electrode 23b is electrically connected to the first anode 41 by, for example, a bonding wire 132. The first cathode 42 of the first diode 40 (not shown in FIG. 19) is provided on the lower surface of the first diode 40 and is electrically connected to the plate 112 and the first terminal 101.

[0116] In the semiconductor device 210 using the p-type normally-off transistor 30, the second terminal 102 and the second electrode 32 are electrically connected. On the other hand, when using the n-type normally-off transistor 10, a plurality of second terminals 102 and the first electrode 11 are electrically connected. Therefore, when using the p-type normally-off transistor 30, it is possible to perform a Kelvin connection at a position closer to the third terminal 103 without passing through the normally-off transistor. Thereby, modulation, delay, ringing, etc. of the drive current can be further suppressed.

[0117] Also, in this way, the upper and lower terminals (the first terminal 101 and the third terminal 103) of the semiconductor package 110 serve as the drain terminal and the source terminal of the semiconductor device 210, and the lateral terminals (the second terminal 102, the fourth terminal 104, the fifth terminal 105) serve as the control terminals (the gate terminal and the Kelvin source terminal). When forming a half-bridge or full-bridge circuit, the packages of the high-side elements and the packages of the low-side elements can be arranged close to each other, so that the wiring on the PCB board can be shortened. Therefore, the parasitic inductance of the main loop (between the source and drain of the normally-off transistor and between the source and drain of the normally-on transistor) can be reduced.

[0118] Note that the first diode 40 and the Zener diode 80 may not be provided.

[0119] Also in the semiconductor device of this embodiment, it is possible to provide a semiconductor device applicable to various usage modes.

[0120] (Fourth Embodiment) The semiconductor device of this embodiment is different from the semiconductor devices of the first to third embodiments in that the third terminal 103 and the first terminal 101 are not separated. Here, the description of the content overlapping with the first to third embodiments is omitted.

[0121] FIG. 20 is a schematic top view of the semiconductor device 220 of this embodiment. The third terminal 103 is integrated and does not have separated parts such as the third terminals 103a, 103b, 103c,..., 103q. Note that the same applies to the second terminal 102, the fifth terminal 105, the first terminal 101, the terminal 106, and the terminal 107.

[0122] Also in the semiconductor device of this embodiment, it is possible to provide a semiconductor device applicable to various usage modes.

[0123] (Fifth Embodiment) The semiconductor device of this embodiment is different from the semiconductor devices of the first to fourth embodiments in that electrical connection is performed using a metal plate instead of a bonding wire. Here, descriptions of content overlapping with the first to fourth embodiments are omitted.

[0124] FIG. 21 is a schematic top view of the semiconductor device 230 of this embodiment. A metal plate 129 is used instead of the bonding wire 128, and a metal plate 127 is used instead of the bonding wire 126. The metal plate 127 and the metal plate 129 are formed of a metal such as Cu (copper) or Al (aluminum). Note that it is also possible to use a metal plate for other bonding wires as well.

[0125] Also in the semiconductor device of this embodiment, it is possible to provide a semiconductor device applicable to various usage modes.

[0126] (Sixth Embodiment) The semiconductor device of this embodiment is different from the semiconductor device of the third embodiment in that the first diode 40 and the Zener diode 80 are not provided in the semiconductor package 110. Here, descriptions of content overlapping with the first to fifth embodiments are omitted.

[0127] FIG. 22 is a circuit diagram of the semiconductor device 240 of this embodiment. FIG. 23 is a schematic top view of the semiconductor device 240 of this embodiment. By not providing the first diode 40 and the Zener diode 80 in the semiconductor package 110, an advantage is obtained in that the degree of freedom in the design of the semiconductor device is increased.

[0128] Also in the semiconductor device of this embodiment, it is possible to provide a semiconductor device applicable to various usage modes.

[0129] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

[0130] (Appendix) Each of the above embodiments can be summarized as follows.

[0131] (Claim 1) An n-type normally-off transistor having a first electrode, a second electrode, and a first control electrode; A normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode; A first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the first electrode or the third electrode; A Zener diode having a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode; A semiconductor package having the above; A first terminal provided on the semiconductor package and electrically connected to the first electrode; A plurality of second terminals provided on the semiconductor package, electrically connected to the first electrode, and arranged in a first direction; A third terminal provided on the semiconductor package and electrically connected to the fourth electrode; A fourth terminal provided on the semiconductor package and electrically connected to the first control electrode; A plurality of fifth terminals provided on the semiconductor package, electrically connected to the second control electrode, and arranged in the first direction; A semiconductor device comprising the above.

[0132] (Claim 2) The semiconductor device according to claim 1, wherein the sixth terminal of the chip resistor or chip ferrite bead having the sixth terminal and the seventh terminal is electrically connected to any one of the plurality of second terminals, and the seventh terminal is electrically connected to any one of the plurality of fifth terminals.

[0133] (Item 3) The semiconductor device according to claim 1, wherein the third cathode of the first chip diode having the third anode and the third cathode is electrically connected to any one of the plurality of second terminals, the third anode is electrically connected to any one of the plurality of fifth terminals, The semiconductor device according to claim 1, wherein the sixth terminal of the chip resistor or chip ferrite bead having the sixth terminal and the seventh terminal is electrically connected to any one of the plurality of second terminals, The semiconductor device according to claim 1, wherein the fourth cathode of the second chip diode having the fourth anode and the fourth cathode is electrically connected to any one of the plurality of fifth terminals, the seventh terminal and the fourth cathode are electrically connected, The semiconductor device according to claim 1.

[0134] (Item 4) The semiconductor device according to claim 1, wherein any one of the plurality of second terminals and any one of the plurality of fifth terminals are electrically connected by wiring. The semiconductor device according to claim 1.

[0135] (Item 5) The semiconductor device according to claim 1, wherein the eighth terminal of the capacitor having the eighth terminal and the ninth terminal is electrically connected to the fifth terminal. The semiconductor device according to claim 1.

[0136] (Item 6) The semiconductor device according to claim 1, wherein the tenth terminal of the resistor having the tenth terminal and the eleventh terminal is electrically connected to the fourth terminal, the eleventh terminal is electrically connected to the ninth terminal, The fifth anode of the second diode having a fifth anode and a fifth cathode is electrically connected to the eleventh terminal, the fifth cathode is electrically connected to the tenth terminal, the second diode is electrically connected in parallel to the resistor, The semiconductor device according to claim 5.

[0137] (Claim 7) The semiconductor device according to any one of claims 1 to 6, wherein the plurality of second terminals and the plurality of fifth terminals are provided at an end of the semiconductor package.

[0138] (Claim 8) The semiconductor device according to any one of claims 1 to 7, wherein the first terminal, the third terminal, and the fourth terminal are not provided between the plurality of second terminals and the plurality of fifth terminals.

[0139] (Claim 9) The semiconductor device according to any one of claims 1 to 7, wherein the plurality of second terminals are adjacent to the plurality of fifth terminals without passing through the first terminal, the third terminal, and the fourth terminal.

[0140] (Claim 10) The semiconductor device according to any one of claims 1 to 7, wherein the first terminal, the third terminal, and the fifth terminal are not provided between the plurality of second terminals and the plurality of fourth terminals.

[0141] (Claim 11) The semiconductor device according to any one of claims 1 to 7, wherein the plurality of second terminals are adjacent to the plurality of fourth terminals without passing through the first terminal, the third terminal, and the fifth terminal.

Description of reference numerals

[0142] 10 n-type normally-off transistor 11 First electrode 12 Second electrode 13 First control electrode 14 Body diode 15 Anode 16 Cathode 20 Normally - on Transistor 21 Third Electrode 22 Fourth Electrode 23 Second Control Electrode 30 p - type Normally - off Transistor 31 First Electrode 32 Second Electrode 33 First Control Electrode 34 Body Diode 35 Anode 36 Cathode 40 First Diode 41 First Anode 42 First Cathode 70 Second Diode 71 Fifth Anode 72 Fifth Cathode 75 Resistor 76 Tenth Terminal 77 Eleventh Terminal 80 Zener Diode 81 Second Anode 82 Second Cathode 85 Capacitor 86 Eighth Terminal 87 Ninth Terminal 100 Semiconductor Device 101 First Terminal 102 Second Terminal 103 Third Terminal 104 Fourth Terminal 105 Fifth Terminal 110 Semiconductor Package 150 Chip Resistor 152 Sixth Terminal 154 Seventh Terminal 156 Chip Ferrite Bead 160 First Chip Diode 162 Third Anode 164 Third Cathode 170 Second Chip Diode 172 Fourth Anode 174 Fourth Cathode 180 Wiring 200 Semiconductor device 210 Semiconductor device 220 Semiconductor device 230 Semiconductor device 240 Semiconductor device

Claims

1. A normally-off transistor, a normally-on transistor cascode-connected to the normally-off transistor, a semiconductor package having the same, a plurality of second terminals provided in the semiconductor package, electrically connected to the normally-off transistor, arranged in a first direction respectively, and passed through by a virtual straight line; a fourth terminal provided in the semiconductor package and electrically connected to the normally-off transistor; a plurality of fifth terminals provided in the semiconductor package, electrically connected to the normally-on transistor, arranged in the first direction respectively, and passed through by the virtual straight line; a semiconductor device comprising the same.

2. The semiconductor device according to claim 1, wherein a chip resistor or a chip ferrite bead is electrically connected to any one of the plurality of second terminals and the fifth terminal.

3. A first chip diode electrically connected to any one of the plurality of second terminals and the fifth terminal; a chip resistor or a chip ferrite bead electrically connected to any one of the plurality of second terminals; a second chip diode electrically connected to the chip resistor or the chip ferrite bead and the fifth terminal; The semiconductor device according to claim 1, further comprising the same.

4. The semiconductor device according to claim 1, wherein any one of the plurality of second terminals and the fifth terminal are electrically connected by wiring.

5. A capacitor is electrically connected to the fifth terminal, The semiconductor device according to claim 1.

6. A resistor is electrically connected to the fourth terminal and the capacitor, a second diode is electrically connected to the fourth terminal, The semiconductor device according to claim 5.

7. The plurality of second terminals and the fifth terminal are provided at an end of the semiconductor package, The semiconductor device according to claim 1.

8. The fourth terminal is not provided between the plurality of second terminals and the fifth terminal, The semiconductor device according to claim 1.

9. The plurality of second terminals are adjacent to the fifth terminal without passing through the fourth terminal, The semiconductor device according to claim 1.

10. The fifth terminal is not provided between the plurality of second terminals and the fourth terminal, The semiconductor device according to claim 1.

11. The plurality of second terminals are adjacent to the fourth terminal without passing through the fifth terminal, The semiconductor device according to claim 1.

12. a first diode electrically connected to the normally-on transistor; The semiconductor device according to claim 1, further comprising the same.

13. The semiconductor device according to claim 12, wherein the semiconductor package has the first diode. The semiconductor device according to claim 12.

14. The semiconductor device according to claim 12, wherein the first diode is not provided within the semiconductor package. The semiconductor device according to claim 12.

15. a Zener diode electrically connected to the normally-off transistor or the normally-on transistor; The semiconductor device according to claim 1, further comprising the same.

16. The semiconductor device according to claim 15, wherein the Zener diode is not provided within the semiconductor package. The semiconductor device according to claim 15.

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