DRAM Memory with Persistent Retention Architecture and Cleanup Circuit

Abstract

To provide a DRAM with persistent retain architecture.SOLUTION: A DRAM has a first supply voltage source for generating a voltage level corresponding to a signal ONE utilized by a DRAM chip, and a DRAM cell including an access transistor and a holding capacitor. The first voltage level is higher than a voltage level corresponding to a signal ONE, and the first voltage level is generated by a first sustaining voltage generation unit. The first sustaining voltage generation unit is electrically coupled to the holding capacitor of the DRAM cell during a turn-off period of the access transistor of the DRAM cell. A cleanup circuit is provided to reduce the difference between the voltage on BL / BLB and a target reference voltage during equalization.SELECTED DRAWING: Figure 15C

Description

Technical Field

[0001] The present invention relates to dynamic memories, and more particularly to dynamic memories having a persistent retention architecture and a cleanup circuit.

Background Art

[0002] The most widely used DRAM cell has one access transistor with its source connected to a holding capacitor and its drain coupled to a bit line. The bit line is coupled to a first stage of cross-coupled sense amplifiers, which transfer the signal read from the cell array through a column switch to a second stage of sense amplifiers. The second stage of sense amplifiers is connected to an I / O line (known as a data line). During a write operation, the signal driven by the I / O buffer is stabilized on the data line, the data is further stabilized on the first stage of sense amplifiers, and an appropriate signal is written to the holding capacitor through the access transistor. The access transistor is involved in the accurate read or write operation to the holding capacitor during the active mode (i.e., the access transistor is on), but also avoids loss of the held signal while the access transistor is in the non-active mode (i.e., the access transistor is off).

[0003] The access transistor is designed to have a high threshold voltage to minimize current leakage through the transistor. However, as a drawback, the access transistor will degrade its performance when it is turned on. As a result, the word line has to be bootstrapped to enable the access transistor to have a high driveability for writing signals to the holding capacitor or (usually) connected to a high VPP (from the word line voltage source). Such a high VPP is passed through a word line driver to be loaded onto the gate or word line of the access transistor. Since VPP is a high voltage stress applied to the access transistor, the dielectric material of the transistor (e.g., oxide layer or high-K material) has to be designed to be thicker than that used for transistors in other support circuits or peripheral circuits of the DRAM (e.g., command decoder, address decoder, and other I / O circuits, etc.). Therefore, the design of the access transistor faces the challenge of maintaining either high performance or high reliability, presenting a difficult trade-off between reliability and performance. The widely used access transistor design is focused on achieving high reliability, but at the expense of the performance of the access transistor.

[0004] Briefly speaking, regarding the conventional access transistor design, it has a high threshold voltage to reduce leakage current to help with a long retention time of holding charge in the holding capacitor and a thick gate dielectric material to maintain a high word line voltage such as VPP, sacrificing the performance of the access transistor. As a result, the writing (WRITE) or reading (READ) of a signal called ONE, usually referred to as the VCC level, takes longer or the signal ONE cannot be fully restored. That is, the write time becomes longer to satisfy the full signal VCC for being fully written to the holding capacitor.

[0005] A conventional design of a DRAM cell is shown in FIG. 1A. The DRAM cell includes an access transistor 11 and a holding capacitor 12. The gate of the access transistor 11 is coupled to a word line (WL), and a cross-coupled sense amplifier 20 with four cross-connected transistors is coupled to the access transistor 11 through a bit line (BL). SAP (PMOS side of the sense amplifier) is a signal or voltage connected to two PMOS transistors of the sense amplifier 20, and SAN (NMOS side of the sense amplifier) is a signal or voltage connected to two NMOS transistors of the sense amplifier. When the switch transistor between the voltage source VCCSA and SAP is turned on, the voltage value of SAP is approximately equal to the value of the voltage source VCCSA (the voltage source coupled to SAP) or Vcc which usually corresponds to the signal "1" held in the DRAM cell. Similarly, when the switch transistor between the voltage source VSS and SAN is turned on, the voltage value of SAN is approximately equal to the value of the voltage source VSS or Ground which usually corresponds to the signal "0" held in the DRAM cell.

[0006] The DRAM cell uses the access transistor 11 as a switch to control the charge held in the capacitor from the bit line (BL) in the write mode or transferred to the bit line in the read mode. At this time, a plurality of DRAM cells are respectively connected to the bit line. In this example, by amplifying the signal transferred by the cell signal on the bit line, the signal ONE (assumed to be 1.2V. The signal ONE is usually the level voltage of the voltage source VCCSA or the cross-coupled sense amplifier 20 to supplied to Vcc. ) and ZERO (assumed to be 0V. The signal ZERO is usually the level voltage of the voltage source VSS or the cross-coupled sense amplifier 20 to supplied to ground) exist. Alternatively, these signals ONE and ZERO are written externally to twist the sense amplifier so as to hold the correct signal in the cell in the write mode.

[0007] Figure 1B shows the relevant signal waveforms during the access (read or write) operation of most current DRAMs. For example, a 25-nanometer DRAM cell generally has the following parameters that are relevant to (enclosed in) the array design. Bit line ONE has a voltage of 1.2V, word line ON has a VPP of up to 2.7V, word line OFF has a voltage of about -0.3V, the threshold voltage of the cell is in the range of about 0.7 to 0.9V, the dielectric of the access transistor needs to maintain an electric field strength of less than 2.7V (under burn-in stress, this number becomes up to 3.4V for an acceptable reliability margin), and the word line driver device also needs to use a thick gate dielectric, thereby sacrificing performance.

[0008] As shown in Figure 1B, first, the holding capacitor of the DRAM is in the standby or non-active mode (i.e., the access transistor is off), and the voltage level of the word line coupled to the gate of the access transistor is the standby negative voltage (-0.3V). The bit line and the bit line bar are equalized (by the voltage equalization circuit described later) at a voltage level of half VCCSA between the ONE level at VCCSA = 1.2V and the ZERO level of 0V.

[0009] When the holding capacitor enters the active mode to start the access operation (i.e., the access transistor is on), the voltage level of the word line rises from the standby negative voltage (-0.3V) and is pulled up to a high level VPP (e.g., 2.7V) much higher than the voltage obtained by adding the threshold voltage Vt of the access transistor (which can be 0.7 or 0.8V) to VCCSA (1.2V) to supply a drive large enough for the gate-source voltage of the access transistor (e.g., 2.7V - 1.2V - 0.8V = 0.7V). The bit lines are coupled to the holding capacitor for charge sharing. The word line is continuously ON at such a high voltage VPP for the access operation (e.g., read or write), and the cross-coupled sense amplifier 20 amplifies the voltage difference between the bit lines (BL and BLB).

[0010] Furthermore, the RESTORE phase proceeds following the access operation. During the RESTORE phase, the cross-coupled sense amplifier 20 recharges the holding capacitor based on the signal ONE or ZERO in the holding capacitor. After the RESTORE phase, the word line is pulled down from VPP to the voltage of the word line in the standby mode (-0.3V), and the access transistor is in the non-active mode.

[0011] For purposes of detailed explanation, the operation of the aforementioned conventional DRAM circuit, hereinafter, the access read operation of the corresponding DRAM cell that holds the signal “1” is used as an example, and the following is cited from Bruce Jacob, et al., “Memory Systems - Cache Dram and Disk”, Elservier Inc., 2008, pages 362 - 365 (Non-Patent Document 1). The content thereof is incorporated herein by reference. Refer to FIG. 1C showing a conventional circuit of a DRAM cell including a sense amplifier circuit (or sensing circuit) 20 and a voltage equalization circuit 21. The voltage equalization circuit 21 should ensure that the voltages on the bit line pair match as closely as possible. As described above, the sense amplifier circuit 20 includes four cross-connected transistors (i.e., two P-type transistors (“PFet”) and two N-type transistors (“NFet”)). The sense amplifier circuit 20 drives the bit line pair to complementary voltage extremes according to each voltage on the bit line at the time when the SAN signal and the SAP signal are activated (i.e., as shown in FIG. 1A, the SAN signal and the SAP signal are connected to VSS and VCCSA, respectively). After the assertion of the SAN signal and the SAP signal or the voltage, the bit line is driven to the full voltage level. The Column-Select Line (CSL) then turns on the output transistor, allowing the fully driven voltage to reach the output and be read out from the DRAM device. At the same time, the access transistor of the accessed DRAM cell remains open, and the fully driven voltage on the bit line recharges the holding capacitor 12 at this time.

[0012] Based on the access read operation to a conventional DRAM cell, FIGS. 1D to 1G show four different phases regarding the precharge phase, access phase, sense phase, and restore phase. First, as shown in FIG. 1D, during the precharge phase, the bit lines of the DRAM array are precharged to a reference voltage Vref (usually, Vcc / 2, that is, a voltage in the middle between the power supply voltage Vcc and the ground), and it is used as the reference voltage. In this precharge phase, the voltage equalization circuit 21 is activated to place the reference voltage Vref on the bit line pair. That is, the bit line Bitline (“BL”) and the bit line bar (Outer 1) TIFF0007683883000001.tif5114 (“BLB” or “complementary bit line”) is precharged to Vref. In this precharge phase, the sense amplifier circuit 20 is inactive.

[0013] Next, during the access phase when the voltage equalization circuit is inactive, as shown in FIG. 1E, a voltage (for example, Vcc + Vt or VPP shown in FIG. 1B) is applied to the word line corresponding to the selected DRAM cell. The voltage on the word line activates or turns on the access transistor 11 of the selected DRAM cell, and the holding capacitor 12 of the selected DRAM cell then discharges its content onto each bit line through the charge sharing process. In this case, since the voltage of the holding capacitor 12 represents a digital value of “1” in FIG. 1E, the charge sharing process slightly increases the voltage on the bit line from Vref to Vref+. Then, when the voltage on the bit line changes, the voltage on the bit line begins to affect the operation of the sense amplifier circuit 20. The slightly higher voltage on the bit line starts to drive the lower NFet of the sense amplifier circuit 20 to conduct more than the upper NFet. In contrast, the minute voltage difference also drives the lower PFet of the sense amplifier circuit 20 to be more non - conductive than the upper PFet. The bit line voltage thus biases the sense amplifier circuit 20 for the subsequent sense phase.

[0014] Thereafter, during the sense phase in which the voltage equalization circuit 21 remains inactive, as shown in FIG. 1F, the above-described minute voltage difference drives the bias to the sense amplifier circuit 20, and the SAN signal is the lower (Outer 2) TIFF0007683883000002.tif5114 lowers the voltage. When the SAN signal turns on (i.e., is connected to VSS or ground as shown in FIG. 1A), the more conductive lower NFet allows the SAN signal to be the lower (Outer 3) TIFF0007683883000003.tif5114 to lower the voltage from Vef to ground. Similarly, the SAP signal (connected to VCCSA or Vcc as shown in FIG. 1A) drives the bit line to a fully restored voltage value representing the digital value of "1" corresponding to VCCSA or Vcc. The SAM signal and the SAP signal thus jointly force the bistable sense amplifier circuit to be driven to each maximum or minimum voltage rail.

[0015] Finally, as shown in FIG. 1G for the restore phase, the bit line and the bit line bar (Outer 4) TIFF0007683883000004.tif5114 are driven to their respective maximum (VCCSA or Vcc) and minimum (VSS or ground) voltage values, and then the overdriven word line remains active, and the fully driven bit line voltage now restores the charge of the holding capacitor 12 through the access transistor 11. During the restore phase, a conventional DRAM is known to use the voltage VCCSA or Vcc corresponding to the signal "1" as shown in FIG. 1G to restore the charge to the holding capacitor 12, so the voltage held in the holding capacitor 12 becomes the same as or approximately the same as the voltage corresponding to the signal "1" as shown in FIG. 1G.

[0016] FIG. 1H shows the voltage waveforms of the bit lines and the selected control signals represented in FIGS. 1D - 1G. Before the access operation, the bit lines are pre - charged and the voltage on the bit lines is set to the reference voltage Vref. In phase 1 or the access phase, the word line voltage is overdriven until it is at least Vt higher than Vcc, and the DRAM cell discharges the content of the holding capacitor 12 onto the bit line, raising the voltage from Vref to Vref +. In phase 2 or the sense phase, the sense control signals SAN and SAP drive the voltage on the bit line to the full voltage Vcc representing the signal “1”. The voltage Vcc corresponding to the signal “1” on the bit line then restores the charge of the DRAM cell in phase 3 or the restore phase.

[0017] Thus, based on the above description regarding FIGS. 1C - 1H, the voltage of the bit line (marked by the dashed line in FIG. 1H) is set to Vref (or Vcc / 2) by the voltage equalization circuit 21 during the pre - charge phase. Then, after the word line turns on the access transistor 11, the charge sharing process raises the voltage of the bit line from Vref to Vref + during the access phase. Thereafter, during the sense phase, the voltage of the bit line rises from Vref + to near VCCSA (or Vcc) with the help of the SAP signal connected to the voltage source VCCSA (or Vcc) as shown in FIG. 1A. Finally, during the restore phase, the sense circuit 20 is still active and the voltage source VCCSA (or Vcc) corresponding to the signal “1” is coupled to the bit line through the sense circuit 20 to restore the charge to the holding capacitor 12. Thus, from the access phase to the sense phase and then to the restore phase, there is a high - voltage source VCCSA (or Vcc) coupled to the sense circuit 20 through SAP and a low - voltage source VSS (or ground) coupled to the sense circuit 20 through SAN. In a conventional DRAM circuit, there is no other voltage source coupled to the sense circuit 20 from the access phase to the restore phase.

[0018] However, due to this high VPP voltage for the word line stress, the access transistor will be designed with a thicker gate oxide or gate insulator than those used for the transistors in the peripheral circuit. This degrades access transistor performance such as the degraded short channel effect, the on-off ratio of the transistor current, the swing gradient, etc. Further, although the threshold voltage is designed to be higher than that used for the transistors in the peripheral circuit, the leakage current through the access transistor during the standby mode or the non-active mode is still high enough to reduce the amount of holding charge for sensing. When VCCSA is lower (e.g., 0.6V) in a 12nm or 7nm FinFET process, the leakage problem in the standby mode or the non-active mode is further exacerbated.

Prior Art Documents

Non-Patent Documents

[0019]

Non-Patent Document 1

Summary of the Invention

[0020] Therefore, the present invention should introduce a DRAM with a sustainable retention architecture and a cleanup circuit. According to an aspect of the present invention, the DRAM includes a first retention voltage generation unit that generates a first voltage level higher than the voltage level of signal ONE used in the DRAM chip, a DRAM cell having an access transistor and a retention capacitor, a sense amplifier, an equalization circuit, and a cleanup circuit. The sense amplifier is coupled to a bit line and a complementary bit line, and the bit line is coupled to the retention capacitor through the access transistor. The equalization circuit is also coupled to the bit line and the complementary bit line, and the equalization circuit couples the bit line and the complementary bit line to a pre-set reference voltage during an equalization period. The cleanup circuit is coupled to the sense amplifier or the equalization circuit. Here, the first retention voltage generation unit is electrically coupled to the retention capacitor of the DRAM cell during the turn-off period of the access transistor of the DRAM cell, and the cleanup circuit is activated to reduce the difference between the voltage of the bit line and the target reference voltage during the equalization period.

[0021] According to another object of the present invention, the DRAM further has a word line coupled to the gate terminal of the access transistor, and the word line is selected to turn on the access transistor in a first period and a second period after the first period. The first retention voltage generation unit is electrically coupled to the bit line during the second period.

[0022] According to an aspect of the present invention, the first retention voltage generation unit is electrically coupled to the sense amplifier during the second period, and the first retention voltage generation unit is electrically coupled to the retention capacitor of the DRAM cell through the sense amplifier and the bit line.

[0023] According to one aspect of the present invention, the first period is an access operation period, and the second period is a restore phase period. Further, in other aspects, a kicking charge source is electrically coupled to the bit line of the DRAM chip during the access operation period. The signal of the bit line is raised to a kick voltage level by the kicking charge source during the access operation period, and the kick voltage level is lower than the first voltage level but higher than the voltage level corresponding to signal ONE.

[0024] According to one aspect of the present invention, the first period has a first kick period and a second kick period separated from the first kick period, and the kicking charge source is coupled to the bit line during the first kick period, or is coupled to the bit line during the first kick period and the second kick period.

[0025] According to one aspect of the present invention, the word line is selected to turn on the access transistor in the first period and the second period according to the refresh operation. The kicking charge source is electrically coupled to the bit line in a kick period before the first period, and the first holding voltage generation unit is electrically coupled to the bit line during all of the second period.

[0026] According to one aspect of the present invention, the second period is at least 20% of the sum of the kick period, the first period, and the second period. In other examples, the second period is at least 50% of the sum of the kick period, the first period, and the second period.

[0027] According to one aspect of the present invention, the equalization period is after the turn-off period of the access transistor, and the cleanup circuit is activated during the equalization period so that the voltage of the bit line becomes equal to a reference voltage set in advance after the equalization period. Further, the cleanup circuit is activated by a cleanup pulse, and the width of the cleanup pulse is less than or equal to the width of the equalization period.

[0028] According to one aspect of the present invention, the cleanup circuit is activated by a cleanup pulse, and the rise of the cleanup pulse is substantially aligned with the rise of the equalization period.

[0029] According to one aspect of the present invention, the cleanup circuit has a sense amplifier and a switch circuit coupled to a predetermined voltage. In other examples, the cleanup circuit has an equalization circuit and a switch circuit coupled to a predetermined voltage.

[0030] Another object of the present invention is to provide a DRAM chip including a cleanup circuit. The DRAM chip has DRAM cells having access transistors and holding capacitors, a sense amplifier, an equalization circuit, and a cleanup circuit. The sense amplifier is coupled to a bit line and a complementary bit line, and the bit line is coupled to the holding capacitor through an access transistor. The equalization circuit is also coupled to the bit line and the complementary bit line, and the equalization circuit couples the bit line and the complementary bit line to a pre-set reference voltage during an equalization period. The cleanup circuit is coupled to the sense amplifier or the equalization circuit. Here, the cleanup circuit is activated to reduce the difference between the voltage of the bit line and the pre-set reference voltage during the equalization period.

[0031] According to one aspect of the present invention, the voltage of the bit line is equal to the pre-set reference voltage after the equalization period.

[0032] According to another aspect of the present invention, the cleanup circuit is electrically coupled to the bit line and the complementary bit line during the equalization period through the sense amplifier or the equalization circuit.

[0033] According to another aspect of the present invention, the cleanup circuit has a sense amplifier and a switch circuit coupled to a predetermined voltage. In other examples, the cleanup circuit has an equalization circuit and a switch circuit coupled to a predetermined voltage.

[0034] According to an aspect of the present invention, the cleanup circuit is activated by a cleanup pulse during an equalization period, and the rise of the cleanup pulse is substantially aligned with the rise of the equalization period.

[0035] According to an aspect of the present invention, the DRAM chip receives the voltage of the bit line, the voltage of the complementary bit line, and a pre-set reference voltage at the start or during the equalization period, and when half of the sum of the voltage of the bit line and the voltage of the complementary bit line is not equal to the pre-set reference voltage, it further has a comparator circuit that transmits a control signal to the cleanup circuit.

[0036] These and other objects of the present invention will become clearly apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in various figures and drawings.

Brief Description of the Drawings

[0037]

Figure 1A

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Figure 15C

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] The following detailed description of the disclosed apparatus and method embodiments is presented herein by way of example and not by way of limitation with reference to the figures. Although specific embodiments are illustrated and described in detail, it should be understood that various changes and modifications may be made without departing from the scope of the appended claims. The scope of the present invention is in no way limited to the number of components, their materials, their shapes, their relative arrangements, etc., but is merely disclosed as examples of embodiments of the present invention.

[0039] The present invention is to disclose a DRAM with a sustainable retention architecture, in which a sustain voltage source is electrically coupled to the retention capacitor of the DRAM cell before the access transistor is turned off, and the voltage level of the sustain voltage source is higher than that of the normal signal ONE, or the voltage level of the sustain voltage source is lower than that of the normal signal ZERO. DRAM operations (e.g., auto precharge operation, restore phase, refresh phase, and precharge phase) turn on the access transistor of the selected DRAM cell. Thus, by coupling the above-mentioned sustain voltage source to the retention capacitor of the DRAM cell during the turn-on stage of the access transistor, the retention capacitor can be maintained for a longer period compared to the conventional DRAM structure after the access transistor is turned off, even in the presence of leakage current through the access transistor.

EXAMPLE

[0040] Figure 2 shows the related signal waveforms of the access (read or write) operation of a DRAM cell according to an embodiment of the present invention. By starting from the standby mode of the DRAM, the word line WL is biased at -0.3V to completely turn off the access transistor 11. In this embodiment, VCCSA is set to 1.2V and VSS is set to 0V. In this example, the level of signal ONE is 1.2V and the level of signal ZERO is 0V (ground). The bit lines (BL and BLB) are equalized at a voltage level of 0.6V between the signal ONE level at VCCSA = 1.2V and the signal ZERO level at VSS = 0V.

[0041] At T0, the word line voltage rises from -0.3V to 2.7V, which is much higher than the threshold voltage of the access transistor of 0.8V and VCCSA of 1.2V, so as to transfer either signal ONE or ZERO to the bit line. Until the signal reaches a specific magnitude during the access phase described in Figure 1E, the sense amplifier 20 is activated to amplify the signals across the bit line (BL) and the bit line bar (BLB). After T1, during the sense phase described in Figure 1F, a read operation (by amplifying the signal transferred by the cell signal on the bit line) or a write operation (these signals ONE and ZERO are written externally to twist the sense amplifier 20 to store the correct signal in the DRAM cell) can be executed. Of course, in addition to read or write, other DRAM operations may be executed after T1. That is, the DRAM cell is accessible during the period between T1 and T2.

[0042] After T2, during the restore phase, the dielectric of access transistor 11 is still being loaded by VPP from the word line (WL) for a moderately short restore time. The first sustain voltage source is intentionally coupled to the capacitor of the DRAM cell during this restore phase. The voltage level of the first sustain voltage source is higher than 1.2V (or the voltage level of signal ONE). This is done by connecting or coupling the first sustain voltage source (VCCSA+M1) to the sense amplifier 20 (e.g., by turning on switch 13), as shown in FIG. 3A which represents a schematic circuit of the sense amplifier 20 selectively coupled to the first sustain voltage source. During this restore phase, the original VCCSA voltage source is disconnected from the sense amplifier 20 (e.g., by turning off switch 14), and the first sustain voltage source (VCCSA+M1) is connected to the sense amplifier 20 as shown in FIG. 3A. M1 can be a positive value such that the first sustain voltage source (VCCSA+M1) is higher than VCCSA. In one example, M1 can be in the range from 1 / 3VCCSA to 2 / 3VCCSA (e.g., 0.6V). For example, if signal ONE is originally in the holding capacitor, during this restore phase, a voltage level of 1.2V + 0.6V from the first sustain voltage source is then supplied to the holding capacitor 12 through the sense amplifier 20. That is, in FIG. 2, before the turn-off of access transistor 11 at T3 (i.e., the word line WL is pulled down from 2.7V VPP to the word line voltage in standby mode of -0.3V), the holding capacitor 12 is supplied with a voltage level of the first sustain voltage source higher than that of the normal signal ONE (VCCSA). In this way, after the turn-off of access transistor 11, the holding capacitor 12 can be maintained for a longer period compared to the conventional DRAM structure even if there is a leakage current through access transistor 11. In one embodiment, after the turn-off of access transistor 11 or after the restore phase, the first sustain voltage source (VCCSA+M1) can be disconnected from the sense amplifier 20. Additionally, the bit line (BL) can be coupled to a bit line voltage source having a voltage level of Vb1.Thereby, the voltage level of the bit line (BL) will be reset to Vb1 as shown in FIG. 2.

[0043] In other embodiments, after T2, during the restore phase, a second hold voltage source is intentionally coupled to the capacitor of the DRAM cell during the restore phase. The voltage level of the second hold voltage source is lower than the voltage source VSS (0V or a voltage level of ZERO). This can be done by connecting the second hold voltage source (VSS-M2) to the sense amplifier as shown in FIG. 3B (e.g., by turning on switch 23). FIG. 3B represents a schematic circuit of a sense amplifier selectively coupled to a second hold voltage source (VSS-M2) lower than VSS, and M2 can be a positive number. In one example, M2 can be in the range of 0.4V to 0.8V (e.g., 0.6V). Of course, when the second hold voltage source is coupled to the sense amplifier 20 during the restore phase, the voltage source VSS is disconnected from the sense amplifier 20 (e.g., by turning off switch 24). If the signal ZERO is initially in the holding capacitor 12, during this restore phase, a voltage level of -0.6V is then supplied to the holding capacitor 12. That is, in FIG. 2, before the access transistor 11 is turned off at T3 (i.e., the word line WL is pulled down from VPP to the word line voltage in standby mode), the holding capacitor 12 is supplied with a voltage level of a second hold voltage source lower than that of the normal signal ZERO (VSS). In one embodiment, after the access transistor 11 is turned off or after the restore phase, the second hold voltage source (VSS-M2) can be disconnected from the sense amplifier 20.

[0044] Of course, in other embodiments, both the first and second holding voltage sources may be intentionally coupled to the capacitors of the DRAM during the restore phase. Thus, if the signal ONE is initially in the holding capacitor before the word line WL is pulled down from VPP to the voltage of the word line in standby mode, a voltage level of 1.2V + 0.6V is stored in the holding capacitor, or if the signal ZERO is initially in the holding capacitor, a voltage level of -0.6V is stored in the holding capacitor.

Example

[0045] To reduce leakage current to maintain the stored charge without leaking through the access transistor, the design is usually done to give the access transistor a very high threshold voltage. When VCCSA is reduced to 0.6V, 7nm or 5nm process tri-gate or FinFET transistors are employed for the peripheral circuits in DRAM design, and the threshold voltages of those transistors can be scaled down to 0.3V as appropriate. In this embodiment, the threshold voltage of the access transistor is intentionally increased to a maximum of 0.5 to 0.6V. Therefore, the leakage current from the holding capacitor is significantly reduced by at least 3 to 4 decades (= 0.6 - 0.3 to 0.3V. When the S-factor is 68mV / decade, the leakage can be reduced by 4 decades compared to that of the peripheral tri-gate device, and when the threshold voltage is increased to 0.5V, the leakage current should be 2 to 3 decades.). It is proposed to increase the threshold voltage close to VCCSA or to at least 80% or more of 0.6V. In the embodiment, the gate dielectric thickness of the access transistor (e.g., FinFET or tri-gate transistor) remains the same as that of the peripheral transistor without increasing its thickness, in which case the high-performance merits of using the tri-gate structure can be maintained.

[0046] Figure 4 shows the related signal waveforms of a DRAM cell according to another embodiment of the present invention. In this example, the level of signal ONE is 0.6V and the level of signal ZERO is 0V (GND). After T2, during the restore phase, the first holding voltage source is intentionally coupled to the capacitor of the DRAM cell during the restore phase. The voltage level of the first holding voltage source is higher than 0.6V (or the voltage level of signal ONE). This is done by connecting or coupling the first holding voltage source (VCCSA+K) to the sense amplifier 20, where K can be a positive number. In this example, K can be in the range from 1 / 3 VCCSA to 2 / 3 VCCSA (for example, 0.3V or 0.4V). Thus, if the 0.6V signal ONE is initially in the holding capacitor, during this restore phase, a voltage level of 0.6V + 0.4V is then supplied to the holding capacitor 12. That is, in Figure 4, before the turn-off of the access transistor 11 at T3 (i.e., the word line WL is pulled down from VPP to the word line voltage in standby mode), the holding capacitor 12 is supplied with a voltage level of the first holding voltage source that is higher than that of the normal signal ONE (0.6V of VCCSA). Therefore, after the word line WL is pulled up to VPP, but before the word line WL is pulled down to standby or inactive mode, if the signal ONE is initially in the holding capacitor, a voltage level of 1V is stored in the holding capacitor. In one embodiment, after the restore phase, the bit line (BL) and the bit line bar (BLB) can be coupled to a bit line voltage source having a voltage level of Vb1. Thereby, the voltage levels of the bit line (BL) and the bit line bar (BLB) are reset to Vb1 as shown in Figure 4.

[0047] Of course, as described above, if the signal ZERO is initially in the holding capacitor before the word line WL is pulled down from VPP to the word line voltage in standby mode, the voltage level of the second holding voltage source can be stored in the holding capacitor. At this time, the voltage level of the second holding voltage source is lower than the signal ZERO, for example, -0.4V.

Example

[0048] Figure 5 shows another embodiment regarding a circuit and a functional block diagram for a precharge operation. In this embodiment, VCCSA is set to 0.6V and VSS is set to 0V. In the precharge operation, all DRAM cells connected to the selected word line within the memory section 5 (“Sec5”) will be precharged, and DRAM cells connected to the unselected word lines within other memory sections (e.g., “Sec4”, “Sec6”, etc.) will be in an idle state.

[0049] Sense amplifiers 41 and 42 coupled to the DRAM cells connected to the selected word line are kicked by the precharge kicker 30 to the third holding voltage source VHSA (0.6V + K). Thereby, a stronger drain-source electric field can accelerate the signal restored to the cell. The third holding voltage source VHSA is approximately several hundred mV higher than VCCSA (0.6V), for example, 0.3V or 0.4V higher. Further, before the selected word line turns off (i.e., the access transistor of the DRAM cell coupled to the selected word line turns off), a voltage level of 0.6V + 0.4V higher than the original signal ONE can be stored in the holding capacitor. On the other hand, the sense amplifiers coupled to the DRAM cells connected to the unselected word lines are not kicked up and are still coupled to VCCSA.

[0050] Figure 6 explains the operation of the sense amplifier for the precharge phase, and the meanings of the symbols used in Figure 6 are as follows: VCCSA: Bit line sense amplifier voltage VHSA: Third holding voltage source LSLP: Sense amplifier high voltage of the selected bit line LSLN: Sense amplifier low voltage of the selected bit line Vpl: Plate voltage SN: Hold node WL: Word line BL: Bit line Source-gate voltage between Vsg1,2: P1, P2 Gate-source voltage between Vgs3,4: N3, N4 Source-gate voltage between Vsg5,6: P5, P6 Gate-source voltage between Vgs7,8: N7, N8

[0051] Referring to FIG. 6, word line WL100 is coupled to a plurality of holding nodes such as SN1 and SN9. When the signal ONE (0.6V) is held at the holding node SN1 connected to the word line WL100, a precharge command is issued. After the word line WL100 is selected (i.e., the word line is on), the LSLP of the sense amplifier is coupled to VHSA (1.0V), and then, LSLP is kicked from 0.6V to 1.0V while LSNL remains at 0V. Thus, the transistor P1 of the sense amplifier is off and Vsg1 = 0V. Also, the transistor P2 of the sense amplifier is on and Vsg2 is kicked from 0.6V to 1.0V, and 1.0V is fully coupled to the holding node SN1 through the bit line BL1. On the other hand, the transistor N3 of the sense amplifier is on and Vgs3 is also kicked from 0.6V to 1.0V. Further, the transistor N4 of the sense amplifier is off and Vsg4 is 0V.

[0052] When the signal ZERO (0V) is held at the holding node SN9 connected to the word line WL100, after a precharge command is issued and the word line WL100 is selected, the sense amplifier is coupled to VHSA (1.0V). Thereafter, LSLP is kicked from 0.6V to 1.0V, and LSLN remains at 0V. Thus, the transistor P5 of the sense amplifier is on, and Vsg5 is kicked from 0.6V to 1.0V. Also, the transistor P6 of the sense amplifier is off, and Vsg2 is 0V. On the other hand, the transistor N7 of the sense amplifier is off, and Vsg7 is 0V. Furthermore, the transistor N8 of the sense amplifier is on, and Vgs8 is kicked from 0.6V to 1.0V, and 0V is strongly restored to the holding node SN9 through the bit line BL9. Naturally, as described above, when the signal ZERO is originally in the holding capacitor, LSLN can be coupled to another holding voltage source VLSN (0V - K) during the precharge phase. VLSN is lower than the voltage level of the signal ZERO, and in this case, VLSN can be -0.4V. Then, -0.4V is strongly restored to the holding node through the bit line BL9 during the precharge phase.

[0053] In other embodiments, coupling a first holding voltage source higher than the voltage level of the signal ONE to the sense amplifier (or DRAM holding cell) may be applied to a refresh operation or other operations (e.g., read / write with an auto - precharge operation) as long as the first holding voltage source is coupled to the sense amplifier (or DRAM holding cell) before the word line coupled to the DRAM holding cell turns off. Also, coupling a second holding voltage source lower than the signal ZERO to the sense amplifier (or DRAM holding cell) may be applied to a refresh operation or other operations as long as the second holding voltage source is coupled to the sense amplifier (or DRAM holding cell) before the word line coupled to the DRAM holding cell turns off.

Example

[0054] FIG. 7 shows the related signal waveforms of the operation of a DRAM cell according to another embodiment of the present invention. First, the word line WL is biased to completely turn off the access transistor of the DRAM cell. In this embodiment, VCCSA is set to 1.1V and VSS is set to 0V. In this example, the level of signal ONE is 1.1V and the level of signal ZERO is 0V (GND). The bit line (BL) and the bit line bar (BLB) are equalized between the signal ONE level at VCCSA = 1.1V and the signal ZERO level at VSS = 0V. After T0, the word line voltage is raised to turn on the access transistor of the DRAM cell. During the period from T1 to T2, there is an active command to be executed, and the corresponding first holding voltage source (VCCSA + M1) can be connected to the sense amplifier during the active command (by turning off switch 14 and turning on switch 13 as shown in FIG. 3A). Thus, the signal of the bit line is pumped (or kicked) to at least VCCSA + M2 during the active command. After the execution of the active command, the normal voltage source VCCSA is connected to the sense amplifier (by turning off switch 13 and turning on switch 14 as shown in FIG. 3A), and then the signal of the bit line returns to VCCSA. Such a kick of the bit line promotes signal sensing.

[0055] Similarly, after T2, during the restore (or precharge) phase, a first hold voltage source VCCSA+M1 (or a different hold voltage higher than VCCSA) is intentionally coupled to the capacitor of the DRAM cell during this restore phase. That is, during this restore (or precharge) phase, the original VCCSA voltage source is disconnected from the sense amplifier (e.g., by turning off switch 14 as shown in FIG. 3A), and the first hold voltage source VCCSA+M1 is connected to the sense amplifier 20 (e.g., by turning on switch 13 as shown in FIG. 3A). The signal on the bit line is pumped (or kicked) to at least VCCSA+M1. Thus, before the word line WL is pulled down to fully turn off the access transistor of the DRAM cell, the holding capacitor of the DRAM cell is supplied with a voltage level of the first hold voltage source that is higher than that of the normal signal ONE (VCCSA), and the holding capacitor of the DRAM cell can be maintained for a longer period compared to a conventional DRAM structure even if there is a leakage current through the access transistor.

Embodiment

[0056] FIG. 8A shows the related signal waveforms of the operation of a DRAM cell according to another embodiment of the present invention. Similar to Example 4, during the period from T1 to T2, there is an active command to be executed, and the corresponding first hold voltage source (VCCSA+M1) can be connected to the sense amplifier during the active operation. Thus, the signal on the bit line is pumped (kicked) to at least VCCSA+M1 during the active command. After the execution of the active command, the normal voltage source VCCSA is connected to the sense amplifier, and then the signal on the bit line returns to VCCSA.

[0057] After the active command, one or more read commands may be executed before T2, and the first holding voltage source (VCCSA+M1) may be reconnected to the sense amplifier during the read command. Thereby, the signal of the bit line is pumped (or kicked) to at least VCCSA+M1 during the read command. After the execution of the read command, the normal voltage source VCCSA is reconnected to the sense amplifier (by turning off switch 13 and turning on switch 14 as shown in FIG. 3A), and then the signal of the bit line returns to VCCSA. Such a kick of the bit line during the read command can improve the signal development time. For example, when VCCSA is 1.1V and M1 is 0.2V, the signal development time with a kick during the read command is about 20% to 30% faster than the signal development time without a kick.

[0058] Similarly, after T2, during the restore phase, the original VCCSA voltage source is disconnected from the sense amplifier, and the first holding voltage source VCCSA+M1 is to be connected to the sense amplifier 20, and the signal of the bit line is pumped (or kicked) to at least VCCSA+M1. Thus, the holding capacitor of the DRAM cell is supplied with a voltage level of the first holding voltage source higher than that of the normal signal ONE (VCCSA). In other embodiments, however, after T2, during the restore phase, the original VCCSA voltage source (rather than VCCSA+M1) is still connected to the sense amplifier as shown in FIG. 8B.

[0059] Furthermore, in other embodiments, the signal of the bit line is not kicked to VCCSA+M1 during the active command, and the signal of the bit line is kicked to VCCSA+M1 during the read command. After T2, during the restore phase, the first holding voltage source VCCSA+M1 is connected to the sense amplifier so that the signal of the bit line is pumped (or kicked) to at least VCCSA+M1 as shown in FIG. 8C.

Example

[0060] Figure 8D shows the related signal waveforms of the operation of a DRAM cell according to another embodiment of the present invention. Similar to Figure 8A, during the period from T1 to T2, there are active commands to be executed and at least read commands following the active commands, and the corresponding first holding voltage source (VCCSA+M1) can be connected to the sense amplifier during the active operation and the read command (by turning on switch 13 as shown in Figure 2A). Further, the corresponding second holding voltage source (VSS-M2) can be connected to the sense amplifier during the active operation and the read command (by turning on switch 23 as shown in Figure 3B .). Therefore, during the active command and the read command, the signal of the bit line (BL) is pumped (or kicked) to at least VCCSA+M1, and the signal of the bit line bar (BLB) is pumped (or kicked) to at least VSS-M2. After the execution of the active command and the read command, the normal voltage source VCCSA is connected to the sense amplifier (by turning off switch 13 and turning on switch 14 as shown in Figure 3A), and the normal voltage source VSS is also connected to the sense amplifier (by turning off switch 23 and turning on switch 24 as shown in Figure 3B), then the signal of the bit line returns to VCCSA, and the signal of the bit line bar returns to VSS.

[0061] Similarly, after T2, during the restore phase, the original VCCSA and VSS voltage sources are disconnected from the sense amplifier (for example, by turning off switch 14 and switch 24 in Figures 3A and 3B respectively), the first holding voltage source VCCSA+M1 is connected to the sense amplifier 20 (by turning on switch 13 in Figure 3A), the second holding voltage source VSS-M2 is connected to the sense amplifier 20 (by turning on switch 23 in Figure 3B), the signal of the bit line is pumped (or kicked) to at least VCCSA+M1, and the signal of the bit line bar is pumped (or kicked) to at least VSS-M2.

[0062] FIG. 9 shows the relationship between the signal of the bit line during the operation of the DRAM cell and the kick period. The kick period K4 of the signal of the bit line corresponding to the restore phase (or precharge) is longer than the kick period K1 corresponding to the active command, or longer than the kick periods K2 or K3 corresponding to the read command. Further, the kick period K1 of the signal of the bit line corresponding to the active command is equal to the kick periods K2 or K3 corresponding to the read command. Of course, during the periods K1 to K3, raising the signal of the bit line to the voltage level VCCSA+M1 or other voltage levels (e.g., VCCSA+ΔN, where ΔN<M1) can be performed by the bootstrap circuit. At this time, the charge of the capacitor in the bootstrap circuit is coupled to the bit line. Whatever the voltage source or bootstrap circuit, it can be regarded as a charge source, so the signal of the bit line can be kicked or pumped to the voltage level VCCSA+M1 or VCCSA+ΔN by the charge source. In that way, the signal of the bit line is kicked to VSS-M2 (or VSS-ΔN, where ΔN<M2).

Embodiment

[0063] In another embodiment, as shown in FIG. 10A, after T0, the word line voltage has risen to turn on the access transistor of the DRAM cell. Next, for normal read or write access to the DRAM, there is an active command to be executed. A corresponding voltage slightly higher than VCCSA (e.g., VCCSA + ΔN) may be connected to the sense amplifier during execution of the active command to reduce tRCD defined by JEDEC (as shown in FIG. 3A, by turning off switch 14 and turning on switch 13). Such a voltage level or voltage source is coupled to the bit line during the period from T1 to T2 (i.e., the access operation period). Thus, the corresponding voltage (VCCSA + ΔN) can be connected to the sense amplifier according to the active command. Thereafter, the signal on the bit line is pumped (or kicked) to at least VCCSA + ΔN during execution of the active command. Such a pump or kick of the bit line signal may be called an active kick. Such an active kick on the bit line, similar to the previous one that facilitates signal sensing, raising the bit line to the voltage level VCCSA + ΔN can be done by a bootstrap circuit. At this time, the charge of the capacitor in the bootstrap circuit is coupled to the bit line. Whatever the voltage source or bootstrap circuit, it can be regarded as a charge source, so the signal on the bit line can be kicked or pumped to the voltage level VCCSA + ΔN by the charge source.

[0064] After the execution of an active command or an active kick, the normal voltage source VCCSA is connected to the sense amplifier, and then the signals on the bit lines return to VCCSA during subsequent read or write operations. Similarly, after T2, during the restore phase, the first hold voltage source VCCSA+M1 (or a different hold voltage higher than VCCSA) is coupled to the capacitor of the DRAM cell during this restore phase, just as before. That is, during this restore phase, the original VCCSA voltage source is disconnected from the sense amplifier (e.g., by turning off switch 14 as shown in FIG. 3A), and the first hold voltage source VCCSA+M1 is to be connected to the sense amplifier 20 (e.g., by turning on switch 13 as shown in FIG. 3A). The signals on the bit lines are pumped (or kicked) to at least VCCSA+M1. Such a pump or kick of the bit line signals can be called a restore kick. Thus, before the word line WL is pulled down to fully turn off the access transistor of the DRAM cell, the holding capacitor of the DRAM cell is supplied with a voltage level of the first hold voltage source higher than that of the normal signal ONE (VCCSA), and the holding capacitor of the DRAM cell can be maintained for a longer period compared to the conventional DRAM structure even if there is a leakage current through the access transistor.

[0065] In one embodiment, the corresponding voltage (VCCSA+ΔN) used for the active kick is lower than the first sustain voltage (VCCSA+M1) used for the restore kick. The corresponding voltage (VCCSA+ΔN) and the first sustain voltage (VCCSA+M1) can be generated from two different voltage sources respectively. Alternatively, the corresponding voltage (VCCSA+ΔN) used for the active kick to kick the voltage of the bit line may be generated from the first sustain voltage source (VCCSA+M1), but the duration of connecting the first sustain voltage source (VCCSA+M1) to the bit line is adjusted such that the bit line is just pumped or kicked to the corresponding voltage (VCCSA+ΔN) instead of VCCSA+M1. Of course, in the present invention, the voltage (VCCSA+M1), the voltage (VCCSA+ΔN), and the voltage (VCCSA) may be generated or converted inside the DRAM, or supplied or converted from other voltage sources outside the DRAM chip.

[0066] However, as shown in FIG. 10B, during the restore kick, the first sustain voltage source VCCSA+M1 may not immediately pull up the voltage level of the bit line when there are RC delays due to an incomplete power mesh and bit lines or other delay causes within the DRAM array. That is, the restore kick may prevent the voltage level of the first sustain voltage source VCCSA+M1 from being sufficiently stored in the DRAM holding node or cell through the bit line, and in some cases, only the voltage level of (VCCSA+M1-ΔN) may be stored in the DRAM holding node or cell. Further, in the normal access commands of the DRAM, as shown in FIG. 10B, there are read or write operations executed between the active kick and the restore kick, and it is inappropriate to execute a pre-restore kick to eliminate the RC delay problem.

[0067] Nevertheless, as shown in FIG. 11A, for the execution of the refresh command in the DRAM, there is no read or write operation included in the refresh command. Therefore, it is appropriate to perform a restore kick (hereinafter, "preceding restore kick") in advance (for example, at timing 1, timing 2, or timing 3) to eliminate the RC delay problem. Thereby, the preceding restore kick can make the voltage level of the first holding voltage source VCCSA+M1 be fully or substantially stored in the DRAM holding node or cell through the bit line, rather than the voltage level of "VCCSA+M1-ΔN" based on the previous "restore kick" described only in FIG. 10. Therefore, the holding capacitor can maintain a longer holding period.

[0068] When VCCSA+M1 is too high, there are concerns about reliability (for example, when VCCSA is 1.1V, a value of 1.5V or 1.6V for VCCSA+M1 may be too high). Therefore, optimized voltage and preceding kick timing are essential. Different timings of the preceding restore kick can be generated by internal timing control during refresh. FIG. 11B (preceding restore kick at timing 3) shows that the period Pa between the active kick and the preceding restore kick is less than 50% or 60% of the period Pb between T1' and T3. Here, T1' is the time when the voltage difference between the bit line and the bit line bar is sufficient for the sense amplifier to sense, and T3 is the time when the voltage level of the word line begins to be pulled down. Therefore, the period Pb includes the kick period of the active kick, another period (or the first period) when the VCCSA voltage source is coupled to the bit line, and another period (or the second period) when the VCCSA+M1 voltage source is coupled to the bit line. The VCCSA+M1 voltage can be applied to the bit line (similarly for the holding capacitor of the DRAM cell) for more than about 20% or 30% of the period Pb. In other examples, the active kick may not be required during the refresh operation. That is, the waveform of the bit line during refresh has only the restore kick.

[0069] Figure 11C (precharge kick at timing 2) indicates that the period Pa between the active kick and the precharge kick is less than 30% of the period between T1' and T3. Therefore, the VCCSA+M1 voltage can be applied to the bit line for about 50% or 60% or more of the period Pb. Figure 11D (precharge kick at timing 1) indicates that the period Pa is zero, that is, the precharge kick is used to replace the active kick and is maintained until the voltage level of the word line is pulled down. Therefore, the VCCSA+M1 voltage can be applied to the bit line for about 90% or more of the period Pb. However, when there are concerns about reliability when a higher kick voltage is continuously applied to the sense amplifier and the DRAM cell, the kick voltage VCCSA+M1 used in Figure 11D (precharge kick at timing 1) may be smaller than that used in Figure 11C (precharge kick at timing 2). For example, when VCCSA = 1.1V, the kick voltage VCCSA+M1 used in Figure 11D (precharge kick at timing 1) may be 1.3V, the kick voltage VCCSA+M1 used in Figure 11C (precharge kick at timing 2) may be 1.31 - 1.35V, and the kick voltage VCCSA+M1 used in Figure 11B (precharge kick at timing 3) may be 1.36 - 1.4V.

Example

[0070] On the other hand, in the conventional DRAM operation shown in FIGS. 1B and 1H, after the restore phase and after the voltage of the word line is lowered from VPP (or a value higher than Vcc + Vt) to a lower voltage value (e.g., -0.3V) to deactivate the access transistor of the DRAM cell, the precharge phase starts and the voltage equalization circuit 21 becomes active to place the refresh voltage Vref on both the bit line and the bit line bar. Such Vref is equal to 1 / 2×VCCSA (or 1 / 2×Vcc), or equal to the bit line equalization voltage VBL that is in the middle between the voltage on the bit line and the voltage on the bit line bar during the restore phase. In the conventional DRAM circuit, the value of VBL is also equal to 1 / 2×VCCSA (or 1 / 2×Vcc).

[0071] In the present invention, the voltage on the bit line during the restore phase is kicked up to a voltage higher than VCCSA + M1 or VCCSA (hereinafter, "VCCSAh" or "V2") through the sense amplifier. Similarly, after the restore phase and after the voltage of the word line is lowered to deactivate the access transistor of the DRAM cell, the precharge phase starts and the voltage equalization circuit becomes active to place the reference voltage Vref on both the bit line (hereinafter "BL") and (Outer 5) TIFF0007683883000005.tif5114 (hereinafter, the bit line bar or "BLB"). The target value of the reference voltage Vref (or the target bit line equalization voltage VBL) is set to 1 / 2×VCCSA or 1 / 2×Vcc. However, in this situation, the bit line equalization voltage VBL that is in the middle between the voltage on the bit line and the voltage on the bit line bar during the refresh phase becomes 1 / 2×VCCSAh which is higher than the target reference voltage 1 / 2×VCCSA.

[0072] As shown in FIG. 12A representing the timing diagram of the above operation, by the kick voltage VCCSAh (or "V2", the restore voltage to the cell's holding node) of the bit line, at the start of equalization, BL and BLB are first pulled to V1 which is 1 / 2×VCCSAh (that is, the charge sharing voltage between BL and BLB at the start of bit line equalization), and then gradually lowered to the target VBL voltage (1 / 2×VCCSA). Since V1 is not equal to the target VBL (for example, V1 > 1 / 2×VCCSA), due to the excess voltage (V1 - target VBL), the temporary bit line equalization voltage VBL may increase during equalization. After the voltage equalization circuit becomes inactive instead of the equalization period EQBL, the voltage values of BL, BLB, and the temporary bit line equalization voltage VBL still remain at inappropriate voltage levels. Therefore, the low dropout circuit (LDO) of the VBL generator needs to wait for the temporary bit line equalization voltage VBL to return to the target value of VBL (1 / 2×VCCSA). The correction time is slow so that the next activation is affected. For example, as shown in FIG. 12B, although the next active command occurs after the end of the equalization period EQBL, if the temporary bit line equalization voltage VBL is still higher than the target VBL (or the target reference voltage), it will damage the generation of subsequent small signals by the next active command. Therefore, it is necessary to clean up the excess voltage (V1 - target VBL) during the equalization period so that the accurate bit line equalization voltage level (that is, target VBL = 1 / 2×VCCSA) and the correct generated voltage by the next active command can be achieved.

[0073] Therefore, as shown in FIG. 12A or FIG. 12B, the bit line voltage is kicked up during the restore phase, then the voltage of the word line is lowered to deactivate the access transistor of the DRAM cell, and then the equalization circuit is activated. Nevertheless, the excessive voltage (V1 - target VBL) affects the next active command. Therefore, a cleanup circuit is proposed, and the excessive voltage (V1 - target VBL) or the extra charge in BL / BLB during equalization is reduced or removed with the help of the cleanup circuit. Thereby, before the activation of the next word line, both BL and BLB are set to the target VBL (i.e., 1 / 2 × VCCSA).

[0074] As shown in FIG. 13, the cleanup circuit is controlled by a clean pulse. The start of the clean pulse may be similar to the on-timing of EQBL or triggered by the rising edge of the EQBL pulse. The width of the clean pulse depends on the restore voltage (VCCSAh). The higher the restore voltage, the more the excessive voltage (V1 - target VBL) is, and thus the width of the clean pulse must be wider. By the cleanup circuit controlled by the clean pulse, the voltage of BL / BLB immediately changes from V1 to the target VBL (1 / 2 × VCCSA) before the next activation of the word line, and the same is true for the temporary bit line equalization voltage VBL. Therefore, the correct bit line equalization voltage level (i.e., target VBL = 1 / 2 × VCCSA) and the correct generated voltage by the next active command can be achieved.

[0075] As shown in FIG. 14A, which is similar to FIG. 1C, since both the sense amplifier 20 and the voltage equalization circuit 21 are coupled to the bit line (“BL”) and the bit line bar (“BLB”), the cleanup circuit 141 is coupled to the sense amplifier circuit 20 (shown in FIG. 14B.) or the voltage equalization circuit 21 (shown in FIG. 14C.), and the cleanup circuit 141 can be activated to clean up the excessive voltage during the equalization period EQBL.

[0076] For example, in FIG. 15A, the cleanup circuit 141 includes a switch circuit 142 coupled to the SAP (or LSLP) point of the sense amplifier 20 and to ground (or another predetermined voltage level). Since BL / BLB is coupled to the SAP (or LSLP) point through two P-type transistors (“PFet”) of the sense amplifier circuit 20, the above-mentioned excess voltage (V1 - target VBL) is reduced, and the corresponding extra charge is discharged to ground through the dashed line shown in FIG. 15A when the switch circuit 142 is activated by a cleanup pulse (Clean_Pulse) during the equalization period EQBL. Therefore, at the end of the cleanup pulse, the voltages of BL and BLB are set to the target VBL.

[0077] In another example shown in FIG. 15B, the cleanup circuit 141 includes a switch circuit 142 coupled to the VBL point of the voltage equalization circuit 21 and to ground (or another predetermined voltage level). Since BL / BLB is coupled to the VBL point through two transistors of the voltage equalization circuit 21, the above-mentioned excess voltage (V1 - target VBL) is reduced, and the corresponding extra charge is discharged to ground through the dashed line shown in FIG. 15B when the switch circuit 142 is activated by a cleanup pulse (Clean_Pulse) during the equalization period EQBL. Therefore, at the end of the cleanup pulse, the voltages of BL and BLB are set to the target VBL.

[0078] In fact, the cleanup circuit 141 can be coupled to any position (e.g., point SAN or LSLN) that can clean up the excess voltage during equalization. For example, the cleanup circuit 141 can be electrically coupled directly or indirectly to BL and BLB during the equalization period such that the cleanup circuit reduces the difference between the voltage of BL (or the voltage of BLB) and the target VBL during the equalization period.

[0079] Furthermore, the proposed cleanup circuit can be applied to a DRAM circuit even if there is no kick-up voltage applied during the restore period as long as there is a difference between V1 and the target VBL. For example, when V1 > target VBL, that is, when 1 / 2×(voltage of BL + voltage of BLB) at the start of equalization is higher than the target VBL, the voltages of BL and BLB are pulled down by the cleanup circuit. This is because BL and BLB can be coupled to ground (or other predetermined low voltage) through the cleanup circuit during the cleanup pulse period. Therefore, at the end of the cleanup pulse, the voltages of BL and BLB are set to the target VBL.

[0080] On the other hand, when V1 < target VBL, that is, when 1 / 2×(voltage of BL + voltage of BLB) at the start of equalization is lower than the target VBL, the voltages of BL and BLB are pulled up by the cleanup circuit. This is because BL and BLB can be coupled to VCCSA (or other predetermined high voltage) through the cleanup circuit during the cleanup pulse period. Therefore, at the end of the cleanup pulse, the voltages of BL and BLB are set to the target VBL. The comparator circuit 143 (shown in FIG. 15C.) may be used to compare V1 (or 1 / 2×(voltage of BL + voltage of BLB)) with the target VBL (or a pre-set reference voltage). For example, the comparator circuit 143 receives the voltages of BL, BLB, and the target VBL at the start of the equalization period and compares the value of 1 / 2×(voltage of BL + voltage of BLB) with the target VBL. If V1 is not equal to the target VBL, the comparator circuit 143 sends a control signal to the cleanup circuit 141, and then the cleanup circuit 141 is activated by the cleanup pulse during equalization. In one embodiment, the width of the cleanup pulse is not longer than that of the equalization period. Thus, after the end of the equalization period, the voltages of BL and BLB are set to the target VBL.

[0081] Summarizing the above description, the present invention discloses a DRAM with a sustainable retention architecture. Before the access transistor of the DRAM retention cell turns off (or the word line connected to the DRAM retention cell turns off), a first holding voltage higher than the voltage level of signal ONE can be restored or stored in the DRAM retention cell. Also, before the access transistor of the DRAM retention cell turns off (or the word line connected to the DRAM retention cell turns off), a second holding voltage lower than the voltage level of signal ZERO can also be restored or stored in the DRAM retention cell. Thus, after the access transistor turns off, the holding capacitor can be maintained for a longer period compared to the conventional DRAM structure even if there is a leakage current through the access transistor. Further, a cleanup circuit is provided to clean up the excessive voltage during equalization, thereby achieving an accurate bit line equalization voltage level and an accurate generated voltage by the next active command.

[0082] The present invention has been illustrated and described with reference to embodiments, but the present invention should not be limited to the disclosed embodiments. On the contrary, it is to be understood that the present invention is intended to cover various modifications and equivalent substitutions included within the spirit and scope of the appended claims.

Description of Reference Numerals

[0083] 11 Access transistor 12 Holding capacitor 20 Sense amplifier 21 Voltage equalization circuit 141 Cleanup circuit 142 Switch circuit 143 Comparator circuit BL Bit line BLB Complementary bit line Clean_Pulse Cleanup pulse EQBL Equalization period WL Word line

Claims

1. A DRAM chip, comprising: a first holding voltage generation unit configured to generate a first voltage level higher than a voltage level of a driving power source or a high signal corresponding to a binary value 1 written in the DRAM chip; a DRAM cell having an access transistor and a holding capacitor; a sense amplifier coupled to a bit line and a complementary bit line, wherein the bit line is coupled to the holding capacitor through the access transistor, and the sense amplifier is further connected to a pull-up circuit and a pull-down circuit; an equalization circuit coupled to the bit line and the complementary bit line; a cleanup circuit coupled to the sense amplifier or the equalization circuit, the cleanup circuit being controlled by a cleanup pulse during an equalization period, a width of the cleanup pulse being narrower than a width of the equalization period and adjustable; and having wherein the first holding voltage generation unit is electrically coupled to the bit line continuously from before to during a turn-off period of the access transistor, the equalization period is after the turn-off period of the access transistor, and the cleanup circuit is activated to reduce a difference between a voltage of the bit line and a target reference voltage during the equalization period. A DRAM chip.

2. further comprising a word line coupled to a gate terminal of the access transistor, wherein the word line is selected to turn on the access transistor during a first period and a second period after the first period, and the first holding voltage generation unit is electrically coupled to the bit line during the second period. The DRAM chip according to claim 1.

3. wherein the first holding voltage generation unit is electrically coupled to the sense amplifier during the second period, and the first holding voltage generation unit is electrically coupled to the holding capacitor of the DRAM cell through the sense amplifier and the bit line. The DRAM chip according to claim 2.

4. wherein the first period is an access operation period and the second period is a restore phase period. The DRAM chip according to claim 2.

5. a kicking charge source is electrically coupled to the bit line during the access operation period. The DRAM chip according to claim 4.

6. The first period has a first kick period and a second kick period separated from the first kick period, and the kicking charge source is coupled to the bit line during the first kick period or is coupled to the bit line during the first kick period and the second kick period. The DRAM chip according to claim 2.

7. The voltage level of the kicking charge source is smaller than the voltage level of the first voltage generation unit. The DRAM chip according to claim 6.

8. The word line is selected to turn on the access transistor during the first period and the second period according to a refresh operation. The DRAM chip according to claim 2.

9. The kicking charge source is electrically coupled to the bit line during a kick period that is before the first period, and the first voltage generation unit is electrically coupled to the bit line during all of the second period. The DRAM chip according to claim 8.

10. The second period is at least 20% of the sum of the kick period, the first period, and the second period. The DRAM chip according to claim 9.

11. The second period is at least 50% of the sum of the kick period, the first period, and the second period. The DRAM chip according to claim 9.

12. The equalization period is after the turn-off period of the access transistor, and the cleanup circuit is activated during the equalization period so that the voltage of the bit line becomes equal to the target reference voltage after the equalization period. The DRAM chip according to claim 1.

13. The fall of the cleanup pulse is before the fall of the equalization period. The DRAM chip according to claim 12.

14. The rise of the cleanup pulse is substantially aligned with the rise of the equalization period. The DRAM chip according to claim 12.

15. The cleanup circuit has a sense amplifier and a switch circuit coupled to a predetermined voltage. The DRAM chip according to claim 1.

16. The cleanup circuit has an equalization circuit and a switch circuit coupled to a predetermined voltage. The DRAM chip according to claim 1.

17. A DRAM chip, A first holding voltage generation unit that generates a first voltage level higher than the voltage level of a high signal corresponding to the binary value 1 written to the driving power supply or the DRAM chip; A DRAM cell having an access transistor and a holding capacitor; A sense amplifier coupled to the bit line and the complementary bit line, the bit line being coupled to the holding capacitor through the access transistor, the sense amplifier being further connected to a pull-up circuit and a pull-down circuit; An equalization circuit coupled to the bit line and the complementary bit line; A cleanup circuit electrically coupled to the bit line and the complementary bit line during an equalization period, controlled by a cleanup pulse during the equalization period, the width of the cleanup pulse being narrower than the width of the equalization period and adjustable; And having; The first holding voltage generation unit is electrically coupled to the bit line continuously from before and during the turn-off period of the access transistor, the equalization period is after the turn-off period of the access transistor, the cleanup circuit reduces the difference between the voltage of the bit line and a target reference voltage during the equalization period, and makes the voltage of the bit line and the voltage of the complementary bit line equal to the target reference voltage during the equalization period, the target reference voltage being equal to half of the voltage level of the high signal corresponding to the binary value 1 written to the driving power supply or the DRAM chip; DRAM chip.

18. The voltage of the bit line is equal to the target reference voltage after the equalization period; The DRAM chip according to claim 17.

19. The cleanup circuit is electrically coupled to the bit line and the complementary bit line during the equalization period through the sense amplifier or the equalization circuit; The DRAM chip according to claim 17.

20. The cleanup circuit has a switch circuit coupled to the sense amplifier and a predetermined voltage; The DRAM chip according to claim 19.

21. The cleanup circuit has a switch circuit coupled to the equalization circuit and a predetermined voltage; The DRAM chip according to claim 19.

22. The rise of the clean-up pulse is substantially aligned with the rise of the equalization period. The DRAM chip according to claim 17.

23. A DRAM chip, a first holding voltage generation unit that generates a first voltage level higher than a voltage level of a driving power source or a high signal corresponding to a binary value 1 written to the DRAM chip; a DRAM cell having an access transistor and a holding capacitor; a sense amplifier coupled to a bit line and a complementary bit line, the bit line being coupled to the holding capacitor through the access transistor; the sense amplifier; an equalization circuit coupled to the bit line and the complementary bit line; a clean-up circuit that is electrically coupled to the bit line and the complementary bit line during an equalization period and reduces a difference between a voltage of the bit line and a target reference voltage during the equalization period; a comparator circuit that receives the voltage of the bit line, the voltage of the complementary bit line, and the target reference voltage at a start of the equalization period or during the equalization period, and transmits a control signal to the clean-up circuit when a half of a sum of the voltage of the bit line and the voltage of the complementary bit line is not equal to the target reference voltage; and the first holding voltage generation unit is electrically coupled to the bit line continuously from before to during a turn-off period of the access transistor, and the equalization period is after the turn-off period of the access transistor. The DRAM chip.

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