Distribution of power shared between an acceleration processing unit and a discrete graphics processing unit

Abstract

An integrated coprocessor, such as an accelerated processing unit (APU), generates commands for execution by a discrete coprocessor, such as a discrete graphics processing unit (dGPU). A power distribution circuit selectively supplies power to the APU and the dGPU based on characteristics of workloads executed on the APU and the dGPU and a platform power limit shared by the APU and the dGPU. In some cases, the power distribution circuit determines a first power supplied to the APU and a second power supplied to the dGPU. In some cases, the power distribution circuit increases the second power supplied to the dGPU in response to a sum of the first power and the second power being less than the platform power limit. In some cases, the power distribution circuit varies the power supplied to the APU, the dGPU, or both in response to changes in temperature measured by a series of sensors.

Description

Background Art

[0001] High-performance computing devices such as laptop computers, tablet computers, mobile phones, and smartwatches include heterogeneous processing units such as an acceleration processing unit (APU) that includes multiple types of coprocessors. For example, an APU typically includes one or more central processing unit (CPU) cores and one or more graphics processing unit (GPU) cores, which may also be referred to as an integrated GPU (iGPU). Additional graphics processing capabilities, and in some cases, general-purpose computing capabilities, are provided by including a discrete graphics processing unit (dGPU) in the computing device. The power dissipated by the APU and dGPU tends to increase the temperature of the computing device. Therefore, the APU and dGPU are connected to a heat dissipation system such as a heat pipe that transfers heat from the APU and dGPU towards a corresponding heat sink that dissipates the thermal energy to the environment. The cooling requirements of the system are determined at least in part by the structure of the computing device and the thermal energy dissipated by the APU and dGPU. The heat dissipation system of the APU and dGPU maintains the temperatures of the APU and dGPU below levels that would lead to component damage or shortened service life.

[0002] This disclosure will be better understood by reference to the accompanying drawings, and many of its features and advantages will be apparent to those skilled in the art. When the same reference numerals are used in different drawings, they indicate similar or identical items.

Brief Description of the Drawings

[0003]

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DETAILED DESCRIPTION OF THE INVENTION

[0004] The system management unit (SMU) implements power management techniques for allocating power to an integrated coprocessor core (such as a central processing unit (CPU) core of an accelerated processing unit (APU)) and a discrete coprocessor core (such as a discrete graphics processing unit (dGPU)) based on the power and thermal envelope of the corresponding fixed processor. For example, the SMU allocates power to the CPU core of the APU based on the thermal design point (TDP) set based on executing a large workload on the APU under worst-case conditions. The TDP represents the upper limit of sustainable power and is used to determine the cooling requirements of the system. In another example, the SMU allocates power to the dGPU based on the total graphics power (TGP) that represents the maximum amount of graphics board power provided by the system power to the dGPU. In some cases, the maximum operating temperature of the device is limited by the user's perception rather than the temperature limit of the silicon. The heat generated by the processing unit of the handheld device is conducted to the outer surface of the device such as the display and the casing, and the user interfaces with the device during operation of the device. To provide a comfortable experience for the user, the maximum power budgets allocated to the APU and the dGPU are set to corresponding fixed limits that may be lower than the TDP or the TGP respectively, to keep the surface temperature of the device lower than the value at which the user feels uncomfortably hot.

[0005] In the case of an ultra-thin platform used in the implementation of a handheld or wearable computing device, the thermal capacity of the housing and the thermal solution cannot support the provision of full TDP to the APU while providing full TGP to the dGPU and the associated video memory. Operating the APU at full TDP while operating the dGPU at full TGP will cause the ultra-thin platform device to heat up to temperatures that can damage the device or at least cause discomfort to the user. Therefore, the power supplied to the APU is artificially and statically limited to a low level so that the APU can operate at its (reduced) maximum power level while the dGPU can operate at TGP. Furthermore, the power supplied to the dGPU does not increase in response to the APU operating below its maximum power level, nor does the power supplied to the APU increase in response to the dGPU operating below TGP. In the case of a high-performance platform, the thermal capacity of the housing and the thermal solution supports the provision of full TDP to the APU while providing full TGP to the dGPU and the associated video memory. However, there are limited opportunities for performance improvement for either core-intensive workloads that primarily utilize the APU or graphics-intensive workloads that primarily utilize the dGPU.

[0006] Figures 1-5 disclose embodiments of a computing device that distributes power to one or more integrated coprocessor cores and one or more discrete coprocessor cores based on the characteristics of workloads executed on the integrated coprocessor cores and the discrete coprocessor cores, and the platform power limit shared by the integrated coprocessor cores and the discrete coprocessor cores. In some embodiments, the power distribution circuit manages the power consumption of the APU implementing the integrated coprocessor core and the dGPU implementing the discrete coprocessor core based on the available platform power (e.g., supplied by an AC power source or a battery) and thermal constraints. For example, the power distribution circuit selectively distributes power from the APU to the dGPU for graphics-intensive workloads. The amount of power supplied to the dGPU is determined based on the available platform power and thermal constraints such as the maximum surface temperature of the computing device. The surface temperature is determined based on a pre-calibrated parameter that determines the relationship between the temperature measured using one or more temperature sensors and the surface temperature of the computing device. Also, the power distribution circuit dynamically changes the power supplied to the integrated coprocessor core and the discrete coprocessor core in response to changes in the characteristics of the workloads executed on the integrated coprocessor core and the discrete coprocessor core and changes in the surface temperature. For example, the power distribution circuit shifts power from the dGPU to the APU in response to a shift in the workload from graphics-intensive to core-intensive. In another example, the power distribution circuit reduces the power supplied to the dGPU for a graphics-intensive workload in response to the measured temperature rising above a threshold. Some embodiments of the power distribution circuit distribute power to the APU based on the maximum power loss (Qmax) of the heat pipe associated with the APU.

[0007] FIG. 1 is a block diagram of a device 100 that includes an integrated processing unit 105 and individual discrete coprocessors 110, according to some embodiments. In the illustrated embodiment, the integrated processing unit 105 is implemented as an accelerated processing unit (APU) 105, and the individual discrete coprocessor 110 is implemented as a graphics processing unit (dGPU) 110. However, the integrated processing unit 105 or the discrete coprocessor 110 may be implemented using other types of coprocessors, digital signal processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), etc. in other embodiments. Some embodiments of the device 100 are realized in a handheld or wearable device such as a laptop computer, a handheld computer, a tablet computer, a mobile device, a phone, a personal data assistant (PDA), a music player, a game device, etc.

[0008] The APU 105 includes integrated coprocessor cores such as one or more central processing unit (CPU) cores 115 and one or more graphics processing unit (GPU) cores 120 collectively referred to as an integrated GPU (iGPU) 125. The one or more CPU cores 115 and the one or more iGPUs 125 are disposed on the same integrated circuit (IC) die or on different IC dies within the same IC package. The CPU cores 115 have independently controlled power planes that enable them to be controlled independently of the voltages and frequencies associated with the GPU cores 120. Some embodiments of the dGPU 110 include one or more discrete coprocessor cores 127. The dGPU 110 also has independently controlled power planes that enable the voltages and frequencies provided to the dGPU 110 (or the discrete coprocessor cores 127) to be controlled independently of the voltages and frequencies associated with the APU 105, the CPU cores 115, or the GPU cores 120.

[0009] Device 100 includes a system memory 130, a display 135, and a power source 140 (including a voltage regulator, a battery, and a battery charging unit, which are not shown separately for clarity). Although not shown clearly in FIG. 1, the north bridge controller of the APU 105 provides an interface to the system memory 130. The operation of the device 100 is generally controlled by an operating system that includes software that interfaces with various elements of the device 100. The APU 105 integrates the CPU core 115 and the GPU core 120 on a common semiconductor die, enabling them to share on-die resources such as the memory hierarchy and interconnections.

[0010] Device 100 includes an outer casing 145 that supports the display 135 and surrounds the active components of the device 100. The outer casing 145 also provides the outer surfaces through which a user interfaces with the device 100. The APU 105 controls the display 135 and, in embodiments where the display 135 is a touch screen, receives user input from the display 135. The dGPU 110 or the iGPU 125 provides signals to the display 135 via a bus 150 such as a peripheral device interconnect (PCI, PCI-E) bus. The signals include information representing the color and intensity generated by pixels at the display 135, and these are combined to generate an image visible to a user looking at the display 135. When the display 135 is a touch screen, the bus 150 is used to transmit signals from the display 135 to the APU 105, and the APU 105 uses the signals to initiate operations based on the positions of touch points (and, optionally, the amount or duration of pressure applied by the user) on the display 135.

[0011] One or more temperature sensors 151, 152, such as sensor 151 proximate to casing 145 and sensor 152 proximate to display 135, are provided in device 100. The surface temperature indicating the temperature perceived by the user holding the device is estimated based on the temperatures measured by temperature sensors 151, 152. In some embodiments, the relationship between the measured temperature and the surface temperature is pre-calibrated by comparing the actually measured surface temperature with the measured value. For example, the parameters of the model associating the surface temperature with the measured temperature are determined using a calibration process that directly measures the temperature of portions of the outer casing 145 and correlates these measurements with the temperatures measured by sensors 151, 152. Other counters, such as activity counters like CPU counter 155, GPU counter 160, and memory counters (not shown in FIG. 1 for clarity), are provided in some embodiments of device 100 to generate device activity metrics for components and to estimate the heat generated by the components and how that heat contributes to the surface temperature.

[0012] Power is distributed from power supply 140 to APU 105 and dGPU 110 via power distribution circuit 165. In the illustrated embodiment, APU 105 includes SMU 170, dGPU 110 includes SMU 175, and SMU 175 monitors the power consumption characteristics of dGPU 110, such as the current power dissipated or supplied to dGPU 110. SMU 175 provides information indicative of the power consumption characteristics to APU 105. The power consumption information is provided periodically, at predetermined time intervals, in response to power-related events in dGPU 110, or at other times. Based on the received power consumption information, SMU 170 determines and dynamically adjusts the power supplied by power supply 140 to APU 105 and dGPU 110 based on the characteristics of the workloads executed on APU 105 and dGPU 110. The distribution of power to APU 105 and dGPU 110 is also based on a platform power limit shared by APU 105 and dGPU 110. In some embodiments, the platform power limit is equal to (or determined based on) the sum of the thermal design point (TDP), which is set based on executing a heavy workload on APU 105 under worst-case conditions, and the total graphics power (TGP), which represents the maximum amount of graphics board power that the system power supplies to dGPU 110. The TDP represents the upper limit of sustainable power provided to APU 105 and is used in determining the system cooling requirements. In some embodiments, the power supplied to dGPU 110 may exceed the TGP without damaging dGPU 110 or other circuits within device 100.

[0013] SMU170 changes the power allocated to APU105 and dGPU110 in response to changes in the characteristics of the workloads executed by APU105 or dGPU110. Some embodiments of SMU170 shift power from APU105 to dGPU110 in response to the workload shifting from a core-intensive workload that primarily consumes the resources of APU105 to a graphics-intensive workload that primarily consumes the resources of dGPU110. Also, SMU170 shifts power from dGPU110 to APU105 in response to the workload shifting from a graphics-intensive workload that primarily consumes the resources of dGPU110 to a core-intensive workload that primarily consumes the resources of APU105.

[0014] Some embodiments of SMU170 perform surface temperature tracking (STT). For example, SMU170 can implement an STT controller 172 that sets a dynamic power limit for device 100 based on the determined surface temperature. SMU170 uses the information provided by STT controller 172, in conjunction with the constraints imposed by the platform power limit and the characteristics of the workloads executed on APU105 and dGPU110, to dynamically determine the power distribution between APU105 and dGPU110. Within the power allocated to APU105, the STT controller of SMU170 implements dynamic voltage and frequency scaling (DVFS) to adapt the voltage and clock levels of CPU cores 115 and GPU cores 120. Also, some embodiments of SMU170 control the bandwidth allocated to system memory 130, or the battery charging rate used by power supply 140, to control their respective thermal contributions.

[0015] The surface temperature of device 100 is estimated using a pre-calibrated correlation between the temperatures measured by temperature sensors 151, 152 and the measured value of the surface temperature. The pre-calibrated correlation is used to set the values of parameters that associate the temperatures measured by temperature sensors 151, 152 with the surface temperature perceived by the user using device 100. Based on the estimated surface temperature, SMU 170 changes the power allocated to APU 105 or dGPU 110. For example, if SMU 170 determines that the sum of the first power supplied to APU 105 and the second power supplied to dGPU 110 is less than the platform power limit, SMU 170 increases the power supplied to dGPU 110. Further, SMU 170 (or STT controller 172) determines or changes the power provided to dGPU 110 by an amount determined based on a comparison between the surface temperature and the maximum surface temperature set by the thermal constraints of device 100 or dGPU 110. For example, SMU 170 decreases the power provided to dGPU 110 in response to the surface temperature exceeding the maximum surface temperature. As another example, SMU 170 increases the power provided to dGPU 110 (and, optionally, APU 105) in response to the surface temperature falling below the maximum surface temperature.

[0016] Figure 2 is a block diagram of a processing system 200 including a heat dissipation mechanism for an integrated coprocessor 205 and a discrete coprocessor 210 according to some embodiments. In the illustrated embodiment, the integrated coprocessor 205 is implemented as an APU 205, and the discrete coprocessor 210 is implemented as a dGPU 210. The processing system 200 is used to implement some embodiments of the device 100 shown in FIG. 1. The processing system 200 includes a system management unit (SMU) 215 that distributes power from a power supply 220 to the APU 205 and the dGPU 210. Some embodiments of the power supply 220 include (or are connected to) a power distribution circuit that communicates between the APU 205 and the dGPU 210 to exchange workload activity demand and power limit information with the SMU 215. For example, the GPU 205, the dGPU 210, and the SMU 215 can communicate via a PCIe bus using a serial bus two-wire (I2C) protocol, a one-wire protocol, etc.

[0017] In the illustrated embodiment, the APU 205 is connected to a heat pipe 225 that conducts heat from the APU 205 to a corresponding heat sink 230. The dGPU 210 is connected to a heat pipe 235 that conducts heat from the dGPU 210 to a corresponding heat sink 240, and the heat sink 240 is the same as or different from the heat sink 230 depending on the embodiment. Some embodiments of the SMU 215 distribute power to the APU 205 based on the maximum power loss (Qmax) of the heat pipe 225 and distribute power to the dGPU 210 based on the Qmax of the heat pipe 235.

[0018] FIG. 3 is a plot 300 showing the dynamic shift of shared platform power from an integrated coprocessor to a discrete coprocessor according to some embodiments. Plot 300 shows the dynamic distribution of power performed by a power distribution circuit such as some embodiments of SMU 170 shown in FIG. 1 and SMU 215 shown in FIG. 2. The power distribution circuit distributes power based on the characteristics of the workloads executed by the APU and the dGPU and a platform power limit 305 indicating the total power available for power distribution by the power distribution circuit.

[0019] Before time T1, the power distribution circuit provides a first power 310 to the APU and a second power 315 to the dGPU. In the illustrated embodiment, the device including the APU and the dGPU is executing a workload that is approximately evenly divided between the core workload executed by the APU and the graphics workload executed by the dGPU. Thus, the first power 310 and the second power 315 are approximately equal during the time interval before time T1, although the first power 310 is slightly less than the second power 315 in the illustrated embodiment. The sum of the first power 310 and the second power 315 is determined based on the platform power limit 305.

[0020] The power distribution circuit also takes into account thermal constraints such as the maximum surface temperature to determine the power supplied to the APU and the dGPU. In the illustrated embodiment, due to thermal constraints, less than the total power available under the platform power limit 305 is distributed to the APU and the dGPU. For example, the sum of the power supplied to the APU and the dGPU is equal to a reduced platform power limit 320 that is less than the platform power limit 305 by an amount 325 determined by the thermal constraints.

[0021] The power distribution circuit shifts power from the APU to the dGPU starting from time T1. In the illustrated embodiment, the power distribution circuit shifts power in response to a shift in the workload from core-intensive to graphics-intensive. For example, the power distribution circuit decreases the first power 310 by a first amount and increases the second power 315 by a corresponding amount. In the illustrated embodiment, the decrease in the first power 310 is equal to the increase in the second power 315, but the ratio of the decrease in the first power 310 to the increase in the second power 315 is not necessarily 1:1, and this ratio has different values depending on the power consumption characteristics of the APU and the dGPU. Shifting power from the APU to the dGPU improves the performance of the graphics-intensive workload, but the total of the distributed power still remains below the platform power limit 305 and the reduced platform power limit 320.

[0022] Figure 4 is a plot 400 showing the dynamic shift of shared platform power from a discrete coprocessor to an integrated coprocessor according to some embodiments. Plot 400 shows the dynamic distribution of power executed by a power distribution circuit such as some embodiments of the SMU170 shown in FIG. 1 and the SMU215 shown in FIG. 2. The power distribution circuit distributes power based on the characteristics of the workloads executed on the APU and the dGPU and a platform power limit 405 indicating the total power available for power distribution by the power distribution circuit. The power distribution circuit takes into account thermal constraints such as the maximum surface temperature to determine the power supplied to the APU and the dGPU. In the illustrated embodiment, however, the thermal constraints do not impose a significant constraint on the available power, and the reduced platform power limit 420 is approximately equal to the platform power limit 405.

[0023] Before time T1, the power distribution circuit provides the first power 410 to the APU and the second power 415 to the dGPU. In the illustrated embodiment, the devices including the APU and the dGPU execute a workload that is approximately evenly divided between the core workload executed by the APU and the graphics workload executed by the dGPU. Thus, the first power 410 and the second power 415 are approximately equal during the time interval before time T1, although the first power 410 is slightly less than the second power 415 in the illustrated embodiment. The sum of the first power 410 and the second power 415 is determined based on the platform power limit 405.

[0024] The power distribution circuit shifts power from the dGPU to the APU starting at time T1. In the illustrated embodiment, the power distribution circuit shifts power in response to the workload shifting from being graphics-intensive to core-intensive. For example, the power distribution circuit increases the first power 410 by a first amount and decreases the second power 415 by a corresponding amount. In the illustrated embodiment, the increase in the first power 410 is equal to the decrease in the second power 415, although the ratio of the increase in the first power 410 to the decrease in the second power 415 is not necessarily 1:1 and this ratio has different values depending on the power consumption characteristics of the APU and the dGPU. In some embodiments, the increase in the first power 410 (or the total value of the first power 410) is limited to a value below the TDP of the APU. Thus, shifting power from the dGPU to the APU improves the performance of the core-intensive workload, although the total of the distributed power still remains below the platform power limit 405 and the reduced platform power limit 420.

[0025] Figure 5 is a flowchart 500 of a method for changing power allocation to an integrated coprocessor and a discrete coprocessor based on the characteristics of a workload and platform power limits, according to some embodiments. Method 500 is implemented in some embodiments of the SMU 170 of device 100 shown in FIG. 1 and the SMU 215 of processing system 200 shown in FIG. 2. As described herein, the platform power limit is shared between the APU and the dGPU, and the SMU can freely distribute the shared power between the APU and the dGPU.

[0026] At block 505, the SMU determines the characteristics of the workload. In some embodiments, the characteristics include metrics of the relative core intensity and graphics intensity of the workload. A workload that performs a large number of calculations but does not generate display images is considered more core-intensive, and a workload that performs few calculations but generates high-resolution display images is considered more graphics-intensive.

[0027] At block 510, the SMU collects temperature measurements from one or more sensors distributed throughout the device. In some embodiments, the temperature values measured by the sensors are used to infer thermal conditions (such as surface temperature) that are compared to corresponding thermal constraints (such as maximum surface temperature). As described herein, the thermal conditions are inferred using relationships defined by parameters determined using a calibration process executed during the configuration of the device.

[0028] At decision block 515, the SMU determines whether there has been a change in the workload of the APU or the dGPU. Examples of changes in the workload include, but are not limited to, a shift from a core-intensive workload to a graphics-intensive workload, a shift from a graphics-intensive workload to a core-intensive workload, an increase or decrease in the workload assigned to the APU or the dGPU, etc. If no change in the workload is detected, method 500 returns to block 505. If a change in the workload is detected, method 500 proceeds to block 520.

[0029] At block 520, the SMU changes the power allocated to the APU and the dGPU based on the changed workload characteristics and the platform power limit. The allocated power shifts from the APU to the dGPU in response to the workload shifting from core-intensive to graphics-intensive. The allocated power shifts from the dGPU to the APU in response to the workload shifting from graphics-intensive to core-intensive. In some embodiments, the change in power allocation is determined, at least in part, by thermal constraints such as a maximum surface temperature. For example, the surface temperature of the device is estimated based on measurements from temperature sensors and then compared to the maximum surface temperature. The power allocation is determined to maintain the surface temperature below the maximum surface temperature, for example, by increasing or decreasing the power allocation based on the comparison of the surface temperature and the maximum surface temperature.

[0030] In some embodiments, an apparatus is provided. The apparatus includes an integrated coprocessor that includes at least one central processing unit (CPU) core and at least one graphics processing unit (GPU) core. The integrated coprocessor is configured to generate commands for execution on a discrete coprocessor external to the integrated coprocessor. The apparatus also includes a power distribution circuit configured to selectively provide power to the integrated coprocessor and the discrete coprocessor based on the characteristics of workloads executed on the integrated coprocessor and the discrete coprocessor and based on a platform power limit shared by the integrated coprocessor and the discrete coprocessor.

[0031] In some embodiments, a method is provided. The method includes determining a first power provided to an integrated coprocessor that includes at least one central processing unit (CPU) core and at least one graphics processing unit (GPU) core. The integrated coprocessor is configured to generate commands for execution on a discrete coprocessor external to the integrated coprocessor. The method also includes determining a second power provided to the discrete coprocessor. The method further includes changing at least one of the first power and the second power based on characteristics of a workload executed on the integrated coprocessor and the discrete coprocessor, and based on a platform power limit shared by the integrated coprocessor and the discrete coprocessor.

[0032] In some embodiments, an apparatus is provided. The apparatus includes an integrated coprocessor that includes at least one central processing unit (CPU) core and at least one integrated graphics processing unit (iGPU) core. The CPU is configured to generate commands for execution on the iGPU and the discrete coprocessor. The apparatus also includes a power distribution circuit configured to dynamically shift power between the integrated coprocessor and the discrete coprocessor based on a platform power limit shared by the integrated coprocessor and the discrete coprocessor, and in response to changes in characteristics of a workload executed on the integrated coprocessor and the discrete coprocessor.

[0033] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that is accessible by a computer system during use to provide instructions and / or data to the computer system. Such storage media include, but are not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-ray (registered trademark) disc), magnetic media (e.g., floppy (registered trademark) disc, magnetic tape, magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS)-based storage media. A computer-readable storage medium (e.g., system RAM or ROM) may be built into a computing system, a computer-readable storage medium (e.g., magnetic hard drive) may be fixedly attached to a computing system, a computer-readable storage medium (e.g., optical disc or universal serial bus (USB)-based flash memory) may be removably attached to a computing system, or a computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to a computer system via a wired or wireless network.

[0034] In some embodiments, some aspects of the above technologies may be implemented by one or more processors of a processing system that executes software. The software is stored in a non-transitory computer-readable storage medium or includes one or more sets of executable instructions tangibly embodied on the non-transitory computer-readable storage medium. When the software is executed by one or more processors, it can include instructions and specific data that operate the one or more processors to execute one or more aspects of the above technologies. The non-transitory computer-readable storage medium can include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, cache, random access memory (RAM), or one or more other non-volatile memory devices, etc. The executable instructions stored in the non-transitory computer-readable storage medium can be in source code, assembly language code, object code, or other instruction formats interpretable or executable by one or more processors.

[0035] In addition to the above, it should be noted that not all activities or elements described in the general description are required, some activities or parts of a particular device may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Further, the order in which activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Therefore, the specification and drawings should be considered in an illustrative rather than a limiting sense, and all such modifications are intended to be included within the scope of the invention.

[0036] Advantages, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, advantages, advantages, solutions to problems, and features that may give rise to or manifest any advantage, advantage, or solution are not to be construed as important, essential, or indispensable features of any or all of the claims. Further, the disclosed invention can be modified and practiced in different but similar ways that will be apparent to those skilled in the art having the benefit of the teachings herein, so the specific embodiments described above are merely illustrative. There is no limitation with respect to the details of the construction or design shown herein other than as set forth in the appended claims. Thus, it is apparent that the specific embodiments described above may be changed or modified and that all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is as set forth in the appended claims.

Claims

1. An integrated coprocessor including a first integrated coprocessor core and a second integrated coprocessor core, the integrated coprocessor configured to generate commands for execution by a discrete coprocessor external to the integrated coprocessor. A power distribution circuit including one or more system management units, the power distribution circuit configured to selectively supply power to the integrated coprocessor and the discrete coprocessor based on characteristics of workloads executed by the integrated coprocessor and the discrete coprocessor and a reduced platform power limit that is lower than a platform power limit shared by the integrated coprocessor and the discrete coprocessor. Device.

2. The power distribution circuit is configured to: Determine a first power supplied to the integrated coprocessor and a second power supplied to the discrete coprocessor; Compare a sum of the first power and the second power with the platform power limit; And is configured to perform the above. The device of Claim 1.

3. The power distribution circuit is configured to increase the second power supplied to the discrete coprocessor in response to the sum being less than the platform power limit. The device of Claim 2.

4. Comprising at least one sensor configured to measure at least one temperature, The power distribution circuit is configured to increase the second power supplied to the discrete coprocessor by an amount determined based on a comparison of the at least one temperature and at least one thermal constraint. The device of Claim 3.

5. The power distribution circuit is configured to: Determine a surface temperature of the device based on the at least one temperature; Increase the second power supplied to the discrete coprocessor by an amount determined based on a comparison of the surface temperature and a maximum surface temperature determined by the at least one thermal constraint; And is configured to perform the above. The device of Claim 4.

6. The power distribution circuit is configured to decrease the second power supplied to the discrete coprocessor in response to the surface temperature exceeding the maximum surface temperature. The device of Claim 5.

7. The power distribution circuit is configured to change the power supplied to the integrated coprocessor and the discrete coprocessor in response to a change in the characteristics of the workload executed by at least one of the integrated coprocessor and the discrete coprocessor. The apparatus of claim 1.

8. The power distribution circuit is configured to shift power from the integrated coprocessor to the discrete coprocessor in response to the workload shifting from core-intensive to graphics-intensive. The apparatus of claim 7.

9. The power distribution circuit is configured to shift power from the discrete coprocessor to the integrated coprocessor in response to the workload shifting from graphics-intensive to core-intensive. The apparatus of claim 7.

10. A method executed by an apparatus including an integrated coprocessor, the method comprising: determining a first power supplied to an integrated coprocessor including a first integrated coprocessor core and a second integrated coprocessor core, the integrated coprocessor being configured to generate commands for execution by a discrete coprocessor external to the integrated coprocessor; determining a second power supplied to the discrete coprocessor; changing at least one of the first power and the second power based on characteristics of a workload executed by the integrated coprocessor and the discrete coprocessor and a reduced platform power limit that is lower than a platform power limit shared by the integrated coprocessor and the discrete coprocessor. Method.

11. including comparing a sum of the first power and the second power with the platform power limit. The method of claim 10.

12. including increasing the second power supplied to the discrete coprocessor in response to the sum being less than the platform power limit. The method of claim 11.

13. measuring at least one temperature associated with at least one of the integrated coprocessor and the discrete coprocessor. Increasing the second power supplied to the discrete coprocessor by an amount determined based on a comparison of the at least one temperature and at least one thermal constraint. The method of claim 12. **Claim 14** Determining a surface temperature of a device including the integrated coprocessor based on the at least one temperature. Comparing the surface temperature with a maximum surface temperature determined by the at least one thermal constraint. Increasing the second power supplied to the discrete coprocessor by an amount determined based on the comparison. The method of claim 13. **Claim 15** Including decreasing the second power supplied to the discrete coprocessor in response to the surface temperature exceeding the maximum surface temperature. The method of claim 14. **Claim 16** Including changing the power supplied to the integrated coprocessor and the discrete coprocessor in response to a change in characteristics of a workload executed by at least one of the integrated coprocessor and the discrete coprocessor. The method of claim 10. **Claim 17** Including shifting power from the integrated coprocessor to the discrete coprocessor in response to the workload shifting from a core-intensive type to a graphics-intensive type. The method of claim 16. **Claim 18** Including shifting power from the discrete coprocessor to the integrated coprocessor in response to the workload shifting from a graphics-intensive type to a core-intensive type. The method of claim 16. **Claim 19** An integrated coprocessor including a central processing unit (CPU) and an integrated graphics processing unit (iGPU), wherein the CPU is configured to generate commands for execution by the iGPU and a discrete coprocessor. A power distribution circuit including one or more system management units, configured to dynamically shift power between the integrated coprocessor and the discrete coprocessor in response to changes in the characteristics of the workloads executed by the integrated coprocessor and the discrete coprocessor, based on a reduced platform power limit that is lower than the platform power limit shared by the integrated coprocessor and the discrete coprocessor. Apparatus. Claim 20 Comprising at least one sensor configured to measure at least one temperature. The power distribution circuit is configured to change the power supplied to at least one of the integrated coprocessor and the discrete coprocessor in response to a change in the at least one temperature. The power distribution circuit is configured to exchange workload activity demand and power limit information with the discrete coprocessor. The apparatus of claim 19.

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