3D-NAND memory cell structure

Abstract

To provide a method for forming a 3D-NAND memory cell.SOLUTION: In a method of providing an unsubstituted metal gate (RMG) process in which the height of a metal stack 120 is reduced, and the oxidation of a metal layer 134 exposed to the surrounding oxygen is suppressed in a memory device 100, after an opening is formed, a nitriding process is performed to nitride the surface of the exposed metal layer inside the opening. A metal nitriding region 155 formed on the surface of the metal layer inside the opening functions as a barrier layer for oxygen diffusion. Further, the metal nitriding region functions as an electrode of a charge trap memory cell.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices, as well as methods and apparatuses for manufacturing electronic devices. More specifically, embodiments of the present disclosure provide a method for forming 3D-NAND memory cells.

Background Art

[0002]

[0002] Semiconductor technology has advanced rapidly, and the dimensions of devices have shrunk with the progress of technology, increasing the processing and storage per unit space. In NAND devices, the string current needs to be large enough to obtain a current sufficient to distinguish between on-cells and off-cells. The string current depends on the carrier mobility enhanced by increasing the grain size of the silicon channel.

[0003]

[0003] In existing 3D-NAND memory stacks with alternating layers of oxide and nitride, a replacement metal gate (RMG) process is required to fabricate the word line. As the stack height has become thicker, the etching / filling process of high aspect ratio (HAR) memory holes and stress control have become more difficult. The alternating layers of the stack of oxide and nitride films can be candidates for avoiding the replacement metal gate (RMG) step and reducing the stack height.

[0004]

[0004] In the case of a non-replacement metal gate (RMG) process, the cell components need to be protected from metal diffusion from the metal, and it is necessary to protect the metal from oxidation during the heating process in an oxygen environment.

[0005]

[0005] Therefore, there is a need in the art for 3D-NAND devices with a thinner stack height and protected cell components and metal layers. Furthermore, there is a need in the art for methods and apparatuses for forming 3D-NAND devices.

Summary of the Invention

[0006]

[0006] One or more embodiments of the present disclosure relate to a method of forming a memory device. In one embodiment, a method of forming an electronic device includes forming an opening through a metal stack including alternating layers of a first material layer and a metal layer, and selectively nitriding the metal layer through the opening to form a nitrided region.

[0007]

[0007] Additional embodiments of the present disclosure relate to a semiconductor memory device. In one embodiment, a semiconductor memory device includes a metal stack including alternating first material layers and metal layers in a first portion of the device, and a memory stack in a second portion of the device, the memory stack including alternating first material layers and word lines including a metal layer having a metal nitride region, a plurality of bit lines extending through the memory stack, and word line contacts extending from an upper surface of the word lines.

[0008]

[0008] Further embodiments of the present disclosure relate to a processing tool. In one embodiment, a processing tool includes a central transfer station including a robot configured to move a wafer, a plurality of process stations, each process station being connected to the central transfer station and providing a processing region separated from a processing region of an adjacent process station, the plurality of process stations including a nitridation chamber, and a controller connected to the central transfer station and the plurality of process stations, the controller being configured to operate the robot to move the wafer between the process stations and control processes occurring at each process station.

[0009]

[0009] To better understand the above features of the present disclosure, a more specific description of the present disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present disclosure and should not be considered as limiting its scope. The present disclosure can recognize other equally effective embodiments. The embodiments described herein are shown by way of illustration and not limitation in the figures of the accompanying drawings in which like reference numerals indicate like elements.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 6A

Figure 6B

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12A

Figure 12B

Figure 13

Figure 14

Figure 15

Figure 16

[0011]

[0032] Before describing some exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of the structures or process steps described in the following description. The present disclosure can have other embodiments and can be practiced or carried out in various ways.

[0012]

[0033] In an existing 3D-NAND memory stack in which layers of oxide and nitride are alternating, a replacement metal gate (RMG) process is required to fabricate word lines. As the stack height has been increasing, the etching / filling process of high aspect ratio (HAR) memory holes and stress control have become more difficult.

[0013]

[0034] One or more embodiments advantageously provide a replacement metal gate (RMG) process with a thinner stack height. In one or more embodiments, the memory cell components are protected from metal diffusion from the metal, and the metal is protected from oxidation during exposure to a thermal process in an oxidizing atmosphere. In particular, the memory cell components deposit from the sides of the memory hole etching when the metal stack is exposed to an oxidizing environment.

[0014]

[0035] To control the surface between the polysilicon and the metal, the deposition of the metal and other processes can be performed in an isolated environment (e.g., a cluster process tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules for implementing the method. FIG. 1 shows a process flow diagram of an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 can include any or all of the illustrated processes. Further, the order of the individual processes can be changed in part. Method 10 can start with any of the listed processes without departing from the disclosure. Referring to FIG. 1, in step 15, a memory stack is formed. In step 20, a word line staircase is formed in the memory stack. In step 25, an opening, e.g., a memory hole channel, is patterned in the word line staircase. In step 30, a metal layer is nitrided through the opening. In step 35, a transistor layer is deposited. In step 40, a bit line pad is formed. In step 45, an interlayer dielectric is deposited. In step 50, the memory staircase is slit patterned. In step 55, a sacrificial layer is removed. In step 60, a semiconductor material is deposited. In step 65, the slit is filled, and in step 70, a word line contact is formed.

[0015]

[0036] FIGS. 2-18 show a portion of a memory device 100 according to the process flow shown for method 10 of FIG. 1.

[0016]

[0037] Figure 2 shows an initial or starting metal stack of the electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 shown in FIG. 2 is formed in layers on a bare substrate 105 as shown. The electronic device of FIG. 2 is composed of a substrate 105, a semiconductor layer 110, a sacrificial layer 120, a metal stack 130, and an oxide layer 140.

[0017]

[0038] The substrate 105 can be any suitable material known to those skilled in the art. As used herein and in the appended claims, the term "substrate" refers to the surface or a portion of the surface on which the process acts. It will be understood by those skilled in the art that, unless the context clearly indicates otherwise, a reference to a substrate can refer to only a portion of the substrate. Further, a reference to depositing on a substrate can mean both a bare substrate and a substrate on which one or more films or features have been deposited or formed thereon.

[0018]

[0039] As used herein, "substrate" refers to any substrate on which film processing is performed during the manufacturing process, or the surface of a material formed on a substrate. For example, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials as required by the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be subjected to a pretreatment process for polishing, etching, reducing, oxidizing, hydroxylation, annealing, and / or baking the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on a lower layer formed on the substrate, as will be disclosed in more detail below, and the term "substrate surface" is intended to include the lower layer as indicated by the context. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0019]

[0040] The semiconductor layer 110 is on the substrate 105. In one or more embodiments, the semiconductor layer 110 may also be referred to as a common source line. The semiconductor layer 110 can be formed by any suitable technique known to those skilled in the art and can be made from any suitable material including, but not limited to, polysilicon (poly-Si). In some embodiments, the semiconductor layer 110 is a common source line made of a conductive or semiconductor material. In some embodiments, the source line contact can be formed by changing the layer under the stack of the first metal layer 132 and the second metal layer. Any change to the structure under the stack of the first and second layers is possible.

[0020]

[0041] The sacrificial layer 120 is formed on the semiconductor layer 110 and can be made of any suitable material. In some embodiments, the sacrificial layer 120 is removed and replaced in a later process. In some embodiments, the sacrificial layer 120 is not removed and remains within the memory device 100. In this case, the term "sacrificial" has an extended meaning to include a permanent layer and may be referred to as a conductive layer. In the illustrated embodiment, as further described below, the sacrificial layer 120 is removed in step 55. In one or more embodiments, the sacrificial layer 120 includes a material that can be selectively removed with respect to the adjacent semiconductor layer 110 and metal layer 134.

[0021]

[0042] The metal stack 130 is formed on the sacrificial layer 120. The metal stack 130 in the illustrated embodiment includes a plurality of alternating first material layers 132 and metal layers 134. In some embodiments, the metal stack 130 includes a non-replaced gate such as metal-to-metal, metal-to-metal nitride, or oxide-to-metal. The metal layer 134 includes a metal that is selective for nitridation with respect to the first material layer 132, such that the metal layer 134 can be nitrided without substantially affecting the first material layer 132. In one or more embodiments, the first material layer 132 is tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), zirconium nitride (ZrN), silicon oxide (SiO 2 ), ruthenium oxide (RuO x ), iridium oxide (IrO x ), tungsten oxide (WO x) includes one or more of silicon nitride (SiN), etc. In one or more embodiments, the metal layer 134 includes one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), etc. Thus, in one or more embodiments, the alternating layers of the first material layer 132 and the metal layer 134 are titanium nitride / tungsten (TiN / W), silicon oxide / tungsten (SiO 2 / W), tungsten / molybdenum (W / Mo), tungsten oxide / tungsten (WO x / W), and titanium nitride / molybdenum (TiN / Mo), etc. In one or more embodiments, the first material layer 132 and the metal layer 134 do not include the same material. In one or more specific embodiments, the first material layer 132 includes titanium nitride (TiN). In one or more specific embodiments, the metal layer 143 includes tungsten. In one or more embodiments, the first material layer 132 and the metal layer 134 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0022]

[0043] The individual alternating layers can be formed to any suitable thickness. In some embodiments, the thicknesses of each metal layer 134 are substantially equal. In one or more embodiments, each metal layer 134 has the thickness of the first metal layer. In some embodiments, the thicknesses of each first material layer 132 are substantially equal. As used in this context, substantially equal thicknesses are within + / - 5% of each other.

[0023]

[0044] Referring to FIG. 3, in one or more embodiments, in step 20 of method 10, a staircase structure 131 is generated. The staircase structure 131 exposes the upper surface 135 of the metal layer 134. As will be described below, the upper surface 135 can be used to provide space for forming word line contacts. A suitable filling material 137 can be deposited to occupy the space outside the staircase structure 131. As will be understood by those skilled in the art, the suitable filling material 137 can be any material that prevents electrical short circuits between adjacent word lines. The staircase structure 131 is such that each word line has a narrower width (shown from left to right in the figure) than the lower word line. The use of relative terms such as "upper" and "lower" should not be construed as limiting the scope of the disclosure to a physical orientation within a space.

[0024]

[0045] Referring to FIGS. 4A and 4B, in step 25, in one or more embodiments, an opening 150 is opened through the metal stack 130. In some embodiments, the opening 150 includes a memory hole channel. In some embodiments, opening the opening 150 includes etching through the oxide layer 140, the metal stack 130, the sacrificial layer 120, and into the semiconductor layer 110. Referring to FIG. 4B, which is an enlarged view of region 103, the opening 150 has sidewalls that extend through the metal stack 130 and expose the surface 138 of the first material layer 132 and the surface 139 of the metal layer 134.

[0025]

[0046] In one or more embodiments, the sacrificial layer 120 has a surface 122 that is exposed as a sidewall of the opening 150. The opening 150 extends into the semiconductor layer 110 such that the sidewall surface 112 and the bottom 114 of the opening 150 are formed within the semiconductor layer 110. The bottom 114 of the opening 150 can be formed at any point within the thickness range of the semiconductor layer 110. In some embodiments, the opening 150 extends into the semiconductor layer 110 in a range of about 10% to about 90% of the thickness of the semiconductor layer 110, or in a range of about 20% to about 80% of the thickness of the semiconductor layer 110, or in a range of about 30% to about 70% of the thickness of the semiconductor layer 110, or in a range of about 40% to about 60% of the thickness of the semiconductor layer 110. In some embodiments, the opening 150 extends into the semiconductor layer 110 by 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, or 80% or more of the thickness of the semiconductor layer 110.

[0026]

[0047] FIG. 5A shows step 30 in which the metal layer 134 is nitrided through the opening 150. FIG. 5B is an enlarged view of region 101 of FIG. 5A. In one or more embodiments, the metal layer 134 is nitrided by annealing in an atmosphere of ammonia (NH 3 ) at a temperature in the range of about 400°C to about 1000°C at ambient pressure. In one or more embodiments, the nitridation of the metal layer 134 forms a metal nitride region 155 having a thickness in the range of about 0.1 nm to about 10 nm that extends from the opening 150 to the metal layer 134.

[0027]

[0048] In one or more embodiments, the metal nitride region 155 includes one or more of tungsten nitride (WN), molybdenum nitride (MoN), tantalum nitride (TaN), ruthenium nitride (RuN), niobium nitride (NbN), osmium nitride (OsN), zirconium nitride (ZrN), iridium nitride (IrN), rhenium nitride (ReN), titanium nitride (TiN), etc. In one or more particular embodiments, the metal nitride region 155 includes tungsten nitride (WN).

[0028]

[0049] Referring to FIGS. 5C and 5D, one or more alternative embodiments are shown. As shown in FIG. 5C, in one or more embodiments, the metal nitride region 155 protrudes into the opening 150. In other embodiments, referring to FIG. 5D, the metal layer 134 is recessed through the opening 150. In some embodiments, the metal layer 134 is recessed through the opening 150 using hydrogen peroxide (H 2 O 2 ). The recessed metal layer 134 is then nitrided to form the recessed metal nitride region 155.

[0029]

[0050] Although not intended to be bound by theory, the 3D NAND structure of one or more embodiments and the method of nitriding the metal layer 134 of one or more embodiments are believed to suppress oxidation of the metal layer 134. The metal nitride region 155 formed on the surface of the metal layer 134 inside the opening 150 functions as a barrier layer for oxygen diffusion. Further, the metal nitride region 155 functions as an electrode of the charge trap memory cell.

[0030]

[0051] In one or more embodiments, the presence of the metal nitride region 155 can suppress oxidation of the metal stack 130, and as a result, avoid changes in the volume or interface characteristics between the high-k dielectric and the metal gate. In one or more embodiments, the metal nitride region 155 is a high work function metal nitride desired for a charge trap-based flash memory cell with low cost and reduced process steps. In one or more embodiments, diffusion of the metal from the metal layer 134 to the charge trap-based cell is avoided during the high temperature process.

[0031]

[0052] Figures 6A and 6B illustrate step 35, where transistor layer 165 is conformally deposited within opening 150 adjacent to metal layer 134 and metal nitride region 155. Transistor layer 165 can be formed by any suitable technique known to those skilled in the art. In some embodiments, transistor layer 165 is formed by a conformal deposition process. In some embodiments, transistor layer 165 is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0032]

[0053] In one or more embodiments, the deposition of transistor layer 165 is substantially conformal. As used herein, a layer that is "substantially conformal" refers to a layer that has approximately the same thickness throughout (e.g., at the top, middle, and bottom of the sidewalls, as well as at the bottom of opening 150). A substantially conformal layer has a thickness variation of about 5% or less, about 2% or less, about 1% or less, or about 0.5% or less.

[0033]

[0054] Referring to FIG. 6B, which is an enlarged view of region 101, in one or more embodiments, transistor layer 165 includes a blocking oxide layer 176 (or first oxide layer 176), a nitride trap layer 174 over the first oxide layer 176, a second oxide layer 172 (or tunnel oxide layer 172) over the nitride trap layer 174, and a polysilicon layer 170 within opening 150 over the second oxide layer 172. In one or more embodiments, blocking oxide layer 176, charge trap nitride (SiN) layer 174, and tunnel oxide layer 172 are deposited within opening 150 on the sidewalls of opening 150 or over semiconductor layer 110. In one or more embodiments, a high-k dielectric material such as aluminum oxide or hafnium oxide can be deposited prior to forming the blocking oxide (i.e., the blocking layer is composed of a high-k dielectric and silicon oxide).

[0034]

[0055] In one or more embodiments, a polysilicon (poly-Si) layer 170 is formed in the opening 150 adjacent to the transistor layer 165. The poly-Si layer 170 can be formed directly on the transistor layer 165. The poly-Si layer 170 can be deposited by any suitable technique known to those skilled in the art, including but not limited to atomic layer deposition and chemical vapor deposition. In some embodiments, the polysilicon layer 170 is deposited as a conformal layer so as to be formed on the sidewalls and exposed surfaces 138, 139, 122, 112 and bottom 114 (see FIG. 4B) of the opening 150.

[0035]

[0056] The polysilicon layer 170 can have any suitable thickness, for example, depending on the dimensions of the opening 150. In some embodiments, the polysilicon layer 170 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm. In some embodiments, the polysilicon layer 170 is a continuous film. In one or more embodiments, the polysilicon layer 170 is formed in a macaroni type conformally deposited on the tunnel oxide layer 172, and the polysilicon layer 170 has a thickness in the range of about 1 nm to about 20 nm. Next, the opening 150 is filled with a dielectric material 160.

[0036]

[0057] FIG. 7 shows step 40 of method 10, in which a bit line pad 180 is formed in the polysilicon (poly-Si) layer 160. The bit line pad 180 can be any suitable material known to those skilled in the art, including but not limited to polysilicon.

[0037]

[0058] FIG. 8 shows step 45 of method 10, where an interlayer dielectric 185 is deposited on top of the oxide layer 140 and the bit line pad 180. The interlayer dielectric (ILD) 185 can be deposited by any suitable technique known to those skilled in the art. The interlayer dielectric 185 can include any suitable material known to those skilled in the art. In one or more embodiments, the interlayer dielectric 185 is a low-k dielectric including, but not limited to, materials such as silicon dioxide, silicon oxide, carbon-doped oxide (“CDO”), e.g., carbon-doped silicon dioxide, porous silicon dioxide (SiO 2 ), silicon nitride (SiN), or any combination thereof. The term “silicon oxide” may be used to describe the interlayer dielectric 185, but those skilled in the art will recognize that the present disclosure is not limited to a specific stoichiometry. For example, both the terms “silicon oxide” and “silicon dioxide” can be used to describe a material having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same applies to other materials described in the present disclosure (e.g., silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, etc.).

[0038]

[0059] FIG. 9 shows step 50 of method 10, where the metal stack 130 is slit-patterned to form slit pattern openings 190 extending from the top surface of the interlayer dielectric 185 to the substrate 105.

[0039]

[0060] FIG. 10 shows step 55 of method 10, where the sacrificial layer 120 and transistor dielectrics (e.g., blocking layer, trap layer, and tunnel layer) adjacent to the sacrificial layer 120 are removed to expose the poly-Si channel layer. The sacrificial layer 120 and the transistor dielectrics can be removed by any suitable technique known to those skilled in the art, including but not limited to selective etching.

[0040]

[0061] FIG. 11 shows step 60 of method 10, where semiconductor material (e.g., polysilicon fill) 195 is deposited into slit pattern opening 190. The semiconductor material can be any suitable material known to those skilled in the art.

[0041]

[0062] FIG. 12A shows the removal of semiconductor material 195 from the sidewalls of slit pattern opening 190. Without intending to be bound by theory, slit pattern opening 190 must be larger than the height of common source line 110 (semiconductor layer 110) such that an opening for removing semiconductor material 195 from the sidewalls is in slit pattern opening 190. In one or more embodiments, semiconductor material 195 is removed from the sidewalls of slit pattern opening 190 by an isotropic etching process (e.g., wet etching using TMAH, etc.). FIG. 12B shows an enlarged view of region 101 of FIG. 12A.

[0042]

[0063] FIG. 13 shows step 80 of method 10, where slit pattern opening 190 is filled with fill material 230. The fill material 230 can be any suitable material known to those skilled in the art. In one or more embodiments, fill material 230 includes one or more of a dielectric material or a conductor material. As used herein, the term "dielectric material" refers to a layer of material that is an electrical insulator capable of polarizing in an electric field. In one or more embodiments, the dielectric material includes one or more of an oxide, carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO 2 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH).

[0043]

[0064] Figure 14 shows step 85 of method 10, in which word line contact 235 is formed. The word line contact 235 extends through the metal stack 130 by a distance sufficient to terminate at one of the word lines 225. In one or more embodiments, the word line contact 235 can include any suitable material known to those skilled in the art. In one or more embodiments, the word line contact 235 includes one or more of metal, metal silicide, polysilicon, amorphous silicon, or epitaxial silicon. In one or more embodiments, the word line contact is doped with either an N-type dopant or a P-type dopant to reduce contact resistance. In one or more embodiments, the metal of the word line contact 235 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), and platinum (Pt).

[0044]

[0065] Figure 15 shows a semiconductor memory device according to one or more embodiments. The memory device 100 includes a metal stack 120 including alternating first material layers 132 and metal layers 134 in a first portion 300 of the device 100, and a metal stack 130 including alternating word lines 225 and metal layers 134 in a second portion 400 of the device 100.

[0045]

[0066] In one or more embodiments, the metal stack 120 has a height in the range of about 10 nm to about 500 nm, including from about 12 nm to about 450 nm, and from about 15 nm to about 400 nm.

[0046]

[0067] In one or more embodiments, the first material layer 132 of the metal stack 120 has a thickness in the range of from about 0.5 nm to about 40 nm, including from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, about 30 nm, about 35 nm, and about 40 nm. In one or more embodiments, the metal layer 134 of the metal stack 130 has an average thickness in the range of from about 10 nm to about 20 nm.

[0047]

[0068] The memory device 100 includes a memory stack 133 including alternating first material layers 132 and word line layers in a second portion 400 of the device 100, and the alternating word line layers include metal layers 134 having metal nitride regions 155.

[0048]

[0069] Additional embodiments of the present disclosure are directed to a processing tool 900 for the formation and method of the memory device described, as shown in FIG. 16.

[0049]

[0070] The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are disposed within the central transfer stations 921, 931 and are configured to move robot blades and wafers to each of the plurality of sides.

[0050]

[0071] The cluster tool 900 includes a plurality of process chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also called process stations, connected to a central transfer station. The various process chambers provide separate processing areas that are isolated from adjacent process stations. The process chambers can be any suitable chambers including, but not limited to, a pre-cleaning chamber, a buffer chamber, a transfer space, a wafer orienter / de-gas chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective oxidation chamber, an oxide layer thinning chamber, or a word line deposition chamber. The specific arrangement of the process chambers and components can vary depending on the cluster tool and should not be considered as limiting the scope of the present disclosure.

[0051]

[0072] In some embodiments, the cluster tool 900 includes a nitridation chamber. In some embodiments, the cluster tool 900 includes a pre-cleaning chamber connected to the central transfer station.

[0052]

[0073] In the embodiment shown in FIG. 16, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front face 951 of the factory interface 950. The loading chamber 954 is shown on the left side and the unloading chamber 956 is shown on the right side, but those skilled in the art will understand that this represents only one possible configuration.

[0053]

[0074] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary, for example, according to the substrate being processed in the cluster tool 900. In the embodiment shown, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with a plurality of wafers disposed therein.

[0054]

[0075] Robot 952 is within factory interface 950 and can move between loading chamber 954 and unloading chamber 956. Robot 952 can transfer wafers from a cassette in loading chamber 954 through factory interface 950 to load lock chamber 960. Robot 952 can also transfer wafers from load lock chamber 962 through factory interface 950 to a cassette in unloading chamber 956. As will be understood by those skilled in the art, factory interface 950 can have more than one robot 952. For example, factory interface 950 can have a first robot that transfers wafers between loading chamber 954 and load lock chamber 960 and a second robot that transfers wafers between load lock 962 and unloading chamber 956.

[0055]

[0076] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to factory interface 950 via load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 disposed therein. Robot 925 is also referred to as a robot wafer transfer mechanism. The first transfer chamber 921 is centrally located with respect to load lock chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, robot 925 is a multi-arm robot that can independently move more than one wafer at a time. In some embodiments, the first transfer chamber 921 includes more than one robot wafer transfer mechanism. The robot 925 within the first transfer chamber 921 is configured to move wafers between the chambers around the first transfer chamber 921. Individual wafers are carried on wafer transport blades disposed at the distal ends of the first robotic mechanism.

[0056]

[0077] After processing the wafer in the first section 920, the wafer can be passed through the pass-through chamber to the second section 930. For example, chambers 922, 924 can be one-way or two-way pass-through chambers. Pass-through chambers 922, 924 can be used, for example, to cryogenically cool the wafer before processing in the second section 930 or to enable wafer cooling or post-processing before returning to the first section 920.

[0057]

[0078] System controller 990 is in communication with a first robot 925, a second robot 935, a first plurality of process chambers 902, 904, 916, 918, and a second plurality of process chambers 906, 908, 910, 912, 914. System controller 990 can be any suitable component capable of controlling the process chambers and robots. For example, system controller 990 can be a computer including a central processing unit (CPU) 992, a memory 994, an input / output (I / O) 996, and support circuitry 998. Controller 990 can control the processing tool 900 directly or via a computer (or controller) associated with a particular process chamber and / or support system component.

[0058]

[0079] In one or more embodiments, the controller 990 can be one of any form of general-purpose computer processor that can be used in an industrial environment to control various chambers and sub-processors. The memory 994 of the controller 990 or the computer-readable medium can be one or more of readily available memories such as non-transitory memory (e.g., random access memory (RAM)), read-only memory (ROM), floppy disks, hard disks, optical storage media (such as compact disks and digital video disks), flash drives, or any other form of digital storage, local or remote. The memory 994 can hold an instruction set operable by a processor (CPU 992) to control the parameters and components of the processing tool 900.

[0059]

[0080] The support circuit 998 is coupled to the CPU 992 to support the processor as is conventional. These circuits include caches, power supplies, clock circuits, input / output circuits, and subsystems. When one or more processes are executed or invoked by the processor, they can be stored in the memory 994 as software routines that cause the processor to control the operation of the processing tool 900 or individual processing units in the manner described herein. The software routines can also be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU 992.

[0060]

[0081] Some or all of the processes and methods of the present disclosure may be executed in hardware. Thus, the process may be implemented in software and executed using a computer system, or may be implemented in hardware as, for example, an application specific integrated circuit or other type of hardware implementation, or may be implemented as a combination of software and hardware. When executed by a processor, the software routine converts a general-purpose computer into a dedicated computer (controller) that controls the operation of the chamber so that the process is executed.

[0061]

[0082] In some embodiments, the controller 990 has one or more configurations for executing individual processes or subprocesses to execute the method. The controller 990 can be connected to the intermediate component and configured to operate the intermediate component to execute the functions of the method. For example, the controller 990 can be connected to a nitriding chamber and configured to control the nitriding chamber.

[0062]

[0083] Generally, when executed by a processor, the process can be stored in the memory 994 of the system controller 990 as a software routine that causes the process chamber to execute the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may be executed in hardware. Thus, the process may be implemented in software and executed using a computer system, or may be implemented in hardware as, for example, an application specific integrated circuit or other type of hardware implementation, or may be implemented as a combination of software and hardware. When executed by a processor, the software routine converts a general-purpose computer into a dedicated computer (controller) that controls the operation of the chamber so that the process is executed.

[0063]

[0084] In some embodiments, the system controller 990 controls the nitridation chamber to nitride the metal M layer on the wafer at a temperature in the range of about 400° C. to about 1000° C. in an atmosphere of ambient pressure ammonia (NH 3 ) gas.

[0064]

[0085] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers, a plurality of process stations, each process station being connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including a nitridation chamber and a word line deposition chamber, and a controller connected to the central transfer station and the plurality of process stations, the controller being configured to operate the robot to move wafers between process stations and to control the processes occurring at each process station.

[0065]

[0086] As used in the context of describing the materials and methods discussed in this specification (particularly in the context of the following claims), the terms "a", "an", and "the" and similar designators are to be construed to cover both the singular and the plural forms unless otherwise indicated herein or clearly contradicted by the context. The recitation of a range of values herein is merely intended to serve as a shorthand way of referring individually to each separate value within the range, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by the context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better clarify the materials and methods and does not impose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0066]

[0087] References throughout this specification to "one embodiment", "a particular embodiment", "one or more embodiments" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases "in one or more embodiments", "in a particular embodiment", "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0067]

[0088] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

**Claim 1** A method of forming a memory device, comprising: forming an opening through a metal stack including alternating layers of a first material layer and a metal layer; annealing the metal stack in an atmosphere of ammonia (NH₃) at a temperature in the range of 400°C to 1000°C, and selectively nitriding a part of the metal layer through the opening to form a nitrided region adjacent to the metal layer; comprising: the method, wherein the nitrided region has a thickness in the range of 0.1 nm to 10 nm. **Claim 2** The method according to claim 1, wherein the metal stack is formed on one or more of a substrate, a semiconductor layer, and a sacrificial layer. **Claim 3** The method according to claim 1, further comprising forming a bit line in the opening, wherein forming the bit line comprises: depositing a first oxide channel layer in the opening; depositing a nitride channel layer on the first oxide channel layer; depositing a second oxide channel layer on the nitride channel layer; forming a polysilicon layer on the second oxide channel layer in the opening; forming a bit line pad in the polysilicon layer. comprising: **Claim 4** The method according to claim 3, further comprising depositing an oxide layer on the upper surface of the metal stack before forming the opening. **Claim 5** The method according to claim 4, further comprising depositing an interlayer dielectric on the upper surfaces of the oxide layer and the bit line pad. **Claim 6** The method according to claim 1, wherein the nitrided region protrudes into the opening. **Claim 7** The method according to claim 1, wherein the nitrided region is recessed from the opening. **Claim 8** The method according to claim 1, wherein the metal layer comprises one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), etc. **Claim 9** The first material layer includes one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), zirconium nitride (ZrN), silicon oxide (SiO ２ ), ruthenium oxide (RuO ｘ ), iridium oxide (IrO ｘ ), tungsten oxide (WO ｘ ), silicon nitride (SiN), etc., and the method according to claim 1. **Claim 10** The method according to claim 1, wherein the nitrided region comprises one or more of tungsten nitride (WN), molybdenum nitride (MoN), tantalum nitride (TaN), ruthenium nitride (RuN), niobium nitride (NbN), osmium nitride (OsN), zirconium nitride (ZrN), iridium nitride (IrN), rhenium nitride (ReN), titanium nitride (TiN), etc.

11. The method according to claim 1, further comprising a word line contact comprising one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), and platinum (Pt).

Images