Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device in which a connection portion of a bonding wire is hardly peeled off, and a manufacturing method thereof.SOLUTION: A first conductive layer CL1 is connected to an impurity region that is to be a source region SR or an emitter region ER. The first conductive layer CL1 having an emitter pad EP is separated from a second conductive layer CL2 having a Kelvin emitter pad KP and a relay pad RP. A plane occupation area of the Kelvin emitter pad KP is smaller than a plane occupation area of the emitter pad EP.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device having an electrode pad for detecting the potential of a source or an emitter and a method for manufacturing the same.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2021-111641 (Patent Document 1) discloses an IGBT (Insulated Gate Bipolar Transistor) having a large-area emitter electrode and an electrode pad for a small-area Kelvin emitter. The electrode pad for the Kelvin emitter is used to detect the potential of the emitter electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an electrode pad for a small-area Kelvin emitter electrically connected to a large-area emitter electrode, there is a risk that the connection portion of a bonding wire or a clip conductor may peel off.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to the semiconductor device according to one embodiment, the first conductive layer is connected to an impurity region that becomes a source region or an emitter region. The first conductive layer having the first electrode pad and the second conductive layer having the second electrode pad and the third electrode pad are separated from each other. The first electrode pad and the third electrode pad are electrically connected. The planar occupation area of the second electrode pad is smaller than the planar occupation area of the first electrode pad.

[0007] According to the method of manufacturing a semiconductor device according to one embodiment, it has the following steps. A first conductive layer connected to an impurity region that becomes a source region or an emitter region disposed on a semiconductor substrate and a second conductive layer separated from the first conductive layer are formed on the main surface of the semiconductor substrate. The first electrode pad of the first conductive layer and the third electrode pad of the second conductive layer are electrically connected. The planar occupation area of the second electrode pad is smaller than the planar occupation area of the first electrode pad.

Effect of the Invention

[0008] According to the above embodiment, it is possible to realize a semiconductor device in which the connection portion of the bonding wire or the clip conductor is difficult to peel off and a method of manufacturing the same.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and the drawings, the same reference numerals are given to the same components or corresponding components, and duplicate explanations will not be repeated. In the drawings, for convenience of explanation, the configuration or manufacturing method may be omitted or simplified. Also, at least a part of each embodiment may be arbitrarily combined with each other.

[0011] Note that the plan view in this specification means a viewpoint seen from a direction orthogonal to the first surface FS of the semiconductor substrate. Also, the planar shape means the shape in the plan view.

[0012] (Embodiment 1) <Configuration of the Semiconductor Device> First, the configuration of the semiconductor device according to Embodiment 1 will be described with reference to FIGS. 1 to 3.

[0013] As shown in FIG. 1, the semiconductor device SD in this embodiment has an emitter pad EP (first electrode pad), a Kelvin emitter pad KP (second electrode pad), a relay pad RP (third electrode pad), and a gate pad GP. The planar occupation area of the emitter pad EP is larger than the planar occupation area of each of the Kelvin emitter pad KP, the relay pad RP, and the gate pad GP.

[0014] The emitter pad EP has a planar shape in which one corner of a rectangle is cut out and has a substantially L-shaped planar shape. Each of the Kelvin emitter pad KP, the relay pad RP, and the gate pad GP has a rectangular planar shape. The relay pad RP is disposed in the cut-out region of the rectangle in the planar shape of the emitter pad EP.

[0015] The emitter pad EP and the relay pad RP are electrically connected to each other. Each of the emitter pad EP and the relay pad RP is electrically connected to, for example, a common clip conductor CC. The clip conductor CC is a plate-shaped conductor. The clip conductor CC is made of a metal having a low electrical resistivity such as copper (Cu) or silver (Ag).

[0016] By using the clip conductor CC, it becomes possible to flow a larger current than when a bonding wire is connected to the emitter pad EP. On the other hand, a bonding wire BW is individually connected to each of the Kelvin emitter pad KP and the gate pad GP. Here, the case where the bonding wire BW is connected to each of the Kelvin emitter pad KP and the gate pad GP will be described, but the clip conductor may be connected to each of the Kelvin emitter pad KP and the gate pad GP.

[0017] As shown in FIG. 2, the semiconductor device SD has a semiconductor substrate SB. The semiconductor substrate SB has a first surface FS (main surface) and a second surface SS facing each other. An electrical element having a vertical insulated-gate field-effect transistor portion is formed on the semiconductor substrate SB. This electrical element is, for example, an IGBT. Also, a vertical electrical element means an electrical element through which current flows between the first surface FS and the second surface SS of the semiconductor substrate SB.

[0018] An interlayer insulating layer IL is disposed on the first surface FS of the semiconductor substrate SB. A contact hole CH is provided in the interlayer insulating layer IL. The contact hole CH reaches the first surface FS of the semiconductor substrate SB from the upper surface of the interlayer insulating layer IL.

[0019] The semiconductor device SD further has a first conductive layer CL1, a second conductive layer CL2, and a third conductive layer CL3 (FIG. 1). Each of the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 is on the first surface FS of the semiconductor substrate SB and is disposed on the interlayer insulating layer IL.

[0020] The first conductive layer CL1 is directly connected to the emitter region (impurity region) of the IGBT through the contact hole CH of the interlayer insulating layer IL. The first conductive layer CL1 has an emitter pad EP. A gate electrode GE of the IGBT is disposed in the region directly below the first conductive layer CL1.

[0021] The second conductive layer CL2 is disposed separately from the first conductive layer CL1. The second conductive layer CL2 is not directly connected to the emitter region (impurity region) of the IGBT. The second conductive layer CL2 has a Kelvin emitter pad KP and a relay pad RP. A gate electrode GE of the IGBT is not disposed in the region directly below the first conductive layer CL1.

[0022] The third conductive layer CL3 is disposed separately from each of the first conductive layer CL1 and the second conductive layer CL2. The third conductive layer CL3 is electrically connected to the gate electrode GE of the IGBT through a contact hole (not shown) in the interlayer insulating layer IL. The third conductive layer CL3 has a gate pad GP.

[0023] The first conductive layer CL1 has a barrier metal layer BM1, a first layer FL1, a second layer SL1, and a third layer TL1. The barrier metal layer BM1 is disposed in contact with the upper surface of the interlayer insulating layer IL and the wall surface of the contact hole CH. The barrier metal layer BM1 is made of, for example, titanium-tungsten (TiW). The barrier metal layer BM1 may be a single layer of titanium (Ti) or titanium nitride (TiN), or may be a laminated film of titanium and titanium nitride.

[0024] The first layer FL1 is disposed in contact with the upper surface of the barrier metal layer BM1 and fills the contact hole CH. The first layer FL1 is made of a material containing, for example, aluminum (Al), and is made of, for example, an alloy of aluminum and silicon (Si), an alloy of aluminum and copper, an alloy of aluminum, silicon, and copper, or pure aluminum.

[0025] The second layer SL1 is disposed on the first layer FL1. The second layer SL1 is made of a material containing a first metal. The first metal is a metal different from aluminum and is, for example, nickel (Ni). The first metal may contain a small amount of phosphorus (P) in nickel (Ni).

[0026] Zinc (Zn) may be present between the first layer FL1 and the second layer SL1. Zinc is the remainder of a zinc layer formed when the first layer FL1 is subjected to a zincate treatment.

[0027] The third layer TL1 is disposed in contact with the upper surface of the second layer SL1. The third layer TL1 is made of a material containing a second metal. The second metal is a metal different from the first metal, for example, gold (Au). The second metal may have a two-layer structure in which gold is formed on palladium (Pd). The upper surface of the third layer TL1 is exposed from the insulating layer OI to constitute the emitter pad EP.

[0028] The second conductive layer CL2 has a barrier metal layer BM2, a first layer FL2, second layers SL2k and SL2r, and third layers TL2k and TL2r. The barrier metal layer BM2 is disposed in contact with the upper surface of the interlayer insulating layer IL. The barrier metal layer BM2 is made of, for example, titanium-tungsten.

[0029] The first layer FL2 is disposed in contact with the upper surface of the barrier metal layer BM2. The first layer FL2 is made of a material containing, for example, aluminum, and is made of, for example, pure aluminum.

[0030] Each of the second layers SL2k and SL2r is disposed on the first layer FL2. The second layer SL2k and the second layer SL2r are separated from each other but are electrically connected to each other via the first layer FL2. Each of the second layers SL2k and SL2r is made of a material containing a first metal. The first metal is a metal different from aluminum, for example, nickel.

[0031] Zinc may be present between each of the second layers SL2k and SL2r and the first layer FL2. Zinc is the remainder of a zinc layer formed when the first layer FL2 is subjected to a chelate treatment.

[0032] The third layer TL2k is disposed in contact with the upper surface of the second layer SL2k. The third layer TL2r is disposed in contact with the upper surface of the second layer SL2r. Each of the third layers TL2k and TL2r is made of a material containing a second metal. The second metal is a metal different from the first metal, for example, gold.

[0033] The upper surface of the third layer TL2k is exposed from the insulating layer OI, thereby forming the Kelvin emitter pad KP. The upper surface of the third layer TL2r is exposed from the insulating layer OI, thereby forming the relay pad RP. The Kelvin emitter pad KP and the relay pad RP are electrically connected to each other with the first layer FL2 interposed therebetween.

[0034] The third conductive layer CL3 (FIG. 1) has a barrier metal layer BM3, a first layer FL3, a second layer SL3, and a third layer TL3. The barrier metal layer BM3 is disposed in contact with the upper surface of the interlayer insulating layer IL and the inner wall surface of the contact hole. Thereby, the barrier metal layer BM3 is directly connected to the gate electrode GE.

[0035] The first layer FL3 is disposed in contact with the upper surface of the barrier metal layer BM3. The second layer SL3 is disposed on the first layer FL3. The third layer TL3 is disposed in contact with the upper surface of the second layer SL3. The upper surface of the third layer TL3 is exposed from the insulating layer OI, thereby forming the gate pad GP.

[0036] Since the configuration of the third conductive layer CL3 other than the above is substantially the same as the configuration of the first conductive layer CL1, the description thereof will not be repeated.

[0037] A clip conductor CC is disposed on the emitter pad EP and the relay pad RP. The clip conductor CC is electrically connected to each of the emitter pad EP and the relay pad RP with the solder SOL interposed therebetween. That is, the clip conductor CC is connected to each of the upper surface of the third layer TL1 and the upper surface of the third layer TL2r with the solder SOL interposed therebetween. Thereby, the first conductive layer CL1 and the second conductive layer CL2 are electrically connected to each other. For the connection between the clip conductor CC and each of the emitter pad EP and the relay pad RP, a bonding method of Ag sintering (Ag sinter) or Ag paste may be used in addition to the solder.

[0038] A bonding wire BW is electrically connected to the Kelvin emitter pad KP. That is, the bonding wire BW is connected to the upper surface of the third layer TL2k.

[0039] A bonding wire BW is electrically connected to the gate pad GP (Fig. 1). That is, the bonding wire BW is connected to the upper surface of the third layer TL3.

[0040] The above-mentioned insulating layer OI is made of a material containing an organic insulator. The organic insulator contained in the insulating layer OI is, for example, polyimide. The insulating layer OI is located between the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3, respectively, to separate the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 from each other.

[0041] A collector electrode CE is arranged on the second surface SS of the semiconductor substrate SB. The collector electrode CE is electrically connected to the collector region of the IGBT.

[0042] As shown in Fig. 3, the electrical element formed on the semiconductor substrate SB is, for example, an IGBT. The IGBT mainly has a p + collector region CR, an n + region HR, an n - drift region DRI, a p-type base region BR, a p + contact region CON, an n + emitter region ER, and a gate electrode GE.

[0043] p + The collector region CR is arranged on the second surface SS of the semiconductor substrate SB. The p + On the collector region CR (on the p + collector region CR, on the first surface FS side), an n + region HR is arranged. The n + region HR forms a pn junction with the p + collector region CR.

[0044] n +Above the HR region (n + On the first surface FS side with respect to the HR region) n - The drift region DRI is disposed. n - The drift region DRI is, n + In contact with the HR region. n - The drift region DRI is, n + It has an n-type impurity concentration lower than the n-type impurity concentration of the HR region.

[0045] n - On the drift region DRI (n - On the first surface FS side with respect to the drift region DRI) a p-type base region BR is disposed. The p-type base region BR is, n - Forming a pn junction with the drift region DRI.

[0046] On the p-type base region BR (on the first surface FS side with respect to the p-type base region BR) p + The contact region CON and n + The emitter region ER are disposed. p + The contact region CON is in contact with the p-type base region BR. p + The contact region CON has a p-type impurity concentration higher than the p-type impurity concentration of the p-type base region BR. n + The emitter region ER is, p + Forming a pn junction with each of the contact region CON and the p-type base region BR.

[0047] A trench TR is provided in the semiconductor substrate SB. The trench TR extends from the first surface FS to n + Penetrating each of the emitter region ER and the p-type base region BR to n - Reaching the drift region DRI. A gate insulating layer GI is disposed along the inner wall of the trench TR. The inside of the trench TR is filled with a gate electrode GE. The gate electrode GE faces the p-type base region BR with the gate insulating layer GI interposed therebetween. Thus, the IGBT has an insulated gate field effect transistor portion.

[0048] The first conductive layer CL1 forms an emitter electrode by contacting the emitter region ER through the contact hole CH in the interlayer insulating layer IL. Also, the first conductive layer CL1 contacts the p-contact region CON through the contact hole CH1. + The collector electrode CE is disposed on the second surface SS of the semiconductor substrate SB. The collector electrode CE is electrically connected to the p-collector region CR by contacting the p-collector region CR. +

[0049] The collector electrode CE is disposed on the second surface SS of the semiconductor substrate SB. The collector electrode CE is electrically connected to the p-collector region CR by contacting the p-collector region CR. + +

[0050] <Method of manufacturing a semiconductor device> Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 4 to 6.

[0051] As shown in FIG. 4, first, a semiconductor substrate SB is prepared, and an electrical element (not shown) having a gate electrode GE such as an IGBT is formed on the semiconductor substrate SB. An interlayer insulating layer IL made of, for example, a silicon oxide film is formed so as to cover the first surface FS of the semiconductor substrate SB. In the interlayer insulating layer IL, contact holes CH reaching the emitter region ER and the p-contact region CON are formed by photolithography and etching techniques. + +

[0052] On the interlayer insulating layer IL, a barrier metal layer made of, for example, titanium-tungsten and a first layer made of, for example, an alloy of aluminum and silicon are sequentially laminated and formed. The barrier metal layer is formed so as to directly contact each of the emitter region ER and the p-contact region CON through the contact hole CH. + +

[0053] The barrier metal layer and the first layer are patterned by a photolithography technique and an etching technique. As a result, the barrier metal layer is separated into barrier metal layers BM1, BM2, and BM3. Also, the first layer is separated into first layers FL1, FL2, and FL3. Further, a stacked structure of the barrier metal layer BM1 and the first layer FL1, a stacked structure of the barrier metal layer BM2 and the first layer FL2, and a stacked structure of the barrier metal layer BM3 and the first layer FL3 are formed.

[0054] Thereafter, an organic insulating layer OI is applied to the entire first surface FS of the semiconductor substrate SB. The organic insulating layer OI is, for example, an organic photosensitive film and is a polyimide. The organic insulating layer OI is patterned by a photolithography technique (exposure and development) to become an insulating layer OI having a predetermined pattern shape. As shown in FIG. 1, the insulating layer OI is patterned so as to expose portions that will become the respective electrode pads EP, KP, RP, and GP from the insulating layer OI. In particular, in order to separate between the electrode pads KP and RP, the insulating layer OI has a portion located on the first layer FL2.

[0055] As shown in FIGS. 5 and 6, nickel and gold are formed on the first layers FL1, FL2, and FL3 using an electroless plating method. Through a degreasing treatment, the surfaces of the first layers FL1, FL2, and FL3 are cleaned. Through an etching treatment, the surface oxide layer is removed, and then, after performing an acid wash, a first zincate treatment is executed. Next, through the acid wash, zinc (Zn) formed by the first zincate treatment is removed. Next, as shown in FIG. 5, a second zincate treatment is executed on the first layers FL1, FL2, and FL3. In the zincate treatment, a zincate solution is brought into contact with the surface, and a zinc coating is formed on the surface by a substitution reaction between aluminum and zinc. The zincate treatment is performed to facilitate plating on the aluminum surface. Electroless plating such as nickel plating and gold plating is executed on the first layers FL1, FL2, and FL3 on which the zinc coating ZN is formed. Between each treatment, a pure water washing treatment is performed.

[0056] As shown in FIG. 6, a second layer SL1 made of nickel and a third layer TL1 made of gold are formed on the first layer FL1 by the nickel plating and the gold plating. Thus, the upper surface of the third layer TL1 constitutes the emitter pad EP.

[0057] Also, a second layer SL2k, SL2r made of nickel and a third layer TL2k, TL2r made of gold are formed on the first layer FL2. The laminated structure of the second layer SL2k and the third layer TL2k is formed separately from the laminated structure of the second layer SL2k and the third layer TL2k. Thus, the upper surface of the third layer TL2k constitutes the Kelvin emitter pad KP. Also, the upper surface of the third layer TL2r constitutes the relay pad RP.

[0058] Although not shown, a second layer SL3 made of nickel and a third layer TL3 made of gold are formed on the first layer FL3. Thus, the upper surface of the third layer TL3 constitutes the gate pad GP.

[0059] Note that almost no zinc film ZN remains on the surfaces of the first layers FL1, FL2, and FL3 by nickel plating. However, a small amount of zinc may remain on the surfaces of the first layers FL1, FL2, and FL3.

[0060] As shown in FIG. 2, after the second surface SS of the semiconductor substrate SB is polished to a predetermined thickness, a collector electrode CE is formed on the second surface SS. On the collector electrode CE, an alloy of aluminum (Al) and silicon (Si), titanium (Ti), nickel (Ni), and gold are formed from the semiconductor substrate SB side. Thereafter, the semiconductor wafer is diced into a plurality of semiconductor chips. In the state of the semiconductor chip, the clip conductor CC is connected to the emitter pad EP and the relay pad RP by solder SOL. Also, the bonding wire BW is connected to each of the emitter pad EP and the gate pad GP.

[0061] Note that palladium (Pd) plating may be performed between the nickel plating and the gold plating.

[0062] The semiconductor device SD of the present embodiment is manufactured as described above. <Effect> Next, the effects of the present embodiment will be described in comparison with the comparative examples shown in FIGS. 7 and 8.

[0063] As shown in FIGS. 7 and 8, in the comparative example, the emitter pad EP and the Kelvin emitter pad KP are electrically connected to each other by sharing the first layer FL composed of the barrier metal layer BM and aluminum. Therefore, in the comparative example, it is not necessary to electrically connect the emitter pad EP and the Kelvin emitter pad KP by the clip conductor CC. Thus, no relay pad is provided in the comparative example.

[0064] Since the configurations of the comparative examples other than the above are substantially the same as the configuration of the present embodiment, the same elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0065] As shown in FIG. 8, in the comparative example, the emitter pad EP and the Kelvin emitter pad KP share the first layer FL made of aluminum. Also, the first layer FL is exposed in a large area from the insulating layer OI in the region where the emitter pad EP is formed, and is exposed in a small area from the insulating layer OI in the region where the Kelvin emitter pad is formed.

[0066] During the zincate treatment of the first layer FL made of aluminum, the Al of the first layer FL undergoes the reaction of Al → Al 3+ + 3e - Also, Zn in the chemical solution 2+ obtains the electrons (e - ) in the first layer FL and undergoes the reaction of Zn 2+ + 2e - → Zn. As a result, a zinc film ZN is formed on the first layer FL. The reaction stops when the entire surface of the aluminum is replaced with Zn.

[0067] Also, in the zincate treatment, Zn in the chemical solution 2+is not sufficiently supplied to the first layer FL of the emitter pad EP region that is exposed over a large area, but is sufficiently supplied to the first layer FL of the Kelvin emitter pad KP region that is exposed over a small area. Therefore, the surplus electrons (e - ) in the first layer FL move from the side of the emitter pad EP region that is exposed over a large area to the side of the Kelvin emitter pad KP region that is exposed over a small area through the first layer FL.

[0068] As a result, zinc is excessively deposited on the first layer FL in the Kelvin emitter pad KP region that is exposed over a small area, and a zinc film ZN with a thick film thickness grows. In the Kelvin emitter pad KP region, the adhesion between the first layer FL and the second layer SL2 is reduced by this thick zinc film ZN, and peeling is likely to occur at the location where the bonding wire BW is connected.

[0069] In contrast, in the present embodiment, as shown in FIG. 2, the first layer FL1 of the first conductive layer CL1 having the emitter pad EP and the first layer FL2 of the second conductive layer CL2 having the Kelvin emitter pad KP are separated from each other. Therefore, when the first layers FL1 and FL2 are subjected to the zincate treatment, the surplus electrons (e - ) in the first layer FL1 do not move to the first layer FL2. Thus, excessive deposition of zinc is prevented in each of the Kelvin emitter pad KP and the relay pad RP that are exposed over a small area. Therefore, peeling at the bonding wire connection location due to excessive deposition of zinc is prevented.

[0070] Further, according to the present embodiment, as shown in FIG. 2, the clip conductor CC is disposed on the emitter pad EP and the relay pad RP and is electrically connected to each of the emitter pad EP and the relay pad RP. Since the clip conductor CC is a plate-shaped conductor, it is possible to conduct more current than a linear bonding wire.

[0071] Also, according to this embodiment, as shown in FIG. 2, each of the first conductive layer CL1 and the second conductive layer CL2 has first layers FL1, FL2 and second layers SL1, SL2k, SL2r. Each of the first layers FL1, FL2 contains aluminum. The second layers SL1, SL2k, SL2r are disposed on the first layers FL1, FL2 and contain a first metal (for example, nickel) different from aluminum. When the second layers SL1, SL2k, SL2r made of a metal different from aluminum are formed by electroless plating on the first layers FL1, FL2 containing aluminum, a zincate treatment of the first layers FL1, FL2 is required. In this embodiment, since the excessive precipitation of zinc due to this zincate treatment can be prevented, the peeling of the connection portion of the bonding wire BW can be prevented.

[0072] Also, according to this embodiment, as shown in FIG. 2, when the above zincate treatment is performed, zinc may be present between the first layers FL1, FL2 and the second layers SL1, SL2k, SL2r. However, since the excessive precipitation of zinc due to the zincate treatment can be prevented as described above, even if a small amount of zinc remains, the peeling of the connection portion of the bonding wire BW can be prevented.

[0073] Also, according to this embodiment, as shown in FIG. 2, a gate electrode GE is not disposed in the region directly below the second conductive layer CL2. Also, the second conductive layer CL2 is not directly connected to the n + emitter region ER (impurity region). However, a gate electrode GE is disposed in the region directly below the first conductive layer CL1, and the first conductive layer CL1 is n + directly connected to the emitter region ER. Also, the first conductive layer CL1 and the second conductive layer CL2 are electrically connected to each other by a clip conductor CC. Therefore, the potential of the emitter region ER can be measured at the Kelvin emitter pad KP of the second conductive layer CL2. +

[0074] ​The present inventor also examined the relationship between the ratio of the planar occupied area of the emitter pad EP to the planar occupied area of the Kelvin emitter pad KP (EP / KP) and the amount of zinc deposition in the Kelvin emitter pad KP. The results are shown in FIG. 9.

[0075] As shown in FIG. 9, it was found that when the area ratio (EP / KP) is greater than 60, the amount of zinc deposition increases. Therefore, the configuration in this embodiment is preferably applied to a configuration where the area ratio (EP / KP) is greater than 60. Also, when the area ratio (EP / KP) is 120 or more, it was found that the amount of zinc deposition further increases. Therefore, the configuration in this embodiment is more preferably applied to a configuration where the area ratio (EP / KP) is 120 or more. Further, the ratio (RP / KP) of the planar occupied area of the relay pad RP to the planar occupied area of the Kelvin emitter pad KP shown in FIG. 1 is preferably 60 or less.

[0076] (Embodiment 2) Next, the configuration of the semiconductor device according to Embodiment 2 will be described with reference to FIGS. 10 and 11.

[0077] As shown in FIGS. 10 and 11, the configuration of this embodiment is different from that of Embodiment 1 in that the gate electrode GE of the IGBT and the n + emitter region ER are arranged in the region directly below the second conductive layer CL2, and the second conductive layer CL2 is n + emitter region ER and p + contact region CON are directly connected.

[0078] Since the configuration of this embodiment other than the above is substantially the same as the configuration of Embodiment 1, the same reference numerals are given to the same elements, and the description thereof will not be repeated.

[0079] In this embodiment, as shown in FIG. 11, since the gate electrode GE and the n + emitter region ER are arranged directly below the second conductive layer CL2, the area of the semiconductor chip can be reduced.

[0080] (Embodiment 3) Next, the configuration of the semiconductor device according to Embodiment 3 will be described with reference to FIGS. 12 and 13.

[0081] As shown in FIGS. 12 and 13, the configuration of this embodiment is different from that of Embodiment 2 in that it has a plurality of first conductive layers CL1 and in the planar shapes of the relay pad RP and the second conductive layer CL2.

[0082] Each of the plurality of first conductive layers CL1 is separated from each other. The plurality of first conductive layers CL1 are, for example, three first conductive layers CL1. The plurality of first conductive layers CL1 may be two, or four or more first conductive layers CL1.

[0083] Each of the plurality of first conductive layers CL1 has, for example, a rectangular planar shape. The plurality of first conductive layers CL1 are arranged side by side in a straight line, for example, in a plan view. Specifically, each of the plurality of first conductive layers CL1 has a rectangular planar shape, and the plurality of first conductive layers CL1 are arranged side by side in a straight line along the short side direction of the rectangular planar shape in a plan view.

[0084] Each of the plurality of first conductive layers CL1 has an emitter pad EP. Each of the plurality of emitter pads EP has, for example, a rectangular planar shape. The plurality of emitter pads EP are arranged side by side in a straight line, for example, in a plan view. Specifically, each of the plurality of emitter pads EP has a rectangular planar shape, and the plurality of emitter pads EP are arranged side by side in a straight line along the short side direction of the rectangular planar shape in a plan view.

[0085] The second conductive layer CL2 has, for example, an L-shaped planar shape. The second conductive layer CL2 has a relay pad RP. The relay pad RP has, for example, a rectangular planar shape, and is arranged side by side in a straight line with the plurality of emitter pads EP along the short side direction of the rectangular planar shape in a plan view.

[0086] The clip conductor CC is electrically connected to each of a plurality of emitter pads EP and relay pads RP via solder SOL. By dividing a plurality of large-area emitter pads EP, the stress of the metal film (Al layer, OPM film) is released. As a result, the warpage of the wafer state after the semiconductor substrate SB is thinly polished and the warpage of the chip state after dicing are reduced, which has the advantages of improving manufacturing ease and reducing the defect rate such as cracks.

[0087] In addition, the configuration of this embodiment other than the above is substantially the same as the configuration of Embodiment 2. Therefore, the same elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0088] (Others) In the above-described Embodiments 1 to 3, a vertical IGBT has been described as the electrical element formed on the semiconductor substrate SB. However, the electrical element to which the present disclosure is applied is not limited to the vertical IGBT, and it may be a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as shown in FIG. 14.

[0089] As shown in FIG. 14, the vertical power MOSFET has an n + drain region DR, an n - drift region DRI, a p-type base region BR, a p + contact region CON, an n + source region SR, and a gate electrode GE.

[0090] n + The drain region DR is disposed on the second surface SS of the semiconductor substrate SB. An n + drift region DRI is disposed so as to be in contact with the drain region DR. An n - drift region DRI is disposed so as to be in contact with the drain region DR. An n - The drift region DRI has an n-type impurity concentration lower than the n-type impurity concentration of the drain region DR. An n + drift region DRI has an n-type impurity concentration lower than the n-type impurity concentration of the drain region DR. An n - The drift region DRI and the pn junction are configured such that on the drift region DRI (n - on the drift region DRI (n- A p-type base region BR is disposed on the first surface FS side with respect to the drift region DRI.

[0091] On the p-type base region BR (on the first surface FS side with respect to the p-type base region BR) so as to be in contact with the p-type base region BR, a p + contact region CON and an n + source region SR are disposed. The p + contact region CON has a p-type impurity concentration higher than the p-type impurity concentration of the p-type base region BR. The n + source region SR is the p + contact region CON and the p-type base region BR each form a pn junction.

[0092] In the semiconductor substrate SB, an n + trench TR is provided that penetrates through each of the source region SR and the p-type base region BR and reaches the n - drift region DRI. A gate insulating layer GI is disposed along the wall surface of the trench TR. The inside of the trench TR is filled with a gate electrode GE. The gate electrode GE faces the p-type base region BR with the gate insulating layer GI interposed therebetween. Thus, the power MOSFET has an insulated-gate field-effect transistor portion.

[0093] The first conductive layer CL1 forms a source electrode by contacting the n + source region SR through a contact hole CH in the interlayer insulating layer IL. The first conductive layer CL1 has a source pad SP exposed from the insulating layer OI. In the present embodiment, the Kelvin emitter pad KP in Embodiments 1 and 2 becomes a Kelvin source pad, and the n + potential of the source region SR is measured. A conductive layer DE disposed on the second surface SS of the semiconductor substrate SB forms a drain electrode DE by contacting the n + drain region DR.

[0094] Even in such a MOSFET, the same effects as in Embodiment 1 can be obtained. As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Signs

[0095] BM, BM1, BM3 Barrier metal layer, BR p-type base region, BW Bonding wire, CE Collector electrode, CH Contact hole, CL1 First conductive layer, CL2 Second conductive layer, CL3 Third conductive layer, CON Contact region, CR Collector region, DE Drain electrode, DR Drain region, DRI Drift region, EP Emitter pad, ER Emitter region, FL, FL1, FL2, FL3 First layer, FS First surface, GE Gate electrode, GI Gate insulating layer, GP Gate pad, HR n + Region, IL Interlayer insulating layer, KP Kelvin emitter pad, OI Insulating layer, RP Relay pad, SB Semiconductor substrate, SD Semiconductor device, SL1, SL2k, SL2, SL2r, SL3 Second layer, SOL Solder, SP Source pad, SR Source region, SS Second surface, TL1, TL2k, TL2r, TL3 Third layer, TR Trench, ZN Zinc film.

Claims

1. A semiconductor substrate having a main surface; A plurality of impurity regions disposed on the semiconductor substrate and serving as source regions or emitter regions; An interlayer insulating layer disposed on the main surface; A first conductive layer connected to the plurality of impurity regions and disposed on the interlayer insulating layer; A second conductive layer separated from the first conductive layer and disposed on the interlayer insulating layer so as not to be directly connected to the plurality of impurity regions; An insulating layer formed on the interlayer insulating layer and disposed between the first conductive layer and the second conductive layer, comprising: The first conductive layer has a first electrode pad exposed from the insulating layer; The second conductive layer has a second electrode pad exposed from the insulating layer and a third electrode pad exposed from the insulating layer; A bonding wire is connected to the second electrode pad; A clip conductor is disposed on the first electrode pad and the third electrode pad and electrically connected to each of the first electrode pad and the third electrode pad; A semiconductor device, wherein a planar occupation area of the second electrode pad is smaller than a planar occupation area of the first electrode pad.

2. Further comprising a third conductive layer connected to the plurality of impurity regions and disposed on the interlayer insulating layer separated from the first conductive layer; The third conductive layer has a fourth electrode pad; The semiconductor device according to claim 1, wherein the clip conductor is disposed on the fourth electrode pad and electrically connected to the fourth electrode pad.

3. Each of the first conductive layer and the second conductive layer: A first layer containing aluminum; A second layer disposed on the first layer and containing a metal different from aluminum, the semiconductor device according to claim 1.

4. The semiconductor device according to claim 1, wherein no gate electrode is disposed in a region directly below the second conductive layer.

5. The semiconductor device according to claim 1, further comprising a gate electrode disposed in a region directly below the second conductive layer.

6. An element having a vertical insulated-gate field-effect transistor portion having the plurality of impurity regions is formed on the semiconductor substrate, the semiconductor device according to claim 1.

7. A step of forming a plurality of impurity regions serving as source regions or emitter regions on a semiconductor substrate; A step of forming an interlayer insulating layer on the semiconductor substrate; A step of forming, on the interlayer insulating layer, a first conductive layer connected to the plurality of impurity regions and a second conductive layer separated from the first conductive layer so as not to be directly connected to the plurality of impurity regions; A step of forming an insulating layer that exposes a first electrode pad of the first conductive layer, a second electrode pad and a third electrode pad of the second conductive layer; A step of connecting a bonding wire to the second electrode pad; A step of electrically connecting a clip conductor to each of the first electrode pad and the third electrode pad, and a manufacturing method of a semiconductor device, wherein a planar occupation area of the second electrode pad is smaller than a planar occupation area of the first electrode pad.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the first conductive layer and the second conductive layer are formed by separating a common conductive layer.

9. The step of forming the common conductive layer includes A step of forming a first layer containing aluminum; A step of performing a zinkate treatment on the first layer; The method of manufacturing a semiconductor device according to claim 8, including a step of forming a second layer made of a metal different from aluminum on the first layer by plating the first layer subjected to the zinkate treatment.

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