Semiconductor device

Abstract

To provide a method for manufacturing a highly reliable semiconductor device having a stable electric property and a thin film transistor arranged by use of an oxide semiconductor.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: forming an oxide semiconductor film on a gate electrode with a gate insulative film interposed therebetween over an insulative plane; forming a first conductive film including titanium, molybdenum or tungsten on the oxide semiconductor film; forming a second conductive film including a metal lower than hydrogen in electronegativity on the first conductive film; forming a source electrode and a drain electrode by etching the first and second conductive films; and forming a dielectric film on the oxide semiconductor film, the source electrode and the drain electrode, which is in contact with the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] Thin film transistors using semiconductor films formed on insulating surfaces are essential for semiconductor devices. Thin-film transistors are essential semiconductor elements. The manufacturing of thin-film transistors is limited by the heat resistance of the substrate. In order to achieve this, amorphous silicon, which can be formed at a relatively low temperature, and laser light or catalytic elements are used. A thin film transistor having an active layer made of polysilicon or the like obtained by crystallization using the above method is a semiconductor. This has become the mainstream type of transistor used in semiconductor displays.

[0003] In recent years, the high mobility provided by polysilicon and the low-temperature properties provided by amorphous silicon have been A new semiconductor material called oxide semiconductor has been developed that has both uniform device characteristics and excellent thermal conductivity. Metal oxides that exhibit semiconducting properties have been attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid crystal displays and other Metal oxides that exhibit semiconducting properties include, for example, , tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides exhibiting these characteristics in the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-123861 A [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] Transistors used in semiconductor devices are desired to have a small variation in threshold voltage due to deterioration over time, and also to have good characteristics such as on-current. By using a transistor with a small variation in threshold voltage due to deterioration over time, the reliability of the semiconductor device can be improved. Also, by using a transistor with good characteristics such as on-current, the semiconductor device can be driven at a higher frequency.

[0006] One object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device. Alternatively, one object of the present invention is to provide a method for manufacturing a semiconductor device capable of high-speed driving. Alternatively, one object of the present invention is to provide a highly reliable semiconductor device. Alternatively, one object of the present invention is to provide a semiconductor device capable of high-speed driving.

MEANS FOR SOLVING THE PROBLEMS

[0007] The inventors of the present invention focused on the fact that impurities such as hydrogen and water present in the oxide semiconductor film are factors that cause deterioration over time such as a shift in the threshold voltage in the transistor. Then, by using a conductive film made of a metal with a low electronegativity, specifically a metal with a lower electronegativity than hydrogen, as the conductive film for the source electrode and the drain electrode and forming it above or below the oxide semiconductor film, impurities such as hydrogen and water present in the oxide semiconductor film are drawn out to the above conductive film, and the purity of the oxide semiconductor film is increased. As a result, the transistor caused by impurities such as hydrogen and water I thought that the deterioration over time might be suppressed. By processing the above conductive film into a desired shape by etching or the like, a source electrode and a drain electrode can be formed.

[0008] Specifically, in one aspect of the present invention, in the fabrication of a semiconductor device having a transistor using an oxide semiconductor film as an active layer, a first conductive film made of a metal material such as titanium, tungsten, or molybdenum having a low contact resistance with the oxide semiconductor film is formed so as to be in contact with the oxide semiconductor film. Further, a second conductive film made of a metal, metal compound, or alloy having a low electronegativity is formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween. Then, by processing the first conductive film and the second conductive film into a desired shape by etching or the like, a source electrode and a drain electrode are formed.

[0009] Alternatively, the first conductive film is formed so as to be in contact with the oxide semiconductor film, and after the second conductive film is formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween, the second conductive film is removed by etching. In this case, after removing the second conductive film, a third conductive film made of a metal, metal compound, or alloy having a low electronegativity is newly formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween. Then, by processing the first conductive film and the third conductive film into a desired shape by etching or the like, a source electrode and a drain electrode are formed.

[0010] Alternatively, the first conductive film is formed so as to be in contact with the oxide semiconductor film, and after the second conductive film is formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween, the second The first conductive film is removed by etching. Then, after removing the second conductive film, A third conductive film using a metal, metal compound, or alloy having a low resistance is sandwiched between the first conductive film. The third conductive film is formed so as to overlap with the oxide semiconductor film. The fourth type uses metallic materials such as titanium, tungsten, or molybdenum, which have low contact resistance. The conductive film is formed so as to overlap with the oxide semiconductor film. The fifth type uses metallic materials such as titanium, tungsten, or molybdenum, which have low contact resistance. A conductive film may be formed between the first conductive film and the third conductive film. the first conductive film, the third conductive film and the fourth conductive film, or the first conductive film, the third conductive film and the fourth conductive film The first conductive film and the fifth conductive film are processed into a desired shape by etching or the like, thereby forming a saw. A source electrode and a drain electrode are formed.

[0011] In one embodiment of the present invention, the first conductive film constituting the source electrode and the drain electrode is formed of an oxide A metal material having low contact resistance with the semiconductor film is used, and the metal material is in contact with the oxide semiconductor film. Therefore, the contact resistance between the source electrode or drain electrode and the oxide semiconductor film is low. As a result, the on-current and field effect mobility of the TFT can be increased. The second conductive film and the third conductive film are made of a metal, a metal compound, or an alloy having low electronegativity. Therefore, the oxide semiconductor film, the gate insulating film, or the oxide semiconductor film and other insulating films are Impurities such as moisture or hydrogen that exist at the interface and its vicinity may cause the second conductive film and the third conductive film to be damaged. Therefore, impurities such as moisture and hydrogen are absorbed or adsorbed in the conductive film. By using the above impurities, it is possible to obtain an oxide semiconductor that is almost i-type. Prevent the deterioration of transistor characteristics such as threshold voltage shift, and reduce the off-current can be reduced.

[0012] Examples of metals with low electronegativity include aluminum and magnesium. A mixture, metal compound, or alloy containing any one or more of the above metals can be used as the second conductive film and the third conductive film. Also, an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, or an alloy containing one or more of the above elements as components, or a heat-resistant conductive material such as a nitride containing the above elements as components can be combined with aluminum and used as the second conductive film and the third conductive film. Among the above metals with low contact resistance with the oxide semiconductor film, titanium has a lower electronegativity than hydrogen, so it is easy to extract impurities such as moisture or hydrogen from the oxide semiconductor film. Therefore, by using titanium for the first conductive film, the fourth conductive film, and the fifth conductive film, the impurities in the oxide semiconductor film can be further reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. In addition to the above configuration, a heat treatment may be performed in a reduced-pressure atmosphere or an inert gas atmosphere with the second conductive film, the third conductive film, or the fourth conductive film exposed, to remove moisture, oxygen, etc. adsorbed on the surface or inside of the second conductive film, the third conductive film, or the fourth conductive film. The temperature range of the heat treatment is 200°C to 450°C. By performing the above heat treatment, inside the oxide semiconductor film, inside the gate insulating film, or between the oxide semiconductor film and another insulating film

[0013] Among the above metals with low contact resistance with the oxide semiconductor film, since titanium has a lower electronegativity than hydrogen, it is easy to extract impurities such as moisture or hydrogen from the oxide semiconductor film. Thus, by using titanium for the first conductive film, the fourth conductive film, and the fifth conductive film, the impurities in the oxide semiconductor film can be reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. Since titanium has a lower electronegativity than hydrogen among the above metals with low contact resistance with the oxide semiconductor film, it is easy to extract impurities such as moisture or hydrogen from the oxide semiconductor film. Therefore, by using titanium for the first conductive film, the fourth conductive film, and the fifth conductive film, the impurities in the oxide semiconductor film can be further reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. oxide semiconductor film impurities can be reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. oxide semiconductor film impurities can be reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. oxide semiconductor film impurities can be reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed.

[0014] Also, in addition to the above configuration, a heat treatment may be performed in a reduced-pressure atmosphere or an inert gas atmosphere with the second conductive film, the third conductive film, or the fourth conductive film exposed, to remove moisture, oxygen, etc. adsorbed on the surface or inside of the second conductive film, the third conductive film, or the fourth conductive film. The temperature range of the heat treatment is 200°C to 450°C. By performing the above heat treatment, inside the oxide semiconductor film, inside the gate insulating film, or between the oxide semiconductor film and another insulating film oxide semiconductor film impurities can be reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. oxide semiconductor film impurities can be reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. oxide semiconductor film impurities can be reduced, and a source electrode or drain electrode with low contact resistance with the oxide semiconductor film can be formed. Moisture or impurities such as hydrogen present at the interface and in its vicinity can be easily occluded or adsorbed by the second conductive film, the third conductive film, or the fourth conductive film.

[0015] After forming the source electrode and the drain electrode, a single insulating film or a plurality of stacked insulating films may be formed so as to cover the source electrode, the drain electrode, and the oxide semiconductor film. It is desirable to use a material with high barrier properties for the above-mentioned insulating film. For example, as the insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of stacked insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the above-mentioned insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film. Then, with the insulating film with a lower nitrogen ratio sandwiched in between, a barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface or inside of the conductive film. Also, moisture or impurities such as hydrogen can be prevented from entering the oxide semiconductor film, the gate insulating film, or the interface and its vicinity between the oxide semiconductor film and other insulating films. Furthermore, a gate insulating film having a structure in which an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio are stacked between the gate electrode and the oxide semiconductor film may be formed. The insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the barrier insulating film and the oxide semiconductor film. The barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film with the insulating film having a lower nitrogen ratio sandwiched in between. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface or inside of the conductive film. Also, moisture or impurities such as hydrogen can be prevented from entering the oxide semiconductor film, the gate insulating film, or the interface and its vicinity between the oxide semiconductor film and other insulating films. the interface and its vicinity between the oxide semiconductor film and other insulating films. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface or inside of the conductive film. Also, moisture or impurities such as hydrogen can be prevented from entering the oxide semiconductor film, the gate insulating film, or the interface and its vicinity between the oxide semiconductor film and other insulating films. Furthermore, a gate insulating film having a structure in which an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio are stacked between the gate electrode and the oxide semiconductor film may be formed. The insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the barrier insulating film and the oxide semiconductor film. The barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film with the insulating film having a lower nitrogen ratio sandwiched in between. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface or inside of the conductive film. Also, moisture or impurities such as hydrogen can be prevented from entering the oxide semiconductor film, the gate insulating film, or the interface and its vicinity between the oxide semiconductor film and other insulating films.

[0016] Also, between the gate electrode and the oxide semiconductor film, an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio are stacked to form a gate insulating film. The insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the barrier insulating film and the oxide semiconductor film. The barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film with the insulating film having a lower nitrogen ratio sandwiched in between. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface or inside of the conductive film. Also, moisture or impurities such as hydrogen can be prevented from entering the oxide semiconductor film, the gate insulating film, or the interface and its vicinity between the oxide semiconductor film and other insulating films. Furthermore, a gate insulating film having a structure in which an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio are stacked between the gate electrode and the oxide semiconductor film may be formed. The insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the barrier insulating film and the oxide semiconductor film. The barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film with the insulating film having a lower nitrogen ratio sandwiched in between. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface or inside of the conductive film. Also, moisture or impurities such as hydrogen can be prevented from entering the oxide semiconductor film, the gate insulating film, or the interface and its vicinity between the oxide semiconductor film and other insulating films. By using this, impurities such as moisture, impurities in the atmosphere such as hydrogen, or alkali metals, heavy metals, etc. contained in the substrate can be prevented from entering into the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and the vicinity thereof.

[0017] Furthermore, in order to reduce moisture or impurities such as hydrogen in the oxide semiconductor film, after forming the oxide semiconductor film, a heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) with the oxide semiconductor film exposed. The temperature range of the above heat treatment is desirably carried out at 500°C or higher and 750°C or lower (or a temperature below the strain point of the glass substrate). In addition, this heat treatment should not exceed the heat-resistant temperature of the substrate used.

[0018] The oxide semiconductor can be a quaternary metal oxide such as In-Sn-Ga-Zn-O-based oxide semiconductor, a ternary metal oxide such as In-Ga-Zn-O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, Sn-Al-Zn-O-based oxide semiconductor, a binary metal oxide such as In-Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-Ga-O-based oxide semiconductor, or In-O-based oxide semiconductor, Sn-O-based oxide semiconductor, Zn-O-based oxide semiconductor, etc. In this specification, for example, the In-Sn-Ga-Zn-O-based oxide semiconductor means indium (In), tin (Sn), gallium (Ga), zinc (Zn) ​​​​​​​​​​​​​​​It means a metal oxide having a composition ratio that is not particularly limited. Further, the above oxide The semiconductor may contain silicon.

[0019] Alternatively, the oxide semiconductor has a chemical formula InMO 3 (ZnO) m (m > 0) and can be expressed as such. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co and indicates.

[0020] Note that in the oxide semiconductor film, impurities such as moisture are desorbed by heat treatment, resulting in an increase in carrier concentration and a decrease in resistance. Subsequently, when an insulating film such as silicon oxide or silicon oxynitride is formed in contact with the low-resistance oxide semiconductor film, oxygen is supplied to at least the region in contact with the insulating film of the low-resistance oxide semiconductor film, causing the carrier concentration to decrease (preferably less than 1×10 / cm 18 and more preferably 1×10 3 / cm 14 or less), and the resistance increases. Thus, during the process of the semiconductor device, by forming an insulating film such as silicon oxide or silicon oxynitride 3 , the carrier concentration and resistance of the oxide semiconductor film can be controlled, enabling the production and provision of a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability.

[0021] Also, the transistor may be of a bottom-gate type, a top-gate type, or a bottom-contact type. A bottom-gate type transistor has a gate electrode on an insulating surface , a gate insulating film on the gate electrode, an oxide semiconductor film overlapping the gate electrode on the gate insulating film, a source electrode and a drain electrode on the oxide semiconductor film, and a source electrode on the oxide semiconductor film. ​ and has a drain electrode and an insulating film on the oxide semiconductor film. A top gate type transistor has an oxide semiconductor film on an insulating surface, a gate insulating film on the oxide semiconductor film, and a gate electrode that overlaps the oxide semiconductor film on the gate insulating film and functions as a conductive film, a drain electrode, a source electrode, a drain electrode, and an insulating film on the oxide semiconductor film. A bottom contact type transistor has a gate electrode on an insulating surface, a gate insulating film on the gate electrode, a source electrode and a drain electrode on the gate insulating film, and an oxide semiconductor film that is on the source electrode and the drain electrode and overlaps the gate electrode on the gate insulating film, a source electrode, a drain electrode, and an insulating film on the oxide semiconductor film. The heat treatment uses heat treatment in a furnace or a rapid thermal annealing method (RTA method). The RTA method includes a method using a lamp light source and a method of moving a substrate in a heated gas to perform a short-time heat treatment. When the RTA method is used, the time required for the heat treatment can be made shorter than 0.1 hour. However, when a glass substrate is used as the substrate, the heat treatment is performed at a temperature of 300°C or higher

[0022] and at a temperature equal to or lower than the strain point of the glass substrate. and at a temperature equal to or lower than the strain point of the glass substrate.

Advantages of the Invention

Brief Description of the Drawings

[0023]

[0024]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and its form and details can be variously changed without departing from the spirit and scope of the present invention. This will be easily understood by those skilled in the art. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0026] Note that the present invention can be used in the fabrication of various semiconductor devices such as integrated circuits such as microprocessors and image processing circuits, RF tags, and semiconductor display devices. A semiconductor device means all devices that can function by utilizing semiconductor characteristics. Semiconductor display devices, semiconductor circuits and electronic devices are all semiconductor devices. Semiconductor display devices include liquid crystal display devices, light-emitting devices having light-emitting elements such as organic light-emitting elements (OLEDs) in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Displa y), etc., and other semiconductor display devices having circuit elements using a semiconductor film in the drive circuit are included in that category.

[0027] (Embodiment 1) Taking a bottom-gate type thin film transistor with a channel etch structure as an example, the manufacturing method will be described with reference to FIGS. 1 to 3.

[0028] As shown in FIG. 1(A), a gate electrode 101 is formed on a substrate 100.

[0029] An insulating film serving as an underlayer film may be formed between the substrate 100 and the gate electrode 101. Under the layer film, for example, any one of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, nitride aluminum film, or aluminum oxynitride film can be used alone or in a plurality of layers. In particular, for the underlayer film, an insulating film with high barrier properties, such as silicon nitride film, silicon oxynitride film, aluminum nitride film, or aluminum oxynitride film, etc., is used to prevent impurities in the atmosphere such as moisture or hydrogen, or impurities such as alkali metals or heavy metals contained in the substrate 100 from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity. In this specification, oxynitride means a substance having a higher oxygen content than nitrogen in its composition, and oxynitride means a substance having a higher nitrogen content than oxygen in its composition.

[0030]

[0031] substance.

[0031] The material of the gate electrode 101 is molybdenum, titanium, chromium, tantalum, tungsten, ne Metal materials such as osmium and scandium, and alloy materials mainly composed of these metal materials can be used for the conductive film, or nitrides of these metals can be used either singly or in a stacked manner. Note that if it can withstand the temperature of the heat treatment performed in the subsequent process, aluminum and copper can also be used as the above metal materials. Aluminum or copper is preferably used in combination with a high melting point metal material in order to avoid problems such as heat resistance and corrosion resistance. As the high melting point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used.

[0032] For example, as the gate electrode 101 having a two-layer stacked structure, a two-layer stacked structure in which a molybdenum film is stacked on an aluminum film, or a two-layer structure in which a molybdenum film is stacked on a copper film, or a two-layer structure in which a titanium nitride film or a tantalum nitride film is stacked on a copper film, or a two-layer structure in which a titanium nitride film and a molybdenum film are stacked is preferable. As the gate electrode 101 having a three-layer stacked structure, it is preferable to have a structure in which an aluminum film, an aluminum-silicon alloy film, an aluminum-titanium alloy film, or an aluminum-neodymium alloy film is used as an intermediate layer, and a tungsten film, a tungsten nitride film, a titanium nitride film, or a titanium film is used as upper and lower layers and stacked.

[0033] In addition, by using a transparent oxide conductive film such as indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, or gallium zinc oxide for the gate electrode 101, the aperture ratio of the pixel portion can be improved.

[0034] ​​​​​​​​​ The film thickness of the gate electrode 101 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, after forming a conductive film for the gate electrode with a thickness of 150 nm by a sputtering method using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching to form the gate electrode 101.

[0035] Next, a gate insulating film 102 is formed on the gate electrode 101. The gate insulating film 102 can be formed by using a plasma CVD method, a sputtering method, or the like to form a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, aluminum oxide, or tantalum oxide. It is desirable that the gate insulating film 102 contains as few impurities such as moisture and hydrogen as possible. The gate insulating film 102 may have a structure in which an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio are laminated. In this case, the insulating films such as the silicon oxide film and the silicon oxynitride film are formed between the insulating film with barrier properties and the oxide semiconductor film. Examples of the insulating film with high barrier properties include a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film. By using an insulating film with barrier properties, it is possible to prevent impurities such as moisture or hydrogen in the atmosphere or impurities such as alkali metals and heavy metals contained in the substrate from entering the oxide semiconductor film, the gate insulating film 102, or the interface between the oxide semiconductor film and other insulating films and the vicinity thereof. Also, by forming an insulating film such as a silicon nitride film or a silicon oxynitride film with a low nitrogen ratio in contact with the oxide semiconductor film, it is possible to use a material with high barrier properties. It is possible to prevent the insulating film from directly contacting the oxide semiconductor film.

[0036] In this embodiment, on a silicon nitride film with a thickness of 50 nm formed by sputtering, a silicon oxide film with a thickness of 100 nm formed by sputtering is laminated to form a gate insulating film 10 2.

[0037] Next, an oxide semiconductor film is formed on the gate insulating film 102. The oxide semiconductor film uses an oxide semiconductor as a target and is formed by sputtering. Also, the oxide semiconductor film can be formed by sputtering in a rare gas (for example, argon) atmosphere, an oxygen atmosphere, or a rare gas (for example, argon) and an oxygen atmosphere.

[0038] Before forming the oxide semiconductor film by sputtering, it is preferable to perform reverse sputtering to introduce argon gas to generate plasma and remove the dust adhering to the surface of the gate insulating film 102. Reverse sputtering is a method in which a voltage is not applied to the target side, and a voltage is applied to the substrate side using an RF power source in an argon atmosphere to form plasma on the substrate and modify the surface . Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also , it may be performed in an atmosphere in which oxygen, hydrogen, nitrous oxide, etc. are added to the argon atmosphere. Also, , it may be performed in an atmosphere in which chlorine, carbon tetrafluoride, etc. are added to the argon atmosphere.

[0039]

[0040] For the oxide semiconductor film, the above-described oxide semiconductor can be used.

[0040] The thickness of the oxide semiconductor film is 10 nm to 300 nm, preferably 20 nm to 100 nm. In this embodiment, as the oxide semiconductor film, In (indium), Ga (gallium), and an oxide semiconductor target containing Zn (zinc) (molar ratio is In 2 O 3 :Ga 2 O 3 : ZnO = 1:1:1, In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2) is used for sputtering method, and an In-Ga-Zn-O-based oxide semiconductor with a film thickness of 30 nm is used. In this embodiment form, the DC sputtering method is used, the flow rate of argon is 30 sccm, and the flow rate of oxygen is 1 5 sccm, and the substrate temperature is room temperature.

[0041] The gate insulating film 102 and the oxide semiconductor film may be continuously formed without exposing them to the atmosphere. By continuously forming the film without exposing it to the atmosphere, the interface can form each laminated interface without being contaminated by atmospheric components such as water and hydrocarbons and impurity elements floating in the atmosphere, so that the variation in thin film transistor characteristics can be reduced.

[0042] Next, as shown in FIG. 1(A), the oxide semiconductor film is processed (patterned) into a desired shape by etching or the like, and an island-shaped oxide semiconductor film 103 is formed on the gate insulating film 102 at a position overlapping the gate electrode 101.

[0043] Next, the oxide semiconductor film 103 may be heat-treated in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.). By heat-treating the oxide semiconductor film 103 an oxide semiconductor film 104 from which moisture and hydrogen have desorbed is formed. Specifically, under a reduced pressure Measured using a dew point meter of the CRDS (Cavity Ring - down Laser Spectroscopy) method In an atmosphere of air where the moisture content is 20 ppm or less (equivalent to - 55 °C in terms of dew point), preferably 1 ppm or less, more preferably 10 ppb or less, at a temperature of 500 °C or more and 750 °C or less (or a temperature below the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably 600 °C, for about 3 minutes or more and 6 minutes or less of RTA (Rapid Thermal Anneal) treatment can be carried out. By using the RTA method, dehydration or dehydrogenation can be performed in a short time, so that it can be processed even at a temperature exceeding the strain point of the glass substrate. Note that the above heat treatment is not limited to the timing after the formation of the island - shaped oxide semiconductor film 103, and can also be performed on the oxide semiconductor film before the formation of the island - shaped oxide semiconductor film 103. Also, the above heat treatment can be performed multiple times after the formation of the oxide semiconductor film 104. The island - shaped oxide semiconductor film 104 has impurities such as moisture and hydrogen desorbed by the above heat treatment, and becomes an i - type (intrinsic semiconductor) or approaches the i - type as much as possible, so that the deterioration of transistor characteristics such as the threshold voltage shift due to the above impurities is prevented, and the off - current can be reduced. In this embodiment, in a nitrogen atmosphere, at 600 °C, when the substrate temperature reaches the above - set temperature, the heat treatment is performed for 6 minutes. The heat treatment can use a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using heated gas or an LRTA (Lamp Rapid Thermal Anneal) method using lamp light, etc., that is, an instant heating method. For example, when performing heat treatment using an electric furnace, the heat treatment is carried out as follows.

[0044] In this embodiment, in a nitrogen atmosphere, at 600 °C, when the substrate temperature reaches the above - set temperature, the heat treatment is performed for 6 minutes. The heat treatment can use a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using heated gas or an LRTA (Lamp Rapid Thermal Anneal) method using lamp light, etc., that is, an instant heating method. For example, when performing heat treatment using an electric furnace, the heat treatment is carried out as follows. For example, when performing heat treatment using an electric furnace, The heating rate is preferably 0.1 °C / min or more and 20 °C / min or less, and the cooling rate is preferably 0.1 °C / min or more and 15 °C / min or less.

[0045] In the heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0046] Next, as shown in Fig. 1(C), a conductive film for the source electrode and drain electrode is formed on the island-shaped oxide semiconductor film 104. In this embodiment, on the conductive film 105a made of a metal material such as titanium, tungsten, or molybdenum with low contact resistance to the oxide semiconductor film 104 a conductive film 105b made of a metal, metal compound, or alloy with low electronegativity is formed. As the metal with low electronegativity, aluminum or magnesium can also be used. A mixture, metal compound, or alloy containing any one or more of the above metals can be used as the conductive film 105b. Also, when using a material with low heat resistance such as aluminum,

[0047] the heat resistance of the conductive film 105b can be increased by combining aluminum with an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium or an alloy containing one or more of the above elements as components, or a heat-resistant conductive material such as a nitride containing the above elements as components.

[0048]

[0048] ​The thickness of the conductive film 105a is set to 10 nm to 200 nm, preferably 50 nm to 150 nm. The thickness of the conductive film 105b is preferably 100 nm to 300 nm. In the present embodiment, the conductive film 105a is preferably formed to a thickness of 150 nm to 250 nm. A titanium film having a thickness of 100 nm formed by a sputtering method was used as the conductive film 105b. An aluminum film having a thickness of 200 nm formed by sputtering is used.

[0049] In one embodiment of the present invention, the conductive film 105b is made of a metal, a metal compound, or a composite having a low electronegativity. Since gold is used, the gold is deposited in the oxide semiconductor film 104, the gate insulating film 102, or the oxide Impurities such as moisture or hydrogen that exist at and near the interface between the semiconductor film 104 and other insulating films Therefore, impurities such as moisture and hydrogen are desorbed. As a result, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is extremely close to i-type can be obtained. The above impurities can accelerate the degradation of transistor characteristics, such as a shift in threshold voltage. This can prevent the off-state current from being increased and reduce the off-state current.

[0050] In addition to the above configuration, the conductive film 105b may be exposed under a reduced pressure atmosphere, nitrogen, or The heat treatment is performed under an inert gas atmosphere such as rare gas (argon, helium, etc.), and the The moisture and oxygen adsorbed on the surface and inside of the conductive film 105b may be removed. The temperature range of the heat treatment is 200° C. to 450° C. By performing the heat treatment, the acid In the oxide semiconductor film 104, in the gate insulating film 102, or between the oxide semiconductor film 104 and other insulating films, Impurities such as moisture and hydrogen that are present at the interface of the insulating film and its vicinity are absorbed by the conductive film 105b. It can be made easier to be occluded or adsorbed.

[0051] Next, as shown in FIG. 1(D), by processing (patterning) the conductive film 105a and the conductive film 105 b into a desired shape, the source electrode 106 and the drain electrode 1 07 are formed. For example, when a titanium film is used for the conductive film 105a and an aluminum film is used for the conductive film 105b after wet-etching the conductive film 105b using a solution containing phosphoric acid the conductive film 105a may be wet-etched using a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, for ammonia peroxide specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5: 2:2 is used. Alternatively, the conductive film 105a and the conductive film 105b may be dry-etched using a gas containing chlorine (Cl 2 ), boron chloride (BCl 3 ), etc. When the source electrode 106 and the drain electrode 107 are formed by the above patterning, a groove portion (recess) may be formed due to partial etching of the exposed portion of the island-shaped

[0052] oxide semiconductor film 104. In this embodiment, a case where an island-shaped oxide semiconductor film 108 having a groove portion (recess) is formed by the above etching is exemplified. The conductive film 105a used for a part of the source electrode 106 and the drain electrode 107 is in contact with the oxide semiconductor film 108 And, as described above, the conductive film 105a is in contact with the oxide semiconductor film 108 and formed. The source electrode 106, the drain electrode 107 is in contact with the oxide semiconductor film 108 . And still, as described above, the conductive film 105a is in contact with the oxide semiconductor film 108 Since a metal material with low resistance is used, the contact resistance between the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased.

[0053] As shown in Fig. 1(E), after forming the source electrode 106 and the drain electrode 107, an insulating film 109 is formed so as to cover the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108. It is desirable that the insulating film 109 contains as little moisture and impurities such as hydrogen as possible. It may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. It is desirable to use a material with high barrier properties for the insulating film 109. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 108. Then, an insulating film having barrier properties is formed so as to overlap the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108 with the insulating film having a lower nitrogen ratio sandwiched therebetween. By using an insulating film having barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 106 and the drain electrode 107. In addition, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film 108, the gate insulating film 102, or the interface between the oxide semiconductor film 108 and other insulating films and the vicinity thereof. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio in contact with the oxide semiconductor film 108, a material with high barrier properties is used. ​ It is possible to prevent the insulating film from directly contacting the oxide semiconductor film 108.

[0054] In this embodiment, an insulating film 109 having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower. In this embodiment, it is set to 100 °C.

[0055] By providing the exposed region of the oxide semiconductor film 108 provided between the source electrode 106 or the drain electrode 107 in contact with the silicon oxide constituting the insulating film 109, oxygen is supplied to the region of the oxide semiconductor film 108 in contact with the insulating film 109, resulting in an increase in resistance (the carrier concentration decreases, preferably to less than 1×10 / cm ), and an oxide semiconductor film having a high-resistance channel formation region can be formed. 18 / cm 3

[0056] Note that after forming the insulating film 109, a heat treatment may be performed. The heat treatment is performed in an air atmosphere , a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an ultra dry air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm (dew point conversion -55 °C) or less, preferably 1 ppm or less , preferably 10 ppb or less of air) atmosphere, preferably at 200 °C or higher and 400 °C or lower (for example, 250 °C or higher and 350 °C or lower). In this embodiment, for example, a heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. Alternatively, before forming the conductive films 105a and 105 b, similar to the previous heat treatment performed on the oxide semiconductor film, a high-temperature short-time ​ An RTA process may be performed. When this heat treatment is performed, the oxide semiconductor film 108 is heated in contact with the silicon oxide that constitutes the insulating film 109, and further, the oxide semiconductor film 108 is made to have a higher resistance, improving the electrical characteristics of the transistor and reducing variations in the electrical characteristics. This can be achieved. The timing for performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 109, and it can be performed without increasing the number of steps by combining it with other processes, such as a heat treatment during resin film formation or a heat treatment for reducing the resistance of the transparent conductive film. This can be achieved. The timing for performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 109, and it can be performed without increasing the number of steps by combining it with other processes, such as a heat treatment during resin film formation or a heat treatment for reducing the resistance of the transparent conductive film. This can be achieved. The timing for performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 109, and it can be performed without increasing the number of steps by combining it with other processes, such as a heat treatment during resin film formation or a heat treatment for reducing the resistance of the transparent conductive film. This can be achieved. The timing for performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 109, and it can be performed without increasing the number of steps by combining it with other processes, such as a heat treatment during resin film formation or a heat treatment for reducing the resistance of the transparent conductive film. This can be achieved. The timing for performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 109, and it can be performed without increasing the number of steps by combining it with other processes, such as a heat treatment during resin film formation or a heat treatment for reducing the resistance of the transparent conductive film.

[0057] FIG. 2 shows a top view of the semiconductor device shown in FIG. 1(E). FIG. 1(E) corresponds to a cross-sectional view taken along the dashed line A1 - A2 in FIG. 2. FIG. 2 shows a top view of the semiconductor device shown in FIG. 1(E). FIG. 1(E) corresponds to a cross-sectional view taken along the dashed line A1 - A2 in FIG. 2.

[0058] The transistor 110 includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 108 on the gate insulating film 102, a source electrode 106 and a drain electrode 107 on the oxide semiconductor film 108, and an insulating film 109 on the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108. The transistor 110 includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 108 on the gate insulating film 102, a source electrode 106 and a drain electrode 107 on the oxide semiconductor film 108, and an insulating film 109 on the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108. The transistor 110 includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 108 on the gate insulating film 102, a source electrode 106 and a drain electrode 107 on the oxide semiconductor film 108, and an insulating film 109 on the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108. The transistor 110 includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 108 on the gate insulating film 102, a source electrode 106 and a drain electrode 107 on the oxide semiconductor film 108, and an insulating film 109 on the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108.

[0059] Next, after forming a conductive film on the insulating film 109 and patterning the conductive film, a back gate electrode 111 may be formed at a position overlapping the oxide semiconductor film 108 as shown in FIG. 3(A). The back gate electrode 111 can be formed using the same material and structure as the gate electrode 101, or the source electrode 106 and the drain electrode 107. Next, after forming a conductive film on the insulating film 109 and patterning the conductive film, a back gate electrode 111 may be formed at a position overlapping the oxide semiconductor film 108 as shown in FIG. 3(A). The back gate electrode 111 can be formed using the same material and structure as the gate electrode 101, or the source electrode 106 and the drain electrode 107. Next, after forming a conductive film on the insulating film 109 and patterning the conductive film, a back gate electrode 111 may be formed at a position overlapping the oxide semiconductor film 108 as shown in FIG. 3(A). The back gate electrode 111 can be formed using the same material and structure as the gate electrode 101, or the source electrode 106 and the drain electrode 107. Next, after forming a conductive film on the insulating film 109 and patterning the conductive film, a back gate electrode 111 may be formed at a position overlapping the oxide semiconductor film 108 as shown in FIG. 3(A). The back gate electrode 111 can be formed using the same material and structure as the gate electrode 101, or the source electrode 106 and the drain electrode 107.

[0060] The film thickness of the back gate electrode 111 is 10 nm to 400 nm, preferably 100 nm to 20 Set it to 0 nm. In this embodiment, a conductive film having a structure in which a titanium film, an aluminum film, and a titanium film are laminated is formed. Then, a resist mask is formed by photolithography, and unnecessary portions are removed by etching to process (pattern) the conductive film into a desired shape, thereby forming the back gate electrode 111. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. In this embodiment, a 300-nm insulating film is formed by the plasma CVD method. The film formation conditions are as follows: the flow rate of silane gas is set to 4 sccm, the flow rate of dinitrogen monoxide (N2O) is set to 800 sccm, and the substrate temperature is set to 400 °C. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm.

[0061] Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm.

[0062] In this embodiment, a 300-nm insulating film is formed by the plasma CVD method. The film formation conditions are as follows: the flow rate of silane gas is set to 4 sccm, the flow rate of dinitrogen monoxide (N2O) is set to 800 sccm, and the substrate temperature is set to 400 °C. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. 2 Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm. Next, as shown in FIG. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, as a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm.

[0063] FIG. 3(C) shows a top view of the semiconductor device shown in FIG. 3(B). FIG. 3(B) corresponds to a cross-sectional view taken along the dashed line A1 - A2 in FIG. 3(C). FIG. 3(C) shows a top view of the semiconductor device shown in FIG. 3(B). FIG. 3(B) corresponds to a cross-sectional view taken along the dashed line A1 - A2 in FIG. 3(C).

[0064] In FIG. 3(B), the case where the back gate electrode 111 covers the entire oxide semiconductor film 108 is illustrated, but the present invention is not limited to this configuration. The back gate electrode 111 In FIG. 3(B), the case where the back gate electrode 111 covers the entire oxide semiconductor film 108 is illustrated, but the present invention is not limited to this configuration. The back gate electrode 111 , it is only necessary to overlap at least a part of the channel formation region included in the oxide semiconductor film 108. Yes.

[0065] The back gate electrode 111 may be in a floating state electrically insulated. Also, it may be in a state where a potential is applied. In the latter case, the back gate electrode 111 may be applied with the same potential as the gate electrode 101, or may be applied with a fixed potential such as ground. By controlling the height of the potential applied to the back gate electrode 111, the threshold voltage of the transistor 110 can be controlled.

[0066] As in this embodiment, removing impurities such as hydrogen and water contained in the oxide semiconductor film as much as possible, how does purifying the oxide semiconductor film affect the characteristics of the transistor? will be described below.

[0067] FIG. 27 shows a longitudinal sectional view of an inverted staggered thin film transistor using an oxide semiconductor. A gate oxide semiconductor film (OS) is provided on the electrode (GE) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon.

[0068] FIG. 28 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 27. FIG. 28(A) shows the case where the voltage between the source electrode and the drain electrode is set to an equipotential (VD = 0V), and FIG. 28(B) shows the case where a positive potential (VD>0) is applied to the drain electrode with respect to the source electrode. Case.

[0069] FIG. 29 is an energy band diagram (schematic diagram) in the B-B' cross section in FIG. 27. . FIG. 29(A) shows a state where a positive potential (+VG) is applied to the gate (GE), and the source It shows an on state in which carriers (electrons) flow between the source electrode and the drain electrode. Also, FIG. 29 (B) shows a state where a negative potential (-VG) is applied to the gate (G1), and it is an off state (few carriers flow).

[0070] FIG. 30 shows the relationship between the vacuum level, the work function of the metal (φM), and the electron affinity of the oxide semiconductor (χ). is shown.

[0071] Since the metal is degenerate, the conduction band and the Fermi level coincide. On the other hand, conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (Ef) is located away from the intrinsic Fermi level (Ei) located at the center of the bandgap and is located closer to the conduction band (Ec). Note that hydrogen is a donor in the oxide semiconductor, and it is known that this is one of the factors for the oxide semiconductor to become n-type.

[0072] In contrast, the oxide semiconductor according to the present invention uses a metal having an electronegativity lower than that of hydrogen as a source electrode or a conductive film for the drain electrode, thereby removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to a high purity so that impurities other than the main component of the oxide semiconductor are not contained as much as possible. That is, instead of adding impurities to make the oxide semiconductor i-type, impurities such as hydrogen and water are removed as much as possible and purified to a high purity, thereby obtaining an oxide semiconductor that is as close as possible to i-type (intrinsic semiconductor) or i-type (intrinsic semiconductor). As described above, with the above configuration, as shown by the arrow, the Fermi level (Ef) can be made as close as possible to the same level as the intrinsic Fermi level (Ei).

[0073] ​​​​When the band gap (Eg) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is said to be 4.3 eV. The work function of titanium (Ti) constituting the source electrode and the drain electrode is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons.

[0074] That is, when the work function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor, when the two come into contact, an energy band diagram (schematic diagram) as shown in Fig. 28(A) is shown.

[0075] In Fig. 28(B), the black circles (●) represent electrons. When a positive potential is applied to the drain electrode , the electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain electrode . In this case, the height of the barrier (h) changes depending on the gate voltage and the drain voltage, but when a positive drain voltage is applied, the height of the barrier in Fig. 28(A) without voltage application , that is, the height (h) of the barrier is smaller than 1 / 2 of the band gap (Eg).

[0076] At this time, the electrons move to the lowest energy-stable part on the oxide semiconductor side at the interface between the gate insulating film and the highly purified oxide semiconductor as shown in Fig. 29(A).

[0077] Also, in Fig. 29(B), when a negative potential (reverse bias) is applied to the gate electrode (G1) , since the number of minority carriers, holes, is substantially zero, the current becomes a value approaching zero .

[0078] For example, an element with a channel width W of 1×10 4 μm and a channel length of 3 μm Even if it is, the off-current is 10 -13 A or less, and a subthreshold swing value (S value ) of 0.1 V / dec. (gate insulating film thickness: 100 nm) can be obtained.

[0079] In this way, by minimizing the inclusion of impurities such as water and hydrogen other than the main component of the oxide semiconductor, purifying the oxide semiconductor film to a high purity enables the thin film transistor to operate well.

[0080] (Embodiment 2) Taking a bottom gate type thin film transistor with a channel etch structure as an example, the manufacturing method of the semiconductor device will be described with reference to FIG. 4.

[0081] First, according to the manufacturing method shown in Embodiment 1, as shown in FIG. 4(A), on the island-shaped oxide semiconductor film 104, a conductive film 105a made of a metal material such as titanium, tungsten or molybdenum with low contact resistance to the oxide semiconductor film 104, a conductive film 105b made of a metal, metal compound or alloy with low electronegativity is formed. Regarding the types of materials, structures, and the range of their film thicknesses used for the conductive film 105a and the conductive film 105b, they have already been described in Embodiment 1, so the description is omitted here. In this embodiment, as the conductive film 105a, a titanium film with a thickness of 100 nm formed by sputtering is used, and as the conductive film 105b, an aluminum film with a thickness of 200 nm formed by sputtering is used.

[0082] After forming the conductive film 105a and the conductive film 105b, with the conductive film 105b exposed, in a reduced pressure atmosphere, in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), ​​​Heat treatment may be performed. The temperature range of the heat treatment is 200°C to 450°C, similar to that in Embodiment 1. up to 450°C.

[0083] Next, as shown in FIG. 4(B), the conductive film 105b is removed by etching or the like. For the above-mentioned etching, wet etching is preferably used to prevent the conductive film 105a from being etched. Specifically, in this embodiment, since an aluminum film is used for the conductive film 105b, a solution containing phosphoric acid, for example, a mixed acid aluminum solution manufactured by Wako Pure Chemical Industries, Ltd. ( an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) is used for wet etching to remove the conductive film 105b. When dry etching is used to remove the conductive film 105b, a gas containing chlorine (Cl ), boron chloride (BCl 3 ), etc. may be used. However, in the case of dry etching, since there is no difference in the selectivity ratio between the titanium film conductive film 105a and the aluminum film conductive film 105b, the dry etching time may be controlled so that the conductive film 105a remains during etching. 2 3 ) and the like may be used. However, in the case of dry etching, since there is no difference in the selectivity ratio between the titanium film conductive film 105a and the aluminum film conductive film 105b, the dry etching time may be controlled so that the conductive film 105a remains during etching. That is, it is sufficient to control the dry etching time so that the conductive film 105a remains during etching. That's all.

[0084] In the conductive film 105b, impurities such as moisture or hydrogen existing inside the oxide semiconductor film 104, inside the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof are occluded or adsorbed. Therefore, by removing the conductive film 105b, the moisture or impurities such as hydrogen occluded or adsorbed in the conductive film 10 5b can also be removed together. 5b can also be removed together. 5b can also be removed together. That's all.

[0085] Next, as shown in FIG. 4(C), a metal or metallization with a low electronegativity is formed on the conductive film 105a. The conductive film 105c is newly formed using a compound or an alloy. The type of material and the range of the thickness are the same as those of the conductive film 105b. The conductive film 105c is an aluminum film having a thickness of 200 nm formed by sputtering. .

[0086] In one embodiment of the present invention, after removing the conductive film 105b, a metal or a metal compound having low electronegativity is The conductive film 105c is newly formed using a material or alloy. impurities such as moisture or hydrogen are absorbed or adsorbed in the conductive film 105b. Therefore, the oxide semiconductor film 104 and the gate insulating film 102 Alternatively, the impurities present at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof are removed. Therefore, impurities such as moisture and hydrogen can be prevented from being generated. By removing the impurities, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is almost i-type is obtained. The above impurities can cause degradation of transistor characteristics, such as a shift in threshold voltage. This can prevent the promotion of the off-state current and reduce the off-state current.

[0087] After the conductive film 105c is formed, the conductive film 105c is exposed. In a state where the conductive film 105c is exposed, the conductive film 105c is irradiated with nitrogen under a reduced pressure atmosphere. Or heat treatment again under an inert gas atmosphere such as rare gas (argon, helium, etc.) The temperature range of the heat treatment is 200° C. to 450° C., as in the first embodiment. By performing the heat treatment, the oxide semiconductor film 104, the gate insulating film 102, Alternatively, moisture or the like that exists at or near the interface between the oxide semiconductor film 104 and another insulating film may be present. Impurities such as hydrogen can be easily absorbed or adsorbed by the conductive film 105c. .

[0088] Next, as shown in FIG. 4(D), by processing (patterning) the conductive film 105a and the conductive film 105 c into a desired shape, the source electrode 126 and the drain electrode 1 27 are formed. For example, when a titanium film is used for the conductive film 105a and an aluminum film is used for the conductive film 105c after wet-etching the conductive film 105c using a solution containing phosphoric acid the conductive film 105a may be wet-etched using a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, for ammonia peroxide specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5: 2:2 is used. Alternatively, the conductive film 105a and the conductive film 105c may be dry-etched using a gas containing chlorine (Cl 2 ), boron chloride (BCl 3 ), etc. .

[0089] When forming the source electrode 126 and the drain electrode 127 by the above patterning, a groove portion (recess) may be formed by partially etching the exposed portion of the island-shaped oxide semiconductor film 104. In this embodiment, a case where an island-shaped oxide semiconductor film 128 having a groove portion (recess) is formed by the above etching is exemplified. The conductive film 105a used for a part of the source electrode 126 and the drain electrode 127 is in contact with the oxide semiconductor film 128 . And, as described above, the conductive film 105a is in contact with the oxide semiconductor film 128 . . . And, in addition, the conductive film 105a has contact with the oxide semiconductor film 128 as described above Since a metal material with low resistance is used, the source electrode 126, the drain electrode 127, The contact resistance with the oxide semiconductor film 128 is reduced. The current and field effect mobility can be increased.

[0090] After the source electrode 126 and the drain electrode 127 are formed, An insulating film 129 is formed so as to cover the drain electrode 127 and the oxide semiconductor film 128. The type of material used for the film 129, the structure, and the range of the film thickness are described in the first embodiment. In this embodiment, the insulating film 109 is formed by sputtering to a thickness of 20 A silicon nitride film with a thickness of 100 nm was formed by sputtering on a silicon oxide film with a thickness of 0 nm. The substrate temperature during the film formation is set to a value not lower than room temperature and not higher than 300° C. In this embodiment, it is set to 100° C.

[0091] Exposure of the oxide semiconductor film 128 provided between the source electrode 126 or the drain electrode 127 The region is provided in contact with the silicon oxide constituting the insulating film 129, A region of the oxide semiconductor film 128 in contact with the oxide semiconductor film 29 has a high resistance (a low carrier concentration, preferably is 1×10 18 / cm 3 and an oxide semiconductor having a highly resistive channel formation region. A membrane 128 may be formed.

[0092] After the insulating film 129 is formed, heat treatment may be performed. The conditions for the heat treatment are as follows: In the first embodiment, the conditions of the heat treatment performed after the insulating film 109 is formed are referred to. Good.

[0093] The thin film transistor 120 formed according to the above manufacturing method includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 128 on the gate insulating film 102, a source electrode 126 and a drain electrode 127 on the oxide semiconductor film 128, and an insulating film 129 on the source electrode 126, the drain electrode 127, and the oxide semiconductor film 128.

[0094] Next, after forming a conductive film on the insulating film 129, the conductive film may be patterned to form a back gate electrode at a position overlapping the oxide semiconductor film 128. The type, structure, and thickness range of the material used for the back gate electrode are the same as those of the back gate electrode 111 described in Embodiment 1, so the description is omitted here.

[0095] When the back gate electrode is formed, an insulating film is formed so as to cover the back gate electrode. The type, structure, and thickness range of the material used for the insulating film covering the back gate electrode are the same as those of the insulating film 112 described in Embodiment 1, so the description is omitted here.

[0096] This embodiment can be implemented in appropriate combination with the above embodiments.

[0097] (Embodiment 3) Taking a bottom gate type thin film transistor with a channel etch structure as an example, the manufacturing method of the semiconductor device will be described with reference to FIG. 5.

[0098] First, according to the manufacturing method shown in Embodiment 1, as shown in FIG. 5(A), on an island-shaped oxide semiconductor film 104, on a conductive film 105a made of a metal material such as titanium, tungsten, or molybdenum having a low contact resistance with the oxide semiconductor film 104, a metal with a low electronegativity such as gold A conductive film 105b is formed using a metal, metal compound, or alloy. Regarding the type of material, structure, and film thickness range used for the conductive film 105a and the conductive film 105b, since they are already described in Embodiment 1, the description is omitted here. In this embodiment, as the conductive film 105a, a titanium film with a thickness of 100 nm formed by sputtering is used, and as the conductive film 105b, an aluminum film with a thickness of 200 nm formed by sputtering is used. After forming the conductive film 105a and the conductive film 105b, with the conductive film 105b exposed, under a reduced pressure

[0099] atmosphere, heat treatment may be performed in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium). The temperature range of the heat treatment is the same as in Embodiment 1, from 200 °C to 450 °C. Then, as shown in FIG. 5(B), the conductive film 105b is removed by etching or the like. For the above-mentioned

[0100] etching, in order to prevent the conductive film 105a from being etched, it is desirable to use wet etching. Specifically, in this embodiment, since an aluminum film is used for the conductive film 105b, a solution containing phosphoric acid, for example, a mixed acid aluminum solution manufactured by Wako Pure Chemical Industries, Ltd. ([[]]END]] an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) is used for wet etching to remove the conductive film 105b. When dry etching is used to remove the conductive film 105b, a gas containing chlorine (Cl[[[]]END]] 2 ), boron chloride (BCl[[[]]END]] 3 2 ) or the like may be used. However, in the case of dry etching, since there is no difference in the selectivity ratio between the titanium film which is the conductive film 105a and the aluminum film which is the conductive film 105b, the The dry etching time may be controlled so that the conductive film 105a remains during etching. That's all.

[0101] In the conductive film 105b, moisture, impurities such as hydrogen, are occluded or adsorbed in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof. Therefore, by removing the conductive film 105b, the moisture or impurities such as hydrogen occluded or adsorbed in the conductive film 105b can also be removed together. That's all. Next, as shown in FIG. 5(C), a conductive film 105c made of a metal, metallized compound or alloy having a low electronegativity and a conductive film 105d made of a metal material such as titanium, tungsten or molybdenum that can prevent oxidation of the conductive film 105c are newly formed on the conductive film 105a. The type of material used for the conductive film 105c and the range of its film thickness are the same as those of the conductive film 105b. Also, the film thickness of the conductive film 105d is desirably 10 nm to 200 nm, preferably 50 nm to 150 nm. In the present embodiment, an aluminum film with a film thickness of 200 nm formed by a sputtering method is used as the conductive film 105c, and a titanium film with a film thickness of 100 nm formed by a sputtering method is used as the conductive film 105d. That's all. That's all.

[0102] Next, as shown in FIG. 5(C), a conductive film 105c made of a metal, metallized compound or alloy having a low electronegativity and a conductive film 105d made of a metal material such as titanium, tungsten or molybdenum that can prevent oxidation of the conductive film 105c are newly formed on the conductive film 105a. The type of material used for the conductive film 105c and the range of its film thickness are the same as those of the conductive film 105b. Also, the film thickness of the conductive film 105d is desirably 10 nm to 200 nm, preferably 50 nm to 150 nm. In the present embodiment, an aluminum film with a film thickness of 200 nm formed by a sputtering method is used as the conductive film 105c, and a titanium film with a film thickness of 100 nm formed by a sputtering method is used as the conductive film 105d. That's all. That's all. The type of material used for the conductive film 105c and the range of its film thickness are the same as those of the conductive film 105b. Also, the film thickness of the conductive film 105d is desirably 10 nm to 200 nm, preferably 50 nm to 150 nm. In the present embodiment, an aluminum film with a film thickness of 200 nm formed by a sputtering method is used as the conductive film 105c, and a titanium film with a film thickness of 100 nm formed by a sputtering method is used as the conductive film 105d. That's all. That's all. That's all. That's all.

[0103] In one aspect of the present invention, after removing the conductive film 105b, a new conductive film 105c is formed using a metal, metallized compound or alloy having a low electronegativity. The conductive film 105c is more likely to occlude or adsorb moisture or impurities such as hydrogen than the conductive film 105b that already has impurities occluded or adsorbed. Therefore, in the oxide semiconductor film 104, in the gate insulating film 102 That's all. That's all. That's all. , or the impurities present at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof can be reduced more than in the case of Embodiment 1. Therefore, by desorbing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is extremely close to the i-type can be obtained, preventing deterioration of transistor characteristics such as threshold voltage shift caused by the above impurities, and reducing the off-current.

[0104] After forming the conductive film 105d, in a state where the conductive film 105d is exposed, heat treatment may be performed again in a reduced-pressure atmosphere or an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). The temperature range of the heat treatment is 200°C to 450°C, similar to Embodiment 1. By performing the above heat treatment, moisture or impurities such as hydrogen present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof can be more easily occluded or adsorbed by the conductive film 105c.

[0105] Next, as shown in FIG. 5(D), by processing (patterning) the conductive films 105a, 105c, and 105d into a desired shape by etching or the like, the source electrode 136 and the drain electrode 137 are formed. For example, when a titanium film is used for the conductive film 105a, an aluminum film is used for the conductive film 105c, and a titanium film is used for the conductive film 105d, after wet-etching the conductive film 105d using a solution containing ammonia and hydrogen peroxide water (ammonia peroxide), the conductive film 105c is wet-etched using a solution containing phosphoric acid, and then the conductive film 105a is wet-etched using a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). ​ Specifically, in this embodiment, the solution containing phosphoric acid is Wako Pure Chemical Industries, Ltd. Aluminum mixed acid solution (2.0% by weight of nitric acid, 9.8% by weight of acetic acid, 72.3% by weight of % by weight of phosphoric acid) is used. 31% hydrogen peroxide, 28% ammonia and water were mixed in a volume ratio of 5:2:2. Alternatively, use a mixed aqueous solution of chlorine (Cl 2 ), boron chloride (BCl 3 ) and other gases The conductive film 105a, the conductive film 105c, and the conductive film 105d are dry-etched using is also good.

[0106] When the source electrode 136 and the drain electrode 137 are formed by the above patterning, island-like The exposed portion of the oxide semiconductor film 104 is partially etched to form a groove (a recess). In this embodiment, an island having a groove (recess) is formed by the above etching. In the example shown, the oxide semiconductor film 138 having a source electrode 136 and a drain electrode 137 is formed. The conductive film 105a used as a part of the electrode 137 is in contact with the oxide semiconductor film 138. In addition, the conductive film 105a has a low contact resistance with the oxide semiconductor film as described above. Since a low-temperature metal material is used, the source electrode 136, the drain electrode 137, and the oxide The contact resistance with the semiconductor film 138 is reduced. The field effect mobility can be increased.

[0107] After the source electrode 136 and the drain electrode 137 are formed, An insulating film 139 is formed so as to cover the drain electrode 137 and the oxide semiconductor film 138. Regarding the type, structure, and thickness range of the material used for the film 139, it is the same as the insulating film 109 described in Embodiment 1. In this embodiment, a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering. An insulating film 139 having such a structure is formed. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is 100°C. The exposed region of the oxide semiconductor film 138 provided between the source electrode 136 or the drain electrode 137 is provided in contact with the silicon oxide constituting the insulating film 139, so that oxygen is supplied to the region of the oxide semiconductor film 138 in contact with the insulating film 139, resulting in an increase in resistance (a decrease in carrier concentration, preferably less than 1×10 / cm), and an oxide semiconductor film 138 having a channel formation region with increased resistance can be formed. After forming the insulating film 139, a heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1. The thin film transistor 130 formed according to the above manufacturing method has a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 138 on the gate insulating film 102, a source electrode 136 and a drain electrode 137 on the oxide semiconductor film 138, and an insulating film 139 on the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138. Next, after forming a conductive film on the insulating film 139, the conductive film is patterned to form a source electrode 136 and a drain electrode 137.

[0108] The exposed region of the oxide semiconductor film 138 provided between the source electrode 136 or the drain electrode 137 is provided in contact with the silicon oxide constituting the insulating film 139, so that oxygen is supplied to the region of the oxide semiconductor film 138 in contact with the insulating film 139, resulting in an increase in resistance (a decrease in carrier concentration, preferably less than 1×10 / cm), and an oxide semiconductor film 138 having a channel formation region with increased resistance can be formed. After forming the insulating film 139, a heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1. The thin film transistor 130 formed according to the above manufacturing method has a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 138 on the gate insulating film 102, a source electrode 136 and a drain electrode 137 on the oxide semiconductor film 138, and an insulating film 139 on the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138. Next, after forming a conductive film on the insulating film 139, the conductive film is patterned to form a source electrode 136 and a drain electrode 137. 18 / cm 3 The exposed region of the oxide semiconductor film 138 provided between the source electrode 136 or the drain electrode 137 is provided in contact with the silicon oxide constituting the insulating film 139, so that oxygen is supplied to the region of the oxide semiconductor film 138 in contact with the insulating film 139, resulting in an increase in resistance (a decrease in carrier concentration, preferably less than 1×10 / cm), and an oxide semiconductor film 138 having a channel formation region with increased resistance can be formed. After forming the insulating film 139, a heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1.

[0109] After forming the insulating film 139, a heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1. After forming the insulating film 139, a heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1.

[0110] The thin film transistor 130 formed according to the above manufacturing method has a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 138 on the gate insulating film 102, a source electrode 136 and a drain electrode 137 on the oxide semiconductor film 138, and an insulating film 139 on the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138. The thin film transistor 130 formed according to the above manufacturing method has a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 138 on the gate insulating film 102, a source electrode 136 and a drain electrode 137 on the oxide semiconductor film 138, and an insulating film 139 on the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138. The thin film transistor 130 formed according to the above manufacturing method has a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 138 on the gate insulating film 102, a source electrode 136 and a drain electrode 137 on the oxide semiconductor film 138, and an insulating film 139 on the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138. The thin film transistor 130 formed according to the above manufacturing method has a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 138 on the gate insulating film 102, a source electrode 136 and a drain electrode 137 on the oxide semiconductor film 138, and an insulating film 139 on the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138.

[0111] Next, after forming a conductive film on the insulating film 139, the conductive film is patterned to form a source electrode 136 and a drain electrode 137. A back gate electrode may be formed at a position overlapping with the oxide semiconductor film 138. Regarding the type, structure, and thickness range of the material used for the back gate electrode, since it is the same as the back gate electrode 111 described in Embodiment 1, the description is omitted here.

[0112] When the back gate electrode is formed, an insulating film is formed so as to cover the back gate electrode. Regarding the type, structure, and thickness range of the material used for the insulating film covering the back gate electrode, since it is the same as the insulating film 112 described in Embodiment 1, the description is omitted here.

[0113] This embodiment can be implemented in appropriate combination with the above-described embodiments.

[0114] (Embodiment 4) Taking a bottom gate type thin film transistor having a channel etch structure as an example, a method for manufacturing a semiconductor device will be described with reference to FIG. 6.

[0115] First, according to the manufacturing method shown in Embodiment 1, as shown in FIG. 6(A), on the island-shaped oxide semiconductor film 104, a conductive film 105a made of a metal material such as titanium, tungsten, or molybdenum having a low contact resistance with the oxide semiconductor film 104, and a conductive film 105b made of a metal, metal compound, or alloy having a low electronegativity are formed. Regarding the type, structure, and thickness range of the material used for the conductive film 105a and the conductive film 105b, since they have already been described in Embodiment 1, the description is omitted here. In this embodiment, as the conductive film 105a, a titanium film having a thickness of 100 nm formed by sputtering is used, and as the conductive film 105b, an aluminum film having a thickness of 200 nm formed by sputtering is used.

[0116] After forming the conductive film 105a and the conductive film 105b, in a state where the conductive film 105b is exposed, under reduced pressure atmosphere, heat treatment may be performed in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.). The temperature range of the heat treatment is 200°C to 450°C, similar to that in Embodiment 1.

[0117] Next, as shown in FIG. 6(B), the conductive film 105b is removed by etching or the like. In order to prevent the conductive film 105a from being etched during the above-mentioned etching, it is desirable to use wet etching. Specifically, in this embodiment, since an aluminum film is used for the conductive film 105b, a solution containing phosphoric acid, for example, a mixed acid aluminum solution manufactured by Wako Pure Chemical Industries, Ltd. (an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) is used for wet etching to remove the conductive film 105b. When dry etching is used to remove the conductive film 105b, a gas containing chlorine (Cl 2 3 ) or boron chloride (BCl ) etc. may be used. However, in the case of dry etching, since there is no difference in the selectivity ratio between the conductive film 105a which is a titanium film and the conductive film 105b which is an aluminum film, the dry etching time may be controlled so that the conductive film 105a remains during etching. 3 ) etc. may be used. However, in the case of dry etching, since there is no difference in the selectivity ratio between the conductive film 105a which is a titanium film and the conductive film 105b which is an aluminum film, the dry etching time may be controlled so that the conductive film 105a remains during etching. conductive film 105a and the conductive film 105b which is an aluminum film, the dry etching time may be controlled so that the conductive film 105a remains during etching. That's all right. Yes.

[0118] In the conductive film 105b, impurities such as moisture or hydrogen are occluded or adsorbed, which exist inside the oxide semiconductor film 104, inside the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof. Therefore, by removing the conductive film 105b, the conductive film 1 By removing the conductive film 105b, the conductive film 1 It is also possible to remove impurities such as moisture and hydrogen that are absorbed or adsorbed in 05b. can.

[0119] Next, as shown in FIG. 6C, a conductive film 105a having a contact with the oxide semiconductor film 104 is Conductive film 105 made of a metal material such as titanium, tungsten, or molybdenum with low resistance e, a conductive film 105c using a metal, a metal compound, or an alloy with low electronegativity, and a conductive film Metallic materials such as titanium, tungsten or molybdenum that can prevent oxidation of 105c The conductive film 105d is newly formed using the conductive material. The range of the thickness is the same as that of the conductive film 105a. The thickness range of the conductive film 105c is the same as that of the conductive film 105b. An aluminum film having a thickness of 200 nm formed by sputtering was used as the conductive film 105. A titanium film having a thickness of 100 nm formed by sputtering is used as the conductive film 105e. A titanium film having a thickness of 100 nm formed by sputtering is used.

[0120] In one embodiment of the present invention, after removing the conductive film 105b, a metal or a metal compound having low electronegativity is The conductive film 105c is newly formed using a material or alloy. impurities such as moisture or hydrogen are absorbed or adsorbed in the conductive film 105b. Therefore, the oxide semiconductor film 104 and the gate insulating film 102 Alternatively, the impurities present at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof are removed. Therefore, impurities such as moisture and hydrogen can be prevented from being generated. By removing the impurities, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is almost i-type is obtained. can be achieved, and deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced.

[0121] After forming the conductive film 105d, in a state where the conductive film 105d is exposed, under a reduced-pressure atmosphere, in an inert gas atmosphere of nitrogen, or a rare gas (such as argon or helium), heat treatment may be performed again. The temperature range of the heat treatment is 200°C to 450°C, similar to Embodiment 1 shall be. By performing the above heat treatment, moisture or hydrogen and other impurities present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof can be easily occluded or adsorbed by the conductive film 105c .

[0122] Next, as shown in FIG. 6(D), by processing (patterning) the conductive film 105a, the conductive film 105c , the conductive film 105d, and the conductive film 105e into a desired shape, the source electrode 146 and the drain electrode 147 are formed. For example, a titanium film is formed on the conductive film 105a , an aluminum film is formed on the conductive film 105c, a titanium film is formed on the conductive film 105d, and a titanium film is used for the conductive film 105e. When using a solution containing ammonia and hydrogen peroxide (ammonia peroxide) to wet-etch the conductive film 105d, and then using a solution containing phosphoric acid to wet-etch the conductive film 105 c, and then using a solution containing ammonia and hydrogen peroxide (ammonia peroxide) to wet-etch the conductive film 105e and the conductive film 105a. Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid A manufactured by Wako Pure Chemical Industries, Ltd. Use a lumi solution (an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid). Also, specifically for the aqueous ammonia peroxide, use an aqueous solution prepared by mixing 31 wt% hydrogen peroxide water, 28 wt% aqueous ammonia, and water in a volume ratio of 5:2:2 ). Alternatively, a gas containing chlorine (Cl ), boron chloride (BCl ), etc. can be used to dry-etch the conductive films 10 2 5a, the conductive film 105c, the conductive film 105d, and the conductive film 105e 3 ). When forming the source electrode 146 and the drain electrode 147 by the above patterning, a groove portion (recess) may be formed by partially etching the exposed portion of the island-shaped oxide semiconductor film 104. In this embodiment, a case where an island-shaped oxide semiconductor film 148 having a groove portion (recess) is formed by the above etching is exemplified. The conductive film 105a used for a part of the source electrode 146 and the drain electrode 147 is in contact with the oxide semiconductor film 148 . And since a metal material having a low contact resistance with the oxide semiconductor film 148 as described above is used for the conductive film 105a, the contact resistance between the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased

[0123] . . After forming the source electrode 146 and the drain electrode 147, an insulating film 149 is formed so as to cover the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148. Regarding the type of material, the structure, and the range of the film thickness of the insulating film 149, refer to Embodiment 1 . . . . . . .

[0124] . . . In this embodiment, the insulating film 109 is formed by sputtering to a thickness of 20 A silicon nitride film with a thickness of 100 nm was formed by sputtering on a silicon oxide film with a thickness of 0 nm. The substrate temperature during the film formation is set to a value not lower than room temperature and not higher than 300° C. In this embodiment, it is set to 100° C.

[0125] Exposure of the oxide semiconductor film 148 provided between the source electrode 146 or the drain electrode 147 The region is provided in contact with the silicon oxide constituting the insulating film 149, Oxygen is supplied to a region of the oxide semiconductor film 148 in contact with the oxide semiconductor film 49, and the region becomes highly resistive (the carrier concentration is Lower, preferably 1×10 18 / cm 3 (less than 1000 nm) and has a highly resistive channel formation region. In this way, the oxide semiconductor film 148 can be formed.

[0126] After the insulating film 149 is formed, heat treatment may be performed. The conditions for the heat treatment are as follows: In the first embodiment, the conditions of the heat treatment performed after the insulating film 109 is formed are referred to. Good.

[0127] The thin film transistor 140 formed according to the above-mentioned manufacturing method includes a gate electrode 101 and a gate A gate insulating film 102 on the gate electrode 101 and an oxide semiconductor film 148 on the gate insulating film 102 a source electrode 146 and a drain electrode 147 on the oxide semiconductor film 148; 146 , a drain electrode 147 , and an insulating film 149 over an oxide semiconductor film 148 .

[0128] Next, a conductive film is formed over the insulating film 149, and then the conductive film is patterned to form an oxide film. A back gate electrode may be formed at a position overlapping the nitride semiconductor film 148. Regarding the types, structures, and thickness ranges of the materials extremely used, they are the same as those of the back gate electrode 111 described in Embodiment 1, so the description is omitted here.

[0129] When forming the back gate electrode, an insulating film is formed so as to cover the back gate electrode. Regarding the types, structures, and thickness ranges of the materials used for the insulating film covering the back gate electrode, they are the same as those of the insulating film 112 described in Embodiment 1, so the description is omitted here.

[0130] This embodiment can be implemented in appropriate combination with the above embodiments.

[0131] (Embodiment 5) In this embodiment, a bottom gate type thin film transistor of a channel protection structure is taken as an example, and a method for manufacturing a semiconductor device will be described with reference to FIGS. 7, 8, and 9. Note that the same parts or parts having the same functions as those in Embodiment 1, and the processes can be performed in the same manner as in Embodiment 1, so repeated descriptions are omitted.

[0132] As shown in FIG. 7(A), a gate electrode 301 is formed on a substrate 300 having an insulating surface. An insulating film serving as an underlayer film may be provided between the substrate 300 and the gate electrode 301. Regarding the material, structure, and thickness of the gate electrode 301, reference may be made to the description of the gate electrode 301 shown in Embodiment 1. Regarding the material, structure, and thickness of the underlayer film, reference may be made to the description of the underlayer film shown in Embodiment 1.

[0133] Next, a gate insulating film 302 is formed on the gate electrode 301. Regarding the material, thickness, and structure of the gate insulating film 302, and the manufacturing method, reference may be made to the gate insulating film 302 shown in Embodiment 1. ​ Refer to the following description.

[0134] Next, an island-shaped oxide semiconductor film 303 is formed on the gate insulating film 302. For the material, film thickness, structure, and manufacturing method of the island-shaped oxide semiconductor film 303, refer to the description of the oxide semiconductor film 103 shown in Embodiment 1. semiconductor film 303, refer to the description of the oxide semiconductor film 103 shown in Embodiment 1. Refer to the following description.

[0135] Next, in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm or less (dew point conversion of -55 °C), preferably 1 ppm or less, preferably 10 ppb or less), the island-shaped oxide semiconductor film 303 is heat-treated. For the heat treatment of the oxide semiconductor film 303, refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. or air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm or less (dew point conversion of -55 °C), preferably 1 ppm or less, preferably 10 ppb or less), the island-shaped oxide semiconductor film 303 is heat-treated. For the heat treatment of the oxide semiconductor film 303, refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. m or less, preferably 10 ppb or less), the island-shaped oxide semiconductor film 303 is heat-treated. For the heat treatment of the oxide semiconductor film 303, refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. m or less, preferably 10 ppb or less), the island-shaped oxide semiconductor film 303 is heat-treated. For the heat treatment of the oxide semiconductor film 303, refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. 03 is heat-treated. For the heat treatment of the oxide semiconductor film 303, refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. Refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current. oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen by the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i, thus preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities and reducing the off-current.

[0136] Next, as shown in FIG. 7(C), a channel protection film 311 is formed on the oxide semiconductor film 304 so as to overlap with the portion that becomes the channel formation region of the oxide semiconductor film 304. Next, as shown in FIG. 7(C), a channel protection film 311 is formed on the oxide semiconductor film 304 so as to overlap with the portion that becomes the channel formation region of the oxide semiconductor film 304. By providing the protective film 311, damage (such as film loss due to plasma or etching agent during etching) to the portion that will become the channel formation region of the oxide semiconductor film 304 during subsequent processes can be prevented. Therefore, the reliability of the thin film transistor can be improved. For the portion that will become the channel formation region of the oxide semiconductor film 304, damage during subsequent processes (such as film loss due to plasma or etching agent during etching) can be prevented. Therefore, the reliability of the thin film transistor can be improved. For the portion that will become the channel formation region of the oxide semiconductor film 304, damage during subsequent processes (such as film loss due to plasma or etching agent during etching) can be prevented. Therefore, the reliability of the thin film transistor can be improved. For the portion that will become the channel formation region of the oxide semiconductor film 304, damage during subsequent processes (such as film loss due to plasma or etching agent during etching) can be prevented. Therefore, the reliability of the thin film transistor can be improved.

[0137] For the channel protective film 311, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. The channel protective film 311 can be formed using a vapor phase growth method such as plasma CVD method or thermal CVD method, or a sputtering method. The shape of the channel protective film 311 is processed by etching after film formation. Here, a silicon oxide film is formed by sputtering method, and the channel protective film 311 is formed by etching using a mask by photolithography. For the channel protective film 311, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. The channel protective film 311 can be formed using a vapor phase growth method such as plasma CVD method or thermal CVD method, or a sputtering method. The shape of the channel protective film 311 is processed by etching after film formation. Here, a silicon oxide film is formed by sputtering method, and the channel protective film 311 is formed by etching using a mask by photolithography. For the channel protective film 311, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. The channel protective film 311 can be formed using a vapor phase growth method such as plasma CVD method or thermal CVD method, or a sputtering method. The shape of the channel protective film 311 is processed by etching after film formation. Here, a silicon oxide film is formed by sputtering method, and the channel protective film 311 is formed by etching using a mask by photolithography. For the channel protective film 311, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. The channel protective film 311 can be formed using a vapor phase growth method such as plasma CVD method or thermal CVD method, or a sputtering method. The shape of the channel protective film 311 is processed by etching after film formation. Here, a silicon oxide film is formed by sputtering method, and the channel protective film 311 is formed by etching using a mask by photolithography. For the channel protective film 311, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. The channel protective film 311 can be formed using a vapor phase growth method such as plasma CVD method or thermal CVD method, or a sputtering method. The shape of the channel protective film 311 is processed by etching after film formation. Here, a silicon oxide film is formed by sputtering method, and the channel protective film 311 is formed by etching using a mask by photolithography. For the channel protective film 311, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. The channel protective film 311 can be formed using a vapor phase growth method such as plasma CVD method or thermal CVD method, or a sputtering method. The shape of the channel protective film 311 is processed by etching after film formation. Here, a silicon oxide film is formed by sputtering method, and the channel protective film 311 is formed by etching using a mask by photolithography.

[0138] Also, when a channel protective film 311, which is an insulating film such as silicon oxide or silicon oxynitride, is formed by sputtering method or PCVD method in contact with the island-shaped oxide semiconductor film 304, oxygen is supplied to at least the region in contact with the channel protective film 311 in the island-shaped oxide semiconductor film 304, and the carrier concentration preferably becomes lower than 1×10 Also, when a channel protective film 311, which is an insulating film such as silicon oxide or silicon oxynitride, is formed by sputtering method or PCVD method in contact with the island-shaped oxide semiconductor film 304, oxygen is supplied to at least the region in contact with the channel protective film 311 in the island-shaped oxide semiconductor film 304, and the carrier concentration preferably becomes lower than 1×10 Also, when a channel protective film 311, which is an insulating film such as silicon oxide or silicon oxynitride, is formed by sputtering method or PCVD method in contact with the island-shaped oxide semiconductor film 304, oxygen is supplied to at least the region in contact with the channel protective film 311 in the island-shaped oxide semiconductor film 304, and the carrier concentration preferably becomes lower than 1×10 Also, when a channel protective film 311, which is an insulating film such as silicon oxide or silicon oxynitride, is formed by sputtering method or PCVD method in contact with the island-shaped oxide semiconductor film 304, oxygen is supplied to at least the region in contact with the channel protective film 311 in the island-shaped oxide semiconductor film 304, and the carrier concentration preferably becomes lower than 1×10 18 / cm 3 / cm 1 4 / cm 3 / cm By forming the channel protective film 311, the oxide semiconductor film 304 can have a high-resistance oxide semiconductor region near the interface with the channel protective film 311. By forming the channel protective film 311, the oxide semiconductor film 304 can have a high-resistance oxide semiconductor region near the interface with the channel protective film 311.

[0139] Next, on the island-shaped oxide semiconductor film 304, a conductive film 305a made of a metal material such as titanium, tungsten, or molybdenum with low contact resistance to the oxide semiconductor film 304 and a conductive film 305b made of a metal, metal compound, or alloy with low electron negativity are formed in sequence. For the types, structures, film thickness ranges, and manufacturing methods of the materials used for the conductive film 305a and the conductive film 305b, refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. In this embodiment, as the conductive film 305a, a titanium film with a film thickness of 100 nm formed by sputtering is used, and as the conductive film 305b, an aluminum film with a film thickness of 200 nm formed by sputtering is used. In one aspect of the present invention, since a metal, metal compound, or alloy with low electron negativity is used as the conductive film 305b, moisture or impurities such as hydrogen present in the oxide semiconductor film 304, in the gate insulating film 302, or at the interface between the oxide semiconductor film 304 and other insulating films and in the vicinity thereof are occluded or adsorbed by the conductive film 305b. Therefore, by removing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 304 that is extremely close to the i-type can be obtained, preventing the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities, and reducing the off-current. After forming the conductive film 305a and the conductive film 305b, in a state where the conductive film 305b is exposed, heat treatment may be performed in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) under a reduced pressure atmosphere. The temperature range of the heat treatment is 200°C to 450°C, similar to Embodiment 1.

[0140]

[0141]

[0142] Next, as shown in FIG. 7(D), by processing (patterning) the conductive film 305a and the conductive film 305 b into a desired shape, the source electrode 306 and the drain electrode 3 07 are formed. For example, when a titanium film is used for the conductive film 305a and an aluminum film is used for the conductive film 305b After wet-etching the conductive film 305b using a solution containing phosphoric acid , a solution containing ammonia and hydrogen peroxide water (ammonia peroxide water) can be used to wet-etch the conductive film 305a . Specifically, in this embodiment, as the solution containing phosphoric acid, A mixed acid aluminum solution manufactured by Wako Pure Chemical Industries, Ltd. (an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid , and 72.3 wt% phosphoric acid) is used. Also, for ammonia peroxide water, Specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5: 2:2 is used. Alternatively, a gas containing chlorine (Cl 2 ), boron chloride (BCl 3 ), etc can be used to dry-etch the conductive film 305a and the conductive film 305b.

[0143] The conductive film 305a used for a part of the source electrode 306 and the drain electrode 307 is in contact with the oxide semiconductor film 304. And, as described above, since a metal material with low contact resistance with the oxide semiconductor film is used for the conductive film 305a , the contact resistance between the source electrode 306, the drain electrode 307, and the oxide semiconductor film 304 is reduced. Therefore , the on-current and the field-effect mobility of the TFT can be increased.

[0144] Then, as shown in FIG. 7(E), after forming the source electrode 306 and the drain electrode 307 includes an oxide semiconductor film 304, a source electrode 306, a drain electrode 307, and a channel protection film An insulating film 309 is formed so as to cover 311. The type of material used for the insulating film 309, its structure, and the range of its film thickness are the same as those of the insulating film 109 described in Embodiment 1. In this embodiment, an insulating film 309 having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering is formed . The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and is 1 00°C in this embodiment.

[0145] After forming the insulating film 309, a heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1 .

[0146] FIG. 8 shows a top view of the semiconductor device shown in FIG. 7(E). FIG. 7(E) corresponds to a cross-sectional view taken along the dashed line C1- C2 in FIG. 8.

[0147] The thin film transistor 310 formed according to the above manufacturing method includes a gate electrode 301, a gate insulating film 302 on the gate electrode 301, an oxide semiconductor film 304 on the gate insulating film 302 , a channel protection film 311 on the oxide semiconductor film 304, a source electrode 306 and a drain electrode 307 on the oxide semiconductor film 304 , and an insulating film 309 on the oxide semiconductor film 304, the source electrode 306, the drain electrode 307, and the channel protection film 311.

[0148] Next, as shown in FIG. 9(A), after forming a conductive film on the insulating film 309, the conductive film is patterned to form a back gate electrode 312 at a position overlapping the oxide semiconductor film 304. It may be formed. Regarding the type, structure, and film thickness range of the material used for the back gate electrode 312, since they are the same as those of the back gate electrode 111 described in Embodiment 1, the description is omitted here.

[0149] When the back gate electrode 312 is formed, as shown in FIG. 9(B), an insulating film 313 is formed to cover the back gate electrode 312. Regarding the type, structure, and film thickness range of the material used for the insulating film 313, since they are the same as those of the insulating film 112 described in Embodiment 1, the description is omitted here.

[0150] FIG. 9(C) shows a top view of the semiconductor device shown in FIG. 9(B). FIG. 9(B) corresponds to a cross-sectional view taken along the dashed line C1 - C2 in FIG. 9(C).

[0151] In this embodiment, an example is shown in which the source electrode and the drain electrode are formed according to the manufacturing method shown in Embodiment 1, but the present invention is not limited to this configuration. The source electrode and the drain electrode may be formed according to the manufacturing methods shown in Embodiments 2 to 4.

[0152] This embodiment can be implemented in appropriate combination with the above embodiments.

[0153] (Embodiment 6) In this embodiment, a bottom contact type thin film transistor is taken as an example, and the manufacturing method of the semiconductor device will be described with reference to FIGS. 10 and 11. Note that the same parts or parts having the same functions as those in Embodiment 1, and the steps can be performed in the same manner as in Embodiment 1, so repeated descriptions are omitted.

[0154] As shown in FIG. 10(A), a gate electrode 401 is formed on a substrate 400 having an insulating surface. An insulating film serving as an underlayer film may be provided between the substrate 400 and the gate electrode 401. Regarding the material, structure, and film thickness of the gate electrode 401, reference may be made to the description of the gate electrode 401 shown in Embodiment 1. Regarding the material, structure, and film thickness of the underlayer film, reference may be made to the description of the underlayer film shown in Embodiment 1. Next, a gate insulating film 402 is formed on the gate electrode 401. Regarding the material, film thickness, and structure of the gate insulating film 402, and the manufacturing method, reference may be made to the description of the gate insulating film 402 shown in Embodiment 1. Next, on the gate insulating film 402, a conductive film 405a made of a metal, metal compound, or alloy with a low electronegativity and a conductive film 405b made of a metal material such as titanium, tungsten, or molybdenum, which has a low contact resistance with the oxide semiconductor film 404, are sequentially formed. Regarding the types, structures, film thickness ranges, and manufacturing methods of the materials used for the conductive film 405b and the conductive film 405a, reference may be made to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. In this embodiment, as the conductive film 405a, an aluminum film with a film thickness of 200 nm formed by sputtering is used, and as the conductive film 405b, a titanium film with a film thickness of 100 nm formed by sputtering is used. After forming the conductive film 405a and the conductive film 405b, with the conductive film 405b exposed, in a reduced-pressure atmosphere or an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.).

[0155]

[0156]

[0157] ​​​​​​​​​​​​​​Heat treatment may be performed. The temperature range of the heat treatment is 200°C to 450°C, similar to that in Embodiment 1. For example, when an aluminum film is used for the conductive film 405a and a titanium film is used for the conductive film 405b, after wet-etching the conductive film 405b using a solution containing ammonia and hydrogen peroxide water (ammonia peroxide), the conductive film 405a may be wet-etched using a solution containing phosphoric acid. Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, for ammonia peroxide, specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5:2:2 is used. Alternatively, a gas containing chlorine (Cl) or boron chloride (BCl) may be used to dry-etch the conductive film 405a and the conductive film 405b. Next, as shown in FIG. 10(B), by processing (patterning) the conductive film 405a and the conductive film 405b into a desired shape by etching or the like, the source electrode 406 and the drain electrode 407 are formed. Next, as shown in FIG. 10(C), an island-shaped oxide semiconductor film 403 is formed on the gate insulating film 402, the source electrode 406, and the drain electrode 407. For the material, film thickness, structure, and manufacturing method of the island-shaped oxide semiconductor film 403, reference may be made to the description of the oxide semiconductor film 103 in Embodiment 1. 2 3

[0158]

[0159]

[0160]

[0160] ​​​​​​​​​​Next, in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or in an atmosphere of ultradry air (with a moisture content of 20 ppm or less (dew point equivalent to -55 °C), preferably 1 pp m or less, preferably 10 ppb or less of air) measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the island-shaped oxide semiconductor film 4 03 is heat-treated. For the heat treatment of the oxide semiconductor film 403, reference may be made to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 403 in the above atmosphere, as shown in FIG. 10(D), an island-shaped oxide semiconductor film 404 in which moisture and hydrogen contained in the oxide semiconductor film 403 are desorbed is formed. The island-shaped oxide semiconductor film 404 has impurities such as moisture and hydrogen desorbed by the above heat treatment, and becomes type i (intrinsic semiconductor) or extremely close to type i. Therefore, it is possible to prevent the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities, and reduce the off-current.

[0161] In one aspect of the present invention, since a metal, metal compound, or alloy with a low electronegativity is used as the conductive film 405a, impurities such as moisture or hydrogen present in the oxide semiconductor film 404, in the gate insulating film 402, or at and near the interface between the oxide semiconductor film 404 and another insulating film are occluded or adsorbed by the conductive film 405a. Therefore, it is possible to obtain an oxide semiconductor film 404 that is type i (intrinsic semiconductor) or extremely close to type i due to the desorption of impurities such as moisture and hydrogen, prevent the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities, and reduce the off-current.

[0162] In addition, the conductive film 405b used for a part of the source electrode 406 and the drain electrode 407 is in contact with the oxide semiconductor film 404. And since a metal material having a low contact resistance with the oxide semiconductor film as described above is used for the conductive film 405b, the contact resistance between the source electrode 4 06, the drain electrode 407, and the oxide semiconductor film 404 is reduced . Therefore, the on-current and the field-effect mobility of the TFT can be increased.

[0163] Next, as shown in FIG. 10(E), after forming the source electrode 406 and the drain electrode 407, an insulating film 409 is formed so as to cover the oxide semiconductor film 404, the source electrode 406, and the drain electrode 407. Regarding the type of material, the structure, and the range of the film thickness of the insulating film 409 used, it is the same as the insulating film 109 described in Embodiment 1. In this embodiment, an insulating film 409 having a structure in which a silicon nitride film with a thickness of 100 nm formed by a sputtering method is laminated on a silicon oxide film with a thickness of 200 nm formed by a sputtering method is formed. The substrate temperature during film formation may be from room temperature to 300°C or lower, and in this embodiment, it is 100°C. nm formed by a sputtering method is laminated on a silicon oxide film with a thickness of 200 nm formed by a sputtering method is formed. The substrate temperature during film formation may be from room temperature to 300°C or lower, and in this embodiment, it is 100°C.

[0164] After forming the insulating film 409, a heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1.

[0165] FIG. 11 shows a top view of the semiconductor device shown in FIG. 10(E). FIG. 10(E) corresponds to a cross-sectional view taken along the broken line B1 - B2 in FIG. 11.

[0166] The thin film transistor 410 formed according to the above manufacturing method includes a gate electrode 401 and a gate​​ A gate insulating film 402 on the top electrode 401, a source electrode 406 on the gate insulating film 402, and a drain electrode 407, and an oxide semiconductor film 404 on the gate insulating film 402, the source electrode 406, and the drain electrode 407 and an insulating film 409 on the oxide semiconductor film 404, the source electrode 406, and the drain electrode 407. It has.

[0167] Next, after forming a conductive film on the insulating film 409, the conductive film may be patterned to form a back gate electrode at a position overlapping the oxide semiconductor film 404. Regarding the type, structure, and thickness range of the material used for the back gate electrode, they are the same as those of the back gate electrode 111 described in Embodiment 1, so the description is omitted here. When forming the back gate electrode, an insulating film is formed so as to cover the back gate electrode. Regarding the type, structure, and thickness range of the material used for the above insulating film, they are the same as those of the insulating film 112 described in Embodiment 1, so the description is omitted here.

[0168] This embodiment can be implemented in appropriate combination with the above embodiment.

[0169]

[0170] (Embodiment 7) In this embodiment, a method for manufacturing a semiconductor display device according to an aspect of the present invention will be described with reference to FIGS. 12 to 17.

[0171] Note that in this specification, continuous film formation means that during a series of processes from the first film formation step performed by sputtering to the second film formation step performed by sputtering, the atmosphere in which the substrate to be processed is placed does not come into contact with a contaminated atmosphere such as air, and is always in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere). ​​​​​​​It is said that it is controlled in a gas atmosphere. By performing continuous film formation, reattachment of moisture and the like on the processed substrate can be avoided, and film formation can be performed. By performing continuous film formation, reattachment of moisture and the like on the processed substrate can be avoided, and film formation can be performed.

[0172] Performing a series of processes from the first film formation step to the second film formation step within the same chamber is considered to be within the scope of continuous film formation in this specification. Performing a series of processes from the first film formation step to the second film formation step within the same chamber is considered to be within the scope of continuous film formation in this specification.

[0173] Also, when performing a series of processes from the first film formation step to the second film formation step in different chambers, after completing the first film formation step, the substrate is transported between the chambers without being exposed to the atmosphere, and performing the second film formation is also considered to be within the scope of continuous film formation in this specification. Also, when performing a series of processes from the first film formation step to the second film formation step in different chambers, after completing the first film formation step, the substrate is transported between the chambers without being exposed to the atmosphere, and performing the second film formation is also considered to be within the scope of continuous film formation in this specification. Also, when performing a series of processes from the first film formation step to the second film formation step in different chambers, after completing the first film formation step, the substrate is transported between the chambers without being exposed to the atmosphere, and performing the second film formation is also considered to be within the scope of continuous film formation in this specification.

[0174] Note that between the first film formation step and the second film formation step, there may be a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc., and it is considered to be within the scope of continuous film formation in this specification. Note that between the first film formation step and the second film formation step, there may be a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc., and it is considered to be within the scope of continuous film formation in this specification. Note that between the first film formation step and the second film formation step, there may be a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc., and it is considered to be within the scope of continuous film formation in this specification.

[0175] However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as defined in this specification. However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as defined in this specification. However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as defined in this specification.

[0176] In FIG. 12(A), for the substrate 800 having translucency, in addition to a glass substrate produced by a fusion method or a float method, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless steel alloy may be applied. Also, a substrate made of a flexible synthetic resin such as plastic generally has a tendency of a low heat-resistant temperature, but if it can withstand the processing temperature in the subsequent manufacturing process, it can be used as the substrate 800. As the plastic substrate, polyethylene In FIG. 12(A), for the substrate 800 having translucency, in addition to a glass substrate produced by a fusion method or a float method, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless steel alloy may be applied. Also, a substrate made of a flexible synthetic resin such as plastic generally has a tendency of a low heat-resistant temperature, but if it can withstand the processing temperature in the subsequent manufacturing process, it can be used as the substrate 800. As the plastic substrate, polyethylene In FIG. 12(A), for the substrate 800 having translucency, in addition to a glass substrate produced by a fusion method or a float method, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless steel alloy may be applied. Also, a substrate made of a flexible synthetic resin such as plastic generally has a tendency of a low heat-resistant temperature, but if it can withstand the processing temperature in the subsequent manufacturing process, it can be used as the substrate 800. As the plastic substrate, polyethylene In FIG. 12(A), for the substrate 800 having translucency, in addition to a glass substrate produced by a fusion method or a float method, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless steel alloy may be applied. Also, a substrate made of a flexible synthetic resin such as plastic generally has a tendency of a low heat-resistant temperature, but if it can withstand the processing temperature in the subsequent manufacturing process, it can be used as the substrate 800. As the plastic substrate, polyethylene In FIG. 12(A), for the substrate 800 having translucency, in addition to a glass substrate produced by a fusion method or a float method, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless steel alloy may be applied. Also, a substrate made of a flexible synthetic resin such as plastic generally has a tendency of a low heat-resistant temperature, but if it can withstand the processing temperature in the subsequent manufacturing process, it can be used as the substrate 800. As the plastic substrate, polyethylene Polyesters represented by terephthalate (PET), polyethersulfone (PES) , polyethylene naphthalate (PEN), polycarbonate (PC), polyether ether ketone (PEEK), polysulfone (PSF), polyetherimide (PEI), poly arylate (PAR), polybutylene terephthalate (PBT), polyimide, acry lonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate , acrylic resin, and the like can be mentioned.

[0177] In addition, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use one with a strain point of 730 °C or higher . Further, as the glass substrate, for example, glass materials such as aluminosilicate glass, a luminoborosilicate glass, and barium borosilicate glass are used . By including more barium oxide (BaO) compared to boric acid, a more practical heat-resistant glass can be obtained.

[0178] In addition, instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used . In addition, crystallized glass or the like can be used.

[0179] Next, after forming a conductive film on the entire surface of the substrate 800, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wiring and electrodes (gate gate wiring including the gate electrode 801, capacitor wiring 822, and the first terminal 821). At this time, etching is performed so that a tapered shape is formed at least at the end of the gate electrode 801 .

[0180] As the material of the conductive film, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc., alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in layers. If it can withstand the temperature of the heat treatment performed in the subsequent process, aluminum and copper can also be used as the above metal materials. For example, as a conductive film having a two-layer laminated structure, a two-layer laminated structure in which molybdenum is laminated on aluminum, or a two-layer structure in which molybdenum is laminated on a copper layer, or a two-layer structure in which titanium nitride or tantalum nitride is laminated on copper, or a two-layer structure in which titanium nitride and molybdenum are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which aluminum, an alloy of aluminum and silicon, an alloy of aluminum and titanium, or an alloy of aluminum and neodymium is used as an intermediate layer, and tungsten, tungsten nitride, titanium nitride, or titanium is used as upper and lower layers. In addition, the aperture ratio can be improved by using an oxide conductive film having translucency for some electrodes and wirings. For example, indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, or gallium zinc oxide can be used for the oxide conductive film. The film thicknesses of the gate electrode 801, the capacitor wiring 822, and the first terminal 821 are 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, after forming a 100-nm conductive film for the gate electrode by sputtering using a tungsten target, the conductive

[0181]

[0182]

[0183] ​ By processing (patterning) the film into a desired shape by etching, the gate electrode 801 , the capacitor wiring 822, and the first terminal 821 are formed.

[0184] Note that an insulating film serving as an underlying film may be provided between the substrate 800 and the gate electrode 801, the capacitor wiring 822, and the first terminal 821. As the underlying film, for example, a silicon oxide film, a silicon oxynitride film , a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used either singly or as a stack of multiple layers. In particular, for the underlying film, an insulating film with high barrier properties, such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or also an aluminum oxynitride film, etc., can be used to prevent moisture, impurities in the atmosphere such as hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate 800 from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity.

[0185] Next, as shown in FIG. 12(B), a gate insulating film 802 is formed on the gate electrode 801, the capacitor wiring 822, and the first terminal 8 21. The gate insulating film 802 can be formed by using the plasma CVD method or the sputtering method, etc., as a single layer or a stack of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxynitride film, aluminum oxide, or tantalum oxide. . It is desirable that the gate insulating film 802 contains as little moisture and impurities such as hydrogen as possible. A gate insulating film 802 having a structure in which an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio are stacked may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films are formed between the barrier insulating film and the oxide and the semiconductor film. Examples of the insulating film with high barrier properties include a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. By using the insulating film with barrier properties, it is possible to prevent impurities in the atmosphere such as moisture or hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate from entering the oxide semiconductor film, the gate insulating film 80 2, or the interface between the oxide semiconductor film and other insulating films and the vicinity thereof. In addition, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio in contact with the oxide semiconductor film, it is possible to prevent the insulating film using a material

[0186] with high barrier properties from directly contacting the oxide semiconductor film. In this embodiment, the gate insulating film 80 2 has a structure in which a 100-nm-thick silicon oxide film formed by sputtering is laminated on a 50-nm-thick

[0187] silicon nitride film formed by sputtering. Next, after forming an oxide semiconductor film on the gate insulating film 802, the oxide semiconductor film is processed into a desired shape by etching or the like to form an island-shaped oxide semiconductor film 803. The oxide semiconductor film is formed by sputtering using an oxide semiconductor as a target. In addition, the oxide semiconductor film can be formed by sputtering in a rare gas (for example, argon) atmosphere, an oxygen atmosphere, or a rare gas (for example, argon) and oxygen atmosphere.

[0188] Note that before forming the oxide semiconductor film by sputtering, argon gas is introduced to generate plasma. Perform reverse sputtering to generate plasma and remove the dust adhering to the surface of the gate insulating film 802. This is preferable. Reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma on the substrate and modify the surface. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Also, it may be performed in an atmosphere in which oxygen, hydrogen, nitrous oxide, or the like is added to the argon atmosphere. Further, it may be performed in an atmosphere in which chlorine, carbon tetrafluoride, or the like is added to the argon atmosphere.

[0189] For the oxide semiconductor film for forming the channel formation region, an oxide material having semiconductor characteristics as described above may be used.

[0190] The film thickness of the oxide semiconductor film is set to 10 nm to 300 nm, preferably 20 nm to 100 nm. In this embodiment, here, an oxide semiconductor target containing In, Ga, and Zn (molar ratio is In O 2 :Ga 3 O 2 :ZnO = 1:1:1, In 3 O 2 :Ga 3 O 2 : 3 ZnO = 1:1:2) is used, the distance between the substrate and the target is 100 mm, the pressure is 0. 6 Pa, a DC power source of 0.5 kW, and film formation is performed in an oxygen (oxygen flow ratio 100%) atmosphere. Note that when a pulsed DC power source is used, dust can be reduced and the film thickness distribution becomes uniform, which is preferable. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based oxide semiconductor target is used, and an In-Ga-Zn-O system non-single crystal film with a film thickness of 30 nm is formed by a sputtering apparatus.

[0191] Note that by forming an oxide semiconductor film without exposing it to the atmosphere after plasma treatment, it is possible to prevent dust and moisture from adhering to the interface between the gate insulating film 802 and the oxide semiconductor film. Also when using a pulsed direct current (DC) power supply, dust can be reduced and the film thickness distribution becomes uniform, which is preferable

[0192] Also, the relative density of the oxide semiconductor target is preferably 80% or more, more preferably 95% or more, and even more preferably 99.9% or more. Using a target with a high relative density can reduce the impurity concentration in the formed oxide semiconductor film and obtain a thin film transistor with high electrical characteristics or reliability

[0193] There is also a multi-source sputtering apparatus capable of installing a plurality of targets made of different materials. The multi-source sputtering apparatus can deposit different material films in the same chamber or discharge a plurality of types of materials simultaneously in the same chamber to form a film

[0194] There is also a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber or an ECR sputtering apparatus using plasma generated using microwaves without using glow discharge

[0195] Also, as a film forming method using the sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, or a bias sputtering method in which a voltage is also applied to the substrate during film formation

[0196] Also, during film formation by the sputtering method, the substrate is heated to 400 °C or higher and 700 °C or lower by light or a heater ​​​​​​It may be heated. By heating during film formation, damage caused by sputtering can be repaired simultaneously with film formation. .

[0197] Also, before forming the oxide semiconductor film, a preheating treatment may be performed to remove moisture or hydrogen remaining in the inner wall of the sputtering apparatus, on the target surface, or in the target material. It is advisable to perform a preheating treatment to remove moisture or hydrogen remaining in the inner wall of the sputtering apparatus, on the target surface, or in the target material before forming the oxide semiconductor film. As the preheating treatment, there are methods such as heating the inside of the film formation chamber to 200°C to 600°C under reduced pressure, or repeatedly introducing and exhausting nitrogen or an inert gas while heating. After the preheating treatment, the substrate or the sputtering apparatus is cooled and then the oxide semiconductor film is formed without being exposed to the atmosphere. In this case, it is preferable to use a coolant for the target other than water, such as oil or grease. Although a certain effect can be obtained by repeatedly introducing and exhausting nitrogen without heating, it is even better to perform it while heating. It is also preferable to remove moisture and the like remaining in the sputtering apparatus using a cryopump before, during, or after forming the oxide semiconductor film. In the second photolithography process, for example, an island-shaped oxide semiconductor film 803 can be formed by wet etching the oxide semiconductor film into a desired shape using a solution of phosphoric acid, acetic acid, and nitric acid. The island-shaped oxide semiconductor film 803 is formed so as to overlap with the gate electrode 801. Also, for etching the oxide semiconductor film, organic acids such as citric acid and oxalic acid can be used as the etching agent. In this embodiment, unnecessary portions are removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) to form the island-shaped oxide semiconductor film 803. Also, the etching here is not limited to wet etching. Although a certain effect can be obtained by repeatedly introducing and exhausting nitrogen without heating, it is even better to perform it while heating. It is even better.

[0198] Also, before, during, or after forming the oxide semiconductor film, it is preferable to remove moisture and the like remaining in the sputtering apparatus using a cryopump. In the second photolithography process, for example, an island-shaped oxide semiconductor film 803 can be formed by wet etching the oxide semiconductor film into a desired shape using a solution of phosphoric acid, acetic acid, and nitric acid. The island-shaped oxide semiconductor film 803 is formed so as to overlap with the gate electrode 801. Also, for etching the oxide semiconductor film, organic acids such as citric acid and oxalic acid can be used as the etching agent. In this embodiment, unnecessary portions are removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) to form the island-shaped oxide semiconductor film 803. Also, the etching here is not limited to wet etching.

[0199] In the second photolithography process, for example, an island-shaped oxide semiconductor film 803 can be formed by wet etching the oxide semiconductor film into a desired shape using a solution of phosphoric acid, acetic acid, and nitric acid. The island-shaped oxide semiconductor film 803 can be formed by wet etching the oxide semiconductor film into a desired shape using a solution of phosphoric acid, acetic acid, and nitric acid. The island-shaped oxide semiconductor film 803 is formed so as to overlap with the gate electrode 801. Also, for etching the oxide semiconductor film, organic acids such as citric acid and oxalic acid can be used as the etching agent. In this embodiment, unnecessary portions are removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) to form the island-shaped oxide semiconductor film 803. (Manufactured by Kanto Chemical Co., Inc.) to form the island-shaped oxide semiconductor film 803 by removing unnecessary portions. Also, the etching here is not limited to wet etching. It may not be performed and dry etching may be used instead.

[0200] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl 2 ), boron chloride (BCl 3 ), silicon chloride (SiCl 4 ), carbon tetrachloride (CCl l 4 ), etc.) is preferred.

[0201] Also, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (CHF 3 ), etc.), hydrogen bromide (HBr ), oxygen (O 2 ), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0202] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that etching can be performed to obtain the desired processed shape.

[0203] Also, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. Indium, etc. contained in the oxide semiconductor film may be recovered from the waste liquid after the etching. By recovering and reusing the material, resources can be effectively utilized and costs can be reduced.

[0204] The etching conditions (etching solution, etch ing time, temperature, etc.) are appropriately adjusted according to the material so that it can be processed into a desired shape.

[0205] Next, as shown in Fig. 12(C), in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas atmosphere, an oxygen gas atmosphere, or an ultra-dry air (the moisture content when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method is 20 ppm (dew point conversion of -55 °C or less), preferably 1 ppm or less, preferably 10 ppb or less of air) atmosphere, the oxide semiconductor film 803 may be heat-treated. By heat-treating the oxide semiconductor film 803, the oxide semiconductor film 804 is formed. Specifically, in an inert gas atmosphere (nitrogen or helium, neon, argon, etc.), at 500 °C or higher and 750 °C or lower (if the temperature is below the strain point of the glass substrate), for about 1 minute or more and 10 minutes or less, preferably 650 °C for about 3 minutes or more and 6 minutes or less of RTA (Rapid Thermal Anneal) treatment can be performed. By using the RTA method, dehydration or dehydrogenation can be performed in a short time, so that treatment can be performed even at a temperature exceeding the strain point of the glass substrate. Note that the above heat treatment is not limited to the timing after the formation of the island-shaped oxide semiconductor film 803, and may be performed on the oxide semiconductor film before etching. Also, the above heat treatment may be performed multiple times after the formation of the island-shaped oxide semiconductor film 803.

[0206] In this embodiment, in a nitrogen atmosphere, at 600 °C, when the substrate temperature reaches the above set temperature Perform heat treatment for 6 minutes in this state. The heat treatment can use a heating method using an electric furnace, or a GRTA (Gas Rapid Thermal Anneal) method using heated gas or an LRTA (Lamp Rapid Thermal Anneal) method using lamp light, etc., such as an instantaneous heating method. For example, when performing heat treatment using an electric furnace, it is preferable that the temperature rising characteristic is 0.1 °C / min or more and 20 °C / min or less, and the temperature falling characteristic is 0.1 °C / min or more and 15 °C / min or less.

[0207] In the heat treatment, it is preferable that nitrogen or rare gases such as helium, neon, and argon do not contain water vapor, hydrogen, etc. Alternatively, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0208] Note that the cross-sectional view within the range of the dashed line D1 - D2 in Fig. 12(C) and the cross-sectional view within the range of the dashed line E1 - E2 correspond to the cross-sectional view at the dashed line D1 - D2 and the cross-sectional view at the dashed line E1 - E2 of the plan view shown in Fig. 15.

[0209] Next, as shown in Fig. 13(A), a conductive film 806 to be used as a source electrode or a drain electrode is formed on the oxide semiconductor film 804 by sputtering or vacuum evaporation. In this embodiment , a conductive film 806 using a metal material such as titanium, tungsten, or molybdenum with low contact resistance with the oxide semiconductor film 804 is used, and a conductive film 806b using a metal, metal compound, or alloy with low electronegativity is laminated thereon.

[0210] As metals with low electronegativity, aluminum and magnesium can also be used. The above A mixture, metal compound, or alloy containing any one or more of the above metals can be used as the conductive film 806b. Also, when using a material with low heat resistance such as aluminum, To aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium An element selected from yttrium, or an alloy containing one or more of the above elements as components, or By combining a heat-resistant conductive material such as a nitride containing the above elements as components, the heat resistance of the conductive film 806b may be increased. The thickness of the conductive film 806a is preferably 10 nm to 200 nm, more preferably 50 nm to 150 nm.

[0211] The thickness of the conductive film 806b is preferably 100 nm to 300 nm, more preferably 150 nm to 250 nm. In this embodiment, as the conductive film 806a, A titanium film with a thickness of 100 nm formed by sputtering is used, and as the conductive film 806b, a sputtered An aluminum film with a thickness of 200 nm formed by the method is used.

[0212] In one aspect of the present invention, since a metal, metal compound, or alloy with low electronegativity is used as the conductive film 806b, moisture, such as water, or impurities such as hydrogen present in the oxide semiconductor film 804, within the gate insulating film 802, or at the interface between the oxide semiconductor film 804 and other insulating films and in the vicinity thereof, is occluded or adsorbed by the conductive film 806b. Therefore, by removing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 804 that is extremely close to the i-type can be obtained. ​​​​​This can prevent the degradation of transistor characteristics such as the threshold voltage shift caused by the above impurities, and can reduce the off-current. In addition to the above configuration, in a state where the conductive film 806b is exposed, heat treatment may be performed in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to remove moisture, oxygen, etc. adsorbed on the surface and inside of the conductive film 806b.

[0213] In addition to the above configuration, in a state where the conductive film 806b is exposed, heat treatment may be performed in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to remove moisture, oxygen, etc. adsorbed on the surface and inside of the conductive film 806b. In addition to the above configuration, in a state where the conductive film 806b is exposed, heat treatment may be performed in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to remove moisture, oxygen, etc. adsorbed on the surface and inside of the conductive film 806b. In addition to the above configuration, in a state where the conductive film 806b is exposed, heat treatment may be performed in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to remove moisture, oxygen, etc. adsorbed on the surface and inside of the conductive film 806b. The temperature range of the heat treatment is 200°C to 450°C. By performing the above heat treatment, impurities such as moisture or hydrogen present in the oxide semiconductor film 804, the gate insulating film 802, or at the interface and its vicinity between the oxide semiconductor film 804 and other insulating films can be more easily occluded or adsorbed by the conductive film 806b. The temperature range of the heat treatment is 200°C to 450°C. By performing the above heat treatment, impurities such as moisture or hydrogen present in the oxide semiconductor film 804, the gate insulating film 802, or at the interface and its vicinity between the oxide semiconductor film 804 and other insulating films can be more easily occluded or adsorbed by the conductive film 806b. The temperature range of the heat treatment is 200°C to 450°C. By performing the above heat treatment, impurities such as moisture or hydrogen present in the oxide semiconductor film 804, the gate insulating film 802, or at the interface and its vicinity between the oxide semiconductor film 804 and other insulating films can be more easily occluded or adsorbed by the conductive film 806b. The temperature range of the heat treatment is 200°C to 450°C. By performing the above heat treatment, impurities such as moisture or hydrogen present in the oxide semiconductor film 804, the gate insulating film 802, or at the interface and its vicinity between the oxide semiconductor film 804 and other insulating films can be more easily occluded or adsorbed by the conductive film 806b.

[0214] Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 Next, as shown in Fig. 13(B), a third photolithography process is performed, and the conductive films 806a and 806b are processed (patterned) into a desired shape by etching or the like to form the source electrode 807 and the drain electrode 808. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically, ammonia peroxide is 31 wt% hydrogen peroxide water and 28 An aqueous solution obtained by mixing aqueous ammonia and water at a volume ratio of 5:2:2 by weight% is used. Alternatively, a salt element (Cl 2 ), boron chloride (BCl 3 ), etc., a gas containing the same may be used to dry-etch the conductive film 806a and the conductive film 806b.

[0215] When forming the source electrode 807 and the drain electrode 808 by the above patterning, a part of the exposed portion of the island-shaped oxide semiconductor film 804 is etched, and a groove portion (recess) may be formed. In the present embodiment, a case where an island-shaped oxide semiconductor film 805 having a groove portion (recess) is formed by the above etching is exemplified. The conductive film 806a used for a part of the source electrode 807 and the drain electrode 808 is in contact with the oxide semiconductor film 805. And since a metal material having a low contact resistance with the oxide semiconductor film is used for the conductive film 806a as described above, the contact resistance between the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 is reduced. Therefore, the on-current and field-effect mobility of the TFT can be increased. In addition, in this third photolithography process, the second terminal 820 made of the same material as the source electrode 807 or the drain electrode 808 is left at the terminal portion. The second terminal 820 is electrically connected to the

[0216] source wiring (source wiring including the source electrode 807 or the drain electrode 808). 808. Furthermore, when using a resist mask having a plurality (for example, two types) of regions with different thicknesses formed by a multi-tone mask, the number of resist masks can be reduced, so that the process can be simplified and the cost

[0217] can be reduced. ​​​

[0218] Note that the cross-sectional views within the range of the dashed lines D1 - D2 in FIG. 13(B) and the cross-sectional views within the range of the dashed lines E1 - E2 are equivalent to the cross-sectional views at the dashed lines D1 - D2 and the cross-sectional views at the dashed lines E1 - E2 in the plan view shown in FIG. 16. Note that in this embodiment, an example is shown in which the source electrode and the drain electrode are formed according to the manufacturing method shown in Embodiment 1. However, they may also be formed according to the manufacturing methods shown in Embodiments 2 to 4. As shown in FIG. 14(A), after forming the source electrode 807 and the drain electrode 808, an insulating film 809 is formed so as to cover the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. It is desirable that the insulating film 809 contains as few impurities such as moisture and hydrogen as possible. It may be a single-layer insulating film or may be composed of a plurality of laminated insulating films.

[0219] Note that in this embodiment, an example is shown in which the source electrode and the drain electrode are formed according to the manufacturing method shown in Embodiment 1. However, they may also be formed according to the manufacturing methods shown in Embodiments 2 to 4. Note that in this embodiment, an example is shown in which the source electrode and the drain electrode are formed according to the manufacturing method shown in Embodiment 1. However, they may also be formed according to the manufacturing methods shown in Embodiments 2 to 4. Note that in this embodiment, an example is shown in which the source electrode and the drain electrode are formed according to the manufacturing method shown in Embodiment 1. However, they may also be formed according to the manufacturing methods shown in Embodiments 2 to 4.

[0220] As shown in FIG. 14(A), after forming the source electrode 807 and the drain electrode 808, an insulating film 809 is formed so as to cover the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. It is desirable that the insulating film 809 contains as few impurities such as moisture and hydrogen as possible. It may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. As shown in FIG. 14(A), after forming the source electrode 807 and the drain electrode 808, an insulating film 809 is formed so as to cover the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. It is desirable that the insulating film 809 contains as few impurities such as moisture and hydrogen as possible. It may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. As shown in FIG. 14(A), after forming the source electrode 807 and the drain electrode 808, an insulating film 809 is formed so as to cover the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. It is desirable that the insulating film 809 contains as few impurities such as moisture and hydrogen as possible. It may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. As shown in FIG. 14(A), after forming the source electrode 807 and the drain electrode 808, an insulating film 809 is formed so as to cover the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. It is desirable that the insulating film 809 contains as few impurities such as moisture and hydrogen as possible. It may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. It is desirable to use a material with high barrier properties for the insulating film 809. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, an insulating film with barrier properties is formed so as to overlap the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 with the insulating film with a lower nitrogen ratio sandwiched therebetween. By using an insulating film with barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. In addition, in the oxide semiconductor film 805, the gate insulating film 802, or the oxide semiconductor Impurities such as moisture or hydrogen enter the interface between the insulating film 805 and other insulating films and its vicinity. In addition, when an oxide semiconductor film having a low ratio of nitrogen is formed in contact with the oxide semiconductor film 805, By forming an insulating film such as a silicon nitride film or a silicon oxynitride film, a material with high barrier properties is used. This can prevent the insulating film from being in direct contact with the oxide semiconductor film 805.

[0221] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 809 has a structure in which a silicon nitride film having a thickness of 100 nm formed by the method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. in this embodiment. The temperature is 100°C.

[0222] Exposure of the oxide semiconductor film 805 provided between the source electrode 807 or the drain electrode 808 The region is provided in contact with the silicon oxide constituting the insulating film 809, Oxygen is supplied to a region of the oxide semiconductor film 805 in contact with the oxide semiconductor film 809, and the region becomes highly resistive (the carrier concentration is Lower, preferably 1×10 18 / cm 3 (less than 1000 nm) and has a highly resistive channel formation region. In this case, the oxide semiconductor film 805 can be formed.

[0223] Next, after the insulating film 809 is formed, heat treatment may be performed. , in air or inert gas atmosphere (nitrogen, helium, neon, argon, etc.) Preferably, the temperature is 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. For example, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Similarly to the heat treatment, an RTA treatment with high temperature and short time may be performed. When this heat treatment is carried out, the oxide semiconductor film 805 will be heated in contact with the silicon oxide that constitutes the insulating film 809, further increasing the resistance of the oxide semiconductor film 805 to improve the electrical characteristics of the transistor and reduce the variation in electrical characteristics. This heat treatment is not particularly limited as long as it is performed after the formation of the insulating film 809, and can be combined with other processes, such as the heat treatment during resin film formation or the heat treatment for reducing the resistance of the transparent conductive film, so that it can be carried out without increasing the number of steps. .

[0224] The thin film transistor 813 can be fabricated through the above processes.

[0225] Next, a fourth photolithography process is performed to form a resist mask, and contact holes are formed by etching the insulating film 809 and the gate insulating film 802, exposing a part of the drain electrode 80 8, a part of the first terminal 821, and a part of the second terminal 820. Then, after removing the resist mask, a transparent conductive film is formed. As materials for the transparent conductive film, indium oxide (In ), indium tin oxide alloy (In 2 O 3 ), abbreviated as ITO 2 O 3 ―SnO 2 ), etc. are formed using sputtering or vacuum evaporation methods. The etching treatment of such materials is performed using a hydrochloric acid-based solution. However, especially for ITO etching, residues are likely to occur , so an indium zinc oxide alloy (In O 2 O 3 ―ZnO) may be used to improve the etching processability. Also, a heat treatment for reducing the resistance of the transparent conductive film is performed In such a case, the oxide semiconductor film 805 can be made to have a higher resistance, which can also serve as a heat treatment for improving the electrical characteristics of the transistor and reducing variations in the electrical characteristics.

[0226] Next, a fifth photolithography process is performed to form a resist mask, and by etching unnecessary portions are removed to form a pixel electrode 814 connected to the drain electrode 808, a transparent conductive film 815 connected to the first terminal 821, and a transparent conductive film 81 6 connected to the second terminal 820.

[0227] The transparent conductive film 815 and the transparent conductive film 816 serve as electrodes or wirings used for connection to the FPC. The transparent conductive film 815 formed on the first terminal 821 serves as a terminal electrode for connection that functions as an input terminal of the gate wiring. The transparent conductive film 816 formed on the second terminal 820 is a terminal electrode for connection that functions as an input terminal of the source wiring.

[0228] In this sixth photolithography process, a holding capacitor 819 is formed by the capacitor wiring 822 and the pixel electrode 814, with the gate insulating film 802 and the insulating film 809 serving as dielectrics.

[0229] A cross-sectional view at the stage where the resist mask has been removed is shown in FIG. 14(B). Note that the cross-sectional view within the range of the dashed line D1 - D2 in FIG. 14(B) and the cross-sectional view within the range of the dashed line E1 - E2 correspond to the cross-sectional view along the dashed line D1 - D2 and the cross-sectional view along the dashed line E1 - E2 in the plan view shown in FIG. 17. .

[0230] In this way, through six photolithography processes, using six photomasks, a pixel having a thin-film transistor 813 with a bottom gate type reverse staggered structure is formed. The thin film transistor portion and the storage capacitor 819 can be completed. By configuring the pixel section in a matrix corresponding to the pixels of In this specification, for the sake of convenience, Such a substrate is called an active matrix substrate.

[0231] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The opposing substrate is fixed.

[0232] In addition, the capacitance wiring is not provided, and the pixel electrode is connected to the gate wiring, the insulating film, and the gate insulating film of the adjacent pixels. A storage volume may be formed by stacking the layers via a membrane.

[0233] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0234] When a light-emitting display device is manufactured, a partition made of an organic resin film is provided between each of the organic light-emitting elements. In that case, the oxide semiconductor film 805 is heated to perform heat treatment on the organic resin film. Heat treatment to improve the electrical characteristics of transistors by making them resistive and to reduce the variation in electrical characteristics It can be combined with reason.

[0235] By forming a thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, by reducing impurities such as moisture, hydrogen, and OH by heat treatment, even without using a special sputtering apparatus with a lowered dew point in the film formation chamber or an ultra-high purity oxide semiconductor target to increase the purity of the oxide semiconductor film, a semiconductor display device having a thin film transistor with good electrical characteristics and high reliability can be manufactured. Since the semiconductor film in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are

[0236] stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor display device having a thin film transistor with good electrical characteristics and high reliability. This embodiment can be implemented in combination with the above embodiment.

[0237]

[0238] (Embodiment 8) In this embodiment, the configuration of a semiconductor display device, which is one of the semiconductor display devices formed using the manufacturing method of the present invention and is called an electronic paper or a digital paper, will be described.

[0239] An electronic paper uses a display element that can control gradation by applying a voltage and has a memory property. Specifically, display elements used in electronic paper include non-aqueous electrophoresis display elements, PDLC (polymer dispersed liquid crystal) display elements in which liquid crystal droplets are dispersed in a polymer material between two electrodes, and display elements having a chiral nematic liquid crystal or a cholesteric liquid crystal between two electrodes. ​​​​​​​An element having charged fine particles between two electrodes, and moving the fine particles in a powder by an electric field A powder movement type display element or the like can be used. Also, in a non-aqueous electrophoresis type display element is a display element sandwiching a dispersion liquid in which charged fine particles are dispersed between two electrodes, a charged display element having a dispersion liquid in which fine particles are dispersed on two electrodes with an insulating film sandwiched therebetween, a twisting ball having two hemispheres charged with different charges dispersed in a solvent between two electrodes, a display element having a plurality of charged fine particles dispersed in a solution and including a microcapsule between two electrodes and the like.

[0240] Fig. 18(A) shows a top view of a pixel portion 700 of an electronic paper, a signal line driving circuit 701, and a scanning line driving circuit 702.

[0241] The pixel portion 700 has a plurality of pixels 703. Also, a plurality of signal lines 707 are routed into the pixel portion 700 from the signal line driving circuit 701. A plurality of scanning lines 708 are routed into the pixel portion 700 from the scanning line driving circuit 702.

[0242] Each pixel 703 has a transistor 704, a display element 705, and a holding capacitor 706. The gate electrode of the transistor 704 is connected to one of the scanning lines 708. Also, one of the source electrode and the drain electrode of the transistor 704 is connected to one of the signal lines 707, and the other is connected to the pixel electrode of the display element 705. connected to the pixel electrode of the display element 705.

[0243] In Fig. 18(A), a holding capacitor 706 is connected in parallel with the display element 705 in order to hold the voltage applied between the pixel electrode and the counter electrode of the display element 705. However, the display element 7 ​​​If the memory property of 05 is high enough to maintain the display, the holding capacity 70 is not necessarily required to be provided.

[0244] In FIG. 18(A), the configuration of the pixel portion of the active matrix type in which one transistor functioning as a switching element is provided for each pixel has been described. However, the electronic paper according to one aspect of the present invention is not limited to this configuration. The number of transistors provided in the pixel may be plural, and elements such as a capacitor, a resistor, and a coil may be connected in addition to the transistor. is not limited to this configuration. The number of transistors provided in the pixel may be plural, and elements such as a capacitor, a resistor, and a coil may be connected in addition to the transistor. is not limited to this configuration. The number of transistors provided in the pixel may be plural, and elements such as a capacitor, a resistor, and a coil may be connected in addition to the transistor. is.

[0245] In FIG. 18(B), an electrophoretic type electronic paper having microcapsules is taken as an example, and a cross-sectional view of the display element 705 provided in each pixel 703 is shown. is shown.

[0246] The display element 705 includes a pixel electrode 710, a counter electrode 711, and microcapsules 712 to which a voltage is applied by the pixel electrode 710 and the counter electrode 711. One of the source electrode or the drain electrode 713 of the transistor 70 4 is connected to the pixel electrode 710. 4 is connected to the pixel electrode 710.

[0247] In the microcapsules 712, a positively charged white pigment such as titanium oxide and a negatively charged black pigment such as carbon black are encapsulated together with a dispersion medium such as oil. In the microcapsules 712, a positively charged white pigment such as titanium oxide and a negatively charged black pigment such as carbon black are encapsulated together with a dispersion medium such as oil. According to the voltage of the video signal applied to the pixel electrode 710, a voltage is applied between the pixel electrode and the counter electrode, and the black pigment is attracted to the positive electrode side and the white pigment is attracted to the negative electrode side, so that a gradation display can be performed. so that a gradation display can be performed.

[0248] In FIG. 18(B), the microcapsules 712 are the pixel electrode 710 and the counter electrode 711 However, the present invention uses this structure. The structure is not limited to the above, and may be formed by a microcapsule 712, a pixel electrode 710, and a counter electrode 711. The space formed may be filled with a gas such as air or an inert gas. In this case, the microcapsules 712 are attached to the pixel electrodes 710 and the counter electrodes 711 by adhesive or the like. It is desirable to fix both or either one of them.

[0249] The number of microcapsules 712 included in the display element 705 is as shown in FIG. A single display element 705 may have multiple microcapsules 712. Alternatively, multiple display elements 705 may have one microcapsule 712. For example, two display elements 705 may share one microcapsule 712. A positive voltage is applied to the pixel electrode 710 of the display element 705, and a positive voltage is applied to the pixel electrode 710 of the other display element 705. Suppose a negative voltage is applied to the pixel electrode 710. In this case, a positive voltage is applied to In the area overlapping with the pixel electrode 710 to which the voltage is applied, a black face is formed within the microcapsule 712. The white pigment is attracted to the pixel electrode 710 side, and the white pigment is attracted to the counter electrode 711 side. Conversely, in the area overlapping with the pixel electrode 710 to which a negative voltage is applied, the microcapsule In the cell 712, the white pigment is attracted to the pixel electrode 710 side, and the black pigment is attracted to the counter electrode 71 It gravitates towards one side.

[0250] Next, regarding a specific method for driving electronic paper, the above-mentioned electrophoretic electronic paper will be Let me explain with an example.

[0251] The operation of electronic paper can be explained by dividing it into an initialization period, a writing period, and a retention period. It can be achieved.

[0252] Before switching the displayed image, first, in the initialization period, the gradation of each pixel in the pixel portion is once unified to initialize the display element. By initializing the display element, it is possible to prevent the remaining image. Specifically, in the case of electrophoresis type, the gradation displayed by the microcapsules 712 included in the display element 705 is adjusted so that the display of each pixel becomes white or black.

[0253] In the present embodiment, after inputting an initialization video signal for displaying black to the pixel, the operation of initialization in the case of inputting an initialization video signal for displaying white to the pixel will be described. For example, in the case of an electrophoresis type electronic paper that displays an image toward the counter electrode 711 side, first, a voltage is applied to the display element 705 so that the black pigment in the microcapsule 712 faces the counter electrode 711 side and the white pigment faces the pixel electrode 710 side. Next, a voltage is applied to the display element 705 so that the white pigment in the microcapsule 712 faces the counter electrode 711 side and the black pigment faces the pixel electrode 710 side.

[0254] Also, if the input of the initialization video signal to the pixel is only once, depending on the gradation displayed before the initialization period, the movement of the white pigment and the black pigment in the microcapsule 712 may end halfway, and there may be a difference in the gradation displayed between pixels even after the initialization period ends. Therefore, it is desirable to display black by applying a negative voltage -Vp to the pixel electrode 710 a plurality of times with respect to the common voltage Vcom, and to display white by applying a positive voltage Vp to the pixel electrode 710 a plurality of times with respect to the common voltage Vcom.

[0255] Note that if the gradations displayed by the display elements of the respective pixels before the initialization period are different, the minimum number of times required to input the initialization video signal also differs. Therefore, the number of times of inputting the initialization video signal may be changed among the pixels according to the gradations displayed before the initialization period. In this case, it is advisable to input a common voltage Vcom to the pixels for which there is no longer a need to input the initialization video signal.

[0256] Note that in order to apply the voltage Vp or the voltage -Vp of the initialization video signal to the pixel electrode 710 a plurality of times, during the period when the pulse of the selection signal is applied to each scanning line, a series of operations of inputting the initialization video signal to the pixels of the line having the scanning line are performed a plurality of times. By applying the voltage Vp or the voltage -Vp of the initialization video signal to the pixel electrode 710 a plurality of times, the movement of the white pigment and the black pigment in the microcapsule 712 can be converged to prevent a gradation difference from occurring among the pixels, and the pixels of the pixel portion can be initialized.

[0257] Note that during the initialization period, instead of displaying black after displaying white for each pixel, it may be possible to display black after displaying white. Alternatively, during the initialization period, for each pixel, it may be possible to display black after displaying white, and then display white again.

[0258] Also, the timing at which the initialization period starts does not need to be the same for all the pixels in the pixel portion. For example, the timing at which the initialization period starts may be made different for each pixel or for each pixel belonging to the same line.

[0259] Next, during the writing period, a video signal having image information is input to the pixel.

[0260] When displaying an image across the entire pixel portion, during one frame period, selection signals with voltage pulses shifted in sequence are input to all scanning lines. Then, within one line period during which a pulse appears in the selection signal, a video signal having image information is input to all signal lines.

[0261] According to the voltage of the video signal applied to the pixel electrode 710, the white pigment and the black pigment in the microcapsule 712 move to the side of the pixel electrode 710 or the counter electrode 711, and thus the display element 705 displays gradation.

[0262] During the writing period as well, it is desirable to apply the voltage of the video signal to the pixel electrode 710 a plurality of times, similar to the initialization period. Therefore, during the period when the pulse of the selection signal is applied to each scanning line, a series of operations of inputting a video signal to the pixels of the line having the scanning line are performed a plurality of times.

[0263] Next, during the holding period, after inputting a common voltage Vcom to all pixels via the signal lines, no input of a selection signal to the scanning lines or a video signal to the signal lines is performed. Therefore, the white pigment and the black pigment in the microcapsule 712 of the display element 705 are held in their positions unless a plus or minus voltage is applied between the pixel electrode 710 and the counter electrode 711, and thus the gradation displayed by the display element 705 is maintained. Therefore, the image written during the writing period is also maintained during the holding period.

[0264] Note that for the display element used in the electronic paper, the voltage required to change the gradation is lower than that of liquid crystal​ It is higher than that of a light-emitting element such as a liquid crystal element used in a display device or an organic light-emitting element used in a light-emitting device. Therefore, the transistor 704 of the pixel used as the switching element has a tendency to have a large potential difference between its source electrode and drain electrode during the writing period, so that the off-current becomes high, and as a result, the potential of the pixel electrode 710 fluctuates and display disturbance occurs. To prevent the potential of the pixel electrode 710 from fluctuating due to the off-current of the transistor 704, it is effective to increase the capacitance of the holding capacitor 706. Also, not only the voltage between the pixel electrode 71 0 and the counter electrode 711, but also the voltage generated between the signal line 707 and the counter electrode 711 is applied to the microcapsule 712, which may cause noise in the display of the display element 705. To prevent the occurrence of this noise, it is effective to ensure a wide area of the pixel electrode 710 and prevent the voltage generated between the signal line 707 and the counter electrode 711 from being applied to the microcapsule 712. However, as described above, increasing the capacitance of the holding capacitor 706 to prevent the potential of the pixel electrode 710 from fluctuating, or widening the area of the pixel electrode 710 to prevent noise from occurring in the display, will increase the current value to be supplied to the pixel during the writing period, resulting in a longer time for inputting the video signal. In the electronic paper according to one aspect of the present invention, since the transistor 704 used in the pixel as the switching element has a high field-effect mobility, a high on-current can be obtained. Therefore, even if the capacitance of the holding capacitor 706 is increased or the area of the pixel electrode 710 is widened, the video signal can be quickly input to the pixel. Therefore, the length of the writing period is short. 704 has a high field-effect mobility, so a high on-current can be obtained. Thus, even if the capacitance of the holding capacitor 706 is increased or the area of the pixel electrode 710 is enlarged, the video signal can be quickly input to the pixel. Therefore, the length of the writing period can be suppressed, and the switching to the displayed image can be performed smoothly. Also, the transistor 704 of the pixel used as the etching element has a large potential difference between its source electrode and drain electrode during the writing period, so it is prone to deterioration. However, in one aspect of the present invention, the variation in the threshold voltage due to the deterioration of the transistor 704 over time can be suppressed, so the reliability of the electronic paper can be

[0265] This embodiment can be implemented in combination with the above embodiment.

[0266] (Embodiment 9) An example of a block diagram of an active matrix type semiconductor display device is shown in Fig. 19(A). On the substrate 5300 of the display device, there are a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304. In the pixel portion 5301, a plurality of signal lines extend from the signal line driving circuit 5304 and are arranged, and a plurality of scanning lines extend from the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 and are arranged. In the intersection region of the scanning lines and the signal lines, pixels each having a display

[0267] element are arranged in a matrix. Also, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller Therefore, the number of components such as a drive circuit provided externally is reduced, not only miniaturizing the display device but also enabling cost reduction by reducing the assembly process and inspection process. Also, for the substrate 5300 the number of connections at the connection part can be reduced by extending the wiring when a drive circuit is provided externally, and thus it is possible to prevent a decrease in yield due to a connection failure between the drive circuit and the pixel part, and prevent a decrease in reliability due to low mechanical strength at the connection points.

[0268] Note that the timing control circuit 5305 supplies, as an example, a start signal for the first scanning line drive circuit (GSP1) and a clock signal for the scanning line drive circuit (GCK1) to the first scanning line drive circuit 5302. Also, the timing control circuit 5305 supplies, as an example, a start signal for the second scanning line drive circuit (GSP2) (also referred to as a start pulse) and a clock signal for the scanning line drive circuit (GCK2) to the second scanning line drive circuit 5303. The signal line drive circuit 5304 is supplied with a start signal for the signal line drive circuit (SSP), a clock signal for the signal line drive circuit (SCK), video signal data (simply referred to as a video signal), and a latch signal (LAT). Note that either one of the first scanning line drive circuit 5302 and the second scanning line drive circuit 5303 can be omitted. scanning line drive circuit 5303 can be omitted. It is assumed that a latch signal (LAT) is supplied to the signal line drive circuit 5304. Note that either one of the first scanning line drive circuit 5302 and the second scanning line drive circuit 5303 can be omitted.

[0269] In FIG. 19(B), a circuit with a low drive frequency (for example, the first scanning line drive circuit 5302, the second scanning line drive circuit 5303) is formed on one substrate 5300 together with the pixel part 5301, and the signal line drive circuit 5304 is formed on a substrate different from the pixel part 5301, showing a configuration. Also, among the signal line drive circuit 5304, the ana used in the sampling circuit Circuits with a low driving frequency, such as a log switch, can be partially formed on a single substrate 5300 together with the pixel section 5301. In this way, by partially adopting a system-on-panel, it is possible to avoid problems such as a reduction in yield due to the above-described connection failure and a low mechanical strength at the connection point, and to reduce costs by reducing the assembly process and the inspection process, thereby enjoying some of the advantages of the system-on-panel. Furthermore, compared to a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is also possible to form a pixel section with a large area, which is difficult to achieve when using a single-crystalline semiconductor. It is also possible. By adopting a system-on-panel as described above, it is possible to avoid problems such as a reduction in yield due to the above-described connection failure and a low mechanical strength at the connection point, and to reduce costs by reducing the assembly process and the inspection process, thereby enjoying some of the advantages of the system-on-panel. Furthermore, compared to a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is also possible to form a pixel section with a large area, which is difficult to achieve when using a single-crystalline semiconductor. Furthermore, compared to a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is also possible to form a pixel section with a large area, which is difficult to achieve when using a single-crystalline semiconductor. Furthermore, compared to a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is also possible to form a pixel section with a large area, which is difficult to achieve when using a single-crystalline semiconductor. Furthermore, compared to a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is also possible to form a pixel section with a large area, which is difficult to achieve when using a single-crystalline semiconductor. Furthermore, compared to a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is also possible to form a pixel section with a large area, which is difficult to achieve when using a single-crystalline semiconductor. Furthermore, compared to a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is also possible to form a pixel section with a large area, which is difficult to achieve when using a single-crystalline semiconductor.

[0270] Next, the configuration of a signal line driving circuit using an n-channel type transistor will be described.

[0271] The signal line driving circuit shown in FIG. 20(A) includes a shift register 5601 and a sampling circuit 5602. The sampling circuit 5602 includes a plurality of switching circuits 5602_1 to 5602_N (N is a natural number). The sampling circuit 5602 includes a plurality of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of n-channel type transistors 5603_1 to 5603_k (k is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of n-channel type transistors 5603_1 to 5603_k (k is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of n-channel type transistors 5603_1 to 5603_k (k is a natural number).

[0272] The connection relationship of the signal line driving circuit will be described by taking the switching circuit 5602_1 as an example. Hereinafter, one of the source electrode and the drain electrode of the transistor will be referred to as the first terminal, and the other will be referred to as the second terminal. The connection relationship of the signal line driving circuit will be described by taking the switching circuit 5602_1 as an example. Hereinafter, one of the source electrode and the drain electrode of the transistor will be referred to as the first terminal, and the other will be referred to as the second terminal. The connection relationship of the signal line driving circuit will be described by taking the switching circuit 5602_1 as an example. Hereinafter, one of the source electrode and the drain electrode of the transistor will be referred to as the first terminal, and the other will be referred to as the second terminal.

[0273] The first terminals of transistors 5603_1 to 5603_k are each connected to wirings 5604_1 to 56 04_k. Video signals are respectively input to wirings 5604_1 to 5604_k. The second terminals of transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gate electrodes of transistors 5603_1 to 5603_k are connected to the shift register 5601.

[0274] The shift register 5601 outputs a timing signal having a high-level voltage (H level) in the order of wirings 5605_1 to 5605_N, and has a function of sequentially selecting switching circuits 5602_1 to 560 2_N.

[0275] The switching circuit 5602_1 has a function of controlling the conduction state between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk (conduction between the first terminal and the second terminal) by switching of transistors 5603_1 to 5603_k, that is, a function of controlling whether to supply the electric potential of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk.

[0276] Next, the operation of the signal line driving circuit in Fig. 20(A) will be described with reference to the timing chart in Fig. 20(B). In Fig. 20(B), timing signals Sout_1 to Sout_N respectively input to wirings 5605_1 to 5605_N from the shift register 5601 and a timing chart of video signals Vdata_1 to Vd ata_k respectively input to wirings 5604_1 to 5604_k are shown as an example.

[0277] Note that one operation period of the signal line driving circuit corresponds to one line period in the display device. Fig. 2 ​​​​​​​​In 0(B), the case where one line period is divided into periods T1 to TN is illustrated. The periods T1 to TN are each a period for writing a video signal to one pixel belonging to the selected row .

[0278] During periods T1 to TN, the shift register 5601 outputs a high-level timing signal to the wirings 5605_1 to 5605_N in order. For example, during period T1, the shift register 5601 outputs a high-level signal to the wiring 5605_1. Then, the transistors 5603_1 to 5603_k included in the switching circuit 5602_1 turn on, and the wirings 5604_1 to 5604_k and the signal lines S1 to Sk become conductive. At this time, Data(S1) to Data(Sk) are input to the wirings 5604_1 to 5604_k. Data(S1) to Data(Sk) are each written to the pixels in the 1st to kth columns among the pixels belonging to the selected row via the transistors 5603_1 to 5 603_k. Thus, during periods T1 to TN, the video signal is written to the pixels belonging to the selected row sequentially by k columns at a time.

[0279] As described above, by writing the video signal to the pixels by a plurality of columns at a time, the number of video signals or the number of wirings can be reduced. Therefore, the number of connections with an external circuit such as a controller can be reduced. Also, by writing the video signal to the pixels by a plurality of columns at a time, the writing time can be lengthened, and insufficient writing of the video signal can be prevented. .

[0280] Next, a form of the shift register used in a signal line driving circuit or a scanning line driving circuit will be described with reference to FIG. This will be described with reference to FIGS. 21 and 22.

[0281] The shift register has first to N-th pulse output circuits 10_1 to 10_N ( where N is a natural number of 3 or more) (see FIG. 21(A)). The first to N-th pulse output circuits 10_ 1 to 10_N are supplied with a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14. Further, in the first pulse output circuit 10_ 1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. Further, in the n-th pulse output circuit 10_n (n is a natural number of 2 or more and N or less) from the second stage onward, a signal (referred to as a previous stage signal OUT(n - 1)) from the pulse output circuit 10_n - 1 in the immediately previous stage is input. Further, in the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 in the second subsequent stage is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, a signal (referred to as a subsequent stage signal OUT(n + 2)) from the (n + 2)-th pulse output circuit 10_ (n + 2) in the second subsequent stage is input. Therefore, from each stage of the pulse output circuit, first output signals OUT(1)(SR) to OUT(N)(SR) for input to the subsequent stage and the pulse output circuit two stages before, and second output signals (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 21(A), since the subsequent stage signal OUT(n + 2) is not input to the two stages at the final stage of the shift register, as an example, a second start pulse SP2 and a third start pulse SP3 may be separately input.

[0282] ​​​​​​​ The clock signal (CK) is a signal that alternates between a high level (H) and a low level (low voltage level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal ( CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first clock signal ( CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit, etc. Note that depending on the input drive circuit, the clock signal may be referred to as GCK or SCK, but here it will be described as CK.

[0283] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 21(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is connected to the third wiring 13 electrically, and the third input terminal 23 is electrically connected to the fourth wiring 14.

[0284] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 21(B)). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third input terminal 23 has the third clock signal CK3 input thereto, and the fourth input terminal 24 has the fourth clock signal CK4 input thereto. A third clock signal CK3 is input to the input terminal 23, and a start pulse is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, and a first output signal OUT(1)(SR) is output from the first output terminal 26, and from the second output terminal 27 a second output signal OUT(1) is output.

[0285] Next, an example of the specific circuit configuration of the pulse output circuit is shown in Fig. 22(A).

[0286] Each pulse output circuit has first transistors 31 to thirteenth transistors 43 (see Fig. 22(A)). Also, in addition to the first input terminal 21 to the fifth input terminal 25, and the first output terminal 26 and the second output terminal 27 described above, a first high power supply potential VDD is supplied to the power supply line 51, a second high power supply potential VCC is supplied to the power supply line 52, and a low power supply potential VSS is supplied to the power supply line 53. Signals or power supply potentials are supplied from the power supply line 51, the power supply line 52, and the power supply line 53 to the first transistors 31 to the thirteenth transistors 43. Here, the relationship of the heights of the power supply potentials of the respective power supply lines in Fig. 22(A) is that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, but it is assumed that they are VDD at the H level and VSS at the L level. By making the potential V DD of the power supply line 51 higher than the potential VCC of the power supply line 52, without affecting the operation the potential applied to the gate electrode of the transistor can be kept low, the shift of the threshold voltage of the transistor can be reduced, and deterioration can be suppressed.

[0287] In FIG. 22(A), for the first transistor 31, the first terminal is electrically connected to the power line 51 and the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the fourth input terminal 24. For the second transistor 32, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. For the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. For the fourth transistor 34, the first terminal is electrically connected to the power line 53, and the second terminal is electrically connected to the first output terminal 26 . For the fifth transistor 35, the first terminal is electrically connected to the power line 53, and the second terminal is electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34 , and the gate electrode is electrically connected to the fourth input terminal 24. For the sixth transistor 36, the first terminal is electrically connected to the power line 52, and the second terminal is electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34, and the gate electrode is electrically connected to the fifth input terminal 25. For the seventh transistor 3 7, the first terminal is electrically connected to the power line 52, the second terminal is electrically connected to the second terminal of the eighth transistor 38, and the gate electrode is electrically connected to the third input terminal 23 . For the eighth transistor 38, the first terminal is electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34, and the gate electrode is electrically connected to the second input terminal 2 . and the gate electrode is electrically connected to the second input terminal 2 ​​​is electrically connected to 2. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrode of the seventh transistor 37. The thirteenth transistor 43 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the first output terminal 26, and its gate electrode electrically connected to the gate electrode of the seventh transistor 37. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39.

[0288] In FIG. 22(A), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is defined as node A. In FIG. 22(A), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is defined as node A. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power supply line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. Set the connection point of the first terminal of the switch 38 and the eleventh transistor 41 as node B (see Fig. 2 2(A)).

[0289] Regarding the timing chart of the shift register having a plurality of pulse output circuits shown in Fig. 22(A), it is shown in Fig. 22(B).

[0290] As shown in Fig. 22(A), by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, there are the following advantages before and after the bootstrap operation.

[0291] When there is no ninth transistor 39 to which the second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source electrode, which is the second terminal of the first transistor 31, rises and becomes higher than the first power supply potential VDD. Then, the source electrode of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate electrode and the source electrode and between the gate electrode and the drain electrode, so a large stress is applied, which can be a factor in transistor degradation. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the bootstrap operation, the potential of the second terminal of the first transistor 31 can be prevented from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate electrode and the source electrode of the first transistor 31 can be reduced. Therefore, by adopting the circuit configuration of this embodiment ​​​​​​​​​​​​​, the negative bias voltage applied between the gate electrode and the source electrode of the first transistor 31 can also be reduced, so that deterioration of the first transistor 31 due to stress can be suppressed.

[0292] Regarding the location where the ninth transistor 39 is provided, as long as it is configured to be connected between the second terminal of the first transistor 31 and the gate electrode of the third transistor 33 via the first terminal and the second terminal. In the case of a shift register including a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having a larger number of stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, and there is an advantage that the number of transistors can be reduced.

[0293] By using an oxide semiconductor as the active layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the transistor can be reduced, and the on-current and the field-effect mobility can be increased, and furthermore, the degree of deterioration can be reduced. Therefore, malfunction within the circuit can be reduced. In addition, a transistor using an oxide semiconductor has less deterioration of the transistor due to the application of a high potential to the gate electrode compared to a transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC, and the number of power supply lines routed between circuits can be reduced, so that the circuit can be miniaturized.

[0294] The clock signal supplied to the gate electrode of the seventh transistor 37 by the third input terminal 23, and the signal supplied to the gate electrode of the eighth transistor 38 by the second input terminal 22 The clock signal to be output is supplied to the gate electrode of the seventh transistor by the second input terminal 22. The clock signal supplied to the gate electrode of the eighth transistor by the third input terminal 23 has the same effect even if the wiring relationship is changed. At this time, in the shift register shown in FIG. 22(A), from the state where both the seventh transistor 37 and the eighth transistor 38 are on, the seventh transistor 37 is turned off, the eighth transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor 38 is off. By changing to this state, the potentials of the second input terminal 22 and the third input terminal 23 decrease. As a result, the decrease in the potential of node B caused by this occurs twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. On the other hand, as in the period of FIG. 22(B), the shift register shown in FIG. 22(A) is changed from the state where both the seventh transistor 37 and the eighth transistor 38 are on, the seventh transistor 37 is on, the eighth transistor 38 is off, and then the seventh transistor 37 is off and the eighth transistor 38 is off. By changing to this state, the decrease in the potential of node B caused by the decrease in the potentials of the second input terminal 22 and the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, it is preferable to have a wiring relationship in which the clock signal is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and the clock signal is supplied from the second input terminal 22 to the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. This is because the number of fluctuations in the potential of node B is reduced. ​ This is because noise can be reduced as well.

[0295] In this way, by configuring the potential of the first output terminal 26 and the second output terminal 27 to be held at the L level, and periodically supplying an H-level signal to node B during that period, malfunctions of the pulse output circuit can be suppressed.

[0296]

[0297] This embodiment can be implemented in combination with the above-described embodiment. (Embodiment 10) The liquid crystal display device according to one aspect of the present invention uses a thin film transistor having high mobility and on-current, and high reliability, so that the contrast and visibility are high. In this embodiment, the configuration of the liquid crystal display device according to one aspect of the present invention will be described.

[0298] FIG. 23 shows, as an example, a cross-sectional view of a pixel of the liquid crystal display device according to one aspect of the present invention. The thin film transistor 1401 shown in FIG. 23 has a gate electrode 1402 formed on an insulating surface, a gate insulating film 1403 on the gate electrode, an oxide semiconductor film 1404 overlapping the gate electrode 1402 on the gate insulating film 1403, and a pair of conductive films 1406a and 1406b formed so as to be laminated in order on the oxide semiconductor film 1404 and functioning as a source electrode or a drain electrode. Further, the thin film transistor 1401 may include an insulating film 1407 formed on the oxide semiconductor film 1404 as a component thereof. The insulating film 1407 is formed so as to cover the gate electrode 1402, the gate insulating film 1403, the oxide semiconductor film 1404, and the conductive films 1406a and 1406b.

[0299] ​​​​​​​​​​​​ In this embodiment, a source electrode formed according to the manufacturing method shown in Embodiment 1 and a drain electrode are taken as examples, but source electrodes and drain electrodes formed according to the manufacturing methods shown in Embodiments 2 to 4 may also be used. An insulating film 1408 is formed on the insulating film 1407. Openings are provided in a part of the insulating film 1407 and the insulating film 140

[0300] 8, and a pixel electrode 1410 is formed so as to be in contact with one of the conductive films 1406b at the opening. Furthermore, a spacer 141 7 for controlling the cell gap of the liquid crystal element is formed on the insulating film 1408. The spacer 1417 can be formed by etching the insulating film into a desired shape, but the cell gap may be controlled by dispersing a filler on the insulating film 1408.

[0301] An alignment film 1411 is formed on the pixel electrode 1410. A counter electrode 1413 is provided at a position facing the pixel electrode 14 10, and an alignment film 1414 is formed on the side of the counter electrode 1413 close to the pixel electrode 1410. The alignment films 1411 and 1 414 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and an alignment treatment for arranging liquid crystal molecules in a certain direction, such as rubbing, is performed on the surface thereof. Rubbing can be performed by rotating a roller wrapped with a cloth such as nylon while applying pressure to the alignment film to rub the surface of the alignment film in a certain direction. Note that

[0302] using an inorganic material such as silicon oxide and performing an alignment treatment without performing an alignment treatment, an alignment characteristic can be obtained by a vapor deposition method. 10, and an alignment film 1414 is formed on the side of the counter electrode 1413 close to the pixel electrode 1410. The alignment films 1411 and 1 414 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and an alignment treatment for arranging liquid crystal molecules in a certain direction, such as rubbing, is performed on the surface thereof. 414 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and an alignment treatment for arranging liquid crystal molecules in a certain direction, such as rubbing, is performed on the surface thereof. 414 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and an alignment treatment for arranging liquid crystal molecules in a certain direction, such as rubbing, is performed on the surface thereof. 414 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and an alignment treatment for arranging liquid crystal molecules in a certain direction, such as rubbing, is performed on the surface thereof. 414 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and an alignment treatment for arranging liquid crystal molecules in a certain direction, such as rubbing, is performed on the surface thereof. Furthermore, using an inorganic material such as silicon oxide and performing an alignment treatment without performing an alignment treatment, an alignment characteristic can be obtained by a vapor deposition method. It is also possible to directly form the alignment films 1411 and 1414.

[0303] And, between the pixel electrode 1410 and the counter electrode 1413, a region surrounded by the sealing material 1416 is provided with a liquid crystal 1415. The injection of the liquid crystal 1415 may use a dispenser type ( droplet type), or may use a dip type (suction type). Note that a filler may be mixed into the sealing material 1416.

[0304] Also, the liquid crystal element formed by the pixel electrode 1410, the counter electrode 1413, and the liquid crystal 1415 may overlap with a color filter that can transmit light in a specific wavelength region. The color filter may be formed on the substrate (counter substrate) 1420 on which the counter electrode 1413 is formed. The color filter may be formed by applying an organic resin such as an acrylic resin in which a pigment is dispersed on the substrate 1 420 and then selectively forming it using photolithography. Also, after applying a polyimide resin in which a pigment is dispersed on the substrate 1420, it can also be selectively formed using etching. Or, a color filter can also be selectively formed by using a droplet ejection method such as inkjet.

[0305] Also, in order to prevent disclination caused by the disturbance of the alignment of the liquid crystal 1415 between pixels from being visually recognized, a shielding film that can shield light may be formed between pixels. For the shielding film, an organic resin containing a black pigment such as carbon black or low-order titanium oxide can be used. Or, it is also possible to form the shielding film with a film using chromium.

[0306] ​​​​​The pixel electrode 1410 and the counter electrode 1413 can be made of a transparent conductive material such as indium tin oxide (ITSO), indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or zinc oxide doped with gallium (GZO). In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown. However, the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type. Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown. However, the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type. Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence.

[0307] Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type.

[0308] In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Although a TN (Twisted Nematic) type is shown as the liquid crystal display device in this embodiment, the thin film transistor of the present invention can also be used in other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In addition, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal 1415 to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence.

[0309] FIG. 24 is an example of a perspective view showing the structure of the liquid crystal display device of the present invention. The liquid crystal display device shown in FIG. 24 includes a liquid crystal panel 1601 in which liquid crystal elements are formed between a pair of substrates, a first diffusion plate 1 602, a prism sheet 1603, a second diffusion plate 1604, a light guide plate 1605, a reflective plate 1606, a light source 1607, and a circuit board 1608.

[0310] The liquid crystal panel 1601, the first diffusion plate 1602, the prism sheet 1603, the second diffusion plate 1604, the light guide plate 1605, and the reflective plate 1606 are laminated in order. The light source 1 607 is provided at an end of the light guide plate 1605, and the light from the light source 1607 diffused inside the light guide plate 1605 is uniformly irradiated onto the liquid crystal panel 1601 by the first diffusion plate 1602, the prism sheet 1603, and the second diffusion plate 1604.

[0311] In this embodiment, the first diffusion plate 1602 and the second diffusion plate 1604 are used, but the number of diffusion plates is not limited to this, and it may be single or three or more. And the diffusion plate may be provided between the light guide plate 1605 and the liquid crystal panel 1601. Therefore, even if the diffusion plate is provided only on the side closer to the liquid crystal panel 1601 than the prism sheet 1603 or even if the diffusion plate is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603 it is okay.

[0312] Also, the prism sheet 1603 is not limited to the shape with a sawtooth cross section shown in FIG. 24, and it may have a shape capable of condensing the light from the light guide plate 1605 toward the liquid crystal panel 1601 side.

[0313] The circuit board 1608 includes a circuit that generates various signals input to the liquid crystal panel 1601, and also A circuit or the like for processing these signals is provided. And in FIG. 24, the circuit board 16 08 and the liquid crystal panel 1601 are connected via an FPC (Flexible Printed Circ uit) 1609. Note that the above circuit may be connected to the liquid crystal panel 1601 using the COG (Chip ON Glass) method, or a part of the above circuit may be connected to the FPC 1609 using the COF (Chip On Film) method as well.

[0314] In FIG. 24, a circuit of a control system for controlling the driving of the light source 1607 is provided on the circuit board 1608 and an example in which the circuit of the control system and the light source 1607 are connected via the FPC 1610 is shown. However, the above control system circuit may be formed on the liquid crystal panel 1601, and in this case, the liquid crystal panel 1601 and the light source 1607 are connected by an FPC or the like so as to be.

[0315] Note that FIG. 24 illustrates an edge light type light source in which the light source 1607 is arranged at the edge of the liquid crystal panel 1601, but the liquid crystal display device of the present invention may be a direct bottom type in which the light source 1607 is arranged directly below the liquid crystal panel 1601 as well.

[0316] This embodiment can be implemented in appropriate combination with the above embodiment.

[0317] (Embodiment 11) In this embodiment, a configuration of a light emitting device using a thin film transistor according to an aspect of the present invention as a pixel will be described. In this embodiment, a transistor for driving a light emitting element will be described with reference to FIG. 25 regarding the cross-sectional structure of a pixel in the case of an n-type. Note that in FIG. 25 ​​This will describe the case where the first electrode is the cathode and the second electrode is the anode. However, the first electrode may be the anode , and the second electrode may be the cathode.

[0318] Fig. 25(A) shows a cross-sectional view of a pixel when the transistor 6031 is of the n-type and the light emitted from the light-emitting element 6033 is extracted from the side of the first electrode 6034. The transistor 6031 is covered with an insulating film 6037, and a partition wall 6038 having an opening is formed on the insulating film 6037 . A part of the first electrode 6034 is exposed at the opening of the partition wall 6038 , and at this opening, the first electrode 6034, the electroluminescent layer 6035, and the second electrode 6036 are stacked in sequence .

[0319] The first electrode 6034 can be formed of a material that transmits light or with a film thickness, and also with a small work function metal, alloy, electrically conductive compound, and mixtures thereof. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr metals, alloys containing these (such as Mg:Ag, Al:Li, Mg:In, etc.), and their chemical compounds (calcium fluoride, calcium nitride), and in addition, rare earth metals such as Yb and Er can be used . When providing an electron injection layer, it is also possible to use other conductive layers such as aluminum . And the first electrode 6034 is formed with a film thickness that allows light to pass through (preferably about 5 nm to 30 nm). Furthermore, a conductive layer having light transmittance is formed using a light-transmissive oxide conductive material so as to be in contact with the upper or lower side of the above conductive layer having a film thickness that allows light to pass through , and the sheet resistance of the first electrode 6034 may be suppressed. Note that indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and adding gallium to etc. It is also possible to use only a conductive layer made of other translucent oxide conductive materials such as added zinc oxide (GZO). Also, indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITS O), or indium oxide containing silicon oxide, further mixed with 2 to 20% zinc oxide (Zn O) may be used. When using a translucent oxide conductive material, it is desirable to provide an electron injection layer in the electroluminescent layer 6 035.

[0320] Also, the second electrode 6036 is formed of a material and film thickness that reflect or shield light, and is formed of a material suitable for use as an anode. For example, one or more of titanium nitride, zirconium nitride, titanium, tungsten, nickel, platinum, chromium, silver, aluminum, etc. In addition to a single-layer film composed of, a laminate of a film mainly composed of titanium nitride and aluminum, a three-layer structure of a film mainly composed of titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film can be used for the second electrode 6036

[0321] The electroluminescent layer 6035 is composed of one or more layers. When composed of a plurality of layers, these layers can be classified into a hole injection layer, a hole transport layer, a light-emitting layer, from the viewpoint of carrier transport characteristics, an electron transport layer, an electron injection layer, etc. When the electroluminescent layer 6035 has any one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer in addition to the light-emitting layer, the first electrode 6034 stacks in the order of an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer. Note that the boundaries between the layers do not necessarily have to be clear, and there may be cases where the materials constituting the mutual layers are partially mixed and the interface becomes unclear. Each layer contains organic materials, inorganic materials, or both. It is possible to use organic materials. As organic materials, any of polymer-based, medium-molecule-based, and low-molecule-based materials can be used. Note that medium-molecule-based materials correspond to low polymers with a degree of polymerization (number of repeating structural units) of about 2 to 20. The distinction between the hole injection layer and the hole transport layer is not necessarily strict, and they are the same in the sense that hole transportability (hole mobility) is a particularly important characteristic. For convenience, the hole injection layer is the layer on the side in contact with the anode, and the layer in contact with the hole injection layer is called the hole transport layer for distinction. The same applies to the electron transport layer and the electron injection layer. The layer in contact with the cathode is called the electron injection layer, and the layer in contact with the electron injection layer is called the electron transport layer. The light-emitting layer may also serve as an electron transport layer and is also called a light-emitting electron transport layer. In the case of the pixel shown in Fig. 25(A), the light emitted from the light-emitting element 6033 can be taken out from the side of the first electrode 6034 as indicated by the white arrow. Next, Fig. 25(B) shows a cross-sectional view of a pixel when the transistor 6041 is of the n-type and the light emitted from the light-emitting element 6043 is taken out from the side of the second electrode 6046. The transistor 6041 is covered with an insulating film 6047, and a partition wall 6048 having an opening is formed on the insulating film 6047. At the opening of the partition wall 6048, a part of the first electrode 6044 is exposed, and at this opening, the first electrode 6044, the electroluminescent layer 6045, and the second electrode 6046 are laminated in this order. The first electrode 6044 is formed of a material and film thickness that reflect or shield light, and is also formed of a metal, alloy, electrically conductive compound, and mixtures thereof with a small work function.

[0322]

[0323]

[0324] ​​​​​​​​​​​​​​It is possible. Specifically, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, alloys containing these (such as Mg:Ag, Al:Li, Mg:In, etc.), and in addition to these compounds (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er can be used. When providing an electron injection layer, other conductive layers such as aluminum can also be used.

[0325] Also, the second electrode 6046 is formed of a material that transmits light or with a film thickness, and is formed of a material suitable for use as an anode. For example, indium tin oxide (ITO), zinc oxide ( ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), etc. Other light-transmissive oxide conductive materials can be used for the second electrode 6046. Also, indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITSO), or indium oxide containing silicon oxide to which 2 to 20% of zinc oxide (ZnO) is further mixed can be used for the second electrode 6046. In addition to the above light-transmissive oxide conductive materials, for example, a single-layer film composed of one or more of titanium nitride , zirconium nitride, titanium, tungsten, nickel, platinum, chromium, silver, aluminum etc., or a laminate of a film mainly composed of titanium nitride and aluminum , a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. can also be used for the second electrode 6046. However, when using a material other than the light-transmissive oxide conductive material, the second electrode 6046 is formed with a film thickness that allows light to pass through (preferably about 5 nm to 30 nm).

[0326] The electroluminescent layer 6045 can be formed in the same manner as the electroluminescent layer 6035 in FIG. 25(A). It is.

[0327] In the case of the pixel shown in FIG. 25(B), the light emitted from the light-emitting element 6043 can be extracted from the side of the second electrode 6046 as indicated by the white arrow. It can be taken out.

[0328] Next, FIG. 25(C) shows a cross-sectional view of a pixel in the case where the transistor 6051 is an n-type and the light emitted from the light-emitting element 6053 is extracted from the side of the first electrode 6054 and the side of the second electrode 6056. The transistor 6051 is covered with an insulating film 6057, and a partition wall 6058 having an opening is formed on the insulating film 6057. At the opening of the partition wall 6058, a part of the first electrode 6054 is exposed, and at the opening, the first electrode 6054, the electroluminescent layer 60 55, and the second electrode 6056 are laminated in this order. The first electrode 6054 can be formed in the same manner as the first electrode 6034 in FIG. 25(A). The second electrode 6056 can be formed in the same manner as the second electrode 6046 in FIG. 25(B). The electroluminescent layer 6055 can be formed in the same manner as the electroluminescent layer 6035 in FIG. 25(A).

[0329] The first electrode 6054 can be formed in the same manner as the first electrode 6034 in FIG. 25(A). The second electrode 6056 can be formed in the same manner as the second electrode 6046 in FIG. 25(B). The electroluminescent layer 6055 can be formed in the same manner as the electroluminescent layer 6035 in FIG. 25(A). It can be.

[0330] In the case of the pixel shown in FIG. 25(C), the light emitted from the light-emitting element 6053 can be extracted from the side of the first electrode 6054 and the side of the second electrode 6056 as indicated by the white arrow. It can be taken out. .

[0331] This embodiment can be implemented in appropriate combination with other embodiments.

Example

[0332] By using the semiconductor device according to one aspect of the present invention, an electronic device with high reliability and high-speed driving can be It is possible to provide. Further, by using the semiconductor display device according to one aspect of the present invention , it is possible to provide an electronic device capable of high-reliability display with high contrast and visibility .

[0333] Further, in the semiconductor device of the present invention, the temperature of the heat treatment in the manufacturing process can be suppressed . Therefore, even on a substrate made of a flexible synthetic resin such as plastic, which has inferior heat resistance to glass , it is possible to fabricate a thin film transistor with excellent characteristics and high reliability . Therefore, by using the manufacturing method according to one aspect of the present invention, it is possible to provide a highly reliable, lightweight and flexible semiconductor device. Examples of plastic substrates include polyesters typified by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), poly ether ether ketone (PEEK), polysulfone (PSF), polyetherimide ( PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide , acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, poly vinyl acetate, acrylic resin, and the like.

[0334] The semiconductor device according to one aspect of the present invention can be used in a display device, a notebook personal computer, a recording medium-equipped image playback device (typically a device having a display capable of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying the image). In addition, as electronic devices in which the semiconductor device according to one aspect of the present invention can be used, mobile phones, portable game machines, portable information terminals, electronic books, video cameras, digital cameras, etc. can be mentioned. Digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, all-in-one printers, automated teller machines (A TM), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 26.

[0335] FIG. 26(A) is an e-book, which has a housing 7001, a display unit 7002, etc. The semiconductor display device according to one aspect of the present invention can be used for the display unit 7002. By using the semiconductor display device according to one aspect of the present invention for the display unit 7002, an e-book capable of providing a highly reliable display with high contrast and visibility can be provided. Further, the semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the drive of the e-book. By using the semiconductor device according to one aspect of the present invention for an integrated circuit for controlling the drive of the e-book, an e-book capable of providing a highly reliable and high-speed drive can be provided. Further, by using a flexible substrate, flexibility can be imparted to the semiconductor device and the semiconductor display device, so that a flexible, lightweight, and easy-to-use e-book can be provided.

[0336] FIG. 26(B) is a display device, which has a housing 7011, a display unit 7012, a support base 7013, etc. The semiconductor display device according to one aspect of the present invention can be used for the display unit 7012. By using the semiconductor display device according to one aspect of the present invention for the display unit 7012, a display device capable of providing a highly reliable display with high contrast and visibility can be provided. Further, the semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the drive of the display device. of the present invention can be used for an integrated circuit for controlling the drive of the display device. It is possible. By using the semiconductor device according to one aspect of the present invention in an integrated circuit for controlling the driving of a display device, a display device with high reliability and capable of high-speed driving can be provided. Note that the display device includes all information display devices such as those for personal computers, TV broadcast reception, and advertisement display.

[0337] FIG. 26(C) shows a display device having a housing 7021, a display unit 7022, etc. The semiconductor display device according to one aspect of the present invention can be used for the display unit 7022. By using the semiconductor display device according to one aspect of the present invention for the display unit 7022, a display device capable of providing a display with high reliability, high contrast, and high visibility can be provided. Further, the semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the driving of a display device. By using the semiconductor device according to one aspect of the present invention in an integrated circuit for controlling the driving of a display device, a display device with high reliability and capable of high-speed driving can be provided. Also, by using a flexible substrate, the semiconductor device and the semiconductor display device can be made flexible, so that a flexible, lightweight, and easy-to-use display device can be provided. Therefore, as shown in FIG. 26(C), the display device can be fixed to a fabric or the like and used, and the range of application of the display device is significantly expanded.

[0338] FIG. 26(D) shows a portable game machine having a housing 7031, a housing 7032, a display unit 7033, a display unit 7034, a microphone 7035, a speaker 7036, operation keys 7037, a It can be used for the display unit 7034. By using the semiconductor display device according to one aspect of the present invention in the display unit 7033 and the display unit 7034, a portable game machine with high reliability, high contrast, and high visibility can be provided. Further, the semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the drive of a portable game machine. By using the semiconductor device according to one aspect of the present invention in the integrated circuit for controlling the drive of a portable game machine, a portable game machine with high reliability and capable of high-speed driving can be provided. Note that the portable game machine shown in FIG. 26(D) has two...

Claims

1. An oxide semiconductor film containing In, Ga, and Zn, a first conductive film and a second conductive film having regions positioned so as to sandwich the oxide semiconductor film therebetween, a first silicon oxide film positioned between the oxide semiconductor film and the first conductive film and having a region in contact with the oxide semiconductor film, a second silicon oxide film positioned between the oxide semiconductor film and the second conductive film and having a region in contact with the oxide semiconductor film, a third conductive film having a region in contact with the oxide semiconductor film, a fourth conductive film having a region in contact with the oxide semiconductor film, and the first conductive film and the second conductive film each have a function as a gate electrode, the third conductive film has a function as a source electrode, the fourth conductive film has a function as a drain electrode, in a cross-sectional view in the channel length direction, the length of the second conductive film is longer than the length of the oxide semiconductor film, and the length of the first conductive film is shorter than the length of the oxide semiconductor film, the third conductive film or the fourth conductive film contains titanium, tungsten, or molybdenum, a semiconductor device (however, excluding a semiconductor device in which the potential applied to the second conductive film is fixed and is lower than the potential applied to the third conductive film).

2. An oxide semiconductor film containing In, Ga, and Zn, a first conductive film and a second conductive film having regions positioned so as to sandwich the oxide semiconductor film therebetween, a first silicon oxide film positioned between the oxide semiconductor film and the first conductive film and having a region in contact with the oxide semiconductor film, a second silicon oxide film positioned between the oxide semiconductor film and the second conductive film and having a region in contact with the oxide semiconductor film, a third conductive film having a region in contact with the oxide semiconductor film, a fourth conductive film having a region in contact with the oxide semiconductor film, and the first conductive film and the second conductive film each have a function as a gate electrode, different potentials are applied to the first conductive film and the second conductive film, respectively, the third conductive film has a function as a source electrode, the fourth conductive film has a function as a drain electrode, in a cross-sectional view in the channel length direction, the length of the second conductive film is longer than the length of the oxide semiconductor film, and the length of the first conductive film is shorter than the length of the oxide semiconductor film, The third conductive film or the fourth conductive film includes titanium, tungsten, or molybdenum, and is a semiconductor device (excluding semiconductor devices in which the potential applied to the second conductive film is fixed and is lower than the potential applied to the third conductive film).

Images