Semiconductor device

Abstract

To provide a semiconductor device including a circuit that deteriorates less.SOLUTION: A semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. The first transistor has a first terminal thereof connected to a first wire, and a second terminal thereof connected to a second wire. The second transistor has a gate and a first terminal thereof connected to the first wire, and a second terminal thereof connected to a gate of the first transistor. The first switch is connected between the second wire and a third wire. The second switch is connected between the second wire and the third wire. The third switch is connected between the gate of the first transistor and the third wire.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a driving method thereof. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single crystal semiconductors are used to form a pixel region. The technology of configuring driving circuits such as gate drivers on the board reduces manufacturing costs and improves reliability. It is being actively developed to make a significant contribution to

[0003] However, transistors using non-single crystal semiconductors are subject to degradation. As a result, the mobility is reduced. In particular, in the gate driver, A transistor ( This degradation is most noticeable in the case of the gate signal When the line is not selected, the pull-down transistor turns on to This is because a negative voltage is supplied to the gate signal line. In other words, the gate signal line is not selected. Therefore, the pull-down transistor is on for most of the frame period. do.

[0004] To solve this problem, Patent Document 1 describes a method for suppressing the deterioration of a pull-down transistor. In Patent Document 1, a gate driver capable of In order to suppress deterioration, a circuit capable of outputting a pulse (for example, FIG. 7 of Patent Document 1) is used. A holding control unit 350 is provided for each stage of the gate driver. Then, the conduction state of the pull-down transistor is controlled using the output signal of the circuit. When the circuit outputs a pulse in synchronization with a clock signal or the like. Therefore, the time during which the pull-down transistor is turned on can be shortened, so that deterioration of the pull-down transistor can be suppressed. However, the circuit capable of outputting the above pulse includes a transistor Q32 that is turned on during most of one frame period. For this reason, the transistor Q32 deteriorates. Since the time during which the pull-down transistor is turned on can be shortened, deterioration of the pull-down transistor can be suppressed. However, the circuit capable of outputting the above pulse includes a transistor Q32 that is turned on during most of one frame period. For this reason, the transistor Q32 deteriorates. However, the circuit capable of outputting the above pulse includes a transistor Q32 that is turned on during most of one frame period. For this reason, the transistor Q32 deteriorates. However, the circuit capable of outputting the above pulse includes a transistor Q32 that is turned on during most of one frame period. For this reason, the transistor Q32 deteriorates. However, the circuit capable of outputting the above pulse includes a transistor Q32 that is turned on during most of one frame period. For this reason, the transistor Q32 deteriorates.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present invention suppresses deterioration of the first to second transistors and the first to third switches in a semiconductor device having the first to second transistors and the first to third switches. Or, in a semiconductor device having the first to fifth transistors, deterioration of the first to fifth transistors is suppressed. Or, in a semiconductor device further having a sixth transistor, deterioration of the first to sixth transistors is suppressed. Or, in a semiconductor device further having a seventh transistor, deterioration of the first to seventh transistors is suppressed. One aspect of the present invention suppresses deterioration of the first to second transistors and the first to third switches in a semiconductor device having the first to second transistors and the first to third switches. Or, in a semiconductor device having the first to fifth transistors, deterioration of the first to fifth transistors is suppressed. Or, in a semiconductor device further having a sixth transistor, deterioration of the first to sixth transistors is suppressed. Or, in a semiconductor device further having a seventh transistor, deterioration of the first to seventh transistors is suppressed. One aspect of the present invention suppresses deterioration of the first to second transistors and the first to third switches in a semiconductor device having the first to second transistors and the first to third switches. Or, in a semiconductor device having the first to fifth transistors, deterioration of the first to fifth transistors is suppressed. Or, in a semiconductor device further having a sixth transistor, deterioration of the first to sixth transistors is suppressed. Or, in a semiconductor device further having a seventh transistor, deterioration of the first to seventh transistors is suppressed. One aspect of the present invention suppresses deterioration of the first to second transistors and the first to third switches in a semiconductor device having the first to second transistors and the first to third switches. Or, in a semiconductor device having the first to fifth transistors, deterioration of the first to fifth transistors is suppressed. Or, in a semiconductor device further having a sixth transistor, deterioration of the first to sixth transistors is suppressed. Or, in a semiconductor device further having a seventh transistor, deterioration of the first to seventh transistors is suppressed. One aspect of the present invention suppresses deterioration of the first to second transistors and the first to third switches in a semiconductor device having the first to second transistors and the first to third switches. Or, in a semiconductor device having the first to fifth transistors, deterioration of the first to fifth transistors is suppressed. Or, in a semiconductor device further having a sixth transistor, deterioration of the first to sixth transistors is suppressed. Or, in a semiconductor device further having a seventh transistor, deterioration of the first to seventh transistors is suppressed. One aspect of the present invention suppresses deterioration of the first to second transistors and the first to third switches in a semiconductor device having the first to second transistors and the first to third switches. Or, in a semiconductor device having the first to fifth transistors, deterioration of the first to fifth transistors is suppressed. Or, in a semiconductor device further having a sixth transistor, deterioration of the first to sixth transistors is suppressed. Or, in a semiconductor device further having a seventh transistor, deterioration of the first to seventh transistors is suppressed.

Means for Solving the Problems

[0007] One aspect of the present invention is a first transistor, a second transistor, a first switch, a second It has a switch and a third switch. The first terminal of the first transistor is connected to the first wiring, the second terminal is connected to the second wiring, the gate and the first terminal of the second transistor are connected to the first wiring, the second terminal is connected to the gate of the first transistor, the first switch is connected between the second wiring and the third wiring, the second switch is connected between the second wiring and the third wiring, and the third switch is connected between the gate of the first transistor and the third wiring. It is a semiconductor device.

[0008] In the above aspect, it has a first period and a second period. In the first period, the first switch, the second switch and the third switch are turned off, the potential of the first wiring becomes the H level, and in the second period, the first switch is turned off, the second switch and the third switch are turned on, and the potential of the first wiring may become the L level.

[0009] One aspect of the present invention has a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor. The first terminal of the first transistor is connected to the first wiring, the second terminal is connected to the second wiring, the gate and the first terminal of the second transistor are connected to the first wiring, the second terminal is connected to the gate of the first transistor, the gate of the third transistor is connected to the fourth wiring, the first terminal is connected to the third wiring, the second terminal is connected to the second wiring, the gate of the fourth transistor is connected to the fifth wiring, the first terminal is connected to the third wiring, the second terminal is connected to the second wiring, the gate of the fifth transistor is connected to the fifth wiring, the first terminal is connected to the third wiring, and the second terminal is connected to the second wiring. ​​​​​​​A semiconductor device in which a second terminal is connected to the gate of a first transistor, and continues.

[0010] In the above aspect, the channel width of the fifth transistor is larger than the channel width of the second transistor, and the channel width of the second transistor may be larger than the channel width of the first transistor. In the above aspect, it may have a sixth transistor, the gate of the sixth transistor is connected to a second wiring, the first terminal is connected to a third wiring, and the second terminal is connected to a sixth wiring. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level.

[0011] In the above aspect, it may have a seventh transistor, the gate of the seventh transistor is connected to the fourth wiring, the first terminal is connected to the first wiring, and the second terminal is connected to the sixth wiring. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it may have a seventh transistor, the gate of the seventh transistor is connected to the fourth wiring, the first terminal is connected to the first wiring, and the second terminal is connected to the sixth wiring.

[0012] In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level. In the above aspect, it has a period A and a period B. In period A, the potential of the first wiring becomes the H level, the potentials of the fifth wiring and the fourth wiring become the L level, the first transistor, the second transistor, and the sixth transistor turn on, the third transistor, the fourth transistor, and the fifth transistor turn off, and the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, and the sixth transistor turn off, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level.

[0013] In the above aspect, it may have a seventh transistor, the gate of the seventh transistor is connected to the fourth wiring, the first terminal is connected to the first wiring, and the second terminal is connected to the sixth wiring. In the above aspect, it may have a seventh transistor, the gate of the seventh transistor is connected to the fourth wiring, the first terminal is connected to the first wiring, and the second terminal is connected to the sixth wiring. In the above aspect, it may have a seventh transistor, the gate of the seventh transistor is connected to the fourth wiring, the first terminal is connected to the first wiring, and the second terminal is connected to the sixth wiring.

[0014] In the above aspect, it has periods A, B, C, D, and E, and in period A , the potential of the first wiring becomes the H level, and the potentials of the fifth wiring and the fourth wiring become the L level , the first transistor, the second transistor, and the sixth transistor turn on , the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor turn off , the potential of the sixth wiring becomes the L level. In period B, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level , the first transistor, the second transistor, the third transistor, and the sixth transistor turn off , the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring becomes the L level. In period C, the potential of the first wiring becomes the L level , the potentials of the fifth wiring and the fourth wiring become the H level, the first transistor, the second transistor, and the sixth transistor turn off, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor turn on, and the potential of the sixth wiring becomes the L level. In period D, the potential of the first wiring becomes the H level, the potential of the fifth wiring becomes the L level, the potential of the fourth wiring becomes the H level, the first transistor, the second transistor, the third transistor, and the seventh transistor turn on, the fourth transistor, the fifth transistor, and the sixth transistor turn off, and the potential of the sixth wiring becomes the H level. In period E, the potential of the first wiring becomes the L level, the potential of the fifth wiring becomes the H level, the potential of the fourth wiring becomes the L level, the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor turn off becomes F, the fourth transistor and the fifth transistor turn on, and the potential of the sixth wiring may become the L level.

[0015] In each aspect of the present invention described above, various forms of switches can be used. As the switch, an electrical switch, a mechanical switch, or the like can be used. That is, the switch only needs to be able to control current and is not limited to a specific one. Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. Examples of mechanical switches include switches using MEMS (Micro-Electro-Mechanical System) technology such as digital micromirror devices (DMD). The switch has electrodes that can be mechanically moved, and by moving the electrodes, conduction and non-conduction are controlled for operation. tky diodes, MIM (Metal Insulator Metal) diodes, M IS (Metal Insulator Semiconductor) diodes, da ode-connected transistors, etc.), or a logic circuit combining these. As for mechanical switches, there are switches using MEMS (Micro-Electro-Mechanical System) technology such as digital micromirror devices (DMD). The switch has electrodes that can be mechanically moved, and by moving the electrodes, conduction and non-conduction are controlled for operation. When a transistor is used as the switch, since the transistor operates merely as a switch, the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress the off-current, it is desirable to use a transistor with the polarity having a smaller off-current. Transistors with a small off-current include transistors having an LDD region or transistors having a multi-gate structure.

[0016] When a transistor is used as the switch, since the transistor operates merely as a switch, the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress the off-current, it is desirable to use a transistor with the polarity having a smaller off-current. When a transistor is used as the switch, since the transistor operates merely as a switch, the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress the off-current, it is desirable to use a transistor with the polarity having a smaller off-current. Transistors with a small off-current include transistors having an LDD region or transistors having a multi-gate structure. Transistors with a small off-current include transistors having an LDD region or transistors having a multi-gate structure. ​​

[0017] Also, in each aspect of the present invention described above, a transistor is used as the switch, and the potential of the source of the transistor operates at a value close to the potential of the low-potential side power supply (Vss, GND, 0V, etc.). In this case, it is desirable to use an N-channel type transistor as the switch. Conversely, when the potential of the source of the transistor operates at a value close to the potential of the high-potential side power supply (Vdd, etc.), it is desirable to use a P-channel type transistor as the switch. This is because in an N-channel type transistor, when the source operates at a value close to the potential of the low-potential side power supply, and in a P-channel type transistor, when the source operates at a value close to the potential of the high-potential side power supply, the absolute value of the voltage between the gate and the source can be increased. Therefore, as the switch, more accurate operation can be performed. Or, since the transistor is less likely to perform source follower operation, the magnitude of the output voltage is less likely to decrease. This is the reason.

[0018] Also, in each aspect of the present invention described above, as the switch, both an N-channel type transistor and a P channel type transistor may be used to form a CMOS type switch. When a CMOS type switch is used, since current flows as soon as either the P-channel type transistor or the N-channel type transistor conducts, it becomes easy to function as a switch. Thus, even when the voltage of the input signal to the switch is high or low, an appropriate voltage can be output. Or, since the voltage amplitude value of the signal for turning the switch on or off can be reduced, the power consumption can be reduced.

[0019] When using a transistor as a switch, the switch is connected to the input terminal (source or One of the drain terminals), the output terminal (the other of the source or drain), and the terminal that controls conduction On the other hand, when a diode is used as a switch, A switch may not have a terminal that controls conduction. However, using a diode as a switch reduces the amount of wiring required to control the terminal. can be done.

[0020] In the invention disclosed in this specification, transistors of various structures are used as transistors. In other words, there is no limitation on the configuration of the transistors used.

[0021] In this specification, a semiconductor device is a semiconductor element (transistor, diode, silicon However, the function of the device is not limited to the semiconductor characteristics. Any device that can be used for semiconductor devices, or any device that has semiconductor material, may be called a semiconductor device. In the specification, a display device refers to a device having a display element.

[0022] In this specification, a driving device refers to a device having semiconductor elements, electric circuits, and electronic circuits. For example, a transistor (selection transistor) that controls the input of a signal from a source signal line to a pixel (sometimes called a transistor for driving, switching, etc.) a transistor for supplying a voltage or a current to a light-emitting element, etc. is an example of a driving device. A circuit that supplies signals to the source signal lines (sometimes called a gate driver or gate line driver circuit) A pixel electrode (hereinafter sometimes referred to as a pixel electrode driver or a source line driver circuit) is an example of a driver device.

[0023] Also, the present invention relates to a display device, a semiconductor device, a lighting device, a cooling device, a light-emitting device, a reflecting device, and a driving device. The above-mentioned devices and the like can be combined with each other, and such devices are also included in the scope of the present invention. For example, a display device may include a semiconductor device and a light emitting device. The body device may have a display device and a driver.

[0024] In each aspect of the present invention, all of the circuits required to realize a predetermined function are implemented in the same A substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, an SOI substrate, etc.) In this way, it is possible to reduce the cost by reducing the number of parts, or to reduce the number of circuit parts. This improves reliability by reducing the number of connection points with the product.

[0025] In addition, it is possible to avoid forming all of the circuits required to realize a given function on the same substrate. In other words, part of the circuitry required to realize a given function is formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a certain function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. (or SOI substrate). The single crystal substrate (also called IC chip) on which another part of the circuitry required for the semiconductor device is formed is called COG ( By using the Chip On Glass (Chip On Glass) method, the IC is connected to the glass substrate and then attached to the glass substrate. It is possible to place the chip on the board. Or, the IC chip can be placed on the board using TAB (Tape Auto) Automated Bonding), COF (Chip On Film), SMT (Su rface Mount Technology), or using a printed circuit board or the like, it is possible to connect to the glass substrate.

[0026] In this specification, when it is explicitly described that X and Y are connected, it means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Here, X and Y are assumed to be objects (e.g., devices elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and includes those other than the connection relationship shown in the figure or the text.

[0027] As an example of the case where X and Y are electrically connected, an element (e.g., a switch, transistor, capacitor element, inductor, resistor element, diode etc.) that enables the electrical connection between X and Y can be connected by one or more between X and Y.

[0028] As an example of the case where X and Y are functionally connected, a circuit (e.g., a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source , a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or the amount of current, etc., an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit One or more circuits (such as a circuit, a control circuit, etc.) can be connected between X and Y. For example even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y then X and Y are considered to be functionally connected.

[0029] In this specification, for those described explicitly as singular, it is desirable to be singular. However, even in this case, it is also possible to be plural. Similarly, for those described explicitly as plural, it is desirable to be plural. However, even in this case it is also possible to be singular.

[0030] In the drawings of this application, there are cases where the size, layer thickness, or area is exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations, etc. can be included.

[0031] Note that technical terms are often used for the purpose of describing specific embodiments or examples, etc. However, one aspect of the present invention is not limited to be interpreted by technical terms.

[0032] Note that words not defined (including scientific and technical words such as technical terms or academic terms) can be used as having a meaning equivalent to the general meaning understood by a person skilled in the art. Words defined in a dictionary, etc. are preferably interpreted in a meaning that does not conflict with the background of the related art. ​​

[0033] Note that terms such as first, second, third, etc. are used to separately describe various elements, members, regions, layers, areas, etc. Therefore, terms such as first, second, third, etc. do not limit the order and number of elements, members , regions, layers, areas, etc. Further, for example, it is possible to replace "first 's" with "second's" or "third's", etc.

[0034] Also, terms indicating spatial arrangements such as "on", "above", "below", "beneath", "sideways", "right", "left", "diagonal", "rear", "front", "inside", "outside", or "within" are used to simply show, by means of a drawing, the relationship between one element or feature and another element or feature. However, it is not limited to such usage, and terms indicating these spatial arrangements may include other directions in addition to the direction depicted in the drawing. For example, when explicitly shown as Y on X, it is not limited to Y being above X. Since the configuration in the drawing can be inverted or rotated 180°, it is possible to include Y being below X. Thus, the term "on" can include the direction of "below" in addition to the direction of "on". However, it is not limited to this, and since the device in the drawing can be rotated in various directions, the term "on" can include directions such as "sideways ", "right", "left", "diagonal", "rear", "front", "inside", "outside", or "within" in addition to the directions of "on" and "below". That is, it can be appropriately interpreted according to the situation.

[0035] Note that it is explicitly stated that Y is formed on X, or Y is formed upon X. When described, it is not limited to the case where Y is formed in direct contact with X. Direct contact is not the case, that is, it shall also include the case where another object is interposed between X and Y. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0036] Therefore, for example, when it is explicitly described that layer Y is formed on (or above) layer X, it includes the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer.

[0037] Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to the case where Y is in direct contact with X, and it shall also include the case where another object is interposed between X and Y. Therefore, for example, when it is described that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer.

[0038] In addition, when it is explicitly described that Y is formed on X, on X, or above X, it shall also include the case where Y is formed diagonally above X. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer. When described, it is not limited to the case where layer Y is formed in direct contact with layer X, and the case where another layer (for example, layer Z etc.) is formed in direct contact with layer X and layer Y is formed in direct contact with it. Note that another layer (for example, layer Z etc.) may be a single layer or a multiple layer.

[0039] The same applies to the description that Y is below X or Y is beneath X.

[0040] One aspect of the present invention includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. The first terminal of the first transistor is connected to a first wiring, and the second terminal of the first transistor is connected to a second wiring. The first terminal of the second transistor is connected to the first wiring, and the second terminal of the second transistor is connected to the gate of the first transistor. The gate of the second transistor is connected to the first wiring. The first switch is connected between the second wiring and the third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

[0041] One aspect of the present invention can have a first period and a second period. In the first period, the first to third switches can be turned off. And the potential of the first wiring can become the H level. In the second period, the first switch can be turned off, and the second to third switches can be turned on. And the potential of the first wiring can become the L level.

Advantages of the Invention

[0042] In one aspect of the present invention, in a semiconductor device having first - second transistors and first - third switches, the time for the first - second transistors and the first - third switches to turn on can be shortened or the number of times they turn on can be reduced, so deterioration can be suppressed. Or, the first - In a semiconductor device having five transistors, the time for the first to fifth transistors to turn on can be shortened or the number of times they turn on can be reduced, so that deterioration can be suppressed. Or In a semiconductor device further having a sixth transistor, the time for the first to sixth transistors to turn on can be shortened or the number of times they turn on can be reduced, so that deterioration can be suppressed. Or In a semiconductor device further having a seventh transistor, the time for the first to seventh transistors to turn on can be shortened or the number of times they turn on can be reduced, so that deterioration can be suppressed.

Brief Description of the Drawings

[0043]

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Figure 45

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Figure 47

Best Mode for Carrying Out the Invention

[0044] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the embodiments should not be construed as being limited to the described content. In the configurations described below, the same part or parts having similar functions are denoted by common reference numerals among different drawings, and detailed descriptions of the same part or parts having similar functions are omitted.

[0045] (Embodiment 1) The configuration of this embodiment will be described with reference to FIG. 45(A). FIG. 45(A) shows a circuit diagram of the semiconductor device of this embodiment.

[0046] Circuit 100 includes transistor 101 (first transistor), switch 102S (first switch), switch 103S (second switch), transistor 104 (second transistor), and switch 105S (third switch).

[0047] Note that transistors 101 and 104 are of the N-channel type. An N-channel type transistor turns on when the potential difference (Vgs) between the gate and the source exceeds the threshold voltage (Vth). However, it is not limited thereto, and transistors 101 and 104 can be of the P-channel type. A P-channel type transistor turns on when the potential difference (Vgs) between the gate and the source is lower than the threshold voltage (Vth). .

[0048] The first terminal of transistor 101 is connected to wiring 112 (first wiring), and the second terminal of transistor 101 is connected to wiring 111 (second wiring). Switch 102S is connected between wiring 111 and wiring 115 (third wiring). Switch 103S is connected between wiring 111 and wiring 115. The first terminal of transistor 104 is connected to wiring 1 12, the second terminal of transistor 104 is connected to the gate of transistor 101, and the gate of transistor 104 is connected to wiring 112. Switch 105S is connected between wiring 115 and the gate of transistor 101.

[0049] Note that switches 102S, 103S, and 105S can have control terminals. In FIG. 45(B), the control terminal of switch 102S is connected to wiring 114 (fourth wiring), the control terminal of switch 103S is connected to wiring 113 (fifth wiring), and the control terminal of switch 105S is connected to wiring 113, showing the configuration in this case.

[0050] Note that transistors can be used as switches 102S, 103S, and 105S. FIG. 1(A) shows using a transistor as a switch. Examples of using transistors 102 (third transistor), 103 (fourth transistor), and 105 (fifth transistor) as switches 102S, 103S, and 105S respectively are shown. The first terminal of transistor 102 is connected to wiring 115, the second terminal of transistor 102 is connected to wiring 111, and the gate of transistor 102 is connected to wiring 114. Transistor ... The first terminal of transistor 103 is connected to wiring 115, and the second terminal of transistor 103 is connected to wiring 111, and the gate of transistor 103 is connected to wiring 113. The first terminal of transistor 105 is connected to wiring 115, and the second terminal of transistor 105 is connected to the gate of transistor 101, and the gate of transistor 105 is connected to wiring 11 3.

[0051] Note that transistors 102, 103, and 105 are of the same N-channel type as transistor 101. However, transistors 102, 103 , and 105 may also be of P-channel type.

[0052] Note that the connection point between the gate of transistor 101 and the second terminal of transistor 104, or the connection point between the gate of transistor 101 and the second terminal of transistor 105 is denoted as node 11.

[0053] Next, an example of a signal or voltage input or output to / from wirings 111 to 115, and the functions of these wirings will be described.

[0054] Signal OUT is output from wiring 111.

[0055] Signal IN1 is input to wiring 112. Signal IN2 is input to wiring 113. Signal IN3 is input to wiring 114.

[0056] Voltage V1 is supplied to wiring 115. Voltage V1 is a power supply voltage, a reference voltage, a ground voltage, earth, or a negative power supply voltage. However, it is not limited thereto, and a signal (For example, a clock signal or an inverted clock signal, etc.) may be input.

[0057] When described as an L-level signal, an L signal, an L-level potential, or a voltage V1, etc., these potentials are generally V1. When described as an H-level signal, an H signal, an H-level potential, or a voltage V2 etc., these potentials are generally V2 (V2 > V1). Note that "generally" includes various errors such as errors due to noise, process variations, variations in the device fabrication process and / or measurement errors (the same hereinafter).

[0058] For example, if the gate of a transistor is connected to a certain node and the potential of the node becomes the L level, it is assumed that the transistor turns off (or on). In this case, when the potential of the node becomes the L level, it means that the potential of the node becomes a value that can turn off (or on) the transistor. Or, when the potential of the node becomes the L level, it means that the potential of the node becomes a value that can reduce (or increase) the voltage (Vgs) between the gate and the source of the transistor to a degree that allows the circuit including the transistor to achieve a predetermined operation.

[0059] Note that if clock signals are used as signals IN1 to IN3, the clock signals can be balanced or unbalanced (also referred to as non - balanced). Balanced means that the period of being at the H level and the period of being at the L level in one cycle are generally equal. Unbalanced means that the period of being at the H level and the period of being at the L level are different.

[0060] ​​​​For example, a clock signal is used as signal IN1, and a signal whose phase is approximately 180° shifted from signal IN1 is used as signal IN2, and signals IN1 and IN2 are unbalanced. Suppose that. In this case, signal IN2 may not be the inverted signal of signal IN1.

[0061] Here, as shown in FIG. 5(A), signals or voltages are supplied to wirings 112 to 115 from circuit 150. Circuit 150 generates signals or voltages and supplies signals or voltages to wirings 112 to 115.

[0062] Circuit 150 can have circuits 151 to 154. Circuit 151 has a function of generating a signal or voltage and supplying the signal or voltage to wiring 112. Circuit 152 has a function of generating a signal or voltage and supplying the signal or voltage to wiring 113. Circuit 153 has a function of generating a signal or voltage and supplying the signal or voltage to wiring 114. Circuit 154 has a function of generating a signal or voltage and supplying the signal or voltage to wiring 115.

[0063] Circuits 150 to 154 each include an amplifier circuit in FIG. 5(B), a bipolar transistor in FIG. 5(C), a MOS transistor in FIG. 5(D), a capacitor element in FIG. 5(E), an inverter in FIG. 5(F), a DC voltage source in FIG. 5(G), an AC voltage source in FIG. 5(H), and / or a DC current source in FIG. 5(I), etc.

[0064] As shown in FIG. 5(A), protection circuit 160 is connected to wirings 112 to 114.

[0065] Next, the functions of circuit 100 and transistors 101 to 105 will be described.

[0066] ​Circuit 100 has a function of controlling the potential of wiring 111. Or, circuit 100 has a function of controlling the timing of supplying the potential of wiring 1 12, the potential of wiring 113, the potential of wiring 114, or the potential of wiring 115 to wiring 111 . Or, circuit 100 has a function of controlling the timing of supplying a signal or voltage to wiring 111. Or, circuit 100 has a function of controlling the timing of supplying an H signal or voltage V2 to wiring 111. Or circuit 100 has a function of controlling the timing of supplying an L signal or voltage V1 to wiring 111. Or, circuit 100 has a function of controlling the timing of increasing the potential of wiring 111 . Or, circuit 100 has a function of controlling the timing of decreasing the potential of wiring 111. Or, circuit 100 has a function of controlling the timing of maintaining the potential of wiring 111 . As described above, circuit 100 has a function as a control circuit. Note that circuit 100 does not necessarily have all of the above functions. Note that circuit 100 is controlled according to signals IN1 to IN3. In addition, as shown in FIG. 1(B), circuit 100 has a function as a logic circuit including AND. Specifically, circuit 100 has a function as a logic circuit combining a three-input AND and two NOTs. And, signal IN1 is input to the first input terminal of the AND, a signal obtained by inverting signal IN2 by the first NOT is input to the second input terminal of the AND, a signal obtained by inverting signal IN3 by the second NOT is input to the third input terminal of the AND, and signal OUT is output from the output of the AND. That is, circuit 100 has a function of realizing the logical expression shown in FIG. 1(C), or a function of realizing the truth table shown in FIG. 1(D).

[0067] ​ has a function.

[0068] Transistor 101 has a function of controlling the conduction state between wiring 112 and wiring 111. Or, transistor 101 has a function of controlling the timing at which the potential of wiring 112 is supplied to wiring 111. Or, when a signal or voltage is input to wiring 112, transistor 101 has a function of controlling the timing at which the signal or voltage input to wiring 112 is supplied to wiring 111. Or, transistor 101 has a function of controlling the timing at which the potential of wiring 111 is supplied with an H signal or voltage V2. Or, transistor 101 has a function of controlling the timing at which the potential of wiring 111 is supplied with an L signal or voltage V1. Or, transistor 101 has a function of controlling the timing at which the potential of wiring 111 is increased. Or, transistor 101 has a function of controlling the timing at which the potential of wiring 111 is decreased. Or, transistor 101 has a function of performing a bootstrap operation. Or, transistor 101 has a function of increasing the potential of node 11 by means of a bootstrap operation. As described above, transistor 101 has a function as a switch or buffer. Note that transistor 101 does not necessarily have all of the above functions.

[0069] Transistor 102 has a function of controlling the conduction state between wiring 115 and wiring 111. Or, transistor 102 has a function of controlling the timing at which the potential of wiring 115 is supplied to wiring 111. Or, when a signal or voltage is input to wiring 115, transistor 102 has a function of controlling the timing at which the signal or voltage input to wiring 115 is supplied to wiring 111. Or, transistor 102 has a function of controlling the timing at which the signal or voltage input to wiring 115 is supplied to wiring 111. It has a function of controlling. Or, transistor 102 has a function of controlling the timing of supplying an L signal or voltage V1 to wiring 111. Or, transistor 102 has a function of controlling the timing of decreasing the potential of wiring 111. As described above, transistor 102 has a function as a switch. Note that transistor 102 does not necessarily have all of the above functions. Note that transistor 102 can be controlled by the potential of wiring 114 (signal IN3).

[0070] Transistor 103 has a function of controlling the conduction state between wiring 115 and wiring 111. Or, transistor 103 has a function of controlling the timing of supplying the potential of wiring 115 to wiring 111. Or, assuming that a signal or voltage is input to wiring 115, transistor 103 has a function of controlling the timing of supplying the signal or voltage input to wiring 115 to wiring 111. Or, transistor 103 has a function of controlling the timing of supplying an L signal or voltage V1 to wiring 111. Or, transistor 103 has a function of controlling the timing of decreasing the potential of wiring 111. As described above, transistor 103 has a function as a switch. Note that transistor 103 does not necessarily have all of the above functions. Note that transistor 103 can be controlled by the potential of wiring 113 (signal IN2).

[0071] Transistor 104 has a function of controlling the conduction state between wiring 112 and node 11. Or, transistor 104 has a function of controlling the timing of supplying the potential of wiring 112 to node 11. It has a function of controlling. Or, when a signal or voltage is input to wiring 112, the trans istor 104 controls the timing of supplying the signal or voltage input to wiring 112 to node 11. It has a function of controlling. Or, the transistor 104 has a function of controlling the timing of supplying an H signal or voltage V2 to node 11. Or, the transistor 104 has a function of controlling the timing of raising the potential of node 11. Or, the transistor 104 has a function of floating node 11. As described above, the transistor 10 4 has a function as a switch, diode, or diode-connected transistor, etc. Note that the transistor 104 does not necessarily have all of the above functions. Note that the trans istor 104 can be controlled by the potential of wiring 112 (signal IN1) and / or the potential of node 11.

[0072] The transistor 105 has a function of controlling the conduction state between wiring 115 and node 11. Or, the transistor 105 has a function of controlling the timing of supplying the potential of wiring 115 to node 11. Or, when a signal or voltage is input to wiring 115, the trans istor 105 has a function of controlling the timing of supplying the signal or voltage input to wiring 115 to node 11. Or, the transistor 105 has a function of controlling the timing of supplying an L signal or voltage V1 to node 11. Or, the transistor 105 has a function of controlling the timing of decreasing the potential of node 11. As described above, the trans istor 105 has a function as a switch. Note that the transistor 105 does not necessarily have all of the above functions. Note that the transistor 105 is the potential of wiring 113 (signal​​ It can be controlled by signal IN2.

[0073] Next, the operation of circuit 100 will be described with reference to the truth table (also referred to as the operation table) in Fig. 1(D). Fig. 1(D) shows the truth table when signals IN1 to IN3 are digital signals. Therefore, there are 8 patterns of combinations of the H level and L level of signals IN1 to IN3. That is, circuit 100 can perform at least 8 patterns of operations. Here, each of the 8 patterns of operations will be described. Incidentally, circuit 100 does not necessarily perform all of these 8 patterns of operations, and it is possible to select and perform a part of them. Incidentally, circuit 100 can perform operations other than these 8 patterns of operations. For example, when signals IN1 to IN3 have three or more values, or when signals IN1 to IN3 are analog signals, circuit 100 can perform even more operations other than these 8 patterns. First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11.

[0074] Incidentally, circuit 100 does not necessarily perform all of these 8 patterns of operations, and it is possible to select and perform a part of them. Incidentally, circuit 100 can perform operations other than these 8 patterns of operations. For example, when signals IN1 to IN3 have three or more values, or when signals IN1 to IN3 are analog signals, circuit 100 can perform even more operations other than these 8 patterns. Incidentally, circuit 100 does not necessarily perform all of these 8 patterns of operations, and it is possible to select and perform a part of them. Incidentally, circuit 100 can perform operations other than these 8 patterns of operations. For example, when signals IN1 to IN3 have three or more values, or when signals IN1 to IN3 are analog signals, circuit 100 can perform even more operations other than these 8 patterns. For example, when signals IN1 to IN3 have three or more values, or when signals IN1 to IN3 are analog signals, circuit 100 can perform even more operations other than these 8 patterns. For example, when signals IN1 to IN3 have three or more values, or when signals IN1 to IN3 are analog signals, circuit 100 can perform even more operations other than these 8 patterns. For example, when signals IN1 to IN3 have three or more values, or when signals IN1 to IN3 are analog signals, circuit 100 can perform even more operations other than these 8 patterns.

[0075] First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. First, operation 1 of circuit 100 will be described with reference to Fig. 2(A). Since signal IN2 becomes the H level, transistor 105 turns on. Then, wiring 115 and node 11 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. Here, assume that the channel width of transistor 105 is larger than that of transistor 104. Thus, the potential of node 11 becomes the L level. At this time, the potential of node 11 is larger than V1 and smaller than V1 + Vth101 (Vth101 is the threshold voltage of transistor 101). As a result, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. And since signal IN2 becomes the H level, transistor 103 turns on. At this time, since signal IN3 becomes the H level, transistor 102 turns on. Then, since wiring 115 and wiring 111 become conductive, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Thus, the potential of wiring 111 becomes V1, so signal OUT becomes the L level. Note that "the channel width of transistor A is larger than that of transistor B" can be rephrased as "1 / W (W is the channel width) of transistor A is smaller than 1 / W of transistor B", " the L (L is the channel length) of transistor A is smaller than the L of transistor B", " 1 / L of transistor A is larger than 1 / L of transistor B", "

[0076] the W / L of transistor A is larger than the W / L of transistor B", " the Vgs (Vgs is the potential difference between the gate and the source) of transistor A is larger than the Vgs of transistor B", etc. When the transistor has a multi-gate structure and the transistor has a plurality of gates, "the number of gates of transistor A is smaller than the number of gates of transistor B", or "the reciprocal of the number of gates of transistor A is the transistor

[0077] B's​​​​​​​​​ It can be rephrased as "greater than the reciprocal of the number of gates of B".

[0078] Next, operation 2 of circuit 100 will be described with reference to FIG. 2(B). Operation 2 is different from operation 1 in that signal IN3 becomes the L level. Therefore, since signal IN3 becomes the L level transistor 102 turns off. However, although transistor 102 turns off transistor 103 turns on as in operation 1. That is, wiring 115 and wiring 111 become conductive as in operation 1, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level.

[0079] Next, operation 3 of circuit 100 will be described with reference to FIG. 2(C). Since signal IN2 becomes the L level, transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the H level, transistor 104 turns on. Then, wiring 112 and node 11 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. That is, the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to node 11. Then, the potential of node 1 1 starts to rise. Eventually, when the potential of node 11 becomes V1 + Vth101 + Va (Va is a positive number), transistor 101 turns on. Then, wiring 112 and wiring 11 1 become conductive, so the potential of wiring 112 (for example, signal IN1 at the H level) is supplied to wiring 111. After that, the potential of node 11 continues to rise. Eventually, node 11 1 11 ​When the potential of becomes V2 - Vth104 (Vth104 is the threshold voltage of transistor 104), transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. Thus, node 11 becomes floating while maintaining its potential at V2 - Vth104.

[0080] And since signal IN2 becomes the L level, transistor 103 turns off. At this time, since signal IN3 becomes the H level, transistor 102 turns on. Then, wiring 1 15 and wiring 111 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. That is, the potential of wiring 111 (for example, voltage V1) and the potential of wiring 112 (for example, the H-level signal IN1) are supplied to wiring 111. Here, it is assumed that the channel width of transistor 102 is larger than that of transistor 101. Therefore, the potential of wiring 111 becomes the L level. The potential of wiring 111 at this time is lower than the sum of voltage V1 and the threshold voltage of any one of transistors 101 to 105. Thus, since the potential of wiring 111 becomes the L level, signal OUT becomes the L level.

[0081] Next, operation 4 of circuit 100 will be described with reference to Fig. 3(A). Operation 4 is different from operation 3 in that signal IN3 becomes the L level. Therefore, since signal IN3 becomes the L level, transistor 102 turns off. At this time, since transistor 103 is also off, wiring 115 and wiring 111 become non-conductive. That is, the potential of wiring 112 (for example, the H-level signal IN1) is supplied to wiring 111. Therefore, wiring 1 111. ​The potential of 11 starts to rise. At this time, node 11 is in a floating state. Then, due to the parasitic capacitance between the gate and the second terminal of transistor 101, the potential of node 11 rises. As a result, the potential of node 11 becomes V2 + Vth101 + Va. This is the so-called bootstrap operation. Thus, since the potential of wiring 111 becomes V2, signal OUT becomes the H level. Due to the parasitic capacitance between the gate and the second terminal of transistor 101, the potential of node 11 rises. As a result, the potential of node 11 becomes V2 + Vth101 + Va. This is the so-called bootstrap operation. Thus, since the potential of wiring 111 becomes V2, signal OUT becomes the H level. becomes the H level.

[0082] Next, operation 5 of circuit 100 will be described with reference to FIG. 3(B). Since signal IN2 becomes the H level, transistor 105 turns on. Then, since wiring 115 and node 11 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the L level, transistor 104 turns off. Then, wiring 112 and node 11 are in a non-conductive state. That is, the potential of wiring 115 (for example, voltage V1) is supplied to node 11. Therefore, the potential of node 11 becomes V1. Then, since transistor 101 turns off, wiring 112 and wiring 111 are in a non-conductive state. Since signal IN2 becomes the H level, transistor 105 turns on. Then, since wiring 115 and node 11 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 11. Since wiring 115 and node 11 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 11. At this time, since signal IN1 is at the L level, transistor 104 turns off. Then, wiring 112 and node 11 are in a non-conductive state. Then, wiring 112 and node 11 are in a non-conductive state. That is, the potential of wiring 115 (for example, voltage V1) is supplied to node 11. Therefore, the potential of node 11 becomes V1. Then, since transistor 101 turns off, wiring 112 and wiring 111 are in a non-conductive state. Then, since transistor 101 turns off, wiring 112 and wiring 111 are in a non-conductive state. become non-conductive.

[0083] And since signal IN2 is at the H level, transistor 103 turns on. At this time, since signal IN3 is at the H level, transistor 102 turns on. Then, since wiring 115 and wiring 111 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. And since signal IN2 is at the H level, transistor 103 turns on. At this time, since signal IN3 is at the H level, transistor 102 turns on. Then, since wiring 115 and wiring 111 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Then, since wiring 115 and wiring 111 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. becomes the L level.

[0084] Next, operation 6 of circuit 100 will be described with reference to FIG. 3(C). Operation 6 is based on operation 5. Compared with [something not specified], the point where signal IN3 becomes the L level is different. Therefore, since signal IN3 becomes the L level, transistor 102 turns off. However, although transistor 102 turns off, transistor 103 turns on in the same way as in operation 5. That is, wiring 115 and wiring 111 become conductive in the same way as in operation 5, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. However, although transistor 102 turns off, transistor 103 turns on in the same way as in operation 5. That is, wiring 115 and wiring 111 become conductive in the same way as in operation 5, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive.

[0085] Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive. Next, operation 7 of circuit 100 will be described with reference to Fig. 4(A). Signal IN2 becomes the L level, so transistor 105 turns off. Then, wiring 115 and node 11 become non-conductive. At this time, since signal IN1 becomes the L level, transistor 104 turns off. Then, wiring 112 and node 11 become non-conductive. That is, node 11 becomes floating, so it maintains the potential in the previous state. Here, the potential of node 11 is lower than V1 + Vth101. Therefore, transistor 101 turns off, so wiring 112 and wiring 111 become non-conductive.

[0086] And, since signal IN2 becomes the L level, transistor 103 turns off. At this time, since signal IN3 becomes the H level, transistor 102 turns on. Then, wiring 115 and wiring 111 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. And, since signal IN2 becomes the L level, transistor 103 turns off. At this time, since signal IN3 becomes the H level, transistor 102 turns on. Then, wiring 115 and wiring 111 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. And, since signal IN2 becomes the L level, transistor 103 turns off. At this time, since signal IN3 becomes the H level, transistor 102 turns on. Then, wiring 115 and wiring 111 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. And, since signal IN2 becomes the L level, transistor 103 turns off. At this time, since signal IN3 becomes the H level, transistor 102 turns on. Then, wiring 115 and wiring 111 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level. And, since signal IN2 becomes the L level, transistor 103 turns off. At this time, since signal IN3 becomes the H level, transistor 102 turns on. Then, wiring 115 and wiring 111 become conductive, so the potential of wiring 115 (for example, voltage V1) is supplied to wiring 111. Therefore, since the potential of wiring 111 becomes V1, signal OUT becomes the L level.

[0087] Next, operation 8 of circuit 100 will be described with reference to Fig. 4(B). Operation 8 is [description about the relationship with operation 7 which is not provided in the original text, so it's hard to accurately translate this part without more context]. When compared, the point at which signal IN3 becomes the L level is different. Therefore, since signal IN3 becomes the L level, transistor 102 turns off. At this time, since transistor 103 is also off, wiring 115 and wiring 111 are in a non-conductive state. That is, wiring 111 becomes in an indeterminate state Z (floating state, floating condition, or high impedance state). Therefore, if there is no potential fluctuation due to noise or the like, the potential of wiring 111 maintains the value in the previous state. Thus, for example, assume that the operation immediately before operation 8 is one of operations 1 to 3 and operations 5 to 7. In this case, signal OUT becomes the L level. Or, for example, assume that the operation immediately before operation 8 is operation 4. In this case, signal OUT becomes the H level. Since it becomes the L level, transistor 102 turns off. At this time, since transistor 103 is also off, wiring 115 and wiring 111 are in a non-conductive state. That is, wiring 111 becomes in an indeterminate state Z (floating state, floating condition, or high impedance state). Therefore, if there is no potential fluctuation due to noise or the like, the potential of wiring 111 maintains the value in the previous state. Therefore, if there is no potential fluctuation due to noise or the like, the potential of wiring 111 maintains the value in the previous state. Thus, for example, assume that the operation immediately before operation 8 is one of operations 1 to 3 and operations 5 to 7. In this case, signal OUT becomes the L level. Or, for example, assume that the operation immediately before operation 8 is operation 4. In this case, signal OUT becomes the H level. Thus, for example, assume that the operation immediately before operation 8 is one of operations 1 to 3 and operations 5 to 7. In this case, signal OUT becomes the L level. Or, for example, assume that the operation immediately before operation 8 is operation 4. In this case, signal OUT becomes the H level. Thus, for example, assume that the operation immediately before operation 8 is one of operations 1 to 3 and operations 5 to 7. In this case, signal OUT becomes the L level. Or, for example, assume that the operation immediately before operation 8 is operation 4. In this case, signal OUT becomes the H level. Thus, for example, assume that the operation immediately before operation 8 is one of operations 1 to 3 and operations 5 to 7. In this case, signal OUT becomes the L level. Or, for example, assume that the operation immediately before operation 8 is operation 4. In this case, signal OUT becomes the H level. That is, wiring 111 becomes in an indeterminate state Z (floating state, floating condition, or high impedance state).

[0088] As described above, transistors 101 to 105 turn off in any of operations 1 to 8. Therefore, the time for which the transistor turns on can be shortened or the number of times the transistor turns on can be reduced, so that deterioration of the transistor can be suppressed. Therefore, the time for which the transistor turns on can be shortened or the number of times the transistor turns on can be reduced, so that deterioration of the transistor can be suppressed. Therefore, the time for which the transistor turns on can be shortened or the number of times the transistor turns on can be reduced, so that deterioration of the transistor can be suppressed. As a result, characteristic deterioration of the transistor (for example, an increase in threshold voltage or a decrease in mobility) can be suppressed. As a result, characteristic deterioration of the transistor (for example, an increase in threshold voltage or a decrease in mobility) can be suppressed.

[0089] Or, since deterioration of the transistor can be suppressed, or since it is possible to make all the polarities of the transistors included in circuit 100 N-channel type, as the semiconductor layer of the transistor, a material that is more likely to deteriorate than single-crystalline semiconductor (for example, non-single-crystalline semiconductor such as amorphous semiconductor or microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc.) can be used. Or, since deterioration of the transistor can be suppressed, or since it is possible to make all the polarities of the transistors included in circuit 100 N-channel type, as the semiconductor layer of the transistor, a material that is more likely to deteriorate than single-crystalline semiconductor (for example, non-single-crystalline semiconductor such as amorphous semiconductor or microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc.) can be used. Or, since deterioration of the transistor can be suppressed, or since it is possible to make all the polarities of the transistors included in circuit 100 N-channel type, as the semiconductor layer of the transistor, a material that is more likely to deteriorate than single-crystalline semiconductor (for example, non-single-crystalline semiconductor such as amorphous semiconductor or microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc.) can be used. Or, since deterioration of the transistor can be suppressed, or since it is possible to make all the polarities of the transistors included in circuit 100 N-channel type, as the semiconductor layer of the transistor, a material that is more likely to deteriorate than single-crystalline semiconductor (for example, non-single-crystalline semiconductor such as amorphous semiconductor or microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc.) can be used. Therefore, the number of processes can be reduced, the yield can be increased, and / or the manufacturing... Cost can be reduced. Or, for example, assume that the semiconductor device of the present embodiment is used in a display device. In this case, the display device can be made larger.

[0090] Or, considering the case where the transistor deteriorates, it is not necessary to increase the channel width of the transistor. Or, by the bootstrap operation, since the Vgs of the transistor can be increased, the channel width of the transistor can be decreased. Or, since the amplitude of the output signal can be made the same value as the power supply voltage or the same value as the amplitude of the signal, the amplitude of the output signal can be increased. Therefore, the channel width of the transistor controlled by the output signal can be decreased. That is, since the channel width of the transistor can be decreased, the area of the channel of the transistor can be decreased.

[0091] Or, since the area of the channel of the transistor can be decreased, the layout area can be decreased. As a result, for example, assume that the semiconductor device of the present embodiment is used in a display device. In this case, the resolution of the display device can be increased. Or, the frame of the display device can be made smaller.

[0092] Or, since the area of the channel of the transistor can be decreased, the area where the material having the function as a gate and the semiconductor layer overlap via the insulating layer can be decreased. As a result, it is possible to reduce the possibility that the material having the function as a gate and the semiconductor layer are short-circuited. Therefore, it is possible to reduce the variation in the output signal and prevent malfunction. ​​​​​​​​​​​such as increasing the yield, etc. can be achieved.

[0093] Or, it is possible to make all the transistors N-channel type, or make all the transistors P-channel type. Therefore, compared with a CMOS circuit, the number of process steps can be reduced, the yield can be improved, the reliability can be improved, or the manufacturing cost can be reduced. In particular , by making all the transistors N-channel type, the semiconductor layer of the transistor and as such, it becomes possible to use a non-single crystal semiconductor such as an amorphous semiconductor or a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. However, transistors using these semiconductor layers are liable to deteriorate. However, the semiconductor device of the present embodiment can suppress the deterioration of the transistor .

[0094] Next, in addition to Operations 1 to 8, operations that the circuit 100 can perform will be described.

[0095] First, in Operations 1 and 2, by making the channel width of the transistor 104 larger than the channel width of the transistor 1 05, the transistor 101 can be turned on. Then, since the wiring 112 and the wiring 111 are in a conductive state, the potential of the wiring 112 (for example, the signal IN1 of the H level) is supplied to the wiring 111. That is, to the wiring 111 are supplied the potential of the wiring 115 (for example, the voltage V1) and the potential of the wiring 112 (for example, the signal I N1 of the H level). In this case, by making the current supply ability of the transistor 101 small and making the potential of the wiring 111 a value slightly higher than V1, it is possible to make the signal OUT an L level. For this purpose, the channel width of the transistor 101 is the tran It is preferably smaller than the channel width of the resistor 102 or the channel width of the transistor 103. Alternatively, the Vgs of the transistor 101 is preferably smaller than V2 - V1. More preferably, it is preferably smaller than (V2 - V1) × 1 / 2. For example, by controlling the Vgs of the transistor 101, an analog voltage can be output from the wiring 111. That is, the circuit 100 can function as an analog buffer or an amplifier circuit. As another example, by making the channel width of the transistor 101 larger than the sum of the channel width of the transistor 102 and the channel width of the transistor 103, the signal OUT can be set to the H level. Next, it is assumed that the operation switches from operation 4 to operation 6 when the signal IN1 changes from the H level to the L level and the signal IN2 changes from the L level to the H level. In this case, as shown in FIG. 4(C), in operation 6, by turning on the transistor 101 for a while, the potential of the wiring 112 (for example, the signal IN1 at the L level) can be supplied to the wiring 111. By doing so, the fall time of the signal OUT can be shortened. To achieve this, it is possible to delay the timing at which the transistor 101 turns off compared to the timing at which the signal IN1 becomes the L level. Alternatively, it is possible to delay the timing at which the signal IN2 becomes the H level compared to the timing at which the signal IN1 becomes the L level.

[0096] Alternatively, it is possible to make the overshoot of the signal IN2 larger than the overshoot of the signal IN1. Alternatively, it is possible to make the channel width of the transistor 105 larger than the channel width of the transistor 103. By doing so, the potential of the wiring 112 (for example, the signal IN1 at the L level) can be supplied to the wiring 111. This can shorten the fall time of the signal OUT. To achieve this, the timing at which the transistor 101 turns off can be delayed compared to the timing at which the signal IN1 becomes the L level. Alternatively, the timing at which the signal IN2 becomes the H level can be delayed compared to the timing at which the signal IN1 becomes the L level. Alternatively, the overshoot of the signal IN2 can be made larger than the overshoot of the signal IN1. Alternatively, the channel width of the transistor 105 can be made larger than the channel width of the transistor 103. ​​​Alternatively, one electrode of the capacitor may be connected to the node 11. The other electrode of the capacitance element can be connected to a power supply line or a signal line (for example, a wiring 1). The capacitance element can be connected to a transistor (15, wiring 111, etc.). Parasitic transistors (e.g., transistor 101, transistor 104, or transistor 105) Alternatively, the wiring 113 may be a capacitor formed on the same substrate as the circuit 100. The signal can be provided by a circuit that is connected to the

[0097] Next, in operations 7 and 8, the potential of the node 11 is V1+Vth101+Va. In this case, the transistor 101 is turned on, and the wiring 112 and the wiring The line 111 is brought into electrical continuity. Then, the potential of the wiring 112 (for example, the signal IN1 at the L level) ) is supplied to the wiring 111. By doing so, particularly in operation 8, the voltage of the wiring 111 Since the potential can be fixed, the circuit can be made more resistant to malfunctions.

[0098] As described above, the semiconductor device of the present embodiment performs various operations in addition to the operations 1 to 8. It is possible.

[0099] Next, the ratio of the channel widths of the transistors 101 to 105 will be described.

[0100] First, the load driven by the transistors 104 and 105 (for example, the gate of the transistor 101) ) is a load driven by the transistors 101 to 103 (for example, a load connected to the wiring 111). (e.g., the gate of a transistor). The channel width is the channel width of the transistor 101, the channel width of the transistor 102, and and / or may be smaller than the channel width of the transistor 103. The channel width of the transistor 105 is the same as that of the transistor 101, and the channel width of the transistor 102. and / or the channel width of transistor 103. In such a case, the channel width of the transistor 101 is It is preferably 20 times or less the width of the panel, and more preferably 10 times or less. More preferably, it is 7 times or less. The channel width of the transistor 105 is preferably 10 times or less than the channel width of the transistor 105. It is preferably 5 times or less, and more preferably 3 times or less. I wish.

[0101] Next, when the signal OUT becomes L level, the potential of the wiring 115 (for example, the voltage V1) A signal is supplied to the wiring 111 through two transistors, a transistor 102 and a transistor 103. On the other hand, when the signal OUT becomes an H level, the potential of the wiring 112 (for example, For example, a high-level signal IN1 is wired through a single transistor called transistor 101. 111. Thus, the channel width of transistor 101 is The channel width of the transistor 102 and / or the channel width of the transistor 103 are larger than In such a case, the channel width of the transistor 101 is It is preferable that the channel width of the first transistor 102 or the second transistor 103 is three times or less. It is more preferable that the ratio is 2 times or less.

[0102] Next, assume that the signal IN1 goes to H level and the transistor 101 turns on. Assume that transistor 102 or transistor 103 is turned on. In this case, in order to set the potential of wiring 111 to the L level, the channel width of transistor 102 can be larger than the channel width of transistor 101. Or, the channel width of transistor 103 can be larger than the channel width of transistor 101. In such a case, the channel width of transistor 101 is preferably 1 times or less of the channel width of transistor 102 or transistor 103. More preferably, it is preferably 0.7 times or less.

[0103] Note that assume that signal IN1 becomes the H level and transistor 101 is turned on. At this time, transistor 103 is turned on, but transistor 102 is rarely turned on. Therefore, the channel width of transistor 103 can be smaller than the channel width of transistor 102.

[0104] Next, in operations 1 to 2, when transistors 104 and 105 are turned on, the potential of wiring 115 (for example, voltage V1) and the potential of wiring 112 (for example, signal IN1 at the H level) are supplied to node 11. Therefore, as already described, in order to set the potential of node 11 to the L level, the channel width of transistor 105 can be larger than the channel width of transistor 104. In such a case, the channel width of transistor 105 is preferably 15 times or less of the channel width of transistor 104. More preferably, it is preferably 10 times or less. Even more preferably, it is preferably 8 times or less. ​​​​It is preferably as follows. For example, by making the channel length of transistor 104 larger than the channel length of transistor 10 5, it is possible to make the W / L ratio of transistor 105 larger than the W / L ratio of transistor 10 4. In such a case, the channel length of transistor 10 4 is preferably 9 times or less the channel length of transistor 105 . More preferably, it is preferably 6 times or less. More preferably, it is preferably 3 times or less .

[0105] As described above, it is preferable to set the ratio of the channel widths of the transistors to appropriate values. Note that , considering the ratio of the sizes of the above transistors, the channel width of transistor 101 is preferably 100 μm or more and 1000 μm or less. More preferably, it is preferably 100 μ m or more, 300 μm or less, or 500 μm or more and 800 μm or less. The channel width of transistor 102 or the channel width of transistor 103 is preferably 100 μm or more and 1500 μm or less. More preferably, it is preferably 100 μm or more and 300 μ m or less, or 700 μm or more and 1200 μm or less. The channel width of transistor 10 4 is preferably 10 μm or more and 300 μm or less. More preferably it is preferably 20 μm or more and 100 μm or less. The channel width of transistor 105 is preferably 30 μm or more and 500 μm or less. More preferably, it is preferably 50 μ m or more and 150 μm or less.

[0106] Next, a semiconductor device having a configuration different from that of FIG. 1(A) will be described.

[0107] First, in the configuration described in FIG. 1(A), the first terminal of transistor 105 can be connected to a wiring different from wiring 11 5 (for example, wiring 112, etc.). Alternatively, the gate of transistor 105 can be connected to a wiring different from wiring 113 (for example, wiring 111, wiring 116, or node 11, etc.).

[0108] Note that voltage V2 can be supplied to wiring 116. Therefore, wiring 116 can have the function of a power supply line. For example, a signal can be input to wiring 116 . Therefore, wiring 116 can have the function of a signal line .

[0109] FIG. 6(A) shows a configuration in the semiconductor device of FIG. 1(A) where the first terminal of transistor 105 is connected to wiring 112. An H signal can be supplied to the first terminal of transistor 105 . Therefore, a reverse bias can be applied to transistor 105, so that the deterioration of transistor 105 can be suppressed .

[0110] FIG. 6(B) shows a configuration in the semiconductor device of FIG. 1(A) where the first terminal of transistor 105 is connected to wiring 112 and the gate of transistor 105 is connected to node 11 . An H signal can be supplied to the first terminal of transistor 105. Therefore , a reverse bias can be applied to transistor 105, so that the deterioration of transistor 105 can be suppressed

[0111] FIG. 6(C) shows a configuration in the semiconductor device of FIG. 1(A) where the first terminal of transistor 105 is ​​, the gate of the transistor 105 connected to the wiring 112 is configured to be connected to the wiring 116. As shown, an H-level signal IN1 can be supplied to the node 11 through the transistors 104 and 105. Therefore, the channel width of the transistor 104 can be made smaller.

[0112] Next, in the configuration described in FIGS. 1(A) and 6(A) to (C), the first terminal of the transistor 103 can be connected to a wiring (for example, the wiring 112) different from the wiring 115. Or, the gate of the transistor 103 can be connected to a wiring (for example, the wiring 111, the wiring 116, or the node 11, etc.) different from the wiring 113.

[0113] FIG. 6(D) shows a configuration in which the first terminal of the transistor 103 is connected to the wiring 112 in the semiconductor device of FIG. 1(A). An H signal can be supplied to the first terminal of the transistor 103. Therefore, a reverse bias can be applied to the transistor 103, so that the deterioration of the transistor 103 can be suppressed.

[0114] FIG. 6(E) shows a configuration in which the first terminal of the transistor 103 is connected to the wiring 112 and the gate of the transistor 103 is connected to the wiring 111 in the semiconductor device of FIG. 1(A). Therefore, a reverse bias can be applied to the transistor 103, so that the deterioration of the transistor 103 can be suppressed.

[0115] FIG. 6(F) shows a configuration in which the first terminal of the transistor 103 is connected to the wiring 112 and the gate of the transistor 103 is connected to the wiring 116 in the semiconductor device of FIG. 1(A). is shown. The signal IN1 at the H level can be supplied to the wiring 111 via the transistor 103 and the transistor 101. Therefore, the channel width of the transistor 101 can be made small.

[0116] Next, in the configuration described in FIGS. 1(A) and 6(A) to (F), the first terminal of the transistor 104 can be connected to a wiring different from the wiring 112 (for example, the wiring 116 or the like). Alternatively, the gate of the transistor 104 can be connected to a wiring different from the wiring 112 (for example, the wiring 116 or the like).

[0117] FIG. 7(A) shows a configuration in which the first terminal of the transistor 104 is connected to the wiring 116 in the semiconductor device of FIG. 1(A).

[0118] FIG. 7(B) shows a configuration in which the gate of the transistor 104 is connected to the wiring 116 in the semiconductor device of FIG. 1(A). The potential of the wiring 112 (for example, the signal IN1 at the L level) can be supplied via the transistor 104. Therefore, since the potential of the node 11 can be fixed, a semiconductor device that is resistant to noise can be obtained.

[0119] Next, in the configuration described in FIGS. 1(A), 6(A) to (F), and 7(A) to (B), the first terminal of the transistor 102 can be connected to a wiring different from the wiring 115 (for example, the wiring 113, the wiring 114, or the node 11). Alternatively, the first terminal of the transistor 103 and / or the first terminal of the transistor 105 can be connected to a wiring different from the wiring 115 (for example, the wiring 113, the wiring 114, or the node 11). ​​​​​​​​​​​​​​

[0120] In FIG. 7(C), in the semiconductor device of FIG. 1(A), the first terminal of transistor 102 is shown as being connected to wiring 113. An H signal can be supplied to the first terminal of transistor 102 Therefore, a reverse bias can be applied to transistor 102, so that deterioration of transistor 102 can be suppressed.

[0121] In FIG. 7(D), in the semiconductor device of FIG. 1(A), the first terminal of transistor 103, and the first terminal of transistor 105 are shown as being connected to wiring 114. An H signal can be supplied to the first terminal of transistor 103 or the first terminal of transistor 105. Therefore, a reverse bias can be applied to transistor 103 or transistor 105, so that deterioration of transistor 103 or transistor 105 can be suppressed.

[0122] Next, in the configurations described with reference to FIGS. 1(A), 6(A) to (F), and 7(A) to (D), each terminal or each electrode of the transistor can be connected to a separate wiring. For example, the first terminal of transistor 101 and the first terminal of transistor 104 can be connected to separate wirings. Or, the gate of transistor 103 and the gate of transistor 105 can be connected to separate wirings. Or, the first terminal of transistor 102, the first terminal of transistor 103, and the first terminal of transistor 105 can be connected to separate wirings. To achieve this, it is possible to divide the wiring into a plurality of wirings.

[0123] ​​In FIG. 7(E), in the semiconductor device of FIG. 1(A), the wiring 112 is divided into a plurality of wirings such as wiring 112A to 112B, the wiring 113 is divided into a plurality of wirings such as wiring 113A to 113B, and the wiring 115 is divided into a plurality of wirings such as wiring 115A to 115C. The first terminal of the transistor 101 is connected to the wiring 112A, the first terminal of the transistor 104 is connected to the wiring 112B, and the gate of the transistor 104 is connected to the wiring 112B. Or, the gate of the transistor 103 is connected to the wiring 113A, and the gate of the transistor 105 is connected to the wiring 113B. Or, the first terminal of the transistor 102 is connected to the wiring 115A, the first terminal of the transistor 103 is connected to the wiring 115B, and the first terminal of the transistor 105 is connected to the wiring 115C. is shown. And, the first terminal of the transistor 101 is connected to the wiring 112A, the first terminal of the transistor 104 is connected to the wiring 112B, and the gate of the transistor 104 is connected to the wiring 112B. Or, the gate of the transistor 103 is connected to the wiring 113A, and the gate of the transistor 105 is connected to the wiring 113B. Or, the first terminal of the transistor 102 is connected to the wiring 115A, the first terminal of the transistor 103 is connected to the wiring 115B, and the first terminal of the transistor 105 is connected to the wiring 115C. Note that the wirings 112A to 112B can have the same function as the wiring 112. Or, the wirings 113A to 113B can have the same function as the wiring 113. Or, the wirings 115A to 115C can have the same function as the wiring 115. Therefore, the signal IN1 can be input to the wirings 112A to 112B. Or, the signal IN2 can be input to the wirings 113A to 113B. Also, the voltage V1 can be supplied to the wirings 115A to 115C. For example, different voltages or different signals can be supplied to the wirings 112A to 112B. Or, different voltages or different signals can be supplied to the wirings 113A to 113B. Or, different voltages or different signals can be supplied to the wirings 115A to 115C. The first terminal of the transistor 101 is connected to the wiring 112A, the first terminal of the transistor 104 is connected to the wiring 112B, and the gate of the transistor 104 is connected to the wiring 112B. Or, the gate of the transistor 103 is connected to the wiring 113A, and the gate of the transistor 105 is connected to the wiring 113B. Or, the first terminal of the transistor 102 is connected to the wiring 115A, the first terminal of the transistor 103 is connected to the wiring 115B, and the first terminal of the transistor 105 is connected to the wiring 115C. The first terminal of the transistor 101 is connected to the wiring 112A, the first terminal of the transistor 104 is connected to the wiring 112B, and the gate of the transistor 104 is connected to the wiring 112B. Or, the gate of the transistor 103 is connected to the wiring 113A, and the gate of the transistor 105 is connected to the wiring 113B. Or, the first terminal of the transistor 102 is connected to the wiring 115A, the first terminal of the transistor 103 is connected to the wiring 115B, and the first terminal of the transistor 105 is connected to the wiring 115C. The first terminal of the transistor 101 is connected to the wiring 112A, the first terminal of the transistor 104 is connected to the wiring 112B, and the gate of the transistor 104 is connected to the wiring 112B. Or, the gate of the transistor 103 is connected to the wiring 113A, and the gate of the transistor 105 is connected to the wiring 113B. Or, the first terminal of the transistor 102 is connected to the wiring 115A, the first terminal of the transistor 103 is connected to the wiring 115B, and the first terminal of the transistor 105 is connected to the wiring 115C. The first terminal of the transistor 101 is connected to the wiring 112A, the first terminal of the transistor 104 is connected to the wiring 112B, and the gate of the transistor 104 is connected to the wiring 112B. Or, the gate of the transistor 103 is connected to the wiring 113A, and the gate of the transistor 105 is connected to the wiring 113B. Or, the first terminal of the transistor 102 is connected to the wiring 115A, the first terminal of the transistor 103 is connected to the wiring 115B, and the first terminal of the transistor 105 is connected to the wiring 115C. The first terminal of the transistor 101 is connected to the wiring 112A, the first terminal of the transistor 104 is connected to the wiring 112B, and the gate of the transistor 104 is connected to the wiring 112B. Or, the gate of the transistor 103 is connected to the wiring 113A, and the gate of the transistor 105 is connected to the wiring 113B. Or, the first terminal of the transistor 102 is connected to the wiring 115A, the first terminal of the transistor 103 is connected to the wiring 115B, and the first terminal of the transistor 105 is connected to the wiring 115C. is connected.

[0124] Note that the wirings 112A to 112B can have the same function as the wiring 112. Or, the wirings 113A to 113B can have the same function as the wiring 113. Or, the wirings 115A to 115C can have the same function as the wiring 115. Therefore, the signal IN1 can be input to the wirings 112A to 112B. Or, the signal IN2 can be input to the wirings 113A to 113B. Also, the voltage V1 can be supplied to the wirings 115A to 115C. For example, different voltages or different signals can be supplied to the wirings 112A to 112B. Or, different voltages or different signals can be supplied to the wirings 113A to 113B. Or, different voltages or different signals can be supplied to the wirings 115A to 115C. Note that the wirings 112A to 112B can have the same function as the wiring 112. Or, the wirings 113A to 113B can have the same function as the wiring 113. Or, the wirings 115A to 115C can have the same function as the wiring 115. is possible.

[0125] Next, in the configurations described in FIGS. 1(A), 6(A) to (F), and 7(A) to (E) , it is possible to newly provide the transistor 105A and / or the transistor 103A .

[0126] FIG. 8(A) shows a configuration in which the transistor 105A is newly provided in the semiconductor device of FIG. 1(A). The transistor 105A can correspond to the transistor 105 and can have a similar function. The first terminal of the transistor 105A is connected to the wiring 112 , the second terminal of the transistor 105A is connected to the node 11, and the gate of the transistor 105A is connected to the wiring 113. For example, similar to FIGS. 6(B) to (C), the gate of the transistor 105A can be connected to the node 11 or the wiring 116. For example, similar to FIGS. 6(B) to (C), the gate of the transistor 105A can be connected to a wiring different from the wiring 113 (for example, the node 11, the wiring 116, or the wiring 111, etc.). This is possible.

[0127] FIG. 8(B) shows a configuration in which the transistor 103A is newly provided in the semiconductor device of FIG. 1(A). The transistor 103A can correspond to the transistor 103 and can have a similar function. The first terminal of the transistor 103A is connected to the wiring 112 , the second terminal of the transistor 103A is connected to the wiring 111, and the gate of the transistor 103A is connected to the wiring 113. For example, similar to FIGS. 6(E) to (F), , the gate of the transistor 103A is a wiring different from the wiring 113 (for example, the wiring 111, the wiring It can be connected to 116 or Node 11, etc.

[0128] Next, in the configurations described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), and 8(A) to (B) it is possible to newly provide the transistor 106.

[0129] FIG. 8(C) shows a configuration in which the transistor 106 is newly provided in the semiconductor device of FIG. 1(A). The transistor 106 is of the N-channel type. However, the present embodiment is not limited to this, and the transistor 106 can be of the P-channel type. The first terminal of the transistor 106 is connected to the wiring 115, the second terminal of the transistor 106 is connected to the node 11, and the gate of the transistor 106 is connected to the wiring 114. The first terminal of the transistor 106 is connected to the wiring 115, the second terminal of the transistor 106 is connected to the node 11, and the gate of the transistor 106 is connected to the wiring 114. The first terminal of the transistor 106 is connected to the wiring 115, the second terminal of the transistor 106 is connected to the node 11, and the gate of the transistor 106 is connected to the wiring 114.

[0130] The function of the transistor 106 will be described. The transistor 106 has a function of controlling the conduction state between the wiring 115 and the node 11. Or, the transistor 106 has a function of controlling the timing of supplying the potential of the wiring 11 5 to the node 11. Or, assuming that a signal or voltage is input to the wiring 11 5, the transistor 106 has a function of controlling the timing of supplying the signal or voltage input to the wiring 115 to the node 11. Or, the transistor 106 has a function of controlling the timing of supplying the L signal or the voltage V1 to the node 11. Or, the transistor 106 has a function of controlling the timing of reducing the potential of the node 11. As described above, the transistor 106 can have a function as a switch. Note that the transistor 106 does not necessarily have all of the above functions. Note that the transistor 106 is based on the potential of the wiring 114 (signal IN3). 5 to the node 11. Or, the transistor 106 has a function of controlling the timing of supplying the signal or voltage input to the wiring 115 to the node 11. Or, the transistor 106 has a function of controlling the timing of supplying the L signal or the voltage V1 to the node 11. Or, the transistor 106 has a function of controlling the timing of reducing the potential of the node 11. As described above, the transistor 106 can have a function as a switch. Note that the transistor 106 does not necessarily have all of the above functions. Note that the transistor 106 is based on the potential of the wiring 114 (signal IN3). 106 has a function of controlling the timing of supplying the L signal or the voltage V1 to the node 11. Or, the transistor 106 has a function of controlling the timing of reducing the potential of the node 11. As described above, the transistor 106 can have a function as a switch. Note that the transistor 106 does not necessarily have all of the above functions. Note that the transistor 106 is based on the potential of the wiring 114 (signal IN3). 106 has a function of controlling the timing of reducing the potential of the node 11. As described above, the transistor 106 can have a function as a switch. Note that the transistor 106 does not necessarily have all of the above functions. Note that the transistor 106 is based on the potential of the wiring 114 (signal IN3). 106 can have a function as a switch. Note that the transistor 106 does not necessarily have all of the above functions. Note that the transistor 106 is based on the potential of the wiring 114 (signal IN3). 106 does not need to have all of the above functions. Note that the transistor 106 is based on the potential of the wiring 114 (signal IN3). It can be controlled.

[0131] The operation of the semiconductor device in Fig. 8(C) will be described. Operations 1, 3, 5, and 7 In this case, since the signal IN3 becomes high level, the transistor 106 turns on. Then , the wiring 115 and the node 11 are in a conductive state, so the potential of the wiring 115 (for example, voltage V1 ) is supplied to the node 11. Thus, the potential of the node 11 can be fixed, and a semiconductor device that is resistant to noise can be obtained. Or, since the potential of the node 11 can be made lower, the transistor 101 is more likely to turn off. Or, since the channel width of the transistor 105 can be reduced, the layout area can be reduced. On the other hand, in Operations 2, 4, 6, and 8, since the signal IN3 becomes low level, the transistor 106 turns off. Thus, since the time during which the transistor 106 is on can be shortened, the deterioration of the transistor 106 can be suppressed.

[0132] Next, in the configurations described in Fig. 1(A), Figs. 6(A) to (F), Figs. 7(A) to (E), and Figs. 8(A) to (C) it is possible to omit the transistor 103 and / or the transistor 105.

[0133] Fig. 8(D) shows a configuration in which the transistor 103 is omitted in the semiconductor device of Fig. 1(A). Even when the transistor 103 is omitted, for example, by delaying the timing at which the transistor 101 switches from on to off from the timing at which the signal IN1 changes from high level to low level, the potential of the wiring 112 (for example, the signal IN1 at low level) can be made...​​ It becomes possible to supply the wiring 111. Therefore, the potential of the wiring 111 can be set to V1. Thus, by omitting the transistor 103, the number of transistors can be reduced.

[0134] Note that in order to delay the timing at which the transistor 101 switches from on to off with respect to the timing at which the signal IN1 changes from the H level to the L level, the channel width of the transistor 105 can be made smaller than the channel width of the transistor 101. Alternatively, the area of the channel of the transistor 101 (for example, L×W) can be made the largest among the transistors included in the circuit 100.

[0135] FIG. 8(E) shows a configuration in which the transistor 105 is omitted in the semiconductor device of FIG. 1(A). By omitting the transistor 105, the number of transistors can be reduced.

[0136] Next, in the configurations described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), and 8(A) to (E), it is possible to connect a capacitor element 107 between the gate of the transistor 101 and the second terminal. For example, as the capacitor element, a MOS capacitor can be used.

[0137] FIG. 8(F) shows a configuration in which a capacitor element 107 is connected between the gate of the transistor 101 and the second terminal in the semiconductor device of FIG. 1(A). During the bootstrap operation, the potential of the node 11 is likely to increase. Therefore, the Vgs of the transistor 101 can be increased. As a result, the channel width of the transistor 101 can be made smaller. Alternatively, the fall time or rise time of the signal OUT can be shortened.

[0138] Note that the material of one electrode of the capacitor element 107 is preferably the same material as the gate of the transistor. Alternatively, the material of the other electrode of the capacitor element 107 is preferably the same material as the source or drain of the transistor. Thus, the layout area can be reduced. Alternatively, the capacitance value can be increased.

[0139] Note that the overlapping area between one electrode and the other electrode of the capacitor element 107 is preferably smaller than the overlapping area between the material used as the gate in the transistor 101 and the semiconductor layer.

[0140] Next, in the configuration described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), and 8(A) to (F) it is possible to newly provide a circuit 120 in the circuit 100.

[0141] FIG. 9(A) shows the configuration in the case where the circuit 120 is newly provided in the semiconductor device of FIG. 1(A). The circuit 120 is connected between the wiring 113 and the connection point between the gate of the transistor 103 and the gate of the transistor 1 05. The circuit 120 has a function of delaying the signal IN2 input to the wiring 113. Therefore, for example, the timing at which the potential of the gate of the transistor 105 rises is later than the timing at which the signal IN2 changes from the L level to the H level. That is, the timing at which the transistor 105 turns on, or the timing at which the potential of the node 11 decreases is delayed compared to the timing at which the signal IN2 changes from the L level to the H level. Therefore, for example, the timing at which the transistor 101 switches from on to off ​​​​ The ring can be made slower than the timing when the signal IN1 changes from the H level to the L level. As a result, since the signal IN1 at the L level can be supplied to the wiring 111, the fall time of the signal OUT can be shortened. For example, as shown in FIG. 9(B), the gate of the transistor 103 is connected to the wiring 113 without passing through the circuit 120, and the gate of the transistor 105 can be connected to the wiring 113 through the circuit 120. This is because the transistor 103 can supply the voltage V1 to the wiring 111 earlier if it turns on earlier. Therefore, the fall time of the signal OUT can be shortened. Another example is that the gate of the transistor 105 can be connected to the wiring 111 through the circuit 120. In this case, the gate of the transistor 103 can be connected to the gate of the transistor 105 or to the wiring 113. That is because the transistor 103 can supply the voltage V1 to the wiring 111 earlier if it turns on earlier. Therefore, the fall time of the signal OUT can be shortened. Another example is that the gate of the transistor 105 can be connected to the wiring 111 through the circuit 120. In this case, the gate of the transistor 103 can be connected to the gate of the transistor 105 or to the wiring 113. Another example is that the gate of the transistor 105 can be connected to the wiring 111 through the circuit 120. In this case, the gate of the transistor 103 can be connected to the gate of the transistor 105 or to the wiring 113. Another example is that the gate of the transistor 105 can be connected to the wiring 111 through the circuit 120. In this case, the gate of the transistor 103 can be connected to the gate of the transistor 105 or to the wiring 113. Another example is that the gate of the transistor 105 can be connected to the wiring 111 through the circuit 120. In this case, the gate of the transistor 103 can be connected to the gate of the transistor 105 or to the wiring 113. Another example is that the gate of the transistor 105 can be connected to the wiring 111 through the circuit 120. In this case, the gate of the transistor 103 can be connected to the gate of the transistor 105 or to the wiring 113.

[0142] Note that the circuit 120 may have at least a capacitive component and a resistive component. For example, as the circuit 120, a resistive element, a capacitive element, a transistor, a diode, a combination of these elements, or various other elements can be used. FIGS. 9(C) to (D) show a configuration in which the circuit 120 has a resistive element 121 and a capacitive element 122. Another example is that as the circuit 120, a buffer circuit, an inverter circuit, a NAND circuit, a NOR circuit, a level shifter circuit, a combination of these circuits, or various other circuits can be used. FIG. 9(E) shows a configuration in which the circuit 120 has a buffer circuit 123. FIG. 9(F) shows a configuration in which the circuit 120 has an inverter circuit 124. Another example is that as the circuit 120, a buffer circuit, an inverter circuit, a NAND circuit, a NOR circuit, a level shifter circuit, a combination of these circuits, or various other circuits can be used. FIG. 9(E) shows a configuration in which the circuit 120 has a buffer circuit 123. FIG. 9(F) shows a configuration in which the circuit 120 has an inverter circuit 124. Another example is that as the circuit 120, a buffer circuit, an inverter circuit, a NAND circuit, a NOR circuit, a level shifter circuit, a combination of these circuits, or various other circuits can be used. FIG. 9(E) shows a configuration in which the circuit 120 has a buffer circuit 123. FIG. 9(F) shows a configuration in which the circuit 120 has an inverter circuit 124. Another example is that as the circuit 120, a buffer circuit, an inverter circuit, a NAND circuit, a NOR circuit, a level shifter circuit, a combination of these circuits, or various other circuits can be used. FIG. 9(E) shows a configuration in which the circuit 120 has a buffer circuit 123. FIG. 9(F) shows a configuration in which the circuit 120 has an inverter circuit 124. Another example is that as the circuit 120, a buffer circuit, an inverter circuit, a NAND circuit, a NOR circuit, a level shifter circuit, a combination of these circuits, or various other circuits can be used. FIG. 9(E) shows a configuration in which the circuit 120 has a buffer circuit 123. FIG. 9(F) shows a configuration in which the circuit 120 has an inverter circuit 124. Another example is that as the circuit 120, a buffer circuit, an inverter circuit, a NAND circuit, a NOR circuit, a level shifter circuit, a combination of these circuits, or various other circuits can be used. FIG. 9(E) shows a configuration in which the circuit 120 has a buffer circuit 123. FIG. 9(F) shows a configuration in which the circuit 120 has an inverter circuit 124. .

[0143] Note that the capacitive component can be a parasitic capacitance, and the resistive component can be a parasitic resistance. That is, as the circuit 120, it is possible to use a wiring, a contact between a material of one layer and a material of another layer, or an FPC pad or the like. Therefore, for example, it is preferable that the wiring resistance of the wiring 113 is larger than the wiring resistance of the wiring 112. To achieve this, it is preferable that the minimum wiring width of the wiring 113 is smaller than the minimum wiring width of the wiring 112. Or, the wiring 113 can contain more of the material having the largest resistance value among conductive materials (for example, a material including the material of the pixel electrode) compared with the wiring 112. Or, for example, assume that a certain material is used for both the wiring 113 and the wiring 112. In this case, the minimum film thickness of the material that the wiring 113 has can be thinner than the minimum film thickness of the material that the wiring 112 has. Note that as the buffer circuit 123, it is possible to use the configuration shown in FIG. 9(G). The buffer circuit includes a transistor 125, a transistor 126, a transistor 127, and a transistor 128. The first terminal of the transistor 125 is connected to the wiring 129, the second terminal of the transistor 125 is connected to the gate of the transistor 103, and the gate of the transistor 125 is connected to the wiring 113. The first terminal of the transistor 126 is connected to the wiring 130, the second terminal of the transistor 126 is connected to the gate of the transistor 103. The first terminal of the transistor 127 is connected to the wiring 129, the second terminal of the transistor 127 is connected to the gate of the transistor 126, and the transistor Further, for example, assume that a certain material is used for both the wiring 113 and the wiring 112. In this case, the minimum film thickness of the material that the wiring 113 has can be thinner than the minimum film thickness of the material that the wiring 112 has.

[0144] Note that as the buffer circuit 123, it is possible to use the configuration shown in FIG. 9(G). The buffer circuit includes a transistor 125, a transistor 126, a transistor 127, and a transistor 128. The first terminal of the transistor 125 is connected to the wiring 129, the second terminal of the transistor 125 is connected to the gate of the transistor 103, and the gate of the transistor 125 is connected to the wiring 113. The first terminal of the transistor 126 is connected to the wiring 130, the second terminal of the transistor 126 is connected to the gate of the transistor 103. The first terminal of the transistor 127 is connected to the wiring 129, the second terminal of the transistor 127 is connected to the gate of the transistor 126, and the transistor The first terminal of the transistor 127 is connected to the wiring 129, and the second terminal of the transistor 127 is connected to the gate of the transistor 126, and the transistor The first terminal of the transistor 127 is connected to the wiring 129, and the second terminal of the transistor 127 is connected to the gate of the transistor 126, and the transistor​ The gate of 127 is connected to wiring 129. The first terminal of transistor 128 is connected to wiring 130, the second terminal of transistor 128 is connected to the gate of transistor 126, and the gate of transistor 128 is connected to wiring 113. Note that a high voltage such as voltage V2 is often supplied to wiring 129, and a negative voltage such as voltage V1 is supplied to wiring 130.

[0145] Note that as the inverter circuit 124, the configuration shown in FIG. 9(H) can be used. The inverter circuit includes transistors 131, 132, 133, and transistor 134. The first terminal of transistor 131 is connected to wiring 129, the second terminal of transistor 131 is connected to the gate of transistor 103, the first terminal of transistor 132 is connected to wiring 130, the second terminal of transistor 132 is connected to the gate of transistor 103, and the gate of transistor 132 is connected to wiring 113. The first terminal of transistor 133 is connected to wiring 129, the second terminal of transistor 133 is connected to the gate of transistor 131, and the gate of transistor 133 is connected to wiring 129. The first terminal of transistor 134 is connected to wiring 130, the second terminal of transistor 134 is connected to the gate of transistor 131, and the gate of transistor 134 is connected to wiring 113.

[0146] Next, in the configurations described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), 8(A) to (F), and also FIGS. 9(A) to (B), replace the transistors with diodes. This is possible. For example, it is possible to connect a transistor in diode connection.

[0147] FIG. 11(A) shows a configuration in which the transistors in the semiconductor device of FIG. 1(A) are replaced with diodes. The transistor 101 can be replaced with a diode 101d in which one electrode (for example, an input terminal) is connected to the node 11 and the other electrode (for example, an output terminal) is connected to the wiring 111. Or, the transistor 102 can be replaced with a diode 102d in which one electrode (for example, an input terminal) is connected to the wiring 111 and the other electrode (for example, an output terminal) is connected to the wiring 114. Or, the transistor 103 can be replaced with a diode 103d in which one electrode (for example, an input terminal) is connected to the wiring 111 and the other electrode (for example, an output terminal) is connected to the wiring 113. Or, the transistor 104 can be replaced with a diode 104d in which one electrode (for example, an input terminal) is connected to the wiring 112 and the other electrode (for example, an output terminal) is connected to the node 11. Or, the transistor 105 can be replaced with a diode 105d in which one electrode (for example, an input terminal) is connected to the node 11 and the other electrode (for example, an output terminal) is connected to the wiring 113. By doing so, the number of signals or power sources can be reduced. That is, the number of wirings can be reduced. Therefore, the number of connections between the substrate on which the circuit 100 is formed and the substrate for supplying signals to the substrate can be reduced, so that the reliability, yield, or manufacturing cost can be improved. A plurality of transistors (for example, transistors) included in the circuit 100 The circuit 100 can be replaced with a diode 104d in which one electrode (for example, an input terminal) is connected to the wiring 112 and the other electrode (for example, an output terminal) is connected to the node 11. Or, the transistor 105 can be replaced with a diode 105d in which one electrode (for example, an input terminal) is connected to the node 11 and the other electrode (for example, an output terminal) is connected to the wiring 113. By doing so, the number of signals or power sources can be reduced. That is, the number of wirings can be reduced. Therefore, the number of connections between the substrate on which the circuit 100 is formed and the substrate for supplying signals to the substrate can be reduced, so that the reliability, yield, or manufacturing cost can be improved. By doing so, the number of signals or power sources can be reduced. That is, the number of wirings can be reduced. Therefore, the number of connections between the substrate on which the circuit 100 is formed and the substrate for supplying signals to the substrate can be reduced, so that the reliability, yield, or manufacturing cost can be improved. Therefore, the number of connections between the substrate on which the circuit 100 is formed and the substrate for supplying signals to the substrate can be reduced, so that the reliability, yield, or manufacturing cost can be improved. For example, the number of transistors included in the circuit 100 Some of the transistors (101 to 105) can be replaced by diodes. 。

[0148] FIG. 11(B) shows the configuration of the semiconductor device of FIG. 1(A) when the transistor is diode-connected. The first terminal of the transistor 101 can be connected to the node 11. Alternatively, the first terminal of the transistor 102 is connected to the wiring 114, and the gate of the transistor 102 can be connected to the wiring 111. Alternatively, the first terminal of the transistor 103 is connected to the wiring 113, and the gate of the transistor 103 can be connected to the wiring 111. Alternatively, the first terminal of the transistor 105 is connected to the wiring 113, and the gate of the transistor 105 can be connected to the node 11. By doing so, the number of signals or power sources can be reduced. That is, the number of wirings can be reduced. Therefore, the number of connections between the substrate on which the circuit 100 is formed and the substrate for supplying signals to the substrate can be reduced, so that the reliability can be improved, the yield can be improved, or the manufacturing cost can be reduced. Some of the plurality of transistors (for example, transistors 101 to 105) included in the circuit 100 can be diode-connected.

[0149] Next, in the configurations described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), 8(A) to (F), 9(A) to (B), and 11(A) to (B), the transistor can be replaced by a capacitive element. For example, it is possible to newly provide the capacitive element without omitting the transistor.

[0150] ​​In FIG. 11(C), in the semiconductor device of FIG. 1(A), the transistor 104 is replaced with a capacitive element 104A connected between the wiring 11 2 and the node 11. The capacitive element 104A can control the potential of the node 11 according to the potential of the wiring 112 by capacitive coupling . In this way, by replacing the transistor 104 with the capacitive element 104A , a steady current can be reduced, so that power consumption can be reduced.

[0151] In FIG. 11(D), in the semiconductor device of FIG. 1(A), a configuration in which a new capacitive element 104A is provided is shown. Since the change in the potential of the node 11 can be made steep, the power consumption can be reduced .

[0152] In FIG. 11(E), in the semiconductor device of FIG. 1(A), the transistors 102, 103 , and the transistor 105 are each replaced with a capacitive element 102A connected between the wiring 114 and the wiring 111 , a capacitive element 103B connected between the wiring 113 and the wiring 111, and a capacitive element 105B connected between the wiring 113 and the node 11, as shown in the configuration . .

[0153] Next, in the configurations described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), 8(A) to (F), 9(A) to (B), and FIGS. 11(A) to (F), it is possible to replace the transistor with a resistive element .

[0154] In FIG. 11(F), in the semiconductor device of FIG. 1(A), a configuration in which the transistor 104 is replaced with a resistive element 1 04R is shown. The resistive element 104R is connected between the wiring 112 and the node 11 .

[0155] Next, in the configurations described with reference to FIGS. 1(A), 6(A) to (F), 7(A) to (E), 8(A) to (F), 9(A) to (B), and 11(A) to (F), the transistor 108 can be newly provided.

[0156] FIG. 46(A) shows a configuration in which the transistor 108 is newly provided in the semiconductor device of FIG. 1(A). The transistor 108 is an N-channel type. However, the present embodiment is not limited to this, and the transistor 108 can be a P-channel type. The first terminal of the transistor 108 is connected to the wiring 111, the second terminal of the transistor 108 is connected to the node 11, and the gate of the transistor 108 is connected to the wiring 112.

[0157] The operation of the semiconductor device in FIG. 46(A) will be described. In operations 1 to 3, since the signal IN1 becomes the H level, the transistor 108 is turned on. Then, since the wiring 111 and the node 11 are in a conductive state, the potential of the wiring 111 is supplied to the node 11. Or, the potential of the node 11 is supplied to the wiring 111. However, in operation 4, although the signal IN3 becomes the H level, since the potential of the node 11 and the potential of the wiring 111 become the H level, the transistor 108 is turned off. However, until the potential of the wiring 111 becomes the H level, the transistor 108 is turned on. Thus, the potential of the node 11 decreases. Then, since the Vgs of the transistor 101 becomes small, breakdown or deterioration of the transistor 101 can be prevented. On the other hand, in operations 5 to 8, since the signal IN1 becomes the L level, the transistor 108 is turned off. Thus, the node 11 and the wiring 111 are in a non-conductive state. ​​​​​​​​​​​​​​​

[0158] Next, in the configurations described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), 8(A) to (F), 9(A) to (B), 11(A) to (F), and 46(A), it is possible to generate a signal other than the signal O UT. For this purpose, it is possible to newly provide a transistor 109 in these semiconductor devices.

[0159] FIG. 46(B) shows a configuration in which a transistor 109 is newly provided in the semiconductor device of FIG. 1(A). The transistor 109 has the same polarity as the transistor 101. And the transistor 109 can have the same function as the transistor 101. The first terminal of the transistor 109 is connected to the wiring 112, the second terminal of the transistor 109 is connected to the wiring 117, and the gate of the transistor 109 can be connected to the node 11.

[0160] Here, it is noted that the configurations described in FIGS. 1(A), 6(A) to (F), 7(A) to (E), 8(A) to (F), 9(A) to (B), 11(A) to (F), and 46(A) to (B) can be appropriately combined.

[0161] FIG. 12(A) shows a configuration in which the configuration described in FIG. 6(B) and the configuration described in FIG. 6(E) are combined. The first terminal of the transistor 103 is connected to the wiring 112, the second terminal of the transistor 103 is connected to the wiring 111, and the gate of the transistor 103 is connected to the wiring 11 1. The first terminal of the transistor 105 is connected to the wiring 112, the transistor 105's second terminal is connected to the node 11, and the gate of the transistor 105 is the no ​​​In this way, the signal IN2 and the wiring 113 can be omitted. Therefore, the number of signals or the number of wirings can be reduced. Reducing the number of connections between the substrate and another substrate, improving reliability, reducing manufacturing costs, and / or It is possible to reduce power consumption, etc.

[0162] FIG. 12B shows a combination of the configuration shown in FIG. 7A and the configuration shown in FIG. 8E. The transistor 105 is omitted, and the first terminal of the transistor 104 is connected to the wiring The second terminal of the transistor 104 is connected to node 112, and the second terminal of the transistor 104 is connected to node 11. The gate of the transistor 104 is connected to the wiring 116. In this way, the number of transistors is reduced. This allows the layout area to be reduced. Since the potential can be fixed at the L level, a circuit that is resistant to noise can be obtained.

[0163] FIG. 12(C) shows a combination of the configuration described in FIG. 7(D) and the configuration described in FIG. 11(C). A first terminal of the transistor 103 is connected to a wiring 114. A first terminal of the transistor 105 is connected to a wiring 114, and a second terminal of the transistor 104 is connected to a wiring 112. It is replaced by a capacitive element 104A connected between the node 10 and the node 11.

[0164] As described above, this embodiment is not limited to the configuration shown in FIG. 1A, and various other configurations may be used. The composition can be used.

[0165] Next, Figs. 1(A), 6(A)-(F), 7(A)-(E), 8(A)-(F), Figs. 9(A)-(B), Figs. 11(A)-(F), Figs. 12(A)-(C), and Figs. 46(A)- In the configuration described in (B), a P-channel transistor can be used as the transistor. It is possible that only some of the plurality of transistors included in the semiconductor device are P-channel type. That is, the semiconductor device of the present embodiment can be a CMOS circuit.

[0166] FIG. 13(A) shows a configuration in the semiconductor device of FIG. 1(A) when a P-channel transistor is used as the transistor. Transistors 101p to 105p have the same functions as transistors 101 to 105 and are P-channel type. In such a case, voltage V2 is supplied to wiring 115.

[0167] In the semiconductor device of FIG. 13(A), as shown in FIG. 13(B), circuit 100 can function as a logic circuit including a NAND. Specifically, circuit 100 can function as a logic circuit combining a three-input NAND and two NOTs. And it is possible for signal IN1 to be input to the first input terminal of the NAND, for a signal obtained by inverting signal IN2 by the first NOT to be input to the second input terminal of the NAND, for a signal obtained by inverting signal IN3 by the second NOT to be input to the third input terminal of the NAND, and for signal OUT to be output from the output of the NAND. That is, circuit 100 can have a function of realizing the logical expression shown in FIG. 13(C) or a function of realizing the truth table obtained by this logical expression. Therefore, when signal IN1 becomes the L level and signals IN2 and IN3 become the H level, signal OUT becomes the L level, and for other input signals, the signal OUT becomes the H level.​​​​​​​​​​​​ It is noted that OUT becomes the H level. FIG. 13(D) shows a truth table when signals IN1 to IN3 are digital signals.

[0168] FIG. 12(D) shows a configuration in which P-channel transistors are used as some of the transistors in the semiconductor device of FIG. 1(A). The gate of transistor 104p is connected to node 11.

[0169] (Embodiment 2) In this embodiment, a semiconductor device in which an element or a circuit is newly provided in the semiconductor device of Embodiment 1 will be described.

[0170] First, a configuration in which a transistor 201 (sixth transistor) is newly provided in the semiconductor device of Embodiment 1 will be described. FIG. 14(A) shows a configuration in which a transistor 201 is newly provided in the semiconductor device of FIG. 1(A).

[0171] Transistor 201 is an N-channel type. However, this embodiment is not limited thereto, and transistor 201 can be a P-channel type. The first terminal of transistor 201 is connected to wiring 115, the second terminal of transistor 201 is connected to wiring 211 (sixth wiring), and the gate of transistor 201 is connected to wiring 111.

[0172] Note that the gate of transistor 201 is denoted as node 12. Since node 12 corresponds to wiring 111 described in Embodiment 1, when referring to wiring 111, it is possible to rephrase wiring 111 as node 12. Therefore, when referring to the potential of wiring 111 (the potential of signal OUT) ​​​​​​​​​​​​When doing so, the potential of wiring 111 (the potential of signal OUT) can be rephrased as the potential of node 12. This is possible.

[0173] The function of transistor 201 will be described. Transistor 201 has a function of controlling the conduction state between wiring 115 and wiring 211. Alternatively, transistor 201 has a function of controlling the timing of supplying the potential of wiring 11 5 to wiring 211. Alternatively, assuming that a signal or voltage is input to wiring 11 5, transistor 201 has a function of controlling the timing of supplying the signal or voltage input to wiring 115 to wiring 211. Alternatively, transistor 201 has a function of controlling the timing of supplying an L signal or voltage V1 to wiring 211. Alternatively, transistor 201 has a function of controlling the timing of decreasing the potential of wiring 211. As described above, transistor 201 can have a function as a switch. Note that transistor 201 does not necessarily have all of the above functions. Note that transistor 201 can be controlled by the output signal of circuit 100.

[0174] Next, the operation of the semiconductor device in Fig. 14(A) will be described with reference to Fig. 15(A). Fig. 15(A) shows a timing chart that can be used for the semiconductor device of this embodiment.

[0175] Note that the timing chart in Fig. 15(A) has period A and period B. And in the timing chart of Fig. 1 5(A), period A and period B are arranged alternately. In the timing chart of Fig. 15( A), a plurality of period A and a plurality of period B are arranged alternately. It is possible. Alternatively, the timing chart of FIG. 15(A) can have periods other than period A and period B, or it is possible to omit one of period A and period B. Moreover, period A and period B are generally of approximately equal length. Or, for example, if a clock signal is input to the semiconductor device of the present embodiment, the lengths of period A and period B are generally approximately equal to half the period of the clock signal. Or, for example, if the semiconductor device of the present embodiment is used for a gate driver, the lengths of period A and period B generally become approximately equal to one gate selection period. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level.

[0176] Moreover, period A and period B are generally of approximately equal length. Or, for example, if a clock signal is input to the semiconductor device of the present embodiment, the lengths of period A and period B are generally approximately equal to half the period of the clock signal. Or, for example, if the semiconductor device of the present embodiment is used for a gate driver, the lengths of period A and period B generally become approximately equal to one gate selection period. Moreover, period A and period B are generally of approximately equal length. Or, for example, if a clock signal is input to the semiconductor device of the present embodiment, the lengths of period A and period B are generally approximately equal to half the period of the clock signal. Or, for example, if the semiconductor device of the present embodiment is used for a gate driver, the lengths of period A and period B generally become approximately equal to one gate selection period. Moreover, period A and period B are generally of approximately equal length. Or, for example, if a clock signal is input to the semiconductor device of the present embodiment, the lengths of period A and period B are generally approximately equal to half the period of the clock signal. Or, for example, if the semiconductor device of the present embodiment is used for a gate driver, the lengths of period A and period B generally become approximately equal to one gate selection period. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level.

[0177] First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level. First, the operation of the semiconductor device in period A will be described with reference to the schematic diagram of FIG. 14(B). In period A, signal IN1 becomes the H level, signal IN2 becomes the L level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 4 of FIG. 3(A), and the potential of node 12 (signal OUT) becomes the H level. As a result, transistor 201 turns on, so that wiring 115 and wiring 211 are in a conductive state. Then, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the L level.

[0178] Next, the operation of the semiconductor device in period B will be described with reference to the schematic diagram of FIG. 14(C). In period B, signal IN1 becomes the L level, signal IN2 becomes the H level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 6 of FIG. 3(C), and the potential of node 12 (signal OUT) becomes the L level. As a result, transistor 201 turns off, so that wiring 115 and wiring 211 are in a non-conductive state. Then, the potential of wiring 115 (for example, voltage V1) is not supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the H level. Next, the operation of the semiconductor device in period B will be described with reference to the schematic diagram of FIG. 14(C). In period B, signal IN1 becomes the L level, signal IN2 becomes the H level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 6 of FIG. 3(C), and the potential of node 12 (signal OUT) becomes the L level. As a result, transistor 201 turns off, so that wiring 115 and wiring 211 are in a non-conductive state. Then, the potential of wiring 115 (for example, voltage V1) is not supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the H level. Next, the operation of the semiconductor device in period B will be described with reference to the schematic diagram of FIG. 14(C). In period B, signal IN1 becomes the L level, signal IN2 becomes the H level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 6 of FIG. 3(C), and the potential of node 12 (signal OUT) becomes the L level. As a result, transistor 201 turns off, so that wiring 115 and wiring 211 are in a non-conductive state. Then, the potential of wiring 115 (for example, voltage V1) is not supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the H level. Next, the operation of the semiconductor device in period B will be described with reference to the schematic diagram of FIG. 14(C). In period B, signal IN1 becomes the L level, signal IN2 becomes the H level, and signal IN3 becomes the L level. Therefore, circuit 100 can perform operation 6 of FIG. 3(C), and the potential of node 12 (signal OUT) becomes the L level. As a result, transistor 201 turns off, so that wiring 115 and wiring 211 are in a non-conductive state. Then, the potential of wiring 115 (for example, voltage V1) is not supplied to wiring 211, so that the potential of wiring 211 (signal GOUT) becomes the H level. Since 01 turns off, the wiring 115 and the wiring 211 become non-conductive. Therefore, the wiring 2 11 becomes floating, so the potential of the wiring 211 is generally maintained at V1.

[0179] As described above, the transistor 201 turns on during period A and turns off during period B. Therefore, the time during which the transistor 201 is on can be shortened. Therefore, the trans istor degradation can be suppressed. Also, during periods A and B, the transistor 1 01, the transistor 102, the transistor 103, the transistor 104, the transistor 1 05, and the transistor 201 do not continuously turn on, and the on time can be shortened or the on number of times can be reduced.

[0180] Next, the functions of the signals IN1 to IN3 and the characteristics of these signals will be described.

[0181] First, the signal IN1 repeats between the H level and the L level for each period. Therefore, the signal IN1 can potentially function as a clock signal. Alternatively, the wiring 112 can potentially function as a clock signal line (clock line, or clock supply line).

[0182] Next, the signal IN2 repeats between the H level and the L level for each period. And the signal IN2 is the inverted signal of the signal IN1, or a signal with a 180° phase shift from the signal IN1. Therefore the signal IN2 can potentially function as an inverted clock signal. Alternatively, the wiring 113 can potentially function as a clock signal line.

[0183] Next, assuming that the signals IN1 and IN2 function as clock signals. This In this case, the signal IN1 and the signal IN2 can be balanced as shown in Fig. 15(A), or can be unbalanced. By "balanced" is meant that the period during which the signal is at the H level and the period during which the signal is at the L level are approximately equal within one cycle. By "unbalanced" is meant that the period during which the signal is at the H level and the period during which the signal is at the L level are different. Here, "different" is defined as being outside the range where they are approximately equal.

[0184] Fig. 15(B) shows the timing chart when the signals IN1 and IN2 are unbalanced in the timing chart of Fig. 15(A).

[0185] Next, an n-phase clock signal can be input to the semiconductor device of this embodiment. Alternatively, some of the n-phase clock signals can be input to the semiconductor device of this embodiment. The n-phase clock signal refers to n clock signals whose periods are shifted by 1 / n period each.

[0186] Fig. 15(C) shows the timing chart when one of the three-phase clock signals is used as the signal IN1 and another one of the three-phase clock signals is used as the signal IN2.

[0187] As described above, as the signals IN1 to IN3, not only the waveforms shown in the timing chart of Fig. 15(A) but also various other waveforms are possible.

[0188] Next, the ratio of the channel widths of the transistors 201 will be described. For example, when the wiring 211 has the function as a gate signal line, the wiring 211 extends into the pixel portion and may be connected to the pixels. That is, a large load is connected to the wiring 211. Therefore, ​​, the channel width of transistor 201 is larger than that of the transistors in circuit 100. In such a case, the channel width of transistor 201 is preferably 10 times or less that of transistor 101. More preferably, the channel width of transistor 201 is preferably 5 times or less that of transistor 101. Even more preferably, the channel width of transistor 201 is preferably 3 times or less that of transistor 101. As described above, it is preferable to set the ratio of the channel widths of the transistors to an appropriate value. Note that considering the ratio of the channel widths of the transistors described above, the channel width of transistor 201 is preferably 1000 μm or more and 5000 μm or less. More preferably, the channel width of transistor 201 is preferably 1500 μm or more and 4000 μm or less. Even more preferably, the channel width of transistor 201 is preferably 2000 μm or more and 3000 μm or less. Next, a semiconductor device having a configuration different from that of FIG. 14(A) will be described. First, in the configuration described in FIG. 14(A), circuit 100 is not limited to the configuration of FIG. 1(A), and various configurations described in Embodiment 1 can be used. As circuit 100, as long as a predetermined function can be satisfied, a configuration other than the configuration described in Embodiment 1 can be used. FIG. 10(A) shows a configuration in which, in the configuration described in FIG. 14(A), the configuration of FIG. 7(B) is used as circuit 100.

[0189]

[0190]

[0191]

[0192] ​​​​​​​​​​​​​​

[0193] In FIG. 10(B), in the configuration described in FIG. 14(A), as circuit 100, FIG. 8(D) shows a configuration using the configuration of. Noise can be prevented from occurring at node 12 through transistor 103 . Therefore, malfunction can be prevented.

[0194] In FIG. 10(C), in the configuration described in FIG. 14(A), as circuit 100, FIG. 8(C) shows the configuration when using the configuration of. Since the potential of node 11 can be made smaller , it is possible to prevent transistor 201 from turning on.

[0195] Next, in the configurations described in FIGS. 10(A) to (C) and FIG. 14(A), transistor 202 can be newly provided.

[0196] FIG. 16(A) shows a configuration in which transistor 202 is newly provided in the semiconductor device of FIG. 14(A). Transistor 202 is an N-channel type. However, this embodiment is not limited thereto, and transistor 202 can be a P-channel type. The first terminal of transistor 202 is connected to wiring 115, and the second terminal of transistor 202 is connected to wiring 211, and the gate of transistor 202 is connected to wiring 113. The gate of transistor 202 can be connected to a wiring different from wiring 113. Or, the first terminal of transistor 202 can be connected to a wiring different from wiring 115 . Or, the first terminal of transistor 202 can be connected to a wiring different from wiring 115 .

[0197] The function of transistor 202 will be described. Transistor 202 has a function of controlling the conduction state between wiring 115 and wiring 211. Or, transistor 202 is wiring 11 It has a function of controlling the timing for supplying the potential of 5 to the wiring 211. Or, the wiring 11 Assuming that a signal or voltage is input to 5, the transistor 202 has a function of controlling the timing for supplying the signal or voltage input to the wiring 115 to the wiring 211. Or, the transistor 202 has a function of controlling the timing for supplying an L signal or a voltage V1 to the wiring 211. Or, the transistor 202 has a function of controlling the timing for reducing the potential of the wiring 211. As described above, the transistor 202 can have a function as a switch. Note that the transistor 202 does not necessarily have all of the above functions. Note that the transistor 202 can be controlled by the potential of the wiring 113 (for example, signal IN2). transistor 202 has a function of controlling the timing for supplying the signal or voltage input to the wiring 115 to the wiring 211. Or, the transistor 202 has a function of controlling the timing for supplying an L signal or a voltage V1 to the wiring 211. Or, the transistor 202 has a function of controlling the timing for reducing the potential of the wiring 211. As described above, the transistor 202 can have a function as a switch. Note that the transistor 202 does not necessarily have all of the above functions. Note that the transistor 202 can be controlled by the potential of the wiring 113 (for example, signal IN2). transistor 202 has a function of controlling the timing for reducing the potential of the wiring 211. As described above, the transistor 202 can have a function as a switch. Note that the transistor 202 does not necessarily have all of the above functions. Note that the transistor 202 can be controlled by the potential of the wiring 113 (for example, signal IN2). function as a switch. Note that the transistor 202 does not necessarily have all of the above functions. Note that the transistor 202 can be controlled by the potential of the wiring 113 (for example, signal IN2). does not need to have all of the above functions. Note that the transistor 202 can be controlled by the potential of the wiring 113 (for example, signal IN2). by the potential of the wiring 113 (for example, signal IN2).

[0198] The operation of the semiconductor device in FIG. 16(A) will be described. During period A, since the signal IN2 becomes a low level, as shown in FIG. 16(B), the transistor 202 turns off. During period B since the signal IN2 becomes a high level, as shown in FIG. 16(C), the transistor 202 turns on. Therefore, even during period B, since the wiring 115 and the wiring 211 are in a conductive state the potential of the wiring 115 (for example, voltage V1) is supplied to the wiring 211. Therefore the noise of the wiring 211 can be reduced. For example, assuming that the semiconductor device in FIG. 16(A) is used in the device shown and the wiring 211 is connected to the gate of the selection transistor of the pixel In this case, it is possible to prevent a video signal from being written to the pixel due to the noise of the wiring 211 to a pixel belonging to another row. Or, due to the noise of the wiring 211 is used in the shown device and the wiring 211 is connected to the gate of the selection transistor of the pixel In this case, it is possible to prevent a video signal from being written to the pixel due to the noise of the wiring 211 to a pixel belonging to another row. Or, due to the noise of the wiring 211 In this case, it is possible to prevent a video signal from being written to the pixel due to the noise of the wiring 211 to a pixel belonging to another row. Or, due to the noise of the wiring 211 It is possible to prevent the video signal held by the pixel from changing. Therefore, the display can be improved in quality.

[0199] Next, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), and FIG. 16(A), it is possible to newly provide a transistor 203 (seventh transistor).

[0200] FIG. 17(A) shows a configuration in which a transistor 203 is newly provided in the semiconductor device of FIG. 14(A). The transistor 203 is an N-channel type. However, the present embodiment is not limited to this, and the transistor 203 can be a P-channel type. The first terminal of the transistor 203 is connected to the wiring 112, and the second terminal of the transistor 203 is connected to the wiring 211. And the gate of the transistor 203 is shown as the node 13. Note that the gate of the transistor 102 can be connected to the node 13. Therefore, it is possible to use the potential (V13) of the node 13 as the signal IN3.

[0201] The function of the transistor 203 will be described. The transistor 203 has a function of controlling the conduction state between the wiring 112 and the wiring 211. Or, the transistor 203 has a function of controlling the timing of supplying the potential of the wiring 112 to the wiring 211. Or, assuming that a signal or voltage is input to the wiring 112, the transistor 203 has a function of controlling the timing of supplying the signal or voltage input to the wiring 112 to the wiring 211. Or, the transistor 203 has a function of controlling the timing of supplying an H signal or a voltage V2 to the wiring 211. Or, the transistor 203 has a function of controlling the timing of supplying an L signal or a voltage V1 to the wiring 211. It has a function of controlling the supply timing. Or, the transistor 203 controls the timing for raising the potential of the wiring 21 It has a function of controlling the timing for raising the potential of the wiring 211. Or, the transistor 203 has a function of controlling the timing for decreasing the potential of the wiring 211. Or, the trans istor 203 has a function of performing a bootstrap operation. Or, the transistor 20 3 has a function of raising the potential of the node 13 by the bootstrap operation. As described above the transistor 203 can function as a switch or a buffer Note that the transistor 203 does not necessarily have all of the above functions. Note also that the transistor 203 can be controlled by the potential of the node 13, the potential of the wiring 112 (signal IN1), and / or, the potential of the wiring 211 (signal GOUT).

[0202] The operation of the semiconductor device in FIG. 17(A) will be described with reference to FIG. 17(B). FIG. 17( B) shows a timing chart that can be used for the semiconductor device of the present embodiment.

[0203] Note that the timing chart in FIG. 17(B) has periods A to E. In the timing chart of FIG. 17(B) periods C, D, and E are arranged in order. And, in the other periods, periods A and B are arranged alternately. Periods A to E can be arranged in various orders The operation of the semiconductor device in period A will be described with reference to the schematic diagram in FIG. 18(A).

[0204] In period A, the signal IN1 becomes the H level, the signal IN2 becomes the L level, and the potential of the node 13 (signal IN3) becomes the L level. Therefore, the circuit 100 performs the operation 4 in FIG. 3(A) (signal IN3) becomes the L level. Therefore, the circuit 100 performs the operation 4 in FIG. 3(A) This makes it possible for the potential of Node 12 (signal OUT) to become the H level. Then, Since transistor 201 turns on, wiring 115 and wiring 211 become conductive. Thus, the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211. At this time, since the potential of Node 13 is at the L level, transistor 203 turns off. Then, the wiring 112 and wiring 211 become non-conductive. As a result of these, since the potential of wiring 115 (for example, voltage V1) is supplied to wiring 211, signal GOUT becomes the L level.

[0205] The operation of the semiconductor device in period B will be described with reference to the schematic diagram of Fig. 18(B). In period B, signal IN1 becomes the L level, signal IN2 becomes the H level, and the potential of Node 13 (signal IN3) remains at the L level. Therefore, since circuit 100 can perform the operation 6 in Fig. 3(C), the potential of Node 12 (signal OUT) becomes the L level. Then, since transistor 201 turns off, wiring 115 and wiring 211 become non-conductive. At this time, since the potential of Node 13 is at the L level, transistor 203 turns off. Then, wiring 112 and wiring 211 become non-conductive. As a result of these, since wiring 211 becomes floating, the potential of wiring 211 is maintained at approximately V1.

[0206] The operation of the semiconductor device in period C will be described with reference to the schematic diagram of Fig. 19(A). In period C, signal IN1 becomes the L level, signal IN2 becomes the H level, and the potential of Node 13 (signal IN3) becomes the H level. Therefore, since circuit 100 can perform the operation 5 in Fig. 3(B), the potential of Node 12 (signal OUT) becomes the L level. Then, Since the transistor 201 turns off, the wiring 115 and the wiring 211 become non-conductive. Thus At this time, since the potential of the node 13 becomes the H level, the transistor 203 turns on. That is to say, since the wiring 112 and the wiring 211 become conductive, the potential of the wiring 112 (the signal IN1 at the L level) is supplied to the wiring 211. As a result of these, since the potential of the wiring 112 (the signal IN1 at the L level) is supplied to the wiring 211, the signal GOUT becomes the L level.

[0207] The operation of the semiconductor device in the period D will be described with reference to the schematic diagram of FIG. 19(B). In the period D, the signal IN1 becomes the H level, the signal IN2 becomes the L level, and the potential of the node 13 (the signal IN3) becomes the H level. Therefore, the circuit 100 can perform the operation 3 of FIG. 2(C), so the potential of the node 12 (the signal OUT) becomes the L level. Then, since the transistor 201 turns off, the wiring 115 and the wiring 211 become non-conductive. Thus At this time, since the potential of the node 13 becomes the H level, the transistor 203 turns on. Then, since the wiring 112 and the wiring 211 become conductive, the potential of the wiring 112 (the signal IN1 at the H level) is supplied to the wiring 211. As a result of these, since the potential of the wiring 112 (the signal IN1 at the H level) is supplied to the wiring 211, the potential of the wiring 211 starts to rise. At this time, it is assumed that the node 13 is in a floating state. Then, due to the parasitic capacitance between the gate of the transistor 203 and the second terminal, the potential of the node 13 rises. As a result, the potential of the node 13 becomes V2 + Vth203 + Va. This is a so-called bootstrap operation. In this way, since the potential of the wiring 211 becomes V2, the signal GOUT becomes the H level. . ​​​​​​

[0208] The operation of the semiconductor device in period E will be described with reference to the schematic diagram of FIG. 19(C). In period E, signal IN1 becomes the L level, signal IN2 becomes the H level, and the potential (signal IN3) of node 13 becomes the L level. Therefore, circuit 100 can perform operation 6 of FIG. 3(C), so the potential (signal OUT) of node 12 becomes the L level. Then, transistor 201 turns off, so wiring 115 and wiring 211 become non-conductive. At this time, the potential of node 13 becomes the L level. Then, transistor 203 turns off, so wiring 112 and wiring 211 become non-conductive. However, the timing at which signal IN1 changes from the H level to the L level can be earlier than the timing at which the potential of node 13 decreases from the H level to the L level. In this case, when transistor 203 is on, that is, when wiring 112 and wiring 211 are conductive, signal IN1 may become the L level. Therefore, the L-level signal IN1 is supplied to wiring 211, so signal G OUT becomes the L level. In addition, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), and FIG. 17(A), the gate of transistor 203 can be connected to node 12. Alternatively, the gate of transistor 201 can be connected to node 13 (FIG. 47(A)).

[0209] In addition, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), and FIG. 47 circuit 100 and other transistors can be connected to separate wirings. In the configuration described in (A), circuit 100 and other transistors can be connected to separate wirings. (FIG. 47(A)).

[0210] In addition, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), and FIG. 47 (A), circuit 100 and other transistors are connected to separate wirings. It is possible to be connected. For example, as shown in FIG. 47(B), the first terminal of transistor 203 can be connected to a wiring (wiring 112A) different from wiring 112. Or, the first terminal of transistor 201 can be connected to a wiring (wiring 115 A) different from wiring 115.

[0211] Next, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), and FIGS. 47 (A) to (B), it is possible to newly provide transistor 204.

[0212] FIG. 20(A) shows a configuration in which transistor 204 is newly provided in the semiconductor device of FIG. 17(A). Transistor 204 is an N-channel type. However, the present embodiment is not limited to this, and transistor 204 can be a P-channel type. The first terminal of transistor 204 is connected to wiring 115, the second terminal of transistor 204 is connected to node 13, and the gate of transistor 204 is connected to node 12.

[0213] The function of transistor 204 will be described. Transistor 204 has a function of controlling the conduction state between wiring 115 and node 13. Or, transistor 204 has a function of controlling the timing of supplying the potential of wiring 11 5 to node 13. Or, assuming that a signal or voltage is input to wiring 11 5, transistor 204 has a function of controlling the timing of supplying the signal or voltage input to wiring 115 to node 13. Or, transistor 204 has a function of controlling the timing of supplying an L signal or voltage V1 to node 13. ​​​​​​​​It has the function of, or the transistor 204 has the function of controlling the timing to decrease the potential of node 13. As described above, the transistor 204 can function as a switch. Note that the transistor 204 does not necessarily have all of the above functions. Note that the transistor 204 can be controlled by the potential of node 12 (for example, signal OUT). The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B. Next, in the configurations described with reference to Figs. 10(A) to (C), Fig. 14(A), Fig. 16(A), Fig. 17(A), Fig. 20(A), and Figs. 47(A) to (B), it is possible to newly provide a transistor 205. Fig. 21(A) shows a configuration in which a transistor 205 is newly provided in the semiconductor device of Fig. 17(A). The transistor 205 is an N-channel type. However, this embodiment is not limited thereto, and the transistor 205 can be a P-channel type. The first terminal of the transistor 205 is connected to the wiring 212, and the second terminal of the transistor 205 is

[0214] The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B. The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B. The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B. The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B. The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B. The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B. The operation of the semiconductor device in Fig. 20(A) will be described. In period A, as shown in Fig. 20(B), since circuit 100 outputs an H signal, the transistor 204 turns on. Then, since wiring 115 and node 13 are in a conductive state, the potential of wiring 115 (for example, voltage V1) is supplied to node 13. In periods B to E, since circuit 100 outputs an L signal, the transistor 204 turns off. Thus, wiring 115 and node 13 are in a non-conductive state. Fig. 20(C) shows a schematic diagram of the semiconductor device in Fig. 20(A) in period B.

[0215] Next, in the configurations described with reference to Figs. 10(A) to (C), Fig. 14(A), Fig. 16(A), Fig. 17(A), Fig. 20(A), and Figs. 47(A) to (B), it is possible to newly provide a transistor 205. Next, in the configurations described with reference to Figs. 10(A) to (C), Fig. 14(A), Fig. 16(A), Fig. 17(A), Fig. 20(A), and Figs. 47(A) to (B), it is possible to newly provide a transistor 205. Next, in the configurations described with reference to Figs. 10(A) to (C), Fig. 14(A), Fig. 16(A), Fig. 17(A), Fig. 20(A), and Figs. 47(A) to (B), it is possible to newly provide a transistor 205.

[0216] Fig. 21(A) shows a configuration in which a transistor 205 is newly provided in the semiconductor device of Fig. 17(A). The transistor 205 is an N-channel type. However, this embodiment is not limited thereto, and the transistor 205 can be a P-channel type. The first terminal of the transistor 205 is connected to the wiring 212, and the second terminal of the transistor 205 is Fig. 21(A) shows a configuration in which a transistor 205 is newly provided in the semiconductor device of Fig. 17(A). The transistor 205 is an N-channel type. However, this embodiment is not limited thereto, and the transistor 205 can be a P-channel type. The first terminal of the transistor 205 is connected to the wiring 212, and the second terminal of the transistor 205 is Fig. 21(A) shows a configuration in which a transistor 205 is newly provided in the semiconductor device of Fig. 17(A). The transistor 205 is an N-channel type. However, this embodiment is not limited thereto, and the transistor 205 can be a P-channel type. The first terminal of the transistor 205 is connected to the wiring 212, and the second terminal of the transistor 205 is Fig. 21(A) shows a configuration in which a transistor 205 is newly provided in the semiconductor device of Fig. 17(A). The transistor 205 is an N-channel type. However, this embodiment is not limited thereto, and the transistor 205 can be a P-channel type. The first terminal of the transistor 205 is connected to the wiring 212, and the second terminal of the transistor 205 is ​is connected to Node 13, and the gate of Transistor 205 is connected to Wiring 212.

[0217] The signal input to Wiring 212 and the function of Wiring 212 will be described. To Wiring 212 Signal IN4 is input. Signal IN4 may have the function as a start pulse. Therefore, Wiring 212 may have the function as a signal line. To the Wiring 212, a certain voltage can be supplied. Therefore, Wiring 212 may have the function as a power line.

[0218] Incidentally, assuming that a plurality of semiconductor devices are connected, Wiring 212 is connected to Wiring 211 of another semiconductor device (for example, the semiconductor device in the previous stage). Therefore, Wiring 212 may have the function as a gate signal line, a scanning line, a selection line, a capacitance line, or a power line. And Signal IN4 may have the function as a gate signal or a scanning signal.

[0219] The function of Transistor 205 will be described. Transistor 205 has the function of controlling the conduction state between Wiring 212 and Node 13. Or, Transistor 205 has the function of controlling the timing to supply the potential of Wiring 21 2 to Node 13. Or, assuming that a signal or a voltage is input to Wiring 21 2, Transistor 205 has the function of controlling the timing to supply the signal or voltage input to Wiring 212 to Node 13. Or, Trans istor 205 has the function of controlling the timing to supply an H signal or a voltage V2 to Node 13. Or, Transistor 205 has the function of not supplying a signal or a voltage to Node 13. Or, Transistor 205 has the function of raising the potential of Node 13 at a certain timing ​ It has a function of controlling the ring. Or, the transistor 205 makes node 13 in a floating state It has a function of doing so. As described above, the transistor 205 can function as a switch, a diode, or a transistor connected in diode configuration, etc. Note that the transistor 205 does not necessarily have all of the above functions. Note that the transistor 205 can be controlled by the potential of the wiring 212 (signal IN4) and / or the potential of node 13

[0220] The operation of the semiconductor device in FIG. 21(A) will be described with reference to FIG. 21(B). In FIG. 21( B), a timing chart that can be used for the semiconductor device of the present embodiment is shown. During period C, as shown in FIG. 22(A), the signal IN4 becomes the H level. Therefore, the transistor 205 turns on, so that the wiring 212 and the node 13 are in a conductive state. That is, the potential of the wiring 212 (for example, the signal IN4 of the H level) is supplied to the node 13. As a result, the potential of the node 13 starts to rise. After that, when the potential of the node 13 reaches a value (V2 - Vth20 5) obtained by subtracting the threshold voltage (Vth20 5) of the transistor 205 from the potential of the gate of the transistor 205 (for example, V2), the transistor 205 turns off. Therefore, the node 13 becomes in a floating state, so that the potential of the node 13 is maintained at V2 - Vth2 05. During periods A to B and periods D to E, the signal IN4 becomes the L level. Therefore, the transistor 205 turns off, so that the wiring 212 and the node 13 are in a non-conductive state. Note that FIG. 22(B) shows a schematic diagram of the operation of the semiconductor device in FIG. 21(A) during period B.

[0221] ​​ Next, in the configurations described in FIGS. 10(A) to (C), 14(A), 16(A), 17(A), 20(A ), 21(A), and 47(A) to (B), it is possible to newly provide the transistor 20 6.

[0222] FIG. 23(A) shows a configuration in which the transistor 206 is provided in the semiconductor device of FIG. 21(A). The transistor 206 is of the N-channel type. However, the present embodiment is not limited thereto, and the transistor 206 can be of the P-channel type. The first terminal of the transistor 2 06 is connected to the wiring 212, the second terminal of the transistor 206 is connected to the node 13, and the gate of the transistor 206 is connected to the wiring 113.

[0223] The function of the transistor 206 will be described. The transistor 206 has a function of controlling the conduction state between the wiring 212 and the node 13. Or, the transistor 206 has a function of controlling the timing of supplying the potential of the wiring 21 2 to the node 13. Or, assuming that a signal or voltage is input to the wiring 21 2, the transistor 206 has a function of controlling the timing of supplying the signal or voltage input to the wiring 212 to the node 13. Or, the trans istor 206 has a function of controlling the timing of supplying an L signal or a voltage V1 to the node 13. Or, the transistor 206 has a function of controlling the timing of supplying an H signal or a voltage V2 to the node 13. Or, the transistor 206 has a function of controlling the timing of decreasing the potential of the node 1 3. Or, the transistor 206 has a function of controlling the timing of increasing the potential of the node 13. As described above, ​​Transistor 206 can have a function as a switch. Note that the transistor 206 does not necessarily have all of the above functions. Note that the transistor 206 can be controlled by the potential of wiring 113 (for example, signal IN2).

[0224] The operation of the semiconductor device in FIG. 23(A) will be described. In period C, as shown in FIG. 23(B), since signal IN2 becomes the H level, transistor 206 turns on. Thus, wiring 212 and node 13 become conductive, and the potential of wiring 212 (for example, the H-level signal IN4) is supplied to node 13. In this way, in period C, the change in the potential of node 13 can be made steep, so that the drive frequency of the semiconductor device can be increased.

[0225] Also in period B and period E, similar to period C, since signal IN2 becomes the H level, the transistor 206 turns on. Thus, wiring 212 and node 13 become conductive, and the potential of wiring 212 (for example, the L-level signal IN4) is supplied to node 13. In this way, in period B, the potential of node 13 can be fixed, so that a semiconductor device with strong noise resistance can be obtained. Or, in period E, since the potential of node 13 can be lowered, transistor 203 can be turned off. Note that FIG. 24(A) shows a schematic diagram of the operation of the semiconductor device in FIG. 23(A) in period B.

[0226] In period A, as shown in FIG. 24(B), since signal IN2 becomes the L level, the transistor 206 turns off. Thus, wiring 212 and node 13 become non-conductive. Thus, Thus, the transistor 206 turns off, and deterioration of the transistor 206 can be suppressed. This is achievable.

[0227] Next, in the configurations described with reference to FIGS. 10(A) to (C), 14(A), 16(A), 17(A), 20(A ), 21(A), 23(A), and 47(A) to (B), it is possible to newly provide a transistor 207. This is achievable.

[0228] FIG. 25(A) shows a configuration in which a transistor 207 is newly provided in the semiconductor device of FIG. 17(A). The transistor 207 is an N-channel type. However, the present embodiment is not limited to this, and the transistor 207 can be a P-channel type. The first terminal of the transistor 207 is connected to the wiring 115, the second terminal of the transistor 207 is connected to the node 13, and the gate of the transistor 207 is connected to the wiring 213. This is achievable. This is achievable.

[0229] The signal input to the wiring 213 and the function of the wiring 213 will be described. A signal IN5 is input to the wiring 213. The signal IN5 can function as a reset signal. Therefore, the wiring 213 can function as a signal line. A constant voltage can be supplied to the wiring 213. Therefore, the wiring 213 can function as a power supply line. This is achievable. This is achievable. This is achievable. This is achievable.

[0230] Note that if a plurality of semiconductor devices are connected, the wiring 213 is connected to the wiring 211 of another semiconductor device (for example, the semiconductor device of the next stage). Therefore, the wiring 213 can function as a gate signal line, a scanning line, a selection line, a capacitance line, or a power supply line. And This is achievable. This is achievable. , signal IN5 can function as a gate signal or a scanning signal.

[0231] The function of the transistor 207 will be described. The transistor 207 is connected to the wiring 115 and the node The transistor 207 has a function of controlling electrical continuity between the wiring 11 and the gate 13. The wiring 11 has a function of controlling the timing at which the potential of the wiring 11 is supplied to the node 13. When a signal or voltage is input to the wiring 115, the transistor 207 The timing of supplying a signal or voltage to the node 13 is controlled. The transistor 207 controls the timing of supplying the L signal or voltage V1 to the node 13. Alternatively, the transistor 207 has a function of decreasing the potential of the node 13. As described above, the transistor 207 functions as a switch. It is possible for the transistor 207 to have all of the above functions. Note that the transistor 207 does not need to be connected to the potential of the wiring 213 (for example, the signal IN5). Thus, it can be controlled.

[0232] The operation of the semiconductor device of FIG. 25(A) will be described with reference to FIG. 25(B). FIG. 1B) shows a timing chart that can be used in the semiconductor device of this embodiment mode. During period E, as shown in FIG. 26(A), the signal IN5 goes to H level. Since the transistor 207 is turned on, electrical continuity is established between the wiring 115 and the node 13. Then, the potential of the wiring 115 (for example, the voltage V1) is supplied to the node 13. The potential of the node 13 decreases. In the periods A to D, the signal IN5 is at the L level. , since the transistor 207 is turned off, the wiring 115 and the node 13 are in a non-conductive state . Note that FIG. 26(B) shows a schematic diagram of the operation of the semiconductor device of FIG. 25(A) in period B. Shown.

[0233] Next, in the configurations described in FIGS. 10(A)-(C), 14(A), 16(A), 17(A), 20(A ), 21(A), 23(A), 25(A), and FIGS. 47(A)-(B), the gate of the transistor 102 can be connected to a wiring (for example, wiring 21 1, etc.) different from the node 13. It is possible.

[0234] FIG. 27(B) shows a configuration in which the gate of the transistor 102 is connected to the wiring 211 in the semiconductor device of FIG. 27(A). By applying a large voltage to the gate of the transistor 102, it is possible to prevent the transistor 102 from being broken down or deteriorated. Shown. When a large voltage is applied to the gate of the transistor 102, it is possible to prevent the transistor 102 from being broken down or deteriorated. By being applied, it is possible to prevent the transistor 102 from being broken down or deteriorated. It can be prevented.

[0235] Note that the semiconductor device of FIG. 27(A) is a configuration in which transistors 20 1 to 207 are newly added to the semiconductor device of FIG. 14(A).

[0236] Next, in the configurations described in FIGS. 10(A)-(C), 14(A), 16(A), 17(A), 20(A ), 21(A), 23(A), 25(A), FIGS. 27(A)-(B), and FIGS. 47( A)-(B), the first terminal of the transistor 204 can be connected to a wiring (for example, wiring 113, wiring 212, wiring 213, node 12, or node 1 3, etc.) different from the wiring 115. Alternatively, the gate of the transistor 204 can be connected to a wiring (for example, wiring 112, etc.) different from the node 12. It is possible. It is possible.

[0237] In FIG. 27(C), in the semiconductor device of FIG. 27(A), the first end of transistor 204 is connected to wiring 211, and the gate of transistor 204 is connected to wiring 112. This configuration is shown. Thus, during period D, the potential of node 13 can be reduced. Therefore, breakdown of transistors (such as transistor 102, transistor 203, transistor 205, or transistor 206, etc.) connected to node 13 can be prevented, or degradation of these transistors can be suppressed.

[0238] Next, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), FIG. 20(A ), FIG. 21(A), FIG. 23(A), FIG. 25(A), FIG. 27(A) to (C), and FIG. 47( A) to (B), the first terminal of transistor 205 can be connected to wiring 212 and another wiring (such as wiring 113, wiring 116, etc.). Also, the gate of transistor 205 can be connected to another wiring (such as wiring 113, wiring 116, etc.) different from wiring 212.

[0239] FIG. 28(A) shows a configuration in the semiconductor device of FIG. 27(A) where the first end of transistor 205 is connected to wiring 116.

[0240] Next, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), FIG. 20(A ), FIG. 21(A), FIG. 23(A), FIG. 25(A), FIG. 27(A) to (C), FIG. 28(A) , and FIG. 47(A) to (B), the second terminal of transistor 207 is , a wiring different from node 13 (such as wiring 211, node 11, or node 12, etc.) is connectable. Alternatively, the first terminal of the transistor 207 is the wiring 115 and another wiring (for example, wiring 112, wiring 116, node 11, or node 12, etc.) is connectable.

[0241] FIG. 28(B) shows a configuration in which, in the semiconductor device of FIG. 27(A), the second end of the transistor 207 is connected to the wiring 211. During the period E, the potential of the wiring 115 (for example voltage V1) can be supplied to the wiring 211 via the transistor 207 . Therefore, the fall time of the signal GOUT can be shortened.

[0242] Next, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), FIG. 20(A ), FIG. 21(A), FIG. 23(A), FIG. 25(A), FIGS. 27(A) to (C), FIG. 28(A) to (B), and FIGS. 47(A) to (B), the first terminal of the transistor 201 is another wiring different from the wiring 115 (for example, wiring 113, wiring 212, wiring 213, no de 12, or node 13, etc.). Alternatively, the first terminal of the transistor 202 is another wiring different from the wiring 115 (for example, wiring 112, or node 12, etc ). Alternatively, the first terminal of the transistor 204 is the wiring 115 and another wiring different from it (for example, wiring 113, wiring 212, wiring 213, node 12, or node 13, etc.). Alternatively, the first terminal of the transistor 207 is another wiring different from the wiring 115 (for example, wiring 112, wiring 116, wiring 212, no de 12, etc.). Each terminal of each transistor is the connection described in the figure It is also possible to be connected to various wirings other than the continuous relationship.

[0243] In FIG. 28(C) of the semiconductor device in FIG. 27(A), the first terminal of the transistor 201 is connected to the wiring 113, the first terminal of the transistor 202 is connected to the wiring 113 , the first terminal of the transistor 204 is connected to the wiring 113, and the first terminal of the transistor 207 is connected to the wiring 112. An H signal is input to the first terminals of the transistors 201, 202, 204, and 207. Since this becomes possible, deterioration of these transistors can be suppressed.

[0244] Next, in the configurations described in FIGS. 10(A) to (C), FIGS. 14(A), FIGS. 16(A), FIGS. 17(A), FIGS. 20(A ), FIGS. 21(A), FIGS. 23(A), FIGS. 25(A), FIGS. 27(A) to (C), FIGS. 28(A) to (C), and FIGS. 47(A) to (B), the transistor can be replaced with a diode. For example, it is possible to connect the transistor in a diode connection.

[0245] FIG. 29(A) shows a configuration in which the transistor is replaced with a diode in the semiconductor device of FIG. 27(A). The transistor 201 can be replaced with a diode 201d in which one electrode (for example, an input terminal) is connected to the wiring 211 and the other electrode (for example, an output terminal) is connected to the node 12. Alternatively, the transistor 202 can be replaced with a diode 202d in which one electrode (for example, an input terminal) is connected to the wiring 211 and the other electrode (for example, an output terminal) is connected to the wiring 1 13. Alternatively, the tra nsistor can be replaced with a diode 202d in which one electrode (for example, an input terminal) is connected to the wiring 211 and the other electrode (for example, an output terminal) is connected to the wiring 113. Or, the tra ​The transistor 203 can be replaced with a diode 203d in which one electrode (e.g., the input terminal) is connected to the node 13 and the other electrode (e.g., the output terminal) is connected to the wiring 211. Or, the transistor 204 can be replaced with a diode 2 04d in which one electrode (e.g., the input terminal) is connected to the node 13 and the other electrode (e.g., the output terminal) is connected to the node 12. Or, the transistor 205 can be replaced with a diode 2 05d in which one electrode (e.g., the input terminal) is connected to the wiring 212 and the other electrode (e.g., the output terminal) is connected to the node 1 3. Or, the transistor 2 07 can be replaced with a diode 207d in which one electrode (e.g., the input terminal) is connected to the node 13 and the other electrode ( e.g., the output terminal) is connected to the wiring 213. Thus, the number of signals or power sources can be reduced. That is, the number of wirings can be reduced . Therefore, the number of connections between the substrate on which the semiconductor device of the present embodiment is formed and the substrate for supplying signals to the substrate can be reduced, so that reliability can be improved, yield can be improved, or manufacturing costs can be reduced. Some of the plurality of transistors in the present embodiment can be replaced with diodes.

[0246] Fig. 29(B) shows a configuration in which transistors are diode-connected in the semiconductor device of Fig. 27(A). For example, the first terminal of the transistor 201 is connected to the node 12 and the gate of the transistor 201 is connected to the wiring 211. Or, for example, the first terminal of the transistor 202 is connected to the wiring 113 and the gate of the transistor 202 is connected to the wiring 113. It is connected to line 211. Or, for example, the first terminal of transistor 203 is connected to node 1 3, and the gate of transistor 203 is connected to node 13. Or, for example the first terminal of transistor 204 is connected to node 12, and the gate of transistor 204 is connected to node 13. Or, for example, the first terminal of transistor 207 is connected to wiring 213, and the gate of transistor 207 is connected to node 13. In this way, the number of signals or power supplies can be reduced. That is, the number of wirings can be reduced. Therefore, the number of connections between the substrate on which the semiconductor device of the present embodiment is formed and the substrate for supplying signals to the substrate can be reduced, so that reliability can be improved, yield can be improved, or manufacturing costs can be reduced. Some of the plurality of transistors in the present embodiment can be diode-connected.

[0247] FIG. 29(C) shows a configuration in which P-channel transistors are diode-connected in the semiconductor device of FIG. 27(A). Transistors 201p, 202p, tra nsistors 203p, 204p, 205p, 207 p each have the same functions as transistors 201, 202, 203, trans istors 204, 205, 207 and are of P-channel type. The semiconductor device of FIG. 29(C) has the same connection relationship as the semiconductor device of FIG. 29(B). However, in order to diode-connect the transistors, compared with the semiconductor device of FIG. 29(B), the gate of transistor 201p is connected to node 12, and transistor 2 The gate of 02p is connected to wiring 113, and the gate of transistor 203p is connected to wiring 211, the gate of transistor 204p is connected to node 12, and the gate of transistor 205 p is connected to node 13, and the gate of transistor 207p is connected to wiring 213 in different ways. In this way, the number of signals or power sources can be reduced. That is, the number of wirings can be reduced. Therefore, the number of connections between the substrate on which the semiconductor device of the present embodiment is formed and the substrate for supplying signals to the substrate can be reduced, so that reliability can be improved, yield can be improved, or manufacturing costs can be reduced, etc. Some of the multiple transistors of the present embodiment can be diode-connected.

[0248] Next, in the configurations described in FIGS. 10(A) to (C), FIGS. 14(A), FIGS. 16(A), FIGS. 17(A), FIGS. 20(A ), FIGS. 21(A), FIGS. 23(A), FIGS. 25(A), FIGS. 27(A) to (C), FIGS. 28(A) to (C), FIGS. 29(A) to (C), and FIGS. 47(A) to (B), each terminal or each electrode of the transistor can be connected to a separate wiring. For example, the first terminal of transistor 101, the first terminal of transistor 104, and the first terminal of transistor 203 can be connected to separate wirings. Or, for example, the gate of transistor 103, the gate of transistor 105, and the gate of transistor 202 can be connected to separate wirings. Or, for example, the first terminal of transistor 102, the first terminal of transistor 105, the first terminal of transistor 201, the first terminal of transistor 202, the first terminal of transistor 204, and the The first terminal of the transistor 207 can be connected to separate wirings. Or , for example, the first terminal of the transistor 205 and the first terminal of the transistor 206 can be connected to separate wirings. To achieve this, it is possible to divide a wiring into a plurality of wirings .

[0249] In FIG. 30(A), in the semiconductor device of FIG. 27(A), the wiring 112 is divided into a plurality of wirings such as the wirings 112A~ 112C, the wiring 113 is divided into a plurality of wirings such as the wirings 113A~113D, the wiring 115 is divided into a plurality of wirings such as the wirings 115A~115G, and the wiring 212 is divided into a plurality of wirings such as the wirings 212A~212B. And the first terminal of the transistor 201 is connected to the wiring 115D. Or, the first terminal of the transistor 202 is connected to the wiring 115E, and the gate of the transistor 202 is connected to the wiring 113C. Or, the first terminal of the transistor 203 is connected to the wiring 11 2C. Or, the first terminal of the transistor 204 is connected to the wiring 115F. Or, the first terminal and the gate of the transistor 205 are connected to the wiring 212A. Or, the first terminal of the transistor 206 is connected to the wiring 212B. Or, the gate of the transistor 206 is connected to the wiring 113D. Or, the first terminal of the transistor 20 7 is connected to the wiring 115G.

[0250] Note that the wirings 112A~112C can have the same function as the wiring 112. Or, the wirings 113A~113D can have the same function as the wiring 113. Or, the wirings 115A~115G can have the same function as the wiring 115.​ Or, the wirings 212A to 212B can have the same function as the wiring 212. Therefore, the signal IN1 can be input to the wirings 112A to 112C. Or, the signal IN2 can be input to the wirings 113A to 113D. Also, the voltage V1 can be supplied to the wirings 115A to 115G. Or, the signal IN4 can be input to the wirings 212A to 212B. The wirings 112A to 112C can be supplied with different voltages or different signals. Or, the wirings 113A to 113D can be supplied with different voltages or different signals. Or, the wirings 115A to 115G can be supplied with different voltages or different signals. Or, the wirings 212A to 212B can be supplied with different voltages or different signals. This is possible.

[0251] Next, in the configurations described in FIGS. 10(A) to (C), FIGS. 14(A), FIGS. 16(A), FIGS. 17(A), FIGS. 20(A ), FIGS. 21(A), FIGS. 23(A), FIGS. 25(A), FIGS. 27(A) to (C), FIGS. 28(A) to (C), FIGS. 29(A) to (C), FIGS. 30(A), and FIGS. 47(A) to (B), some of the transistors can be omitted. For example, one of the transistor 201 and the transistor 204 can be omitted. Or, for example, assuming that the semiconductor device has the transistor 206. In this case, one or both of the transistor 205 and the transistor 207 can be omitted. Also, as needed, a part of the transistors can be omitted.

[0252] FIG. 30B shows a semiconductor device in FIG. 27A in which the transistor 201 and the transistor The configuration in which the transistor 205 is omitted is shown. Since the number of transistors is reduced, the layout area is reduced. Alternatively, the power consumption can be reduced.

[0253] Next, Figs. 10(A)-(C), 14(A), 16(A), 17(A), and 20(A) ), Fig. 21(A), Fig. 23(A), Fig. 25(A), Fig. 27(A)-(C), Fig. 28(A) ~(C), Figs. 29(A)~(C), Figs. 30(A)~(B), and Figs. 47(A)~(B). In the configuration to be described, a capacitor 220 connected between the node 13 and the wiring 211 is newly added. It is possible to provide it in

[0254] In FIG. 30C, a semiconductor device shown in FIG. 17A is provided with a wiring 211 connected between the node 13. In this configuration, a capacitive element 220 is newly provided. During the flip-flop operation, the potential of the node 13 is likely to rise. As a result, the channel width of the transistor 203 can be reduced. Alternatively, the fall time or rise time of the signal GOUT can be shortened. For example, a MOS capacitor can be used as the capacitive element.

[0255] Next, Figs. 10(A)-(C), 14(A), 16(A), 17(A), and 20(A) ), Fig. 21(A), Fig. 23(A), Fig. 25(A), Fig. 27(A)-(C), Fig. 28(A) ~(C), Figs. 29(A)~(C), Figs. 30(A)~(C), and Figs. 47(A)~(B). In the described configuration, it is possible to generate a signal other than the signal GOUT. For example, Assume that the semiconductor device of this embodiment generates a signal SOUT separately from the signal GOUT. And, for example, assume that a plurality of semiconductor devices are connected. In this case, the signal SOUT can be input as a start pulse to a semiconductor device in another stage without being output to the wiring 211. Therefore, the delay or rounding of the signal SOUT becomes smaller compared to the signal GOUT. Therefore, since the semiconductor device can be driven using a signal with a small delay or rounding, the delay of the output signal of the semiconductor device can be reduced. To achieve this, in the configurations described in FIGS. 14(A), 16(A), 17(A), 20(A), 21(A), 23(A), 25(A), 27(A) - (C), 28(A) - (C), 29(A) - (C), 30(A) - (C), and 47(A) - (B), it is possible to newly provide the transistor 208. (A), FIG. 25(A), FIGS. 27(A) - (C), FIGS. 28(A) - (C), FIGS. 29(A) - (C), FIGS. 30(A) - (C), and FIGS. 47(A) - (B), it is possible to newly provide the transistor 208. (C), FIGS. 30(A) - (C), and FIGS. 47(A) - (B), it is possible to newly provide the transistor 208. (C), FIGS. 30(A) - (C), and FIGS. 47(A) - (B), it is possible to newly provide the transistor 208.

[0256] FIG. 31(A) shows a configuration in which the transistor 208 is newly provided in the semiconductor device of FIG. 17(A). The transistor 208 can have the same function as the transistor 203 and has the same polarity. The first terminal of the transistor 208 is connected to the wiring 112, the second terminal of the transistor 208 is connected to the wiring 214, and the gate of the transistor 208 is connected to the node 13. The wiring 214 can have the same function as the wiring 211. And, for example, if a plurality of semiconductor devices are connected, the wiring 211 can be connected to the wiring 212 of another semiconductor device (for example, the semiconductor device in the next stage). For example, as shown in FIG. 31(B), it is possible to newly provide the transistor 209. For example, as shown in FIG. 31(B), it is possible to newly provide the transistor 209. Yes. The transistor 209 can have the same function as the transistor 203 and can have the same polarity. The first terminal of the transistor 209 is connected to the wiring 115 , the second terminal of the transistor 209 is connected to the wiring 214, and the gate of the transistor 2 09 is connected to the node 12. Note that FIG. 31(C) separately shows a timing chart when generating the signal SOUT instead of the signal GOUT.

[0257] As described above, the present embodiment is not limited to the configuration described in FIG. 14(A), and various other configurations can be used.

[0258] Next, in the configurations described in FIGS. 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), FIG. 20(A ), FIG. 21(A), FIG. 23(A), FIG. 25(A), FIG. 27(A) to (C), FIG. 28(A) to (C), FIG. 29(A) to (C), FIG. 30(A) to (C), FIG. 31(A) to (B), and FIG. 47(A) to (B), it is possible to use a P-channel type transistor as the transistor. Only some of the plurality of transistors included in the semiconductor device can be P-channel type. That is, the semiconductor device of the present embodiment can be a CMOS circuit.

[0259] FIG. 32(A) shows a configuration in which a P-channel type transistor is used as the transistor in the semiconductor device of FIG. 27(A). The transistors 201p to 207p have the same functions as the transistors 201 to 207 and are P-channel type. In such a case, the voltage V2 is supplied to the wiring 115. As shown in the timing chart of FIG. 32(B), Sea urchin, signal IN1, signal IN2, signal IN4, signal IN5, potential of node 11, node 1 The potential of 2, the potential of node 13, and signal GOUT can be inverted. It is noted that .

[0260] Next, the ratio of the channel widths of transistors 201 to 209 and the size of the transistors will be described .

[0261] First, transistor 201 supplies a potential to wiring 211. And the load of wiring 211 is larger than the load of node 12. Therefore, the channel width of transistor 201 is larger than the channel width of the transistor that circuit 100 has. In such a case, the channel width of transistor 201 is preferably 10 times or less the channel width of transistor 101 . More preferably, it is preferably 5 times or less. Even more preferably, it is preferably 3 times or less .

[0262] Next, the potential of the gate of transistor 202 changes more steeply than the potential of the gate of transistor 201. Therefore, the channel width of transistor 202 is preferably smaller than the channel width of transistor 201. In such a case, the channel width of transistor 201 is preferably 10 times or less the channel width of transistor 202. More preferably it is preferably 7 times or less. Even more preferably, it is preferably 5 times or less . is preferable. .

[0263] Next, transistor 203 changes the potential of wiring 211 by supplying a potential to wiring 211. And a large load (for example, a gate signal line, a pixel) is connected to wiring 211 . A transistor, a capacitor element, or the like is connected. Therefore, the channel width of transistor 203 is the largest among the transistors of the semiconductor device of the present embodiment. For example, the channel width of transistor 203 is preferably 10 times or less that of transistor 201. More preferably, it is preferably 5 times or less. Even more preferably, it is preferably 2 times or less.

[0264] Next, transistor 204 supplies a potential to node 13. And the load of node 13 is larger than the load of node 12. Therefore, the channel width of transistor 204 is smaller than the channel width of transistor 201. In such a case, the channel width of transistor 201 is preferably 5 times or less that of transistor 204. More preferably, it is preferably 3 times or less. Even more preferably, it is preferably 2 times or less.

[0265] Next, by increasing the channel width of transistor 205, in period A, the change in the potential of node 13 can be made steep, so that the drive frequency of the semiconductor device can be increased. Therefore, the channel width of transistor 205 is larger than the channel width of transistor 201 or the transistors of circuit 100. Or, the channel width of transistor 205 is smaller than the channel width of transistor 203. In such a case, the channel width of transistor 203 is preferably 10 times or less that of transistor 205. More preferably, it is preferably 5 times or less. Even more preferably, it is preferably 2 times or less.

[0266] ​​​​​​Next, the transistor 206 supplies a potential to node 13 to maintain the potential of node 13. Therefore, the channel width of the transistor 206 is smaller than the channel width of the transistor 205. In such a case, it is preferable that the channel width of the transistor 205 is not more than three times the channel width of the transistor 206. More preferably, it is preferable that it is not more than two times. Even more preferably, it is preferable that it is not more than 1.8 times.

[0267] Next, the transistor 207 supplies a potential to node 13 to decrease the potential of node 13. However, by slowing down the decrease in the potential of node 13, the transistor 203 can be turned on during period E. Thus, during period E, since the transistor 203 can supply a potential to the wiring 211, the potential of the wiring 211 can be quickly decreased. Therefore, it is preferable that the channel width of the transistor 207 is smaller than the channel width of the transistor 205. In such a case, it is preferable that the channel width of the transistor 2 05 is not more than ten times the channel width of the transistor 207. More preferably, it is preferable that it is not more than seven times. Even more preferably, it is preferable that it is not more than five times.

[0268] Next, the transistor 208 supplies a potential to the wiring 214. And the load of the wiring 214 is smaller than the load of the wiring 211. Therefore, the channel width of the transistor 208 is smaller than the channel width of the transistor 203. In such a case, it is preferable that the channel width of the transistor 203 is not more than ten times that of the transistor 208. More preferably, it is ​It is preferably less than or equal to [multiple] times. More preferably, it is preferably less than or equal to 4 times.

[0269] Next, the transistor 209 supplies a potential to the wiring 214. And the load of the wiring 214 is smaller than the load of the wiring 211. Therefore, the channel width of the transistor 209 is smaller than the channel width of the transistor 203. In such a case, the channel width of the transistor 203 is preferably less than or equal to 7 times the channel width of the transistor 209. More preferably it is preferably less than or equal to 4 times. Even more preferably, it is preferably less than or equal to 2.5 times is preferable.

[0270] In addition, considering the ratio of the channel widths of the above transistors, the channel width of the transistor 201 is preferably 1000 μm or more and 5000 μm or less. More preferably the channel width of the transistor 201 is preferably 1500 μm or more and 4000 μm or less is preferable. More preferably, the channel width of the transistor 201 is preferably 2000 μm or more and 3 000 μm or less. Or the channel width of the transistor 202 is preferably 2 00 μm or more and 3000 μm or less. More preferably it is preferably 300 μm or more and 2000 μm or less. Even more preferably, it is preferably 400 μm or more and 10 00 μm or less. Or the channel width of the transistor 203 is preferably 20 00 μm or more and 30000 μm or less. More preferably it is preferably 3000 μm or more and 15000 μm or less. Even more preferably, it is preferably 4000 μm or more and 10 0000 μm or less. Or the channel width of the transistor 204 is preferably 20 ​The width is preferably 200 μm or more and 2500 μm or less. More preferably, it is preferably 400 μm or more and 2000 μm or less. Even more preferably, it is preferably 700 μm or more and 1500 μm or less. Or, the channel width of transistor 205 is preferably 500 μm or more and 3000 μm or less. More preferably, it is 1000 μm or more and 2500 μm or less. Even more preferably, it is 1500 μm or more and 2000 μm or less. Or, the channel width of transistor 206 is preferably 300 μm or more and 2000 μm or less. More preferably, it is 500 μm or more and 1500 μm or less. Even more preferably, it is 800 μm or more and 1300 μm or less. Or, the channel width of transistor 207 is preferably 100 μm or more and 1500 μm or less. More preferably, it is 300 μm or more and 1000 μm or less. Even more preferably, it is 400 μm or more and 800 μm or less. Or, the channel width of transistor 208 is preferably 300 μm or more and 5000 μm or less. More preferably, it is 500 μm or more and 2000 μm or less. Even more preferably, it is 800 μm or more and 1500 μm or less. Or, the channel width of transistor 209 is preferably 200 μm or more and 2000 μm or less. More preferably, the channel width of transistor 209 is preferably 400 μm or more and 1500 μm or less. Even more preferably, the channel width of transistor 209 is preferably 500 μm or more and 1000 μm or less.

[0271] (Embodiment 3) In this embodiment, a display device, a pixel included in the display device, and a shift register circuit included in the display device will be described. Note that the shift register circuit can include the semiconductor devices described in Embodiments 1 to 2. First, the display device will be described with reference to FIGS. 33(A) to (D). The display device includes a circuit 1001, a circuit 1002, a circuit 1003_1, a pixel section 1004, and a terminal 1005.

[0272] A plurality of wirings can extend from the circuit 1003_1 and be arranged in the pixel section 1004. The plurality of wirings can function as gate signal lines or scanning lines. Alternatively, a plurality of wirings can extend from the circuit 1002 and be arranged in the pixel section 1004. The plurality of wirings can function as video signal lines or data lines. Then, a plurality of pixels are arranged corresponding to the plurality of wirings extending from the circuit 1003_1 and the plurality of wirings extending from the circuit 1002. For example, various other wirings can be arranged in the pixel section 1004. The wirings can function as gate signal lines, data lines, power supply lines, capacitance lines, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. A plurality of wirings can extend from the circuit 1003_1 and be arranged in the pixel section 1004. The plurality of wirings can function as gate signal lines or scanning lines. Alternatively, a plurality of wirings can extend from the circuit 1002 and be arranged in the pixel section 1004. The plurality of wirings can function as video signal lines or data lines. Then, a plurality of pixels are arranged corresponding to the plurality of wirings extending from the circuit 1003_1 and the plurality of wirings extending from the circuit 1002. For example, various other wirings can be arranged in the pixel section 1004. The wirings can function as gate signal lines, data lines, power supply lines, capacitance lines, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. A plurality of wirings can extend from the circuit 1003_1 and be arranged in the pixel section 1004. The plurality of wirings can function as gate signal lines or scanning lines. Alternatively, a plurality of wirings can extend from the circuit 1002 and be arranged in the pixel section 1004. The plurality of wirings can function as video signal lines or data lines. Then, a plurality of pixels are arranged corresponding to the plurality of wirings extending from the circuit 1003_1 and the plurality of wirings extending from the circuit 1002. For example, various other wirings can be arranged in the pixel section 1004. The wirings can function as gate signal lines, data lines, power supply lines, capacitance lines, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. A plurality of wirings can extend from the circuit 1003_1 and be arranged in the pixel section 1004. The plurality of wirings can function as gate signal lines or scanning lines. Alternatively, a plurality of wirings can extend from the circuit 1002 and be arranged in the pixel section 1004. The plurality of wirings can function as video signal lines or data lines. Then, a plurality of pixels are arranged corresponding to the plurality of wirings extending from the circuit 1003_1 and the plurality of wirings extending from the circuit 1002. For example, various other wirings can be arranged in the pixel section 1004. The wirings can function as gate signal lines, data lines, power supply lines, capacitance lines, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. A plurality of wirings can extend from the circuit 1003_1 and be arranged in the pixel section 1004. The plurality of wirings can function as gate signal lines or scanning lines. Alternatively, a plurality of wirings can extend from the circuit 1002 and be arranged in the pixel section 1004. The plurality of wirings can function as video signal lines or data lines. Then, a plurality of pixels are arranged corresponding to the plurality of wirings extending from the circuit 1003_1 and the plurality of wirings extending from the circuit 1002. For example, various other wirings can be arranged in the pixel section 1004. The wirings can function as gate signal lines, data lines, power supply lines, capacitance lines, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like.

[0273] Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like. Note that the circuit 1001 has a function of supplying a signal, voltage, current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 has a function of controlling the circuit 1002 and the circuit 1003. As described above, the circuit 1001 can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, or the like.

[0274] Note that circuit 1002 has a function of supplying a video signal to pixel section 1004. Or, circuit 1002 has a function of controlling the luminance or transmittance of the pixels included in pixel section 1004 and the like. Thus, circuit 1002 functions as a driving circuit, a source driver, or a signal line driving circuit.

[0275] Note that circuits 1003_1 and 1003_2 have a function of supplying a scanning signal or a gate signal to pixel section 1 004. Or, circuits 1003_1 and 1003_2 have a function of selecting the pixels included in pixel section 1004. Thus, circuits 1003_1 and 1003_2 function as a driving circuit, a gate driver, or a scanning line driving circuit. Note that circuits 1003_1 and 1003_2 can drive the same wiring, and can also drive different wirings. For example, circuit 1003_1 can drive the gate signal lines of odd-numbered rows, and circuit 1003_2 can drive the gate signal lines of even-numbered rows.

[0276] Note that circuits 1001, 1002, 1003_1, and 1003_2 can be formed on the same substrate 1006 as pixel section 1004, or can be formed on a substrate different from pixel section 1004 (for example, a semiconductor substrate or an SOI substrate).

[0277] FIG. 33(A) shows a configuration in which circuit 1003_1 is formed on the same substrate 1006 as pixel section 1004, and circuits 1001 and 1002 are formed on a substrate different from pixel section 1004. The driving frequency of circuit 1003_1 is lower than that of circuit 1001 or circuit 1002. Therefore, ​​​​Thus, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost. This makes it possible to enlarge the display device. The display device can be manufactured at low cost.

[0278] FIG. 33(B) shows a configuration in which circuits 1003_1 and 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuits 1001 and 1002 are formed on a substrate different from the pixel portion 1004. The driving frequencies of circuits 1003_1 and 1003_2 are lower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost. FIG. 33(B) shows a configuration in which circuits 1003_1 and 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuits 1001 and 1002 are formed on a substrate different from the pixel portion 1004. The driving frequencies of circuits 1003_1 and 1003_2 are lower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost. The driving frequencies of circuits 1003_1 and 1003_2 are lower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost. The driving frequencies of circuits 1003_1 and 1003_2 are lower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost. The driving frequencies of circuits 1003_1 and 1003_2 are lower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost. The driving frequencies of circuits 1003_1 and 1003_2 are lower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost. The driving frequencies of circuits 1003_1 and 1003_2 are lower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be enlarged. The display device can be manufactured at low cost.

[0279] FIG. 33(C) shows a configuration in which circuits 1002, 1003_1, and 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuit 1001 is formed on a substrate different from the pixel portion 1004. FIG. 33(C) shows a configuration in which circuits 1002, 1003_1, and 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuit 1001 is formed on a substrate different from the pixel portion 1004. FIG. 33(C) shows a configuration in which circuits 1002, 1003_1, and 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuit 1001 is formed on a substrate different from the pixel portion 1004.

[0280] FIG. 33(D) shows a configuration in which a part of circuit 1002, circuit 1002a, circuit 1003_1, and circuit 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuits 1001 and another part of circuit 1002, circuit 1002b, are formed on a substrate different from the pixel portion 1004. In this case, as circuit 1002a, it is possible to use a circuit having a low driving frequency such as a switch, a shift register, and / or a selector. FIG. 33(D) shows a configuration in which a part of circuit 1002, circuit 1002a, circuit 1003_1, and circuit 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuits 1001 and another part of circuit 1002, circuit 1002b, are formed on a substrate different from the pixel portion 1004. In this case, as circuit 1002a, it is possible to use a circuit having a low driving frequency such as a switch, a shift register, and / or a selector. FIG. 33(D) shows a configuration in which a part of circuit 1002, circuit 1002a, circuit 1003_1, and circuit 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuits 1001 and another part of circuit 1002, circuit 1002b, are formed on a substrate different from the pixel portion 1004. In this case, as circuit 1002a, it is possible to use a circuit having a low driving frequency such as a switch, a shift register, and / or a selector. FIG. 33(D) shows a configuration in which a part of circuit 1002, circuit 1002a, circuit 1003_1, and circuit 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuits 1001 and another part of circuit 1002, circuit 1002b, are formed on a substrate different from the pixel portion 1004. In this case, as circuit 1002a, it is possible to use a circuit having a low driving frequency such as a switch, a shift register, and / or a selector. FIG. 33(D) shows a configuration in which a part of circuit 1002, circuit 1002a, circuit 1003_1, and circuit 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and circuits 1001 and another part of circuit 1002, circuit 1002b, are formed on a substrate different from the pixel portion 1004. In this case, as circuit 1002a, it is possible to use a circuit having a low driving frequency such as a switch, a shift register, and / or a selector.

[0281] ​Next, the pixels included in the pixel section 1004 will be described with reference to FIG. 33(E). Pixel 3 020 includes a transistor 3021, a liquid crystal element 3022, and a capacitor element 3023. The first terminal of the transistor 3021 is connected to the wiring 3031, and the second terminal of the transistor 3021 is connected to one electrode of the liquid crystal element 3022 and one electrode of the capacitor element 3023. The gate of the transistor 3021 is connected to the wiring 3032. The other electrode of the liquid crystal element 302 2 is connected to the electrode 3034, and the other electrode of the capacitor element 3023 is connected to the wiring 3 033.

[0282] A video signal is input to the wiring 3031 from the circuit 1002 described in FIGS. 33(A) to (D). Therefore, the wiring 3031 can function as a signal line, a video signal line, or a source signal line. A scanning signal, a selection signal, or a gate signal is input to the wiring 3032 from the circuit 10 03_1 and / or the circuit 1003_2 described in FIGS. 33(A) to (D). Therefore, the wiring 3032 can function as a signal line, a scanning line, or a gate signal line. A certain voltage can be supplied to the wiring 3033 and the electrode 3034 from the circuit 1001 described in FIGS. 33(A) to (D). Therefore, the wiring 303 3 can function as a power supply line or a capacitor line. Alternatively, the electrode 303 4 can function as a common electrode or a counter electrode. For example, a precharge voltage can be supplied to the wiring 3 031. The precharge voltage is approximately equal to the voltage supplied to the electrode 3034. As another example, a signal can be input to the wiring 3033. In this way, the voltage applied to the liquid crystal element 3022 can be adjusted. For example, a precharge voltage can be supplied to the wiring 3031. The precharge voltage is approximately equal to the voltage supplied to the electrode 3034. As another example, a signal can be input to the wiring 3033. In this way, the voltage applied to the liquid crystal element 3022 can be adjusted. The precharge voltage is approximately equal to the voltage supplied to the electrode 3034. can be adjusted. Thus, the voltage applied to the liquid crystal element 3022 Since it becomes possible to control, the amplitude of the video signal can be reduced, or reverse driving can be realized. Or the like. As another example, a signal can be input to the electrode 3034. In this way, frame reverse driving can be realized.

[0283] The transistor 3021 has a function of controlling the conduction state between the wiring 3031 and one electrode of the liquid crystal element 3022. Or it has a function of controlling the timing for writing a video signal to the pixel. In this way, the transistor 3021 has a function as a switch. The capacitor element 3023 has a function of holding the potential difference between one electrode of the liquid crystal element 3022 and the potential of the wiring 3033. Or it has a function of holding the voltage applied to the liquid crystal element 3022 to be constant. In this way, the capacitor element 3023 has a function as a holding capacitor.

[0284] Next, the shift register circuit will be described with reference to FIG. 34. The shift register circuit may be included in the circuit 1002, the circuit 1003_1, and / or the circuit 1003_2.

[0285] The shift register circuit 1100 has a plurality of flip-flop circuits such as flip-flop circuits 1101_1 to 1101_N (N is a natural number). Note that as the flip-flop circuits 1101_1 to 1101_N, semiconductor devices described in Embodiments 1 to 2 can be used respectively.

[0286] The shift register circuit 1100 is connected to wirings 1111_1 to 1111_N, a wiring 1112, a wiring 1113, a wiring 1114, a wiring 1115, and a wiring 1116. And the flip In the flip-flop circuit 1101_i (where i is any natural number from 1 to N), wiring 2 11 is connected to wiring 1111_i, wiring 112 is connected to wiring 1112, wiring 1 13 is connected to wiring 1113, wiring 212 is connected to wiring 1111_i - 1, and the wiring 213 is connected to wiring 1111_i + 1, and wiring 115 is connected to wiring 1115. However, for the flip-flop circuits in the odd-numbered stages and the flip-flop circuits in the even-numbered stages, the connection destinations of wiring 112 and wiring 113 are reversed. In the flip-flop circuit 1101_1, wiring 212 is connected to wiring 1114. In the flip-flop circuit 1101_N, wiring 213 is connected to wiring 1116.

[0287] Next, an example of the signal or voltage input to or output from each wiring, and the function of each wiring will be described. Signals GOUT_1 to GOUT_N are output from wirings 1111_1 to 1111_N, respectively. The signals GOUT_1 to GOUT_N are often the output signals of the flip- flop circuits 1101_1 to 1101_N, and can have the same function as the signal GOUT. Therefore, the wirings 1111_1 to 1111_N can have the same function as wiring 211. Signal GCK1 is input to wiring 1112, and signal GCK2 is input to wiring 111 3. The signal GCK1 can have the same function as the signal IN2 or the signal IN3, and the signal GCK2 can have the same function as the signal IN2 or the signal IN3. Therefore, wiring 1112 can have the same function as wiring 112 or wiring 113, and wiring 1113 can have the same function as wiring 112 or wiring 113. It is possible to have functions like this. The signal GSP is input to the wiring 1114. The signal GSP can have functions similar to the signal IN4. Therefore, the wiring 1114 can have functions similar to the wiring 212. The voltage V1 is supplied to the wiring 1115 . Therefore, the wiring 1115 can have functions similar to the wiring 115 . The signal GRE is input to the wiring 1116. The signal GRE can have functions similar to the signal IN5. Therefore, the wiring 1116 can have functions similar to the wiring 213 .

[0288] Next, the operation during one frame period of the shift register circuit in FIG. 34 will be described with reference to the timing chart in FIG. 35.

[0289] For example, assume that the signal GOUT_i - 1 becomes the H level. Then, the flip - flop circuit 1101_i starts operating during period C. After that, when the signals GCK1 and GCK 2 are inverted, the flip - flop circuit 1101_i starts operating during period D. Therefore, the signal GOUT_i becomes the H level. Since the signal GOUT_i is input to the flip - flop circuit 1101_i + 1, the flip - flop circuit 1101_i + 1 starts operating during period C. After that, when the signals GCK1 and GCK2 are inverted , the flip - flop circuit 1101_i + 1 starts operating during period D. Then , the signal GOUT_i + 1 becomes the H level. Since the signal GOUT_i + 1 is input to the flip - flop circuit 1101_i, the flip - flop circuit 1101_i starts operating during period E . Therefore, the signal GOUT_i becomes the L level. After that, the signal G Every time CK1 and signal GCK2 are inverted, flip-flop circuit 1101_i alternates between operating in period A and operating in period B. Therefore, signal GOUT_i is maintained at the L level. In FIG. 35, one of signals GCK1 and GCK2 is denoted as GCK .

[0290] Note that the shift register of this embodiment can use the semiconductor devices described in Embodiments 1 to 2. Therefore, since the H-level values of signals GOUT_1 to GOUT_N can be raised to V2, the time during which the transistors included in the pixels are on can be lengthened. As a result, a video signal can be written to the pixels in sufficient time, thereby improving the display quality. Alternatively, since the fall time and rise time of signals GOUT_1 to GOUT_N can be shortened, it is possible to prevent a video signal for pixels belonging to another row from being written to the pixels belonging to the selected row. As a result, the display quality can be improved. Alternatively, since the variation in the fall time of signals GOUT_1 to GOUT_N can be suppressed, the variation in the influence of feed-through on the video signals held by the pixels can be suppressed. Therefore, display unevenness such as crosstalk can be suppressed. Alternatively, since the size of the transistors can be reduced, the load (e.g., parasitic capacitance, etc.) of the shift register can be reduced. As a result, the size of an external circuit having a function of supplying a signal or voltage to the shift register or the current supply ability thereof can be reduced, and thus the size of the external circuit or the size of a display device having the external circuit can be reduced. ​​​​​​​​​​​​​​​

[0291] (Embodiment 4) In this embodiment, a signal line driving circuit will be described. Note that the signal line driving circuit can be represented as a semiconductor device or a signal generation circuit.

[0292] First, the configuration of the signal line driving circuit will be described with reference to FIG. 36(A). The signal line driving circuit includes circuit 2001 and circuit 2002. Circuit 2002 includes a plurality of circuits 2002_1 to 2002_N (N is a natural number). Circuits 2002_1 to 2002_N each include a plurality of transistors 2003_1 to 2003_k (k is a natural number). Transistors 2003_1 to 2003_k are N-channel type. However, it is not limited thereto, and transistors 2003_1 to 2003_k can be P-channel type, or can be CMOS type switches. However, it is not limited thereto, and transistors 2003_1 to 2003_k can be P-channel type, or can be CMOS type switches.

[0293] The connection relationship of the signal line driving circuit will be described by taking circuit 2002_1 as an example. The first terminals of transistors 2003_1 to 2003_k are each connected to wirings 2004_1 to 2004_k. The second terminals of transistors 2003_1 to 2003_k are each connected to wirings S1 to Sk. The gates of transistors 2003_1 to 2003_k are connected to wiring 2005_1.

[0294] Circuit 2001 has a function of controlling the timing to output H-level signals to wirings 2005_1 to 2005_N in order. Or it has a function of selecting circuits 2002_1 to 2002_N in order. Thus, circuit 2001 has a function as a shift register. ​​​​​​​​​​​​Circuit 2001 can output H-level signals to wirings 2005_1 to 2005_N in various orders. Alternatively, circuits 2002_1 to 2002_N can be selected in various orders. In this way, circuit 2001 can function as a decoder. Circuit 2002_1 has a function of controlling the timing at which wirings 2004_1 to 2004_k and wirings S1 to Sk are conducted. Alternatively, circuit 2002_1 has a function of controlling the timing at which the potentials of wirings 2004_1 to 2004_k are supplied to wirings S1 to Sk. In this way, circuit 2002_1 can function as a selector. Note that circuits 2002_2 to 2002_N can have the same functions as circuit 2002_1. Transistors 2003_1 to 2003_N each have a function of controlling the timing at which wirings 2004_1 to 2004_k and wirings S1 to Sk are conducted. Alternatively, transistors 2003_1 to 2003_N each have a function of controlling the timing at which the potentials of wirings 2004_1 to 2004_k are supplied to wirings S1 to Sk. For example, transistor 2003_1 has a function of controlling the timing at which wiring 2004_1 and wiring S1 are conducted. Alternatively, transistor 2003_1 has a function of controlling the timing at which the potential of wiring 2004_1 is supplied to wiring S1. In this way, transistors 2003_1 to 2003_N can each function as a switch. Signals are input to wirings 2004_1 to 2004_k respectively. The signals are

[0295]

[0296]

[0297] ​​​​​​​​​​​​​​​ It is an analog signal corresponding to image information or an image signal. Thus, such a signal can function as a video signal and can have the function of a signal line. Therefore, the wirings 2004_1 to 2004_k can function as signal lines. For example, depending on the pixel configuration, it can be a digital signal, an analog voltage, or an analog current .

[0298] Next, the operation of the signal line driving circuit in FIG. 36(A) will be described with reference to the timing chart in FIG. 36(B). In FIG. 36(B), signals 2015_1 to 2015_N and signals 2014_1 to 2014_k are shown. The signals 2015_1 to 2015_N are each the output signals of circuit 2 001, and the signals 2014_1 to 2014_k are each the signals input to the wirings 2004_1 to 2004_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into period T0 and periods T1 to TN. Period T0 is a period for simultaneously applying a precharge voltage to the pixels belonging to the selected row and can function as a precharge period . Periods T1 to TN are each a period for writing a video signal to the pixels belonging to the selected row and can function as write periods . First, in period T0, circuit 2001 supplies H-level signals to the wirings 2005_1 to 2005_N. Then, for example, in circuit 2002_1, transistors 200 3_1 to 2003_k turn on, so the wirings 2004_1 to 2004_k and wiring S1

[0299] ​​​At this time, the wirings 2004_1 to 2004_k are in a conductive state. Therefore, the precharge voltage Vp is supplied to the transistor 2003_ 1 to 2003_k, and are output to the wirings S1 to Sk, respectively. Since the voltage Vp is written to the pixels in the selected row, The element is precharged.

[0300] In the period T1 to the period TN, the circuit 2001 outputs an H-level signal to the wirings 2005_1 to 2005_2. For example, in the period T1, the circuit 2001 outputs a signal of H level A signal is output to the wiring 2005_1. Then, the transistors 2003_1 to 2003_k is turned on, so that the wiring 2004_1 to 2004_k and the wiring S1 to Sk are in a conductive state. At this time, the wirings 2004_1 to 2004_k are connected to Data(S1) to Data( Data(S1) to Data(Sk) are input to the transistors 20 Among the pixels belonging to the selected row via 03_1 to 2003_k, the pixels in the 1st to kth columns In this way, in the periods T1 to TN, , the video signal is written in k columns in sequence.

[0301] As described above, the video signal is written to the pixels in a number of columns. Therefore, the number of connections to external circuits can be reduced. This allows for improved yield, improved reliability, reduced part count, and / or reduced costs. Alternatively, the video signal can be written to the pixels in multiple columns at a time. This allows the write time to be extended, thus preventing insufficient writing of video signals. Since it can be done, the display quality can be improved.

[0302] Note that by increasing k, the number of connections to the external circuit can be reduced. However , if k is too large, the writing time to the pixel becomes short. Therefore, it is preferable that k ≤ 6 . More preferably, it is preferable that k ≤ 3. Even more preferably, it is preferable that k = 2 .

[0303] In particular, when the color elements of the pixel are n (n is a natural number), it is preferable that k = n, or k = n × d (d is a natural number). For example, when the color elements of the pixel are divided into three: red (R), green (G), and blue (B) , it is preferable that k = 3, or k = 3 × d. For example, when the pixel is divided into m (m is a natural number) sub-pixels (sub-pixels are also referred to as sub-pixels or auxiliary pixels) , it is preferable that k = m, or k = m × d. For example, when the pixel is divided into two sub-pixels, it is preferable that k = 2. Or, when the color elements of the pixel are n pieces, it is preferable that k = m × n, or k = m × n × d.

[0304] For example, this embodiment is used in a display device. In this case, the signal line driving circuit of this embodiment can be formed on the same substrate as the pixel portion, or can be formed on a substrate different from the pixel portion (for example, a silicon substrate or an SOI substrate, etc.). Or, a part of the signal line driving circuit of this embodiment (for example, circuit 2002) is formed on the same substrate as the pixel portion, and another part of the signal line driving circuit of this embodiment (for example, circuit 2001) can be formed on a substrate different from the pixel portion . . .

[0305] ​FIG. 36(C) shows a configuration in which circuit 2001 and circuit 2002 are formed on the same substrate as pixel section 2007. In this way, the number of connections between the substrate on which the pixel section is formed and the external circuit can be reduced, thus achieving an improvement in yield, an improvement in reliability, a reduction in the number of components, or a reduction in cost. In particular, since scanning line drive circuits 2006A and 2006B are also formed on the same substrate as pixel section 2007, the number of connections to the external circuit can be further reduced. FIG. 36(D) shows a configuration in which circuit 2002 is formed on the same substrate as pixel section 2007 and circuit 2001 is formed on a different substrate for pixel section 2007. Even in this case, the number of connections between the substrate on which the pixel section is formed and the external circuit can be reduced, thus achieving an improvement in yield, an improvement in reliability, a reduction in the number of components, or a reduction in cost. Or, since the number of circuits formed on the same substrate as pixel section 2007 is reduced, the frame can be made smaller. Note that it is possible to use the shift register circuit of Embodiment 3 as circuit 2001. In this way, it becomes possible to make the polarity of all transistors N-channel type, thus reducing the manufacturing process. Or, since deterioration of the transistors can be suppressed, the life of the signal line drive circuit can be extended. (Embodiment 5) In this embodiment, a protection circuit will be described. The protection circuit is provided for the purpose of preventing semiconductor devices (such as transistors, capacitor elements, circuits, etc.) connected to a certain wiring from being destroyed by ESD (electrostatic discharge).

[0306]

[0307]

[0308] (Embodiment 5) In this embodiment, a protection circuit will be described. The protection circuit is provided for the purpose of preventing semiconductor devices (such as transistors, capacitor elements, circuits, etc.) connected to a certain wiring from being destroyed by ESD (electrostatic discharge).

[0309] ​​​​​​​​​​​​ First, the protection circuit will be described with reference to FIG. 37(A). The protection circuit 3000 includes a transistor 3001 and a transistor 3002. The transistors 3001 and 3002 are assumed to be N-channel type. However, the present embodiment is not limited to this, and it can be P-channel type.

[0310] The connection relationship of the protection circuit 3000 will be described. The first terminal of the transistor 3001 is connected to the wiring 3012, the second terminal of the transistor 3001 is connected to the wiring 3011, and the gate of the transistor 3001 is connected to the wiring 3011. The first terminal of the transistor 3002 is connected to the wiring 3013, the second terminal of the transistor 3002 is connected to the wiring 3011, and the gate of the transistor 3002 is connected to the wiring 3013.

[0311] An example of a signal or voltage input to the wirings 3011 to 3013 and the functions of these wirings will be described. A signal (for example, a scanning signal, a video signal, a clock signal, a start signal, a reset signal, or a selection signal, etc.) or a voltage (a negative power supply voltage, a ground voltage, a positive power supply voltage, etc.) is supplied to the wiring 3011. Therefore, the wiring 3011 can function as a signal line, a power supply line, etc. A positive power supply voltage (VDD) is supplied to the wiring 3012. Therefore, the wiring 3012 can function as a power supply line. A negative power supply voltage (VSS) or a ground voltage, etc. is supplied to the wiring 3013. Therefore, the wiring 3013 can function as a power supply line.

[0312] The operation of the protection circuit 3000 will be described. If the potential of the wiring 3011 is generally between VSS and VD D, the transistors 3001 and 3002 will turn off. Therefore, the voltage or signal supplied to the wiring 3011 is supplied to the semiconductor device connected to the wiring 3011. However, due to the influence of static electricity or the like, a potential higher than the power supply voltage or a potential lower than the power supply voltage is supplied to the wiring 3011. And, due to this potential higher than the power supply voltage or the potential lower than the power supply voltage, the semiconductor device connected to the wiring 3011 may be damaged. In order to prevent such electrostatic breakdown of the semiconductor device, the change of the wiring 3011 is suppressed by turning on the transistor 3001 or the transistor 3002. For example, when a potential higher than the power supply voltage is supplied to the wiring 3011, the transistor 3001 turns on. Then, the charge of the wiring 3011 moves to the wiring 3012 through the transistor 3001, so the potential of the wiring 3011 decreases. In this way, electrostatic breakdown of the semiconductor device can be prevented. On the other hand, for example, when a potential lower than the power supply voltage is supplied to the wiring 3011, the transistor 3002 turns on. Then, the charge of the wiring 3011 moves to the wiring 3013 through the transistor 3002, so the potential of the wiring 3011 increases. In this way, electrostatic breakdown of the semiconductor device connected to the wiring 3011 can be prevented. In addition, in the configuration described in FIG. 37(A), one of the transistors 3001 and the transistor 3 002 can be omitted. FIG. 37(B) shows a configuration in which the transistor 3002 is omitted in the protection circuit of FIG. 37(A). FIG. 37(C) shows FIG. 37( In the above, electrostatic breakdown of the semiconductor device can be prevented.

[0313] Note that in the configuration described in FIG. 37(A), one of the transistors 3001 and the transistor 3 002 can be omitted. FIG. 37(B) shows a configuration in which the transistor 3002 is omitted in the protection circuit of FIG. 37(A). FIG. 37(C) shows a configuration in which the transistor 3002 is omitted in the protection circuit of FIG. 37(A). A in which the transistor 3002 is omitted is shown. In FIG. 37(C), in FIG. 37( In the protection circuit of (A), a configuration is shown in which the transistor 3001 is omitted.

[0314] In the configuration described with reference to FIGS. 37(A) to (C), between the wiring 3011 and the wiring 3012 it is possible to connect a plurality of transistors in series. Alternatively, between the wiring 3011 and the wir ing 3013, it is possible to connect a plurality of transistors in series. FIG. 37( D) shows a configuration in which, in the protection circuit of FIG. 37(A), between the wiring 3011 and the wiring 3012, the tr ansistor 3001 and the transistor 3003 are connected in series. And between the wiring 3011 and the wiring 3013, the transistor 3002 and the transistor 3004 are shown connected in series. The first terminal of the transistor 3003 is connected to the wiring 3012 and the second terminal of the transistor 3003 is connected to the first terminal of the transistor 3001 and the gate of the transistor 3003 is connected to the first terminal of the transistor 3001 is connected. The first terminal of the transistor 3004 is connected to the wiring 3013, and the transistor 3004's second terminal is connected to the first terminal of the transistor 3002, and the transistor 3004's gate is connected to the first terminal of the transistor 3004. For example, as shown in FIG. 37 (E), the gate of the transistor 3001 and the gate of the transistor 3003 can be connected. Alternatively, the gate of the transistor 3002 and the transistor 3004's gate can be connected. Alternatively, between one of between the wiring 3011 and the wiring 301 2 and between the wiring 3011 and the wiring 3013, a plurality of transistors can be connected in series.

[0315] In the configuration described in FIGS. 37(A) to (E), between wiring 3011 and wiring 3012 a plurality of transistors can be connected in parallel. Alternatively, between wiring 3011 and wiring 3013, a plurality of transistors can be connected in parallel. FIG. 37 (F) shows a configuration in which, in the protection circuit of FIG. 37(A), between wiring 3011 and wiring 3012, transistor 3001 and transistor 3003 are connected in parallel. And between wiring 3011 and wiring 3013, a configuration in which transistor 3002 and transistor 3004 are connected in parallel is shown. The first terminal of transistor 3003 is connected to wiring 3012 , the second terminal of transistor 3003 is connected to wiring 3011, and the gate of the transistor 3003 is connected to wiring 3011. The first terminal of transistor 3004 is connected to wiring 3013, the second terminal of transistor 3004 is connected to wiring 3011 , and the gate of transistor 3004 is connected to wiring 3013.

[0316] In the configuration described in FIGS. 37(A) to (F), between the gate and the first terminal of the transistor a capacitive element and a resistive element can be connected in parallel. Between the gate of the transistor and the first terminal, only one of the capacitive element and the resistive element can be connected . FIG. 37(G) shows a configuration in which, in the protection circuit of FIG. 37(A), between the gate of transistor 3001 and the first terminal, capacitive element 3005 and resistive element 3006 are connected in parallel . And between the gate and the first terminal of transistor 3002, a configuration in which capacitive element 30 07 and resistive element 3008 are connected in parallel is shown. Thus, the protection circuit 3000 itself It is possible to prevent the destruction or deterioration of the body. For example, when a potential higher than the power supply voltage is supplied to the wiring 3011, the Vgs of the transistor 3001 increases. Therefore, since the transistor 3001 turns on, the potential of the wiring 3011 decreases. However, since a large voltage is applied between the gate of the transistor 3001 and the second terminal, the transistor 3001 may be destroyed or deteriorated. To prevent this, the potential of the gate of the transistor 3001 is increased to reduce the Vgs of the transistor 3001. When a potential higher than the power supply voltage is supplied to the wiring 3011, the Vgs of the transistor 3001 increases. Thus, since the transistor 3001 turns on, the potential of the wiring 3011 decreases. However, since a large voltage is applied between the gate of the transistor 3001 and the second terminal, the transistor 3001 may be destroyed or deteriorated. To prevent this, the potential of the gate of the transistor 3001 is increased to reduce the Vgs of the transistor 3001. To achieve this, the capacitive element 3005 is used. When the transistor 3001 turns on the potential of the first terminal of the transistor 3001 instantaneously increases. Then, due to the capacitive coupling of the capacitive element 3005, the potential of the gate of the transistor 3001 increases. Thus the Vgs of the transistor 3001 can be reduced, and the destruction or deterioration of the transistor 3001 can be suppressed. Similarly, when a potential lower than the power supply voltage is supplied to the wiring 3011 the potential of the first terminal of the transistor 3002 instantaneously decreases. Then due to the capacitive coupling of the capacitive element 3007, the potential of the gate of the transistor 3002 decreases Thus, the Vgs of the transistor 3002 can be reduced, so the destruction or deterioration of the transistor 3002 can be suppressed.

[0317] Note that as the capacitive element, it is possible to use the parasitic capacitance between the gate of the transistor and the first terminal. Therefore, the area where the material used as the gate of the transistor and the material used as the first terminal of the transistor overlap is the area where the material used as the gate of the transistor is used. The area where the material used as the first terminal of the transistor overlaps is the area where the material used as the gate of the transistor The area of ​​the material that is to be used as the second terminal of the transistor is larger than the area of ​​overlap between the material that is to be used as the second terminal of the transistor. Larger is preferable.

[0318] The resistor element is made of the material used for the wiring 3011 or the material used for the gate of a transistor. A material with lower conductivity than the material used for the pixel electrode (e.g., the same material as the pixel electrode, the transparent electrode, the non-transparent electrode, etc.) It is possible to use a semiconductor layer doped with a pure material.

[0319] Here, the protection circuit described in FIG. 37(A) to (G) is a protection circuit for various circuits or wiring (e.g., signal lines A driving circuit, a scanning line driving circuit, a level shift circuit, a gate signal line, a source signal line, a power supply line, In FIG. 38(A), a protection circuit is provided for the gate signal line. In this case, the wiring 3012 and the wiring 3013 are gate drivers. It is possible to connect the conductor 3100 to any of the wirings connected to the conductor 3100. This allows the number of power supplies and wiring to be reduced. This shows a configuration in which a protection circuit is provided at a terminal to which a signal or voltage is supplied from the outside. In this case, the wiring 3012 and the wiring 3013 can be connected to any of the external terminals. For example, the wiring 3012 is connected to the terminal 3101a, and the wiring 3013 is connected to the terminal 310. In this case, in the protection circuit provided at the terminal 3101a, It is possible to omit the transistor 3001. Similarly, In the protection circuit, the transistor 3002 can be omitted. This allows the number of transistors to be reduced, thereby reducing the layout area. can be done.

[0320] (Embodiment 6) In this embodiment, the transistor will be described with reference to FIGS. 39(A), (B), and (C). Description will be made.

[0321] FIG. 39(A) is a diagram showing a top-gate type transistor and a display element formed thereon. FIG. 39(B) is a diagram showing a bottom-gate type transistor and a display element formed thereon. It is a diagram showing.

[0322] The transistor in FIG. 39(A) includes a substrate 5260, an insulating layer 5261 formed on the substrate 5260, a semiconductor layer 5262 formed on the insulating layer 5261 and having regions 5262a, 5262b, 5262c, 5262d, and 5262e, an insulating layer 5263 formed so as to cover the semiconductor layer 5262, a conductive layer 5264 formed on the semiconductor layer 5262 and the insulating layer 5263, an insulating layer 5265 formed on the insulating layer 5263 and the conductive layer 5264 and having an opening, and a conductive layer 5266 formed on the insulating layer 5265 and in the opening of the insulating layer 5265.

[0323] The transistor in FIG. 39(B) includes a substrate 5300, a conductive layer 5301 formed on the substrate 5300, an insulating layer 5302 formed so as to cover the conductive layer 5301, a semiconductor layer 5303a formed on the conductive layer 5301 and the insulating layer 5302, a semiconductor layer 5303b formed on the semiconductor layer 5303a, a conductive layer 5304 formed on the semiconductor layer 5303b and on the insulating layer 5302, an insulating layer 5305 formed on the insulating layer 5302 and the conductive layer 5304 and having an opening, and a conductive layer 5306 formed on the insulating layer 5305 and in the opening of the insulating layer 5305. ​​​​​​​​​​​​

[0324] The transistor in Fig. 39(C) has a semiconductor substrate 53 having regions 5353 and 5355 52, an insulating layer 5356 formed on the semiconductor substrate 5352, and the semiconductor substrate 5352 An insulating layer 5354 formed thereon, a conductive layer 5357 formed on the insulating layer 5356, An insulating layer 5358 formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357 and having an opening And a conductive layer formed on the insulating layer 5358 and in the opening of the insulating layer 5358 5359. Thus, transistors are fabricated in regions 5350 and 5351, respectively.

[0325] In addition, in the transistors described in Figs. 39(A) to (C), as shown in Fig. 39(A) , on the transistor, an insulating layer 5267 formed on the conductive layer 5266 and on the insulating layer 5265 and having an opening , a conductive layer 5268 formed on the insulating layer 5267 and in the opening of the insulating layer 5267 , an insulating layer 5269 formed on the insulating layer 5267 and on the conductive layer 5268 and having an opening , a light-emitting layer 5270 formed on the insulating layer 5269 and in the opening of the insulating layer 5269 , and a conductive layer 52 formed on the insulating layer 5269 and on the light-emitting layer 5270 71 can be formed.

[0326] In addition, in the transistors described in Figs. 39(A) to (C), as shown in Fig. 39(B) , a liquid crystal layer 5307 disposed on the transistor, on the insulating layer 5305, and on the conductive layer 5306 , and a conductive layer 5308 formed on the liquid crystal layer 5307 can be formed.

[0327] ​​The insulating layer 5261 can function as an underlying film. The insulating layer 5354 functions as an isolation layer (e.g., a field oxide film) between elements. The insulating layers 5263, 5302, and 5356 can function as gate insulating films. The conductive layers 5264, 5301, and 5357 can function as gate electrodes. The insulating layers 5265, 5267, 5305, and 5358 can function as interlayer films or planarization films. The conductive layers 5266, 5304, and 5 359 can function as wirings, electrodes of transistors, or electrodes of capacitor elements, etc. The conductive layers 5268 and 5306 can function as pixel electrodes or reflective electrodes, etc. The insulating layer 5269 can function as a partition wall. The conductive layers 5271 and 5308 can function as counter electrodes or common electrodes, etc.

[0328] The substrates 5260 and 5300 include glass substrates, quartz substrates, semiconductor substrates (e.g., silicon substrates or single-crystal substrates), SOI substrates, plastic substrates, metal substrates, stainless steel substrates, substrates having stainless steel foils, tungsten substrates, substrates having tungsten foils, or flexible substrates, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Examples of flexible substrates include plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or synthetic resins having flexibility such as acrylic. There are also laminated films (polypropylene, polyester, vinyl, polyvinylidene fluoride, etc.). ​​​​​​Nil, vinyl chloride, etc.), paper containing fibrous materials, base films (polyester, poly amide, polyimide, inorganic vapor-deposited films, papers, etc.) and the like.

[0329] As the semiconductor substrate 5352, a single-crystalline Si substrate having an n-type or p-type conductivity type can be used. However, it is not limited thereto, and a substrate that can be used for the semiconductor substrate 5352 can be used in part or in whole to form the semiconductor substrate 5352. Region 5353 is a region in which impurities are added to the semiconductor substrate 5352 and functions as a well. For example, when the semiconductor substrate 5352 has a p-type conductivity type, region 5353 has an n-type conductivity type and functions as an n-well. On the other hand, when the semiconductor substrate 5352 has an n-type conductivity type, region 5353 has a p-type conductivity type and functions as a p-well. Region 5355 is a region in which impurities are added to the semiconductor substrate 5352 and functions as a source region or a drain region. Note that an LDD region can be formed on the semiconductor substrate 5352.

[0330] As the insulating layer 5261, there are films containing oxygen or nitrogen such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y )(x > y > 0), silicon nitride oxide (SiN x O y )(x > y > 0), etc., or a laminated structure thereof. When the insulating layer 5261 is provided in a two-layer structure, a silicon nitride film can be provided as the first insulating layer, and a silicon oxide film can be provided as the second insulating layer. When the insulating layer 5261 is provided in a three-layer structure, a silicon oxide film can be provided as the first insulating layer, a silicon nitride film can be provided as the second insulating layer, and the third layer can be provided as an insulating layer. It is possible to provide a silicon oxide film as the insulating layer.

[0331] As the semiconductor layers 5262, 5303a, and 5303b, non-single crystal semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.), single crystal semiconductors, compound semiconductors, or oxide semiconductors (e.g., ZnO, InGaZnO, SiGe, GaAs, IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, AlZnSnO (AZTO)), organic semiconductors, or carbon nanotubes, etc. are available. )

[0332] For example, the region 5262a is in an intrinsic state where no impurities are added to the semiconductor layer 5262 and functions as a channel region. However, it is possible to add impurities to the region 5262a, and the impurities added to the region 5262a are preferably lower in concentration than the impurities added to the region 5262b, the region 5262c, the region 5262d, or the region 5262e. The regions 5262b and 5262d are regions where impurities are added at a lower concentration than the region 5262c or the region 5262e and function as LDD (Lightly Doped Drain) regions. However, it is possible to omit the regions 5262b and 5262d. The regions 5262c and 5262e are regions where impurities are added to the semiconductor layer 5262 at a high concentration and function as source regions or drain regions.

[0333] Note that the semiconductor layer 5303b is a semiconductor layer to which an impurity element such as phosphorus is added and has an n-type conductivity type.

[0334] ​When an oxide semiconductor or a compound semiconductor is used as the semiconductor layer 5303a, the semiconductor layer 5303b can be omitted.

[0335] As the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356, silicon oxide (SiO x ) , silicon nitride (SiN x ), silicon oxynitride (SiO x N y )(x > y > 0), silicon nitride oxide (SiN x O y )(x > y > 0), etc., films having oxygen or nitrogen, or laminated structures thereof exist.

[0336] As the conductive layer 5264, the conductive layer 5266, the conductive layer 5268, the conductive layer 5271, the conductive layer 5301, the conductive layer 5304, the conductive layer 5306, the conductive layer 5308, the conductive layer 5357, and the conductive layer 535 9, there are single-layer conductive films or laminated structures thereof. As the conductive film, , aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), t ungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt ), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), nio bium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C), scan dium (Sc), zinc (Zn), gallium (Ga), indium (In), tin (Sn), zirconium (Zr), cerium (Ce), a group composed of these, a single film of one element selected from this group, or a chemical combination containing one element or a plurality of elements selected from this group, etc. exist. Note that the single film or the compound contains phosphorus (P), boron (B), arsenic ( As), It is possible to contain, for example, arsenic (As), and / or oxygen (O).

[0337] Examples of the compound include a compound (such as an alloy) containing one or more elements selected from the plurality of elements described above, a compound of one or more elements selected from the plurality of elements described above and nitrogen (such as a nitride film), a compound of one or more elements selected from the plurality of elements described above and silicon (such as a silicide film), or a nanotube material. Examples of the compound include a compound (such as an alloy) containing one or more elements selected from the plurality of elements described above, a compound of one or more elements selected from the plurality of elements described above and nitrogen (such as a nitride film), a compound of one or more elements selected from the plurality of elements described above and silicon (such as a silicide film), or a nanotube material. Examples of the compound include a compound (such as an alloy) containing one or more elements selected from the plurality of elements described above, a compound of one or more elements selected from the plurality of elements described above and nitrogen (such as a nitride film), a compound of one or more elements selected from the plurality of elements described above and silicon (such as a silicide film), or a nanotube material. Examples of the compound include a compound (such as an alloy) containing one or more elements selected from the plurality of elements described above, a compound of one or more elements selected from the plurality of elements described above and nitrogen (such as a nitride film), a compound of one or more elements selected from the plurality of elements described above and silicon (such as a silicide film), or a nanotube material. Examples of the alloy include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo-Ta), and the like. Examples of the alloy include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo-Ta), and the like. Examples of the alloy include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo-Ta), and the like. Examples of the alloy include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo-Ta), and the like. Examples of the alloy include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo-Ta), and the like. Examples of the alloy include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo-Ta), and the like. Examples of the nitride film include titanium nitride, tantalum nitride, molybdenum nitride, and the like. Examples of the nitride film include titanium nitride, tantalum nitride, molybdenum nitride, and the like. Examples of the silicide film include tungsten silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum silicon, and the like. Examples of the silicide film include tungsten silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum silicon, and the like. Examples of the nanotube material include carbon nanotubes, organic nanotubes, inorganic nanotubes, or metal nanotubes, and the like.

[0338] The insulating layers 5265, 5267, 5269, 5305, and 5358 include a single-layer insulating layer or a stacked structure thereof. Examples of the insulating layer include silicon oxide (SiO Examples of the insulating layer include silicon oxide (SiO x) Silicon nitride (SiN x ), or silicon oxynitride (SiO x N y )(x > y > 0), silicon oxynitride (SiN x O y )(x > y > 0), etc., a film containing oxygen or nitrogen , a film containing carbon such as DLC (diamond-like carbon), or a siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene , or an organic material such as acrylic, etc. There are such materials.

[0339] As the light-emitting layer 5270, there are an organic EL element, an inorganic EL element, etc. As for the organic EL element , a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material , an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, etc., or a single-layer structure of a layer in which a plurality of these materials are mixed, or a laminated structure of these , etc.

[0340] Note that on the insulating layer 5305 and on the conductive layer 5306, an insulating layer that functions as an alignment film, an insulating layer that functions as a protrusion, etc. can be formed.

[0341] Note that on the conductive layer 5308, a color filter, a black matrix, or an insulating layer that functions as a protrusion , etc. can be formed. Under the conductive layer 5308, an insulating layer that functions as an alignment film can be formed.

[0342] The transistor of the present embodiment can be used in the semiconductor devices described in Embodiments 1 to 2. In particular, in FIG. 39(B), as the semiconductor layer, a non-single-crystalline semiconductor, ​When using an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like, the transistor will deteriorate. However, in the semiconductor devices, shift registers, or display devices of Embodiments 1 to 6, it is useful because deterioration of the transistor can be suppressed. .

[0343] (Embodiment 7) In this embodiment, the cross-sectional structure of the display device will be described with reference to FIGS. 40(A), (B), and (C). .

[0344] FIG. 40(A) is a top view of the display device. A driving circuit 5392 and a pixel portion 5393 are formed on a substrate 5391. Examples of the driving circuit 5392 include a scanning line driving circuit or a signal line driving circuit.

[0345] FIG. 40(B) shows the A-B cross section of FIG. 40(A). FIG. 40(B) shows a substrate 5400, a conductive layer 5401 formed on the substrate 5400, an insulating layer 5402 formed to cover the conductive layer 5401, a semiconductor layer 5403a formed on the conductive layer 5401 and the insulating layer 5402, a semiconductor layer 5403b formed on the semiconductor layer 5403a, a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402, an insulating layer 5 402 and on the conductive layer 5404 and having an opening, an insulating layer 5405 formed on the insulating layer 5405, a conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405, an insulating layer 54 05 and on the conductive layer 5406, an insulating layer 5408 disposed on the insulating layer 5405 and on the conductive layer 5406, a liquid crystal layer 5407 formed on the insulating layer 5405, a conductive layer 5409 formed on the liquid crystal layer 5407 and on the insulating layer 5408, and a substrate 5410 formed on the conductive layer 5409. are shown.

[0346] The conductive layer 5401 can function as a gate electrode. The insulating layer 5402 can function as a gate insulating film. The conductive layer 5404 can function as a wiring, an electrode of a transistor, or an electrode of a capacitive element. The insulating layer 5405 can function as an interlayer film or a planarization film. The conductive layer 5406 can function as a wiring, a pixel electrode, or a reflective electrode. The insulating layer 5408 can function as a sealing material. The conductive layer 5409 can function as a counter electrode or a common electrode. Here, a parasitic capacitance may occur between the driving circuit 5392 and the conductive layer 5409. As a result, a distortion or a delay may occur in the output signal of the driving circuit 5392 or the potential of each node. Or, the power consumption may increase. However, as shown in FIG. 40(B), by forming the insulating layer 5408 that can function as a sealing material on the driving circuit 5392, the parasitic capacitance generated between the driving circuit 5392 and the conductive layer 5409 can be reduced. Because the dielectric constant of the sealing material is lower than that of the liquid crystal layer.

[0347] Therefore, the distortion or delay of the output signal of the driving circuit 5392 or the potential of each node can be reduced. Or, the power consumption of the driving circuit 5392 can be reduced. In addition, as shown in FIG. 40(C), it is possible to form the insulating layer 5408 that can function as a sealing material on a part of the driving circuit 5392. Even in such a case, the parasitic capacitance generated between the driving circuit 5392 and the conductive layer 5409 can be reduced.

[0348] ​​​​​​​​​ and it is possible to reduce the noise or delay of the output signal of the drive circuit 5392 or the potential of each node. However, it is not limited to this, and it is possible that an insulating layer 5408 that can function as a sealing material is not formed on the drive circuit 5392.

[0349] Note that the display element is not limited to a liquid crystal element, and various display elements such as an EL elemen...

Claims

1. A gate driver, the gate driver includes first to sixth transistors; the first to sixth transistors are N-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; The other of the source and the drain of the sixth transistor is supplied with an H-level potential, the gate of the sixth transistor is electrically connected to the second clock signal line.

2. A gate driver, the gate driver includes first to sixth transistors; the first to sixth transistors are P-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; an L-level potential is supplied to the other of the source and the drain of the sixth transistor; the gate of the sixth transistor is electrically connected to the second clock signal line.

3. A gate driver, the gate driver includes first to sixth transistors; the first to sixth transistors are N-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; The other of the source and the drain of the sixth transistor is supplied with an H-level potential, a gate of the sixth transistor is electrically connected to the second clock signal line; a channel width of the second transistor is larger than a channel width of the fifth transistor; The semiconductor device, wherein the channel width of the second transistor is larger than the channel width of the sixth transistor.

4. A gate driver, the gate driver includes first to sixth transistors; the first to sixth transistors are P-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; an L-level potential is supplied to the other of the source and the drain of the sixth transistor; a gate of the sixth transistor is electrically connected to the second clock signal line; a channel width of the second transistor is larger than a channel width of the fifth transistor; The semiconductor device, wherein the channel width of the second transistor is larger than the channel width of the sixth transistor.

5. A gate driver, the gate driver includes first to sixth transistors and a capacitance element; the first to sixth transistors are N-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; The other of the source and the drain of the sixth transistor is supplied with an H-level potential, a gate of the sixth transistor is electrically connected to the second clock signal line; one electrode of the capacitance element is electrically connected to the gate of the first transistor; the other electrode of the capacitive element is electrically connected to the second gate signal line.

6. A gate driver, the gate driver includes first to sixth transistors and a capacitance element; the first to sixth transistors are P-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; an L-level potential is supplied to the other of the source and the drain of the sixth transistor; a gate of the sixth transistor is electrically connected to the second clock signal line; one electrode of the capacitance element is electrically connected to the gate of the first transistor; the other electrode of the capacitive element is electrically connected to the second gate signal line.

7. A gate driver, the gate driver includes first to sixth transistors and a capacitance element; the first to sixth transistors are N-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; The other of the source and the drain of the sixth transistor is supplied with an H-level potential, a gate of the sixth transistor is electrically connected to the second clock signal line; one electrode of the capacitance element is electrically connected to the gate of the first transistor; the other electrode of the capacitance element is electrically connected to the second gate signal line; a channel width of the second transistor is larger than a channel width of the fifth transistor; The semiconductor device, wherein the channel width of the second transistor is larger than the channel width of the sixth transistor.

8. A gate driver, the gate driver includes first to sixth transistors and a capacitance element; the first to sixth transistors are P-channel transistors, one of a source and a drain of the first transistor is electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is electrically connected to a second gate signal line; one of a source and a drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the second gate signal line; one of a source and a drain of the third transistor is electrically connected to a first gate signal line; the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor is electrically connected to a second clock signal line; one of a source and a drain of the fourth transistor is electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; a gate of the fourth transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; a gate of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; an L-level potential is supplied to the other of the source and the drain of the sixth transistor; a gate of the sixth transistor is electrically connected to the second clock signal line; one electrode of the capacitance element is electrically connected to the gate of the first transistor; the other electrode of the capacitance element is electrically connected to the second gate signal line; a channel width of the second transistor is larger than a channel width of the fifth transistor; The semiconductor device, wherein the channel width of the second transistor is larger than the channel width of the sixth transistor.

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