Semiconductor device

Abstract

To provide a highly reliable semiconductor device.SOLUTION: A semiconductor device includes first to third transistors, and a capacitance. In the first transistor, a first signal is applied to one of a source and a drain, the other is connected to one electrode of a gate and a capacitance of the second transistor, and a second pulse signal is applied to a gate. In the second transistor, the first pulse signal is applied to one of a source and a drain, and the other is connected to the other electrode of the capacitance and one of a source and a drain of the third transistor. In the third transistor, a first potential is applied to the other of the source and the drain, and a second signal that is an inversion of the first signal is applied to a gate. The first pulse signal is a clock signal and the second pulse signal is a signal whose duty ratio is 55% or less.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a display device. One aspect of the present invention relates to a drive circuit of a display device. One aspect of the present invention relates to an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. The semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] Display devices are applied to various devices such as portable information terminals such as smartphones and television devices. In recent years, an improvement in the screen occupancy rate of devices to which display devices are applied has been demanded. For this purpose, it is required that the display device narrow (narrow the bezel) the area other than the display portion. In addition, a system-on-panel in which part or all of the drive circuit is fabricated on the same substrate as the pixel portion is effective for satisfying the above requirements. In the case of a system-on-panel, it is desirable to fabricate the transistors provided in the drive circuit and the transistors provided in the pixel portion in the same process because the cost required for fabricating the panel can be reduced. Patent Documents 1 and 2 disclose techniques for configuring various circuits such as inverters and shift registers used in the drive circuit of a display device with unipolar transistors.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a sequential circuit that outputs a pulse signal and is used in a drive circuit of a display device, if fluctuations occur in the electrical characteristics of the transistors that make up the sequential circuit, particularly fluctuations in the threshold voltage, problems such as the inability to output a desired signal will occur. As a result, there is a risk that an image cannot be displayed.

[0006] One aspect of the present invention is to provide a highly reliable semiconductor device, display device, or electronic device as one of the problems. One aspect of the present invention is to provide a semiconductor device, display device, or electronic device that can achieve a narrow bezel of a display device as one of the problems. One aspect of the present invention is to provide a semiconductor device, display device, or electronic device that is highly reliable and can be manufactured at low cost as one of the problems. One aspect of the present invention is to provide a semiconductor device, display device, or electronic device having a novel configuration as one of the problems. One aspect of the present invention is to reduce at least one of the problems of the prior art as one of the problems.

[0007] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0008] One aspect of the present invention is a semiconductor device having first to third transistors, a first capacitor, and first to fifth wirings. One of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain is electrically connected to the gate of the second transistor and one electrode of the first capacitor, and the gate is electrically connected to the third wiring. One of the source and drain of the second transistor is electrically connected to the fourth wiring, and the other of the source and drain is electrically connected to the other electrode of the first capacitor and one of the source and drain of the third transistor. For the third transistor, the other of the source and drain is electrically connected to the fifth wiring, and the gate is electrically connected to the second wiring. A first signal is applied to the first wiring, and a second signal obtained by inverting the first signal is applied to the second wiring. A first pulse signal is applied to the fourth wiring. A first potential is applied to the fifth wiring. A second pulse signal is applied to the third wiring. The first pulse signal is a clock signal, and the second pulse signal is a signal having a duty ratio of 55% or less.

[0009] Another aspect of the present invention is a semiconductor device having a control circuit, first to third transistors, a first capacitor, and first to fifth wirings. One of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain is electrically connected to the gate of the second transistor and one electrode of the first capacitor, and the gate is electrically connected to the third wiring. One of the source and drain of the second transistor is electrically connected to the fourth wiring, and the other of the source and drain is electrically connected to the other electrode of the first capacitor and one of the source and drain of the third transistor. The other of the source and drain of the third transistor is electrically connected to the fifth wiring, and the gate is electrically connected to the second wiring. The control circuit outputs a first signal to the first wiring and outputs a second signal obtained by inverting the first signal to the second wiring. A first pulse signal is applied to the fourth wiring. A first potential is applied to the fifth wiring. A second pulse signal is applied to the third wiring. The first pulse signal is a clock signal, and the second pulse signal is a signal having a duty ratio of 55% or less.

[0010] Also, in the above, it is preferable to have a signal generation circuit that outputs the second pulse signal. At this time, it is preferable that a third pulse signal is applied to the signal generation circuit and the control circuit. Further, it is preferable that the third pulse signal is a signal having a duty ratio of 1% or less.

[0011] Also, in the above, it is preferable that the second pulse signal is a signal having a duty ratio of 1% or less.

[0012] Further, in the above, it is preferable that the signal generation circuit includes a fourth transistor, a fifth transistor, and a second capacitor. At this time, one of the source and drain of the fourth transistor is supplied with a second potential higher than the first potential, and the other of the source and drain is electrically connected to one of the third wiring, the source and drain of the fifth transistor, and one electrode of the second capacitor. Also, the fifth transistor is supplied with the first potential at the other of the source and drain. Further, the second capacitor is supplied with the first potential at the other electrode. Furthermore, a third pulse signal is applied to the gate of the fourth transistor, and a fourth pulse signal is applied to the gate of the fifth transistor. At this time, it is preferable that the fourth pulse signal is a signal having a duty ratio of 1% or less.

[0013] Further, in the above, it is preferable that the second pulse signal is applied to the third wiring and the control circuit.

[0014] Further, in the above, it is preferable that the first transistor includes a first semiconductor layer, and a first gate and a second gate that overlap each other via the first semiconductor layer. At this time, it is preferable that the first gate and the second gate are electrically connected.

[0015] Further, in the above, it is preferable that the third transistor includes a second semiconductor layer, and a third gate and a fourth gate that overlap each other via the second semiconductor layer. At this time, it is preferable that one of the third gate and the fourth gate is electrically connected to the second wiring, and the other of the third gate and the fourth gate is electrically connected to the fifth wiring.

[0016] Further, in the above, it is preferable that the fourth gate is located below the second semiconductor layer. At this time, it is preferable that the third gate is electrically connected to the second wiring, and the fourth gate is electrically connected to the fifth wiring.

[0017] Also, one aspect of the present invention is a display device having any one of the semiconductor devices described above and pixels. The pixel has a display element and a sixth transistor. The sixth transistor is preferably provided on the same plane as the first transistor, the second transistor, and the third transistor.

[0018] Also, in the above, the display element is preferably a liquid crystal element or a light emitting element.

[0019] Also, one aspect of the present invention is an electronic device having any one of the display devices described above and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

Advantages of the Invention

[0020] According to one aspect of the present invention, a highly reliable semiconductor device, display device, or electronic device can be provided. Or, a semiconductor device, display device, or electronic device that can achieve a narrow bezel of the display device can be provided. Or, a semiconductor device, display device, or electronic device that is highly reliable and can be manufactured at low cost can be provided. Or, a semiconductor device, display device, or electronic device having a novel configuration can be provided. Or, at least one of the problems of the prior art can be at least reduced.

[0021] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0022]

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DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and scope thereof. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0024] In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same parts or parts having the same functions, and the repeated description thereof is omitted. In addition, when referring to the same function, the hatch patterns may be the same, and there may be cases where no reference numerals are particularly assigned.

[0025] In each of the drawings described in this specification, the sizes of the respective components, the thicknesses of the layers, or the regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0026] Note that ordinal numbers such as “first” and “second” in this specification are attached to avoid confusion of components and are not numerically limiting.

[0027] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage and switching operations for controlling conduction or non - conduction. The transistors in this specification include IGFET (Insulated Gate Field Effect Transistor) and thin - film transistor (TFT: Thin Film Transistor).

[0028] Also, the functions of "source" and "drain" may be interchanged when transistors of different polarities are employed, or when the direction of current changes in circuit operation. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.

[0029] Also, in this specification and the like, "electrically connected" includes cases where it is connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistance elements, coils, capacitance elements, and other elements having various functions.

[0030] In this specification and the like, a display panel, which is an aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is an aspect of an output device.

[0031] Also, in this specification and the like, a display panel with a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) attached to its substrate, or a display panel with an IC mounted on the substrate by a COG (Chip On Glass) method or the like may be referred to as a display panel module, a display module, or simply a display panel.

[0032] (Embodiment 1) In this embodiment, a configuration example of a semiconductor device according to an aspect of the present invention will be described.

[0033] [Configuration Example 1] [Configuration Example 1-1] FIG. 1 shows a configuration example of a sequential circuit 10 according to an aspect of the present invention. The sequential circuit 10 includes a circuit 11 and a circuit 12. The circuit 11 and the circuit 12 are electrically connected via a wiring 15a and a wiring 15b. The circuit 12 can also be called a control circuit.

[0034] Hereinafter, unless otherwise specified, among the signals and potentials applied to the sequential circuit 10, the high potential may be described as the potential VDD and the low potential may be described as the potential VSS.

[0035] The circuit 12 has a function of outputting a first signal to the wiring 15a and a second signal to the wiring 15b according to the potential of the signal LIN and the potential of the signal RIN. Here, the second signal is a signal obtained by inverting the first signal. That is, when the first signal and the second signal are signals having two types of potentials, high potential and low potential, respectively, when a high potential is output from the circuit 12 to the wiring 15a, a low potential is output to the wiring 15b, and when a low potential is output to the wiring 15a, a high potential is output to the wiring 15b.

[0036] The circuit 11 includes a transistor 21, a transistor 22, a transistor 23, and a capacitor C1. The transistor 21, the transistor 22, and the transistor 23 are each an n-channel type transistor. As the transistor 21, the transistor 22, and the transistor 23, a metal oxide (hereinafter also referred to as an oxide semiconductor) showing semiconductor characteristics can be preferably used as the semiconductor in which a channel is formed. Note that the semiconductor is not limited to the oxide semiconductor, and a semiconductor such as silicon (single crystal silicon, polycrystalline silicon, or amorphous silicon), germanium, or a compound semiconductor may be used.

[0037] Transistor 23 has its gate electrically connected to the wiring to which signal BDG is applied, one of its source and drain is electrically connected to wiring 15a, and the other of its source and drain is electrically connected to the gate of transistor 22 and one electrode of capacitor C1. One of the source and drain of transistor 22 is electrically connected to the wiring to which signal CLK is applied, and the other of its source and drain is electrically connected to the other electrode of capacitor C1 and one of the source and drain of transistor 21. The gate of transistor 21 is electrically connected to wiring 15b, and the other of its source and drain is electrically connected to the wiring to which the potential VSS (also referred to as the first potential) is applied. Also, one of the source and drain of transistor 21, the other of the source and drain of transistor 22, and the other electrode of capacitor C1 are electrically connected to output terminal OUT. Note that output terminal OUT is the part to which the output potential from circuit 11 is applied, and it may be a part of the wiring or a part of the electrode.

[0038] A clock signal is input as signal CLK to one of the source and drain of transistor 22. As the clock signal, a signal with a duty ratio (the ratio of the period of high-level potential (high potential) during one period of the signal) of 45% or more and 55% or less can be preferably used. More preferably, a signal with a duty ratio of 50% can be used as the clock signal. Note that the duty ratio of the clock signal is not limited to the above and can be appropriately changed according to the driving method.

[0039] In this specification etc., a clock signal refers to a signal in which high potential and low potential are repeated, and the interval between the rise of the potential and the rise of the next potential, or the interval between the fall of the potential and the fall of the next potential, is constant. Also, in this specification etc., a pulse signal refers to a signal whose potential changes over time. The pulse signal includes a signal whose potential changes periodically. For example, the pulse signal includes signals such as a rectangular wave, a triangular wave, a sawtooth wave, and a sine wave whose potential changes periodically. Therefore, it can be said that the clock signal is one aspect of the pulse signal.

[0040] The signal CLK is a signal in which a high potential and a low potential are alternately applied. At this time, it is preferable that the low potential of the signal CLK is the same potential as the potential VSS. Note that instead of the signal CLK, a high potential (for example, the potential VDD) may be applied to one of the source and drain of the transistor 22.

[0041] Also, the signal BDG applied to the gate of the transistor 23 is a pulsed signal having periodicity. At this time, it is more preferable that the duty ratio of the signal BDG is lower. For example, as the signal BDG, a pulsed signal having a duty ratio of 60% or less, preferably 55% or less, more preferably 50% or less, still more preferably 10% or less, still more preferably 5% or less, and still more preferably 1% or less can be used. The lower limit value of the duty ratio of the signal BDG may be as small as possible as long as it is greater than 0%.

[0042] By applying a pulsed signal with a small duty ratio to the gate of the transistor 23, it becomes possible to suppress fluctuations in the threshold voltage of the transistor 23. Here, for example, if a constant potential that is always at a high potential (that is, a signal with a duty ratio of 100%) is applied to the gate of the transistor 23, the threshold voltage of the transistor 23 is likely to shift positively, so there is a risk that the signal expected from the sequential circuit 10 cannot be output. On the other hand, in one aspect of the present invention, since the signal BDG with a small duty ratio is applied to the gate of the transistor 23, fluctuations in the electrical characteristics of the transistor 23 are suppressed, and as a result, a highly reliable sequential circuit 10 can be realized.

[0043] Here, it is preferable that the signal BDG is a signal generated using a signal for driving the circuit 12. Or, it is preferable that the signal BDG also serves as a signal for driving the circuit 12. Thereby, since it is not necessary to provide a circuit for newly generating the signal BDG outside the sequential circuit 10, the configuration of the device to which the sequential circuit 10 is applied can be simplified.

[0044] The operation of the sequential circuit 10 will be described. When a high potential is applied to the wiring 15a, a low potential is applied to the wiring 15b, and the signal BDG becomes high potential, the transistors 23 and 22 become conductive states (on states), and the transistor 21 becomes a non-conductive state (off state). At this time, the output terminal OUT and the wiring to which the signal CLK is applied are in a conductive state.

[0045] In the circuit 11, since the output terminal OUT and the gate of the transistor 22 are electrically connected via the capacitor C1, due to the bootstrap effect, as the potential of the output terminal OUT rises, the potential of the gate of the transistor 22 rises. Here, if there is no capacitor C1, a potential lower than the high potential of the signal CLK by the threshold voltage of the transistor 22 will be output to the output terminal OUT. However, by having the capacitor C1, the potential of the gate of the transistor 22 rises to a potential close to twice the potential VDD (for example, a potential close to twice the difference between the potential VDD and the potential VSS). Therefore, without being affected by the threshold voltage of the transistor 22, a high potential of the signal CLK (for example, the potential VDD) can be output to the output terminal OUT. As a result, a sequential circuit 10 with high output performance can be realized without increasing the types of power supply potentials.

[0046] Also, since a high potential is applied as the signal BDG and the transistor 23 is in the on state, when a high potential is applied to the wiring 15a, a high potential is applied to the gate of the transistor 22 via the transistor 23. At this time, when the high potential applied to the wiring 15a is equal to the high potential of the signal BDG (for example, both are the potential VDD), a potential lower than the potential VDD by the threshold voltage of the transistor 23 is applied to the gate of the transistor 22. Thereafter, when the signal CLK changes from a low potential to a high potential, the potential of the gate of the transistor 22 (the other potential of the source and drain of the transistor 23) rises due to the bootstrap effect. Here, when the other potential of the source and drain of the transistor 23 exceeds the potential VDD, the transistor 23 becomes in the off state, so that the gate of the transistor 22 and the wiring 15a are electrically disconnected, and the gate of the transistor 22 becomes in a floating state. Also, since the potential of the wiring 15a does not rise from the output potential (VDD) of the circuit 12, it is possible to prevent a potential higher than the output potential from being applied to the transistors in the circuit 12 via the wiring 15a. Thereby, the reliability of the sequential circuit 10 can be improved.

[0047] On the other hand, when a low potential is applied to the wiring 15a and a high potential is applied to the wiring 15b, a low potential is applied to the gate of the transistor 22 via the transistor 23, and the transistor 22 becomes in the off state. Also, the transistor 21 becomes in the on state. At this time, the output terminal OUT and the wiring to which the potential VSS is applied are in a conductive state, and the potential VSS is output to the output terminal OUT. Thereafter, it is preferable to change the signal BDG from a high potential to a low potential to turn off the transistor 23.

[0048] FIG. 2A shows a more detailed configuration example of the sequential circuit 10 illustrated in FIG. 1. The circuit 12 included in the sequential circuit 10 includes a transistor 31, a transistor 32, a transistor 33, and a transistor 34. It is preferable to apply the above-described n-channel type transistors to the transistors 31 to 34. In particular, it is preferable to use a transistor in which an oxide semiconductor is applied to the semiconductor in which the channel is formed.

[0049] The transistors 31 and 34 are selected to be conductive or non-conductive according to the potential of the signal LIN. The transistors 33 and 32 are selected to be conductive or non-conductive according to the potential of the signal RIN.

[0050] When the signal LIN is at a high potential and the signal RIN is at a low potential, the transistor 31 is in an on state and the transistor 33 is in an off state, and the wiring to which the potential VDD is applied and the wiring 15a are electrically connected. Also, the transistor 34 is in an on state and the transistor 32 is in an off state, and the wiring to which the potential VSS is applied and the wiring 15b are electrically connected. On the other hand, when the signal LIN is at a low potential and the signal RIN is at a high potential, the transistor 31 is in an off state and the transistor 33 is in an on state, and the wiring to which the potential VSS is applied and the wiring 15a are electrically connected. Also, the transistor 34 is in an off state and the transistor 32 is in an on state, and the wiring to which the potential VDD is applied and the wiring 15b are electrically connected.

[0051] In the sequential circuit 10, when the signal LIN is at a high potential and the signal RIN is at a low potential, the wiring 15a is at a high potential and the wiring 15b is at a low potential, and the potential of the signal CLK is output to the output terminal OUT. On the other hand, when the signal LIN is at a low potential and the signal RIN is at a high potential, the wiring 15a is at a low potential and the wiring 15b is at a high potential, and the output terminal OUT and the wiring to which the potential VSS is applied are electrically connected.

[0052] By alternately changing the potentials of the signals LIN and RIN input to the sequential circuit 10 between a high potential and a low potential and synchronizing the signal CLK and the signal LIN, a pulsed output signal is output to the output terminal OUT of the sequential circuit 10. By supplying the output signal output to the output terminal OUT of the sequential circuit 10 to a wiring (for example, a scanning line) connected to a plurality of pixels, etc., the sequential circuit 10 can be used as part of a gate driver circuit.

[0053] Figure 2B is a timing chart showing an example of a driving method for the sequential circuit 10 shown in Figure 2A. Figure 2B schematically shows the time variation of the potential at the signal LIN, signal RIN, signal BDG, signal CLK, node N, and output terminal OUT. Here, node N corresponds to the node to which the gate of transistor 22 is connected (see Figure 2A).

[0054] At time T1, the signal LIN and signal BDG are at high potential, and the signal RIN and signal CLK are at low potential. In the period T1 - T2, since a high potential is output from circuit 12 to wiring 15a and transistor 23 is in the on state, the potential of node N rises from the potential of wiring 15a to a potential reduced by the threshold voltage of transistor 23.

[0055] Subsequently, at time T2, the signal LIN becomes low potential and the signal CLK becomes high potential. At this time, since all the transistors 31 to 34 of circuit 12 are in the off state, wiring 15a becomes electrically floating. Therefore, in the period T2 - T3, when the signal CLK becomes high level potential, the potential of node N rises. When the difference between the gate potential of transistor 23 and the potential of node N reaches the threshold voltage of transistor 23, transistor 23 becomes off state and node N becomes floating. Also, when the potential of the gate of transistor 23 rises, the high potential of signal CLK is applied to output terminal OUT.

[0056] Subsequently, at time T3, the signal RIN becomes high potential and the signal CLK becomes low potential. In the period T3 - T4, a high potential is output from circuit 12 to wiring 15b and transistor 21 becomes on state. On the other hand, a low potential is output to wiring 15a and since transistor 23 is in the on state, transistor 22 becomes off state. Thereby, the potential VSS is applied to output terminal OUT.

[0057] Then, at time T4, the signal BDG becomes low potential and transistor 23 becomes off state.

[0058] The above is an explanation of an example of the operation method of the sequential circuit 10.

[0059] Here, the voltage stress applied to the transistor 23 will be described. For simplicity, here, the high potential is described as the potential VDD, and the low potential is described as the potential VSS.

[0060] At time T1, when the potential VDD is applied to the gate of the transistor 23 and the potential VDD is applied to the electrode on the wiring 15a side, the electrode on the node N side of the transistor 23 becomes the source. Subsequently, at time T2, when the signal CLK changes from the potential VSS to the potential VDD, assuming that the potential of the node N rises to a potential twice that of the potential VDD - potential VSS. At this time, since the wiring 15a is in a floating state and remains at the potential VDD, the source and drain of the transistor 23 are interchanged, and the electrode connected to the wiring 15a becomes the source. Also, at time T3, when the potential VSS is applied to the wiring 15a and the potential of the node N drops, the electrode on the wiring 15a side of the transistor 23 also functions as the source. In this way, a transistor whose source and drain functions are interchanged during the operation of the circuit can be called a bi-direction transistor.

[0061] During period T1 - T2, the voltage (potential difference) across the gate - source of transistor 23 becomes VDD - VSS at maximum. However, as the potential of node N rises, the voltage across the source - drain of transistor 23 drops rapidly, so the voltage stress is immediately relaxed. Also, during period T2 - T3, almost no potential difference occurs across the gate - source of transistor 23. Further, during period T3 - T4, the voltage across the gate - source of transistor 23 becomes VDD - VSS. Also, after time T4, no voltage stress occurs in transistor 23. From this, it can be seen that stress is applied across the gate - source of transistor 23 when a low potential is applied to wiring 15a and signal BDG is at a high potential. Therefore, by making the period during which signal BDG is at a high potential as short as possible during the period when a low potential is applied to wiring 15a, the voltage stress on transistor 23 can be reduced and the variation in the threshold voltage can be suppressed.

[0062] Here, the sequential circuit 10 can be used as a driving circuit for a display device. In particular, it can be preferably used as a scanning line driving circuit. At this time, when connecting the scanning lines connected to a plurality of pixels of the display device to the output terminal OUT, the duty ratio of the output signal output from the sequential circuit 10 to the output terminal OUT is significantly smaller than that of the signal CLK or the like. Also, the period during which the potential input to the wiring 15a is at a low potential is significantly longer than the period during which it is at a high potential. Therefore, if a constant high potential is applied to the gate of the transistor 23, the period during which voltage stress is applied between the gate and source of the transistor 23 becomes significantly longer, and the threshold voltage of the transistor 23 is likely to fluctuate. However, in one aspect of the present invention, since the signal BDG, which is a pulse signal with a small duty ratio instead of a constant potential, is applied to the gate of the transistor 23, the fluctuation of the threshold voltage of the transistor 23 can be preferably suppressed. In particular, it is preferable to apply a pulse signal in which the signal BDG becomes high only during the operation period when the sequential circuit 10 outputs a signal to the output terminal OUT (for example, the period T1 - T4 in FIG. 2B), and is always low in other periods. Thereby, the duty ratio of the signal BDG can be reduced to 1% or less, preferably 0.5% or less, more preferably 0.1% or less, and extremely high reliability can be imparted to the sequential circuit 10, and by extension, the semiconductor device, display device, and electronic device using the sequential circuit 10.

[0063] Also, when using the sequential circuit 10 as a driving circuit for a display device, it is preferable to provide the transistors included in the pixels of the display device and the transistors (such as the transistors 21, 22, and 23) that constitute the sequential circuit 10 on the same substrate. In particular, it is preferable to fabricate the transistors provided in the pixels and the transistors that constitute the sequential circuit 10 in the same process.

[0064] 〔Configuration Example 1 - 2〕 FIG. 3A shows a configuration example of a sequential circuit 10a having a circuit 11 with a partially different configuration from that of FIG. 2A.

[0065] The transistor 21 included in the circuit 11 has a pair of gates (hereinafter referred to as the first gate and the second gate). In the transistor 21, the first gate is electrically connected to the wiring 15b, the second gate is electrically connected to the other of its source and drain and the wiring to which the potential VSS is applied, and one of the source and drain is electrically connected to the other of the source and drain of the transistor 22 and the other electrode of the capacitor C1.

[0066] Here, when the sequential circuit 10a is used as a driving circuit of a display device, as described above, the duty ratio of the output signal output from the sequential circuit 10a to the output terminal OUT becomes significantly smaller than that of the signal CLK or the like. At this time, the period during which the transistor 21 is in the on state becomes significantly longer than the period during which it is in the off state. That is, the period during which a high potential is applied to the first gate of the transistor 21 becomes significantly longer than the period during which a low potential is applied. Therefore, the threshold voltage of the transistor 21 is more likely to fluctuate than that of the transistor 22. Specifically, the threshold voltage of the transistor 21 is more likely to shift in the positive direction than that of the transistor 22.

[0067] Therefore, in one aspect of the present invention, the transistor 21 is configured to have a pair of gates overlapping with each other with a semiconductor layer interposed therebetween. And one of the gates is configured to be electrically connected to the wiring to which a low potential is applied (the wiring to which the potential VSS is applied). In other words, it can be said that in the transistor 21, one of the gates and the source are electrically connected to each other. By adopting such a configuration, it is possible to preferably suppress the threshold voltage of the transistor 21 from shifting in the positive direction. Therefore, the reliability of the sequential circuit 10a, and thus semiconductor devices, display devices, electronic devices, etc. using the sequential circuit 10a can be improved.

[0068] Also, by configuring the transistor 21 such that one gate and the source are electrically connected, it is possible to suitably prevent the threshold voltage from becoming a negative value. That is, it becomes easy to make the transistor 21 have a normally-off characteristic. When the transistor 21 has a normally-on characteristic, when the voltage between the other gate and the source of the transistor 21 is 0 V, a leakage current between the source and the drain occurs, and the potential of the output terminal OUT cannot be maintained. Therefore, in order to turn off the transistor 21, it is necessary to apply a potential lower than the potential VSS to the other gate of the transistor 21, and a plurality of power supplies are required. On the other hand, the transistor 21 according to one aspect of the present invention can stably realize the normally-off characteristic, so that the sequential circuit 10a with high output performance can be realized without increasing the types of power supply potentials.

[0069] Also, the transistor 21 has an effect of enhancing the saturation property by configuring one gate and the source to be electrically connected. As a result, the design of the circuit 11 becomes easy, and the circuit 11 can be made into a circuit that can operate stably.

[0070] As described above, in the sequential circuit 10a, for the transistor 21 to which a voltage stress is applied for a significantly long period, a transistor in which one gate and the source are connected is applied, and a pulse signal with a small duty ratio is applied to the gate of the transistor 23 that functions as a bidirectional transistor. As a result, it is possible to suppress fluctuations in the threshold voltage in all three transistors constituting the circuit 11. As a result, it is possible to realize the sequential circuit 10a that achieves both high output performance and high reliability.

[0071] 〔Configuration Example 1-3〕 FIG. 3B shows a configuration example of the sequential circuit 10b. In the sequential circuit 10b, a transistor having a pair of gates and having one gate and the source connected is applied to the transistor 33 included in the circuit 12.

[0072] Transistor 33 is a transistor that, similar to transistor 21 of circuit 11, has a significantly long on-period during the operation of sequential circuit 10b. Therefore, by configuring transistor 33 in the same manner as transistor 21, fluctuations in the threshold voltage can be suppressed, and the reliability of sequential circuit 10b can be enhanced.

[0073] 〔Configuration Example 1-4〕 Fig. 3C shows a configuration example of sequential circuit 10c.

[0074] Sequential circuit 10c applies transistors having a pair of gates, where one gate is connected to the source, not only to transistor 33 of circuit 12 but also to transistor 34.

[0075] Compared with transistor 33, transistor 34 has a short on-period during the operation of sequential circuit 10c, but fluctuations in the threshold voltage can occur when it operates for a long time. Therefore, by configuring transistor 34 in the same manner as transistor 33, fluctuations in the threshold voltage can be suppressed, and the reliability of sequential circuit 10c can be enhanced.

[0076] Also, in sequential circuit 10c, transistors having a pair of gates are applied to transistor 31, transistor 32, transistor 22, and transistor 23.

[0077] In a transistor having a pair of gates via a semiconductor layer, by electrically connecting the pair of gates, compared with the case of using a transistor having one gate or giving a fixed potential to one of the pair of gates, the region where a channel is formed increases, and the current (also referred to as on-current) that can flow between the source and drain can be increased. Therefore, while suppressing a decrease in the on-current, the size of the transistor can be reduced, and thus the area of the sequential circuit 10c and, by extension, the drive circuit using the sequential circuit 10c can be reduced. In particular, since the transistors 22 and 23 are required to have a larger current supply capacity than the transistors provided in the circuit 12, applying such a transistor to the transistors 22 and 23 has an extremely high effect on reducing the area.

[0078] Also, by using a transistor in which a pair of gates are electrically connected, compared with a transistor having one gate, there are advantages such as being more likely to realize normally-off electrical characteristics and improved saturation. As a result, a highly reliable sequential circuit 10c can be realized.

[0079] Also, by applying a transistor with a high current supply capacity to the transistors 31, 32, 22, and 23, the operating frequency of the sequential circuit 10c can be increased.

[0080] In FIG. 3C, an example is shown in which transistors in which a pair of gates are electrically connected are applied to all of the transistors 31, 32, 22, and 23, but the present invention is not limited to this, and the above transistors may be applied to one or more transistors. In particular, it is preferable to apply a transistor in which a pair of gates are electrically connected to the transistors 22 and 23 included in the circuit 11.

[0081] [Configuration Example 2] Hereinafter, a sequential circuit having a configuration different from the above Configuration Example 1 will be described.

[0082] 〔Configuration Example 2-1〕 Fig. 4A shows a configuration example of the sequential circuit 20. The sequential circuit 20 includes a circuit 11 and a circuit 13. The circuit 11 and the circuit 13 are electrically connected by wiring 15a and wiring 15b. The configuration of the circuit 11 can refer to Configuration Example 1.

[0083] The signals BDG and CLK1 are input to the circuit 11. Also, an output terminal SROUT is connected. The signal BDG is input to the gate of the transistor 23. The signal CLK1 is input to one of the source and drain of the transistor 22.

[0084] The circuit 13 includes transistors 41 to 47 and a capacitor C2. The signals LIN, CLK2, CLK3, RIN, and RES are input to the circuit 13. It is preferable to apply the above-described n-channel type transistors to the transistors 41 to 47. In particular, it is preferable to use a transistor in which an oxide semiconductor is applied to the semiconductor in which the channel is formed.

[0085] The circuit 13 has a function of outputting a first signal to the wiring 15a and a second signal obtained by inverting the first signal to the wiring 15b according to various input signals.

[0086] Also, a potential VDD which is a high potential and a potential VSS which is a low potential are supplied to the circuit 11 and the circuit 13.

[0087] Specifically, for transistor 41, one of its gates is electrically connected to the wiring to which signal LIN is applied, one of its source and drain is electrically connected to wiring 15a and one of the source and drain of transistor 46, and the other is electrically connected to the wiring to which potential VDD is applied. For transistor 42, one of its gates is electrically connected to the wiring to which signal CLK3 is applied, one of its source and drain is electrically connected to one of the source and drain of transistor 43, and the other is electrically connected to the wiring to which potential VDD is applied. For transistor 43, one of its gates is electrically connected to the wiring to which signal CLK2 is applied, and the other of its source and drain is electrically connected to wiring 15b, one electrode of capacitor C2, and the gate of transistor 46. For transistor 44, one of its gates is electrically connected to the wiring to which signal RIN is applied, one of its source and drain is electrically connected to wiring 15b, and the other is electrically connected to the wiring to which potential VDD is applied. For transistor 45, one of its gates is electrically connected to the wiring to which signal RES is applied, one of its source and drain is electrically connected to wiring 15b, and the other is electrically connected to the wiring to which potential VDD is applied. The other of the source and drain of transistor 46 is electrically connected to the wiring to which potential VSS is applied. For transistor 47, one of its gates is electrically connected to the wiring to which signal LIN is applied, one of its source and drain is electrically connected to wiring 15b, and the other is electrically connected to the wiring to which potential VSS is applied. The other electrode of capacitor C2 is electrically connected to the wiring to which potential VSS is applied.

[0088] In circuit 13 shown in FIG. 4A, an example in which a transistor having a pair of gates is applied to transistor 46 is shown. One of the pair of gates of transistor 46 is electrically connected to the wiring to which potential VSS is applied.

[0089] Note that, among transistors 41 to 45, transistor 47, transistor 22, and transistor 23, a transistor having a pair of electrically connected gates may be applied to at least one of them. FIG. 4B shows an example in which transistors having a pair of electrically connected gates are applied to all of the transistors.

[0090] 〔Configuration Example 2-2〕 FIG. 5A shows a configuration example of a sequential circuit 30 having two output terminals. The sequential circuit 30 has a configuration in which a circuit 11a is provided instead of the circuit 11 in the sequential circuit 20.

[0091] A signal BDG, a signal CLK1, and a signal PWC are input to the circuit 11a. Also, an output terminal SROUT and an output terminal GOUT are connected to the circuit 11a.

[0092] The circuit 11a has a configuration in which two circuits 11 are connected in parallel. One circuit 11 is constituted by a transistor 21, a transistor 22, a transistor 23, and a capacitor C1, and another circuit 11 is constituted by a transistor 24, a transistor 25, a transistor 26, and a capacitor C3. The connection configurations of the transistors 24 to 26 and the capacitor C3 are the same as those of the circuit 11.

[0093] One of the source and drain of the transistor 25 is electrically connected to a wiring to which the signal PWC is supplied. Also, one of the source and drain of the transistor 24, the other of the source and drain of the transistor 25, and the other electrode of the capacitor C3 are electrically connected to the output terminal GOUT. The gate of the transistor 26 is electrically connected to a wiring to which the signal BDG is supplied.

[0094] In the circuit 11a, when a high potential is applied to the wiring 15a and a low potential is applied to the wiring 15b, the potential of the signal CLK1 is output to the output terminal SROUT, and the potential of the signal PWC is output to the output terminal GOUT. On the other hand, when a low potential is applied to the wiring 15a and a high potential is applied to the wiring 15b, both the output terminal SROUT and the output terminal GOUT are electrically connected to a wiring to which the potential VSS is applied.

[0095] Here, when the sequential circuit 30 is used as part of the gate driver circuit of the display device, the output terminal GOUT can be used as the terminal to which the scanning line is connected, and the output terminal SROUT can be used as the terminal to which the wiring input to the sequential circuit 30 of the next stage is connected. At this time, it is preferable to apply transistors having a higher current supply capacity than the transistors 21 and 22 to the transistors 24 and 25. For example, transistors with a large channel width can be applied to the transistors 24 and 25.

[0096] Here, the signal CLK1 and the signal PWC can use synchronized signals. Specifically, a signal in which the period of the high potential and the period of the low potential match can be used. At this time, it is preferable to use a signal in which the high potential is the potential VDD and the low potential is the potential VSS for the signal CLK1 and the signal PWC, because it is not necessary to increase the types of power supply potentials for driving the sequential circuit 30.

[0097] Also, signals with different amplitudes may be used for the signal CLK1 and the signal PWC. For example, a signal with a larger amplitude than the signal CLK1 can be used for the signal PWC. At this time, it is preferable to use a signal in which the low potential is the potential VSS and the high potential is a potential higher than the potential VDD for the signal PWC. Thereby, a high potential can be output to the output terminal GOUT. Further, by reducing the amplitude of the signal CLK1 and reducing the potential difference between the potential VDD and the potential VSS, the voltage stress applied to the transistors constituting the sequential circuit 30 is reduced. Thereby, variations in electrical characteristics such as the threshold voltage of the transistors can be suppressed, and the reliability of the sequential circuit 30 can be improved. Even in that case, since the potential applied to the gate of the transistor 25 can be made sufficiently higher than the potential VDD by the bootstrap effect of the capacitor C3, the high potential of the signal PWC can be output to the output terminal GOUT without being affected by the threshold voltage of the transistor 25.

[0098] Note that, among transistors 41 to 45, transistor 47, transistors 22, 23, 25, and 26, a transistor having a pair of electrically connected gates may be applied to at least one of them. FIG. 5B shows an example in which transistors having a pair of electrically connected gates are applied to all of the above transistors. In particular, it is preferable to apply transistors having a pair of electrically connected gates and high current driving ability to transistors 22 and 25.

[0099] [Configuration Example of Driving Circuit] Hereinafter, an example of a driving circuit configured by connecting a plurality of stages of sequential circuits and functioning as a shift register will be described.

[0100] [Configuration Example 1 of Driving Circuit] First, a configuration example of a sequential circuit that can be used in the driving circuit will be described. FIG. 6 shows a circuit diagram of the sequential circuit 30a. The sequential circuit 30a includes a circuit 13, a circuit 11a, and a signal generation circuit 14a. The signal generation circuit 14a is a circuit that generates a signal BDG.

[0101] Circuit 13 and circuit 11a can employ the above Configuration Example 2. Note that, in FIG. 6, the signal RIN illustrated in Configuration Example 2 is denoted as signal RIN1. Also, the node to which the gate of transistor 22 in circuit 11a is connected is denoted as node N1, and the node to which the gate of transistor 25 is connected is denoted as node N2.

[0102] The signal generation circuit 14a includes transistors 51, 52, and a capacitor C4. Also, a signal LIN and a signal RIN2 are input to the signal generation circuit 14a.

[0103] The transistor 51 has its gate electrically connected to a wiring to which the signal LIN is input, its source or drain electrically connected to a wiring to which the potential VDD is applied, and the other source or drain electrically connected to one of the source and drain of the transistor 52 and one electrode of the capacitor C4, respectively. The transistor 52 has its gate electrically connected to a wiring to which the signal RIN2 is input, and its other source and drain electrically connected to a wiring to which the potential VSS is applied, respectively. The capacitor C4 has its other electrode electrically connected to a wiring to which the potential VSS is applied.

[0104] In the signal generation circuit 14a, the signal BDG is output to a wiring to which the other source and drain of the transistor 51 are connected. The signal BDG is supplied to the gates of the transistors 23 and 26 of the circuit 11a, respectively.

[0105] When the signal LIN is at a high level and the signal RIN2 is at a low level, the transistor 51 is in an on state, the transistor 52 is in an off state, and the signal BDG output from the signal generation circuit 14a is at a high level. On the other hand, when the signal LIN is at a low level and the signal RIN2 is at a high level, the transistor 51 is in an off state, the transistor 52 is in an on state, and the signal BDG is at a low level.

[0106] Also, a capacitor C4 is connected to the wiring through which the signal BDG is output. As a result, both the signal LIN and the signal RIN2 become low potential, and both the transistor 51 and the transistor 52 turn off, so that even when the wiring through which the signal BDG is output becomes electrically floating, the potential of the wiring can be maintained. Therefore, it is not necessary to continuously output a high potential or a low potential as the signal BDG from the signal generation circuit 14a, and even when signals with a small duty ratio are used for the signal LIN and the signal RIN2, the potential of the wiring can be maintained over a long period. Specifically, since the state in which the signal BDG is at a low potential can be maintained over a long period, the signal BDG can be a signal with an extremely small duty ratio. Also, by providing the capacitor C4, it is possible to prevent the potential of the wiring through which the signal BDG is output from fluctuating due to electrical noise. Also, during the period when the signal BDG is at a low potential, it is not necessary to turn on the transistor 52, so the voltage stress applied to the transistor 52 is alleviated, and fluctuations in the threshold voltage can be suppressed.

[0107] By having such a signal generation circuit 14a, the signal BDG can be a pulse signal with a duty ratio of 5% or less, preferably 3% or less, more preferably 1% or less, still more preferably 0.5% or less, and even more preferably 0.1% or less. Thereby, extremely high reliability can be imparted to the sequential circuit 30a, and by extension, to the semiconductor device, display device, and electronic equipment using the sequential circuit 30a.

[0108] FIG. 6 shows an example in which transistors having a pair of gates electrically connected are applied to the transistor 51 and the transistor 52 included in the signal generation circuit 14a. Note that the present invention is not limited to this, and transistors having one gate may be applied to the transistor 51 and the transistor 52. Also, for the transistor 52, a transistor in which one of the pair of gates is electrically connected to the wiring to which the potential VSS is applied may be applied.

[0109] FIG. 7 shows a timing chart of an example of a driving method for the sequential circuit 30a. In FIG. 7, the time variations of the potentials at the signal CLK1 (signal PWC), signal CLK2, signal CLK3, signal RES, signal LIN, signal RIN1, signal RIN2, signal BDG, node N1 (node N2), and output terminal SROUT (output terminal GOUT) are schematically shown. Note that since signals having the same waveform are used for signal CLK1 and signal PWC, they are collectively shown. Also, since the states of the time variations of the potentials at node N1 and node N2 are generally the same, they are collectively shown. Further, for signal CLK1, signal CLK2, and signal CLK3, clock signals shifted by 1 / 4 cycle in this order are used respectively.

[0110] At time T11, when signal LIN becomes high level and signal RIN2 becomes low level, signal BDG becomes high level. Subsequently, at time T12, when signal CLK1 and signal PWC become high level, the potentials of node N1 and node N2 rise. Also, during the period T12 - T14, high level is output to output terminal SROUT and output terminal GOUT. In period T14, since signal LIN is low level and signal RIN1 is high level, low level is output to output terminal SROUT and output terminal GOUT. Then, at time T15, when signal RIN2 becomes high level, signal BDG becomes low level. Also, even after signal RIN2 becomes low level at time T17, signal BDG remains at low level.

[0111] Subsequently, a driving circuit configured by connecting a plurality of stages of the sequential circuit 30a will be described.

[0112] FIG. 8A is a diagram for explaining the input and output terminals of the sequential circuit 30a. The sequential circuit 30a has, as input terminals, terminals to which signal LIN, signal RIN1, signal RIN2, signal CLK1, signal CLK2, signal CLK3, signal PWC, and signal RES are respectively input, and, as output terminals, output terminal SROUT and output terminal GOUT.

[0113] FIG. 8B shows a configuration example of the drive circuit 40a. The drive circuit 40a has a plurality of sequential circuits. In FIG. 8B, sequential circuits 30a_1 to 30a_6 are shown, and the rest are omitted. The sequential circuits 30a_1 etc. each have the same configuration as the sequential circuit 30a exemplified in FIG. 6. Hereinafter, the sequential circuit located at the n-th position from the side closer to the input of the drive circuit 40a will be denoted as the sequential circuit 30a_n (n is an integer of 1 or more).

[0114] Any three of the signals CK1 to CK4 are used as the signals CLK1, CLK2, and CLK3 for the sequential circuit 30a_n. Also, any one of the signals PWC1 to PWC4 is used as the signal PWC for the sequential circuit 30a_n. The combinations of the signals CK1 to CK4 and the signals PWC1 to PWC4 are the same combination every four stages. That is, the same signals are input as the signals CLK1, CLK2, CLK3, and PWC to the sequential circuit 30a_n and the sequential circuit 30a_n + 4.

[0115] Also, a wiring OUTn which is an output wiring (in FIG. 8B, wirings OUT1 to OUT6 are shown) is connected to the output terminal GOUT of the sequential circuit 30a_n.

[0116] The signal SP is input as the signal LIN to the sequential circuit 30a_1. Also, the signal of the output terminal SROUT of the sequential circuit 30a_n - 1 is input as the signal LIN to the sequential circuit 30a_n where n is 2 or more. Also, the signal of the output terminal SROUT of the sequential circuit 30a_n + 2 is input as the signal RIN1 to the sequential circuit 30a_n. Also, the signal of the output terminal SROUT of the sequential circuit 30a_n + 3 is input as the signal RIN2 to the sequential circuit 30a_n.

[0117] Specifically, the sequential circuit 30a_1 receives as inputs the signal CK1, signal CK2, signal CK3, signal PWC1, signal RES, signal SP, the output signal of the sequential circuit 30a_3, and the output signal of the sequential circuit 30a_4, and outputs an output signal to the wiring OUT1. The sequential circuit 30a_2 receives as inputs the signal CK2, signal CK3, signal CK4, signal PWC2, signal RES, the output signal of the sequential circuit 30a_1, the output signal of the sequential circuit 30a_4, and the output signal of the sequential circuit 30a_5, and outputs an output signal to the wiring OUT2. The sequential circuit 30a_3 receives as inputs the signal CK3, signal CK4, signal CK1, signal PWC3, signal RES, the output signal of the sequential circuit 30a_2, the output signal of the sequential circuit 30a_5, and the output signal of the sequential circuit 30a_6, and outputs an output signal to the wiring OUT3. The sequential circuit 30a_4 receives as inputs the signal CK4, signal CK1, signal CK2, signal PWC4, signal RES, the output signal of the sequential circuit 30a_3, the output signal of the sequential circuit 30a_6, and the output signal of the sequential circuit 30a_7 (not shown), and outputs an output signal to the wiring OUT4. The sequential circuit 30a_5 receives as inputs the signal CK1, signal CK2, signal CK3, signal PWC1, signal RES, the output signal of the sequential circuit 30a_4, the output signal of the sequential circuit 30a_7 (not shown), and the output signal of the sequential circuit 30a_8 (not shown), and outputs an output signal to the wiring OUT5. The sequential circuit 30a_6 receives as inputs the signal CK2, signal CK3, signal CK4, signal PWC2, signal RES, the output signal of the sequential circuit 30a_5, the output signal of the sequential circuit 30a_8 (not shown), and the output signal of the sequential circuit 30a_9 (not shown), and outputs an output signal to the wiring OUT6.

[0118] FIG. 8C shows a timing chart related to the driving method of the driving circuit 40a. In FIG. 8C, the transition of the potential change is shown for each of the signal RES, signal SP, signals CK1 to CK4, and wirings OUT1 to OUT6 from top to bottom. Note that since the signals PWC1 to PWC4 use clock signals having the same phase and period as the signals CK1 to CK4 respectively, they are shown together.

[0119] Before time T0 shown in FIG. 8C, signal SP is at a high level and signal CK1 is at a low level. At this time, a low level is output to wirings OUT1 to OUT6.

[0120] At time T0, when signal CK1 (signal PWC1) changes from a low level to a high level, a high level is output from sequential circuit 30a_1 to wiring OUT1. Thereafter, high levels are sequentially output to the wirings after wiring OUT2 by signals CK1 to CK4 and signals PWC1 to PWC4.

[0121] Signals CK1 to CK4 are signals that are each shifted by a quarter cycle in order. Similarly, signals PWC1 to PWC4 are also signals that are each shifted by a quarter cycle in order. Therefore, as shown in FIG. 8C, signals such as signal CK1 that are shifted by a quarter cycle in order are output to wirings OUT1 to OUT6 and the like.

[0122] Also, the period during which a high level is output to wirings OUT1 to OUT6 and the like is a half cycle period of signals such as signal CK1. That is, the period during which wiring OUTn is at a high level and the period during which wiring OUTn+1 is at a high level overlap. Thereby, since the period for selecting wiring OUTn can be made long, it is preferable to use such a driving method when the load on the wiring is large. That is, when driving circuit 40a is used as a scanning line driving circuit for a display device with a large number of pixels or a display device with a large screen size, it is preferable to use such a driving method because the charge and discharge period of the scanning line can be lengthened. Here, as signals CK1 to CL4, four-phase clock signals shifted by a quarter cycle each are used, and the period during which wiring OUTn becomes (is selected) at a high level is set to a half cycle period of signals such as signal CK1, so that a period during which two adjacent wirings are selected simultaneously is provided. However, the present invention is not limited to this. For example, a configuration may be adopted in which three or more adjacent wirings are selected simultaneously by changing the cycle shift or duty ratio of the clock signal.

[0123] 〔Example Configuration of Driving Circuit 2〕 Hereinafter, a configuration example of a signal generation circuit that is partially different from the signal generation circuit 14a illustrated in FIG. 6 above will be described.

[0124] FIG. 9 shows a circuit diagram of the signal generation circuit 14b. The signal generation circuit 14b is a circuit that generates the signal BDG. Since the signal generation circuit 14b has a configuration that does not use the signal RIN2 as compared with the above-described signal generation circuit 14a, the number of wirings can be reduced.

[0125] The signal generation circuit 14b includes transistors 60 to 69, transistor 71, and transistor 72.

[0126] The transistor 60 has a signal LIN applied to its gate, a potential VDD applied to one of its source and drain, and the other is electrically connected to the gate of the transistor 71. The transistor 61 has a signal CLK3 applied to its gate, a potential VDD applied to one of its source and drain, and the other is electrically connected to the gate of the transistor 71. The transistor 62 has a signal RIN1 applied to its gate, a potential VDD applied to one of its source and drain, and the other is electrically connected to the gate of the transistor 71. The transistor 63 has a signal CLK1 applied to its gate, one of its source and drain is electrically connected to the gate of the transistor 71, and the other is electrically connected to one of the source and drain of the transistor 64. The transistor 64 has a signal CLK2 applied to its gate, and a potential VSS applied to the other of its source and drain. The transistor 65 has a signal CLK2 applied to its gate, a potential VDD applied to one of its source and drain, and the other is electrically connected to one of the source and drain of the transistor 66. The transistor 66 has a signal CLK1 applied to its gate, and the other of its source and drain is electrically connected to the gate of the transistor 72. The transistor 67 has a signal LIN applied to its gate, one of its source and drain is electrically connected to the gate of the transistor 72, and a potential VSS applied to the other. The transistor 68 has a signal CLK3 applied to its gate, one of its source and drain is electrically connected to the gate of the transistor 72, and a potential VSS applied to the other. The transistor 69 has a signal RIN1 applied to its gate, one of its source and drain is electrically connected to the gate of the transistor 72, and a potential VSS applied to the other. The transistor 71 has a potential VDD applied to one of its source and drain, and the other is electrically connected to one of the source and drain of the transistor 72 and the wiring to which the signal BDG is output. The transistor 72 has a potential VSS applied to the other of its source and drain.

[0127] The signal generation circuit 14b can generate a signal BDG with a duty ratio of 45% or more and 55% or less, preferably a duty ratio of 45% or more and 51% or less, and typically 50% or more and 51% or less. Therefore, higher reliability can be achieved with the signal BDG than when using the potential VDD.

[0128] By configuring the signal generation circuit 14b in this way, the signal BDG can be generated using only the signals supplied to the circuit 13 and the circuit 11a.

[0129] 〔Configuration Example 3 of Drive Circuit〕 Hereinafter, a configuration example of a drive circuit without using a signal generation circuit will be described.

[0130] FIG. 10 shows a circuit diagram of the sequential circuit 30b. The sequential circuit 30b is mainly different from the above sequential circuit 30a in that it does not have the signal generation circuit 14a.

[0131] The sequential circuit 30b is configured to use the signal CLK3 as the signal BDG. As a result, compared with the above sequential circuit 30a, since the signal RIN2 and the signal generation circuit 14a are not used, the configuration can be simplified.

[0132] FIG. 11 shows a timing chart of an example of the driving method of the sequential circuit 30b. In FIG. 11, the temporal changes in potential at the signal CLK1 (signal PWC), signal CLK2, signal CLK3, signal RES, signal LIN, signal RIN1, signal BDG, node N1 (node N2), and output terminal SROUT (output terminal GOUT) are schematically shown.

[0133] As shown in FIG. 11, the signal BDG and the signal CLK3 are the same signal.

[0134] At time T21, signal BDG is at a high level, and when signal LIN becomes high level, nodes N1 and N2 become high level. Subsequently, at time T22, when signal CLK1 and signal PWC become high level, the potentials of nodes N1 and N2 rise. Also, during period T22 - T24, a high level is output to output terminal SROUT and output terminal GOUT. At this time, signal BDG becomes low level, and transistors 23 and 26 are in an off state, so nodes N1 and N2 are in an electrically floating state. Subsequently, at time T24, signal LIN is at a low level, signal RIN1 is at a high level, signal BDG is at a high level, and transistors 23 and 26 are in an on state again, so the potentials of nodes N1 and N2 drop to a low level. Therefore, a low level is output to output terminal SROUT and output terminal GOUT. Then, at time T26, signal BDG becomes low level. Thereafter, although high level and low level are repeatedly input as signal BDG, since both signal LIN and signal RIN1 are at a low level, output terminal SROUT and output terminal GOUT maintain a low level.

[0135] Since sequential circuit 30b is configured to use a clock signal as signal BDG, as signal BDG, a pulse signal with a duty ratio of 45% or more and 55% or less, preferably a duty ratio of 45% or more and 51% or less, and typically 50% can be used. Therefore, higher reliability can be achieved compared to the case where potential VDD is used instead of signal BDG.

[0136] FIG. 12A shows a diagram for explaining the input / output terminals of sequential circuit 30b. Sequential circuit 30b is different from the above sequential circuit 30a in that it does not have a terminal to which signal RIN2 is input.

[0137] Also, FIG. 12B shows a configuration example of drive circuit 40b using sequential circuit 30b. Drive circuit 40b has the same configuration as drive circuit 40a except that it does not have a wiring connected to the terminal to which signal RIN2 of sequential circuit 30a_n is input.

[0138] FIG. 12C shows a timing chart of the driving method of the driving circuit 40b. As shown in FIG. 12C, the same output signal can be obtained by the same driving method as that of the driving circuit 40a.

[0139] Since the driving circuit exemplified here functions as a shift register that sequentially supplies pulse signals to a plurality of wirings, it can be suitably used for a gate driver circuit (scanning line driving circuit) of a display device. Note that the present invention is not limited to a display device, and can be suitably used for various devices to which a shift register circuit is applied, such as a storage device.

[0140] The above is the description of the configuration example of the driving circuit.

[0141] [Configuration Example of Transistor] Hereinafter, a configuration example of a transistor that can be used for the sequential circuit exemplified above will be described.

[0142] The transistor exemplified below has a pair of gates sandwiching a semiconductor layer, and one of the gates is electrically connected to one of the source and the drain. The transistor exemplified below can be applied to transistors 21 and the like in the sequential circuit exemplified above.

[0143] Note that by changing the connection of the gate, source, and drain of the transistor exemplified below, a transistor applicable to other transistors such as transistor 22 and transistor 23 in the sequential circuit exemplified above can be manufactured. For example, a transistor in which a pair of gates are electrically connected or a transistor having only one gate can be manufactured in the same manner as the transistor exemplified below by changing the connection portion of each conductive layer and the shape (pattern) of the conductive layer.

[0144] [Configuration Example 1] FIG. 13A shows a schematic top view of the transistor 100. FIG. 13B corresponds to a cross-sectional view of the cut surface along the dashed-dotted line A1 - A2 in FIG. 13A, and FIG. 13C corresponds to a cross-sectional view of the cut surface along the dashed-dotted line A3 - A2 in FIG. 13A. In FIG. 13A, some components (such as the gate insulating layer) of the transistor 100 are omitted from the illustration. Also, the direction of the dashed-dotted line A1 - A2 includes the channel length direction of the transistor 100, and the direction of the dashed-dotted line A3 - A2 includes the channel width direction of the transistor 100. Also, for the top view of the transistor, in the following drawings, as in FIG. 13A, some components will be omitted from the illustration.

[0145] The transistor 100 is provided on a substrate 102 and has a conductive layer 106a, an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a conductive layer 112a, etc. The conductive layer 106a is provided on the substrate 102. The insulating layer 103 is provided to cover the substrate 102 and the conductive layer 106a, etc. The island-shaped semiconductor layer 108 is provided on the insulating layer 103 and has a region overlapping with the conductive layer 106a. The insulating layer 110 is provided to cover the semiconductor layer 108 and the insulating layer 103. The conductive layer 112a is provided on the insulating layer 110 and has a region overlapping with the semiconductor layer 108 and the conductive layer 106a.

[0146] Also, an insulating layer 118 is provided to cover the conductive layer 112a and the insulating layer 110.

[0147] In the transistor 100, a part of the conductive layer 112a functions as a first gate electrode (also referred to as a top gate electrode), and a part of the conductive layer 106a functions as a second gate electrode (also referred to as a bottom gate electrode). Also, a part of the insulating layer 110 functions as a first gate insulating layer, and a part of the insulating layer 103 functions as a second gate insulating layer.

[0148] The semiconductor layer 108 preferably contains a metal oxide. For example, it preferably has indium, M (where M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin. In particular, as the semiconductor layer 108, it is preferable to use an oxide containing indium, gallium, and zinc (also referred to as IGZO). Or, it is preferable to use an oxide containing indium, tin, and zinc. Or, it is preferable to use an oxide containing indium, gallium, tin, and zinc.

[0149] The semiconductor layer 108 has a region 108i that functions as a channel formation region and a pair of low-resistance regions 108n provided with the region 108i interposed therebetween. One of the pair of low-resistance regions 108n functions as a source region of the transistor 100, and the other functions as a drain region. The region 108i overlaps at least one of the conductive layer 112a and the conductive layer 106a. In FIG. 13B, the portion of the semiconductor layer 108 that overlaps the conductive layer 112a is shown as the region 108i that functions as a channel formation region, but actually, a channel may also be formed in a portion that does not overlap the conductive layer 112a but overlaps the conductive layer 106a (a portion including the low-resistance region 108n).

[0150] Also, the low-resistance region 108n can also be referred to as a region having a lower resistance, a region having a higher carrier concentration, a region having a higher oxygen defect density, a region having a higher impurity concentration, or an n-type region than the channel formation region.

[0151] The low-resistance region 108n of the semiconductor layer 108 may be a region containing an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, or a noble gas. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to contain boron or phosphorus. Also, two or more of these elements may be contained.

[0152] The process of adding an impurity to the low-resistance region 108n can be performed through the insulating layer 110 using the conductive layer 112a as a mask.

[0153] The low-resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 or more and 1×10 23 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or more and 5×10 22 atoms / cm 3 or less, more preferably 1×10 20 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less, and preferably includes a region with such an impurity concentration.

[0154] The concentration of the impurity contained in the low-resistance region 108n can be analyzed by an analytical method such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When using XPS analysis, the concentration distribution in the depth direction can be known by combining ion sputtering from the surface side or the back side with an analytical method such as SIMS analysis or XPS analysis.

[0155] In particular, when using hydrogen as the impurity element, it is advisable to use an analysis method using neutron rays.

[0156] Also, in the low-resistance region 108n, it is preferable that the impurity element exists in an oxidized state. For example, it is preferable to use elements that are easily oxidized, such as boron, phosphorus, magnesium, aluminum, and silicon, as the impurity element. Since such easily oxidized elements can stably exist in an oxidized state by bonding with oxygen in the semiconductor layer 108, even when a high temperature (for example, 400 °C or higher, 600 °C or higher, or 800 °C or higher) is applied in a later process, desorption is suppressed. Further, when the impurity element deprives oxygen in the semiconductor layer 108, many oxygen deficiencies are generated in the low-resistance region 108n. Since this oxygen deficiency and hydrogen in the film combine to become a carrier supply source, the low-resistance region 108n becomes an extremely low-resistance state.

[0157] For example, when boron is used as the impurity element, the boron contained in the low-resistance region 108n can exist in a state of being bonded to oxygen. This can be confirmed by observing a spectral peak caused by the B 2 O 3 bond in XPS analysis. Also, in XPS analysis, a spectral peak caused by the state in which the boron element exists in a single state is not observed, or the peak intensity becomes extremely small to the extent that it is buried in the background noise observed near the measurement lower limit.

[0158] In the region of the insulating layer 110 that overlaps with the low-resistance region 108n, the above-described impurity elements may be included. At this time, similar to the low-resistance region 108n, it is preferable that the impurity elements in the insulating layer 110 also exist in a state of being combined with oxygen. Such elements that are easily oxidized can stably exist in an oxidized state by combining with oxygen in the insulating layer 110, so that even when a high temperature is applied in a subsequent process, desorption is suppressed. In particular, when the insulating layer 110 contains oxygen that can be desorbed by heating (also referred to as excess oxygen), the excess oxygen and the impurity elements combine and stabilize, so that it is possible to suppress the supply of oxygen from the insulating layer 110 to the low-resistance region 108n. In addition, a part of the insulating layer 110 containing impurity elements in an oxidized state becomes a state in which oxygen diffuses hardly, so that the supply of oxygen from above the insulating layer 110 to the low-resistance region 108n through the insulating layer 110 is suppressed, and it is also possible to prevent the low-resistance region 108n from becoming high-resistance.

[0159] The insulating layer 103 has a laminated structure in which an insulating film 103a and an insulating film 103b are laminated from the substrate 102 side. At this time, it is preferable to use an insulating film that hardly allows the metal elements contained in the conductive layer 106a to diffuse for the insulating film 103a located on the conductive layer 106a side. For example, it is preferable to use an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or a hafnium oxide film. Also, for the insulating film 103b in contact with the semiconductor layer 108, it is preferable to use an insulating film containing oxygen. For example, it is preferable to use a silicon oxide film or a silicon oxynitride film.

[0160] Note that the insulating layer 103 may have a single-layer structure or a laminated structure in which three or more layers are laminated. Also, in FIGS. 13B and 13C, the insulating layer 110 is shown as having a single-layer structure, but it may have a laminated structure in which two or more layers are laminated.

[0161] In FIGS. 13B and 13C, an example is shown in which the insulating layer 110 is provided to cover the end portion of the semiconductor layer 108, but the configuration is not limited to this. For example, the insulating layer 110 may be processed so that its upper surface shape substantially coincides with that of the conductive layer 112a. At this time, the upper surface of the low-resistance region 108n of the semiconductor layer 108 comes into contact with the insulating layer 118.

[0162] In the present specification and the like, "the upper surface shapes substantially coincide" means that at least a part of the contours overlaps between the two stacked layers. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, strictly speaking, the contours may not overlap exactly, and the upper layer may be located inside the lower layer or outside the lower layer. In this case as well, it is said that "the upper surface shapes substantially coincide".

[0163] Also, a layer that functions as a barrier film may be provided between the conductive layer 112a and the insulating layer 110. For example, a metal film, an alloy film, or a metal oxide film can be provided between the conductive layer 112a and the insulating layer 110. As the layer that functions as a barrier film, it is preferable to use a material that is less permeable to at least one of oxygen and hydrogen, preferably both, than the insulating layer 110. Thereby, it is possible to prevent oxygen from diffusing from the semiconductor layer 108 to the conductive layer 112a side and hydrogen from diffusing from the conductive layer 112a to the semiconductor layer 108. Thereby, the carrier density of the region 108i that functions as the channel formation region of the semiconductor layer 108 can be made extremely low. As the metal oxide film that can be used for the layer that functions as the barrier film, an oxide insulating film such as an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film, or a conductive oxide film such as indium oxide, indium tin oxide, or indium tin oxide containing silicon can be used.

[0164] Alternatively, as the metal oxide film functioning as the barrier film, an oxide material containing one or more elements the same as those of the semiconductor layer 108, preferably a metal oxide film formed using the same sputtering target as the semiconductor layer 108, is preferably applied. When forming the metal oxide film using a sputtering apparatus, by forming it in an atmosphere containing oxygen gas, oxygen can be suitably added to the insulating layer 110, the semiconductor layer 108, or the like. In addition, when the metal oxide film is formed for the purpose of supplying oxygen to the insulating layer 110, the semiconductor layer 108, or the like, it may be removed after forming the metal oxide film.

[0165] Also, as shown in FIGS. 13A and 13B, the transistor 100 has a conductive layer 120a and a conductive layer 120b on the insulating layer 118. The conductive layer 120a functions as one of the source electrode and the drain electrode, and the conductive layer 120b functions as the other of the source electrode and the drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108n of the semiconductor layer 108 at the opening 141a or the opening 141b provided in the insulating layer 118 and the insulating layer 110, respectively.

[0166] The insulating layer 118 functions as a protective layer for protecting the transistor 100. As the insulating layer 118, for example, an inorganic insulating material such as an oxide or a nitride can be used. More specific examples include inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate.

[0167] Also, as shown in FIGS. 13A and 13C, in the channel width direction, it is preferable that the conductive layer 112a and the conductive layer 106a extend outside the end of the semiconductor layer 108. At this time, as shown in FIG. 13C, the entire channel width direction of the semiconductor layer 108 is covered with the conductive layer 112a and the conductive layer 106a via the insulating layer 110 and the insulating layer 103.

[0168] The transistor 100 has a configuration in which a conductive layer 106a functioning as a back gate and a conductive layer 120b functioning as the other of the source electrode and the drain electrode are electrically connected. Specifically, the conductive layer 106a and the conductive layer 120b are electrically connected via a conductive layer 112b.

[0169] The conductive layer 112b is located on the same plane as the conductive layer 112a of the transistor 100 and is a layer formed by processing the same conductive film. The conductive layer 112b and the conductive layer 106a are electrically connected at an opening 143 provided in the insulating layer 110 and the insulating layer 103. Also, the conductive layer 120b and the conductive layer 112b are electrically connected at an opening 144 provided in the insulating layer 118. Thereby, a configuration in which one of the source and the drain of the transistor 100 and the back gate are electrically connected is realized. Thus, it is preferable to form openings in the insulating layer 118, the insulating layer 110, and the insulating layer 103 and electrically connect the conductive layer 120b and the conductive layer 106a via the conductive layer 112b instead of directly connecting them. Thereby, the depth of the opening can be made shallow, so that the step at the opening becomes low, the step coverage of the conductive film covering the opening is enhanced, and a problem that the conductive film is disconnected because the step cannot be completely covered can be prevented.

[0170] Also, in FIGS. 13A and 13C, the conductive layer 112a functioning as a top gate is electrically connected to a conductive layer 106b functioning as a wiring. The conductive layer 112a and the conductive layer 106b are electrically connected at an opening 142 provided in the insulating layer 110 and the insulating layer 103. The conductive layer 106b is preferably located on the same plane as the conductive layer 106a and is a layer formed by processing the same conductive film.

[0171] For example, when the transistor 100 is applied to the transistor 21 or the transistor 24 in the sequential circuit 30 illustrated in FIG. 5A, the conductive layer 106b corresponds to a wiring electrically connected to the wiring 15b, the conductive layer 120a corresponds to a wiring electrically connected to the output terminal GOUT or the output terminal SROUT, and the conductive layer 120b corresponds to a wiring to which the potential VSS is applied.

[0172] Here, it is preferable to use an oxide film for the insulating film 103b in contact with the semiconductor layer 108 of the insulating layer 103. In particular, it is preferable to apply a silicon oxide film or a silicon oxynitride film that can release oxygen by heating. Thereby, oxygen released from the insulating layer 103 due to heat or the like during the manufacturing process of the transistor 100 is supplied to the semiconductor layer 108, and oxygen deficiency in the semiconductor layer 108 can be reduced, so that a highly reliable transistor 100 can be realized.

[0173] At this time, it is preferable to perform a process of supplying oxygen into the insulating film 103b after forming the insulating film 103b and before forming the semiconductor layer 108. Examples of the process of supplying oxygen to the insulating film 103b include plasma treatment or heat treatment in an atmosphere containing oxygen. Alternatively, oxygen may be supplied to the insulating film 103b by an ion doping method or an ion implantation method. Alternatively, as described above, oxygen may be supplied into the insulating film 103b by forming a metal oxide film on the insulating film 103b by sputtering in an atmosphere containing oxygen, and then removing the metal oxide film. Alternatively, the semiconductor layer 108 may be formed by sputtering in an atmosphere containing oxygen, thereby combining the process of forming the semiconductor layer 108 and the process of supplying oxygen to the insulating film 103b.

[0174] In addition, when the insulating film 103b contains excessive oxygen, defect levels may easily be generated at or near the interface between the semiconductor layer 108 and the insulating film 103b. At this time, when a high potential is applied to the conductive layer 106a that functions as the second gate electrode, electrons as carriers are trapped at the defect levels, and the threshold voltage of the transistor 100 may shift positively. However, in the transistor 100, since the source potential (for example, potential VSS) is applied to the conductive layer 106a that functions as the second gate electrode provided via the insulating layer 103, almost no carriers are induced at or near the interface between the semiconductor layer 108 and the insulating film 103b. As a result, even if the above-mentioned defect levels exist, it becomes a state where electrons are hardly trapped, so that the shift of the threshold voltage can be preferably suppressed. Therefore, the transistor 100 can be said to be an extremely reliable transistor.

[0175] 〔Configuration Example 2〕 FIG. 14A shows a schematic top view of a transistor 100A having a partial configuration different from that of the transistor 100. FIG. 14B corresponds to a cross-sectional view of the cut surface along the dashed-dotted line B1 - B2 in FIG. 14A, and FIG. 14C corresponds to a cross-sectional view of the cut surface along the dashed-dotted line B3 - B2 in FIG. 14A.

[0176] The transistor 100A has a configuration in which a conductive layer 112a that functions as a top gate and a conductive layer 120b are electrically connected. Hereinafter, the description of the parts common to the transistor 100 will be omitted, and the different parts will be mainly described.

[0177] The conductive layer 120b and the conductive layer 112a are electrically connected at an opening 144 provided in the insulating layer 118.

[0178] In addition, a part of the conductive layer 106a functions as a wiring.

[0179] For example, when the transistor 100A is applied to the transistor 21 or the transistor 24 in the sequential circuit 30 illustrated in FIG. 5A, the conductive layer 106a corresponds to a wiring electrically connected to the wiring 15b, the conductive layer 120a corresponds to a wiring electrically connected to the output terminal GOUT or the output terminal SROUT, and the conductive layer 120b corresponds to a wiring to which the potential VSS is applied.

[0180] In the transistor 100A, it is preferable to apply an oxide film capable of releasing oxygen by heating to the insulating layer 110. Thereby, oxygen released from the insulating layer 110 is supplied to the semiconductor layer 108 due to heat or the like during the manufacturing process of the transistor 100A, and oxygen deficiency in the semiconductor layer 108 can be reduced, so that a highly reliable transistor 100A can be realized.

[0181] At this time, it is preferable to perform a process of supplying oxygen into the insulating layer 110 after forming the insulating layer 110 and before forming the conductive layer 112a or the like. Examples of the process of supplying oxygen to the insulating layer 110 include plasma treatment or heat treatment in an atmosphere containing oxygen. Alternatively, oxygen may be supplied to the insulating layer 110 by an ion doping method or an ion implantation method. Alternatively, as described above, oxygen may be supplied into the insulating layer 110 by forming a metal oxide film on the insulating layer 110 by a sputtering method in an atmosphere containing oxygen. The metal oxide film may be removed after film formation or may be left between the conductive layer 112a and the insulating layer 110.

[0182] In addition, when the insulating layer 110 contains excessive oxygen, defect levels may be easily generated at or near the interface between the semiconductor layer 108 and the insulating layer 110. Therefore, when a high potential is applied to the conductive layer 112a, the threshold voltage of the transistor 100A may shift positively. However, in the transistor 100A, since the source potential (e.g., potential VSS) is applied to the conductive layer 112a that functions as the first gate electrode, even if there are defect levels at or near the interface between the semiconductor layer 108 and the insulating layer 110, the positive shift of the threshold voltage of the transistor 100A can be suppressed. Therefore, the transistor 100A can be said to be a highly reliable transistor.

[0183] 〔Configuration Example 3〕 Hereinafter, an example of a configuration having two transistors and a capacitor will be described.

[0184] FIG. 15A shows a schematic top view of a configuration in which the transistor 100, the transistor 150, and the capacitor 160 are connected. FIG. 15B corresponds to a cross-sectional view of the cut surface along the dashed-dotted line C1 - C2 in FIG. 15A, and FIG. 15C corresponds to a cross-sectional view of the cut surface along the dashed-dotted line C3 - C4 in FIG. 15A. FIG. 15B includes a cross-section in the channel length direction of the transistor 150 and a cross-section of the capacitor 160. FIG. 15C includes a cross-section in the channel width direction of the transistor 150.

[0185] Further, FIG. 16 shows a schematic top view excluding the conductive layers 120a to 120c in FIG. 15A. In FIG. 16, only the outlines of the conductive layers 120a to 120c are shown by dashed lines.

[0186] The transistor 100 is a transistor in which a second gate electrode (bottom gate electrode) located on the substrate 102 side and one of the source and the drain are electrically connected, and the configuration exemplified in FIG. 13A and the like can be adopted.

[0187] Transistor 150 is a transistor that is located on the same plane as transistor 100 and is fabricated through the same process. Transistor 150 has a configuration in which a pair of gates are electrically connected.

[0188] Capacitor 160 can be fabricated through the same process as transistors 100 and 150.

[0189] Transistor 150 includes a conductive layer 106c that partially functions as a second gate electrode, an insulating layer 103 that partially functions as a second gate insulating layer, a semiconductor layer 108a, an insulating layer 110 that partially functions as a first gate insulating layer, and a conductive layer 112c that partially functions as a first gate electrode. Semiconductor layer 108a has a region 108ai that functions as a channel formation region and a pair of low-resistance regions 108an that function as a source and a drain.

[0190] Transistor 150 also has a conductive layer 120c that is electrically connected to one of the pair of low-resistance regions 108an and a conductive layer 120a that is electrically connected to the other. Conductive layer 120a is electrically connected to a low-resistance region 108n (not shown) of transistor 100. Conductive layer 120a and conductive layer 120c are electrically connected to low-resistance region 108an at openings 141d or 141c provided in insulating layer 118 and insulating layer 110, respectively.

[0191] Also, as shown in FIGS. 15A and 15C, conductive layer 112c and conductive layer 106c are electrically connected at an opening 145 provided in insulating layer 110 and insulating layer 103. That is, transistor 150 has a configuration in which a pair of gate electrodes provided sandwiching semiconductor layer 108a are electrically connected.

[0192] With such a configuration, the semiconductor layer 108a can be electrically surrounded by the electric field generated by the pair of gate electrodes. At this time, in particular, the same potential is applied to the conductive layer 106c and the conductive layer 112c. Thereby, since an electric field for inducing a channel in the semiconductor layer 108a can be effectively applied, the on-current of the transistor 150 can be increased. Therefore, it is also possible to miniaturize the transistor 150.

[0193] Note that the conductive layer 112c and the conductive layer 106c may not be connected. At this time, a fixed potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 150 may be applied to the other. At this time, the threshold voltage when driving the transistor 150 with the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0194] The capacitor 160 is composed of a part of the semiconductor layer 108a (a part of the low-resistance region 108an), a part of the insulating layer 103, and a part of the conductive layer 106c. In the capacitor 160, the insulating layer 103 functions as a dielectric layer, and the conductive layer 106c and the semiconductor layer 108a function as a pair of electrodes, respectively.

[0195] Also, in the region where the low-resistance region 108an and the conductive layer 106c overlap, a plurality of openings 141e are provided in the insulating layer 118 and the insulating layer 110, and in the openings 141e, the conductive layer 120a and the low-resistance region 108an are electrically connected. At this time, in addition to functioning as one of the source electrode or the drain electrode of the transistor 150, the conductive layer 120a functions as an auxiliary wiring (auxiliary electrode) of the capacitor 160. Furthermore, since the conductive layer 120a contacts the low-resistance region 108an at a plurality of locations, these contact resistances can be reduced, and the parasitic resistance of the capacitor 160 can be reduced, which is preferable. Also, compared with a configuration using the conductive layer 106c and the conductive layer 112c or a configuration using the conductive layer 106c and the conductive layer 120a as the pair of electrodes of the capacitor 160, by adopting a configuration using the conductive layer 106c and the low-resistance region 108an, the thickness of the insulating layer functioning as the dielectric layer can be made thinner, and the capacitance can be increased.

[0196] As shown in FIGS. 15A and 16, the conductive layer 120a can also serve as one of the source and drain electrodes of the transistor 100, one of the source and drain electrodes of the transistor 150, and one of the electrodes of the capacitor 160. Further, the island-shaped semiconductor layer 108a can also serve as a part of the transistor 150 and a part of the capacitor 160. With such a configuration, the occupied area of the circuit shown in FIGS. 15A and 16 can be reduced.

[0197] The configuration shown in FIGS. 15A and the like can be applied to a part of the sequential circuit. For example, when applied to the sequential circuit 30 illustrated in FIG. 5B, the transistor 100 can be applied to the transistor 21 or the transistor 24, the transistor 150 can be applied to the transistor 22 or the transistor 25, and the capacitor 160 can be applied to the capacitor C1 or the capacitor C3, respectively. At this time, the conductive layer 106b corresponds to a wiring electrically connected to the wiring 15b, the conductive layer 120a corresponds to a wiring electrically connected to the output terminal GOUT or the output terminal SROUT, the conductive layer 120b corresponds to a wiring to which the potential VSS is applied, the conductive layer 106c corresponds to a wiring electrically connected to the wiring 15a via the transistor 23 or the transistor 26, and the conductive layer 120c corresponds to a wiring to which the signal CLK1 or the signal PWC is applied.

[0198] The above is the description of the configuration example of the transistor.

[0199] [Example of manufacturing method] Hereinafter, an example of a method for manufacturing a transistor according to an aspect of the present invention will be described. Here, the transistor 100 illustrated in Configuration Example 1 and FIGS. 13A to 13C in the above-described configuration example of the transistor will be described as an example.

[0200] Note that thin films (such as insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. As the CVD method, there are plasma enhanced CVD (PECVD) method, thermal CVD method, etc. Also, one of the thermal CVD methods is metal organic CVD (MOCVD) method.

[0201] In addition, thin films (such as insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, knife coating, etc.

[0202] Also, when processing thin films constituting a semiconductor device, it can be processed using photolithography, etc. In addition, the thin film may be processed by nanoimprint method, sandblasting method, lift-off method, etc. Also, island-shaped thin films may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0203] Typically, there are the following two methods as the photolithography method. One is a method of forming a resist mask on the thin film to be processed, processing the thin film by etching, etc., and removing the resist mask. The other is a method of forming a photosensitive thin film and then performing exposure and development to process the thin film into a desired shape.

[0204] In photolithography, as the light used for exposure, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Further, exposure may be performed by immersion lithography technology. Also, as the light used for exposure, extreme ultraviolet (EUV) light, X-rays, etc. may be used. Instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. Note that when performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0205] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, etc. can be used.

[0206] Figures 17A to 18D show cross-sectional views at each stage of the manufacturing process of the transistor 100. In Figures 17A to 18D, to the left of the dashed-dotted line, cross-sections in the channel length direction of the transistor 100 and, to the right, cross-sections in the channel width direction are arranged and shown respectively.

[0207] 〔Formation of the conductive layer 106a〕 A conductive film is formed on the substrate 102 and processed by etching to form a conductive layer 106a that functions as a second gate electrode (Figure 17A).

[0208] At this time, as shown in Figure 17A, it is preferable to process so that the end portion of the conductive layer 106a has a tapered shape. Thereby, the step coverage of the insulating layer 103 to be formed next can be enhanced.

[0209] Also, by using a conductive film containing copper as the conductive layer 106a, the wiring resistance can be reduced. For example, when applying the transistor 100 to a large display device or a display device with high resolution, it is preferable to use a conductive film containing copper for the conductive layer 106a. Further, even when a conductive film containing copper is used for the conductive layer 106a, the diffusion of copper elements to the semiconductor layer 108 side is suppressed by the insulating layer 103, so that a highly reliable transistor can be realized.

[0210] 〔Formation of Insulating Layer 103〕 Subsequently, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106a (Fig. 17B). The insulating layer 103 can be formed using a PECVD method, an ALD method, a sputtering method, or the like.

[0211] Here, the insulating layer 103 is formed by laminating an insulating film 103a and an insulating film 103b. In particular, each insulating film constituting the insulating layer 103 is preferably formed by a PECVD method.

[0212] As the insulating film 103a, for example, an insulating film containing nitrogen such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or a hafnium nitride film can be used. In particular, it is preferable to use a dense silicon nitride film formed using a PECVD apparatus as the insulating film 103a. By using such an insulating film containing nitrogen, even when the thickness is thin, the diffusion of impurities from the side of the surface to be formed can be preferably suppressed.

[0213] Also, by using an insulating film containing nitrogen as the insulating film 103a, the diffusion of oxygen in the insulating film 103b to the conductive layer 106a or the like, the decrease in oxygen contained in the insulating film 103b, and the oxidation of the conductive layer 106a or the like can be suppressed.

[0214] In this specification, the oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and the nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. For example, when silicon oxynitride is described, it refers to a material having a higher oxygen content than nitrogen in its composition, and when silicon nitride oxide is described, it indicates a material having a higher nitrogen content than oxygen in its composition.

[0215] Also, in this specification, when an oxynitride and a nitride oxide containing the same element are described, the oxynitride includes a material that satisfies either one or both of the following conditions: having a higher oxygen content and a lower nitrogen content than the nitride oxide. Similarly, the nitride oxide includes a material that satisfies either one or both of the following conditions: having a lower oxygen content and a higher nitrogen content than the oxynitride. For example, when silicon oxynitride and silicon nitride oxide are described, the silicon oxynitride includes a material having a higher oxygen content and a lower nitrogen content than the silicon nitride oxide. Similarly, the silicon nitride oxide includes a material having a lower oxygen content and a higher nitrogen content than the silicon oxynitride.

[0216] The insulating film 103b in contact with the semiconductor layer 108 is preferably formed of an insulating film containing an oxide. In particular, it is preferable to use an oxide film for the insulating film 103b. Also, as the insulating film 103b, it is preferable to use a dense insulating film on whose surface impurities such as water are less likely to adsorb. Further, it is preferable to use an insulating film with as few defects as possible and with reduced impurities such as water or hydrogen.

[0217] As the insulating film 103b, for example, an insulating film containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used. In particular, it is preferable to use a silicon oxide film or a silicon oxynitride film as the insulating film 103b.

[0218] It is more preferable that the insulating film 103b has a region containing oxygen in excess of the stoichiometric composition. In other words, it is preferable that the insulating film 103b is an insulating film capable of releasing oxygen by heating. For example, forming the insulating film 103b in an oxygen atmosphere, performing a heat treatment on the insulating film 103b after film formation in an oxygen atmosphere, performing plasma treatment or the like on the insulating film 103b after film formation in an oxygen atmosphere, or forming an oxide film on the insulating film 103b in an oxygen atmosphere, etc., can supply oxygen into the insulating film 103b. In addition, in each of the above-mentioned processes for supplying oxygen, an oxidizing gas (for example, nitrous oxide or ozone) may be used instead of or in addition to oxygen. Or, after forming an insulating film capable of releasing oxygen by heating on the insulating film 103b and then performing a heat treatment, oxygen may be supplied from the insulating film into the insulating film 103b. Or, oxygen may be supplied to the insulating film 103b by a plasma ion doping method, an ion implantation method, or the like.

[0219] Here, it is preferable that the insulating film 103b is formed thicker than the insulating film 103a. Thereby, the amount of oxygen that can be released from the insulating film 103b by heating increases, and the amount of hydrogen released from the insulating film 103a is reduced. Therefore, while suppressing the supply of hydrogen to the subsequent semiconductor layer 108, a large amount of oxygen can be supplied, and a highly reliable transistor can be realized. The thickness of the insulating film 103b is preferably 2 times or more and 50 times or less, more preferably 3 times or more and 30 times or less, still more preferably 5 times or more and 20 times or less, and even more preferably 7 times or more and 15 times or less, and typically, it is preferably about 10 times the thickness of the insulating film 103a.

[0220] Also, when forming the metal oxide film to be the semiconductor layer 108 by sputtering in an atmosphere containing oxygen, oxygen can be supplied into the insulating film 103b. Then, after forming the metal oxide film to be the semiconductor layer, a heat treatment may be performed. By the heat treatment, oxygen in the insulating film 103b can be more effectively supplied to the metal oxide film, and oxygen deficiency in the metal oxide film can be reduced.

[0221] 〔Formation of Semiconductor Layer 108〕 Subsequently, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 17C).

[0222] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

[0223] The metal oxide film 108f is preferably made into a dense film with as few defects as possible. Also, the metal oxide film 108f is preferably a film with reduced impurities such as hydrogen or water as much as possible and is a high-purity film. In particular, it is preferable to use a metal oxide film having crystallinity as the metal oxide film 108f.

[0224] Also, when forming the metal oxide film 108f, oxygen gas and an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may be mixed. Note that the higher the ratio of oxygen gas in the entire film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the metal oxide film can be enhanced, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and a transistor with an increased on-current can be obtained.

[0225] When forming the metal oxide film 108f, the higher the substrate temperature, the higher the crystallinity, and a dense metal oxide film can be obtained. On the other hand, the lower the substrate temperature, the lower the crystallinity, and a metal oxide film with high electrical conductivity can be obtained.

[0226] As the film formation conditions for the metal oxide film 108f, the substrate temperature may be set to be not lower than room temperature and not higher than 250°C, preferably not lower than room temperature and not higher than 200°C, and more preferably not lower than room temperature and not higher than 140°C. For example, when the substrate temperature is set to be not lower than room temperature and lower than 140°C, the productivity is increased, which is preferable. In addition, by forming the metal oxide film with the substrate temperature being room temperature or in a state where it is not intentionally heated, the crystallinity can be lowered.

[0227] Here, by forming the metal oxide film 108f in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 103 during the film formation of the metal oxide film 108f. In particular, it is preferable to form the metal oxide film 108f by a sputtering method in an atmosphere containing oxygen.

[0228] During the film formation of the metal oxide film 108f, the higher the ratio of the oxygen flow rate to the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus (oxygen flow rate ratio), or the higher the oxygen partial pressure in the film formation chamber, the more oxygen can be supplied into the insulating layer 103. Since the oxygen flow rate ratio or the oxygen partial pressure during the film formation of the metal oxide film 108f also affects the crystallinity of the metal oxide film 108f or the electrical characteristics of the transistor, it can be determined based on the required electrical characteristics of the transistor and the like. For example, the oxygen flow rate ratio or the oxygen partial pressure during the film formation of the metal oxide film 108f may be appropriately determined within the range of 10% or more and 100% or less, preferably 20% or more and 100% or less.

[0229] In addition, when forming the metal oxide film 108f by a sputtering method in an atmosphere containing oxygen, the surface of the insulating layer 103 is covered with the metal oxide film 108f during the film formation. Thereby, it is possible to prevent a part of the oxygen supplied to the insulating layer 103 from desorbing to the outside during the film formation. As a result, a very large amount of oxygen can be confined in the insulating layer 103.

[0230] Before forming the metal oxide film 108f, it is preferable to perform at least one of a process for desorbing water, hydrogen, organic substances, etc. adsorbed on the surface of the insulating layer 103 and a process for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced-pressure atmosphere. The heat treatment can also be performed in the film formation apparatus for the metal oxide film 108f. Alternatively, plasma treatment in an atmosphere containing oxygen may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N 2 2O). When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while preferably removing the organic substances on the surface of the insulating layer 103. After such treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 103 to the atmosphere.

[0231] When the semiconductor layer 108 has a stacked structure in which a plurality of metal oxide films are stacked, after forming the previously formed metal oxide film, it is preferable to continuously form the next metal oxide film without exposing its surface to the atmosphere.

[0232] When stacking a plurality of metal oxide films, a stacked film in which metal oxide films having different compositions are stacked can be formed using sputtering targets having different compositions. Alternatively, the same sputtering target can be used and the film formation conditions can be varied to stack the metal oxide films. Examples of the film formation conditions include the type of film formation gas, the flow rate of the film formation gas, the flow rate ratio of the film formation gas, the pressure in the film formation chamber, the substrate temperature (stage temperature), and the power.

[0233] Here, when forming a metal oxide film by sputtering, the higher the power, the higher the film formation rate can be. Also, the lower the power, the lower the film formation rate can be, and the in-plane variations such as film thickness and film quality can be reduced. Therefore, by laminating a metal oxide film formed under high-power conditions and a metal oxide film formed under lower-power conditions than this using the same sputtering target, the in-plane variation can be reduced while increasing the film formation rate.

[0234] For example, a metal oxide film can be first formed on the insulating layer 103 at low power, and then a metal oxide film can be formed at higher power than this. Or, a metal oxide film can be first formed at high power, and then a metal oxide film can be formed at lower power than this. Or, film formation at low power and film formation at high power may be repeated.

[0235] The higher the power during film formation, the denser (more compact) the metal oxide film is formed. On the other hand, the lower the power during film formation, the lower-density metal oxide film is obtained. Also, the metal oxide film formed at low power has the characteristic that it can supply more oxygen to the layer located below it during film formation.

[0236] For example, the semiconductor layer 108 can have a laminated structure of a metal oxide film formed at low power from the insulating layer 103 side and a metal oxide film formed at high power. Thereby, a large amount of oxygen can be supplied to the insulating layer 103. Also, since the upper side of the semiconductor layer 108 can be made dense, the semiconductor layer 108 is less likely to be etched during the formation of the subsequent openings 141a and 141b, etc., and the production yield can be increased.

[0237] Further, the semiconductor layer 108 can have a laminated structure of a metal oxide film formed at high power from the side of the insulating layer 103 and a metal oxide film formed at low power. By forming the film at high power, it is possible to suppress the incorporation of impurities remaining in the film formation chamber into the metal oxide film. In particular, by setting the power to high at the initial stage of the film formation process, a metal oxide film with reduced impurities in the film can be formed more effectively. Therefore, it is preferable to use the metal oxide film formed at high power on the side of the insulating layer 103. Further, when a metal oxide film is formed at low power on the dense metal oxide film formed at high power, the second metal oxide film also tends to become dense. In particular, when a dense and highly crystalline film is formed in the first layer, the crystallinity of the second layer can be enhanced by reflecting the crystallinity. Further, by forming the metal oxide film at low power in the second layer, oxygen can be directly supplied to the first metal oxide film, so that oxygen deficiency in the film can be reduced during the formation of the semiconductor layer 108.

[0238] Subsequently, an island-shaped semiconductor layer 108 is formed by etching a part of the metal oxide film 108f (Fig. 17D).

[0239] For the processing of the metal oxide film 108f, either one or both of a wet etching method and a dry etching method may be used. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner. For example, in the insulating layer 103, the insulating film 103b may disappear by etching, and the surface of the insulating film 103a may be exposed.

[0240] Here, after the formation of the metal oxide film 108f or after processing the metal oxide film 108f into the semiconductor layer 108, it is preferable to perform a heat treatment. By the heat treatment, hydrogen or water contained in or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108 can be removed. Further, the film quality of the metal oxide film 108f or the semiconductor layer 108 may be improved by the heat treatment (for example, reduction of defects, improvement of crystallinity, etc.).

[0241] Further, by heat treatment, the oxygen supplied to the insulating layer 103 during the formation of the metal oxide film 108f can be diffused throughout the insulating layer 103. For example, immediately after the formation of the metal oxide film 108f, a large amount of the supplied oxygen may be present in the upper part of the insulating layer 103, and the oxygen may be in a state where it is likely to desorb. At this time, in the formation process of the insulating layer 110 described later, there is a risk that a large amount of oxygen may desorb from the exposed surface of the insulating layer 103. Therefore, by diffusing oxygen throughout the insulating layer 103 by heat treatment, it is possible to maintain a state in which a large amount of oxygen is confined in the insulating layer 103 even after the formation of the insulating layer 110.

[0242] Further, by heat treatment, oxygen can also be supplied from the insulating layer 103 to the metal oxide film 108f or the semiconductor layer 108. At this time, it is more preferable to perform heat treatment before processing the semiconductor layer 108 because oxygen desorbing from the insulating layer 103 can be efficiently supplied to the metal oxide film 108f.

[0243] Further, by heat treatment, water or hydrogen or the like can be desorbed from the insulating layer 103. At this time, if heat treatment is performed after processing the semiconductor layer 108, water or hydrogen or the like is likely to desorb from the exposed portion of the insulating layer 103, and it is possible to prevent water or hydrogen or the like desorbed from the insulating layer 103 from being supplied into the semiconductor layer 108. When the content of water or hydrogen or the like in the insulating layer 103 is high, it is preferable to perform heat treatment after processing the semiconductor layer 108.

[0244] The temperature of the heat treatment can typically be 150°C or higher and lower than the strain point of the substrate, or 200°C or higher and 500°C or lower, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0245] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. Alternatively, after heating in such an atmosphere, it may be heated in an atmosphere containing oxygen. Or it may be heated in a dry air atmosphere. Note that it is preferably that the atmosphere of the above heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment can use an electric furnace or an RTA (Rapid Thermal Anneal) apparatus, etc. By using an RTA apparatus, the heat treatment time can be shortened.

[0246] Note that if the heat treatment is unnecessary, it may not be performed. Also, here the heat treatment is not performed and it may be combined with the heat treatment performed in a later process. Also, in a process at a high temperature in a later process (for example, a film forming process, etc.), there may be a case where it can be combined with the heat treatment.

[0247] 〔Formation of Insulating Layer 110〕 Subsequently, an insulating layer 110 is formed to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 17E).

[0248] The insulating film constituting the insulating layer 110 is preferably formed by the PECVD method.

[0249] As the insulating layer 110, for example, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used.

[0250] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a laminated structure of an oxide insulating film. Further, it is more preferable that the insulating layer 110 has a region containing oxygen in excess of the stoichiometric composition. In other words, it is preferable that the insulating layer 110 has an insulating film capable of releasing oxygen.

[0251] Here, as the insulating layer 110, it is preferable to apply a laminated film in which three insulating films with different film formation conditions are laminated. At this time, in particular, it is preferable to use a silicon oxide film or a silicon oxynitride film for all of the three insulating films.

[0252] Since the first insulating film is formed on the semiconductor layer 108, it is preferably a film formed under conditions that do not damage the semiconductor layer 108 as much as possible. For example, it can be formed under conditions where the film formation rate (also referred to as the film formation speed) is sufficiently low compared to other films. For example, when forming a silicon oxynitride film by plasma CVD as the first insulating film, the film formation rate can be lowered and the damage to the semiconductor layer 108 can be extremely small by forming it under low power conditions, reducing the flow rate of deposition gases containing silicon such as silane and disilane in the film formation gas, and so on.

[0253] The second insulating film is preferably a film formed under conditions with a higher film formation rate than the first insulating film. Thereby, productivity can be improved.

[0254] The third insulating film is preferably an extremely dense film in which surface defects are reduced and impurities contained in the atmosphere such as water are less likely to adsorb. For example, similar to the first insulating film, it can be formed under conditions where the film formation rate is sufficiently low.

[0255] Also, before forming the insulating layer 110, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108. By this plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 can be reduced. Therefore, since impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, a highly reliable transistor can be realized. In particular, it is suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the film formation of the insulating layer 110. As the plasma treatment, for example, it can be performed in an atmosphere containing one or more of oxygen, ozone, nitrogen, nitrous oxide, argon, etc. Also, the plasma treatment and the film formation of the insulating layer 110 are preferably performed continuously without being exposed to the atmosphere.

[0256] Here, after forming the insulating layer 110, it is preferable to perform a heat treatment. By the heat treatment, hydrogen or water contained in or adsorbed on the surface of the insulating layer 110 can be removed. Also, defects in the insulating layer 110 can be reduced.

[0257] Also, by the heat treatment, oxygen contained in the insulating layer 103 can be desorbed and supplied to the semiconductor layer 108. For example, when the semiconductor layer 108 is damaged during the film formation of the insulating layer 110 and defects such as oxygen vacancies are generated in the semiconductor layer 108. Therefore, by performing a heat treatment after the film formation of the insulating layer 110, the oxygen supplied from the insulating layer 103 can reduce the oxygen vacancies in the semiconductor layer 108, and a highly reliable transistor can be realized.

[0258] The conditions of the heat treatment can refer to the above description.

[0259] Note that if the heat treatment is unnecessary, it may not be performed. Also, here, the heat treatment is not performed, and it may be combined with the heat treatment performed in a later process. Also, in some cases, it can be combined with the heat treatment in a later process under high temperature conditions (for example, a film formation process, etc.).

[0260] 〔Formation of the opening 143〕 Subsequently, by etching a part of the insulating layer 110 and the insulating layer 103, an opening 143 reaching the conductive layer 106a is formed.

[0261] 〔Formation of Conductive Layers 112a and 112b〕 Subsequently, a conductive film is formed on the insulating layer 110 so as to cover the opening 143, and the conductive film is processed into a desired shape to form the conductive layer 112a and the conductive layer 112b (FIG. 17F).

[0262] As the conductive layer 112a and the conductive layer 112b, it is preferable to use a low-resistance metal or alloy material. Further, as the conductive layer 112a and the conductive layer 112b, it is preferable to use a material that hardly releases hydrogen and a material in which hydrogen hardly diffuses. Further, as the conductive layer 112a and the conductive layer 112b, it is preferable to use a material that is hardly oxidized.

[0263] For example, the conductive layer 112a and the conductive layer 112b are preferably formed by a sputtering method using a sputtering target containing a metal or an alloy.

[0264] For example, as the conductive layer 112a and the conductive layer 112b, it is preferable to form a laminated film in which a conductive film that is hardly oxidized and in which hydrogen hardly diffuses and a low-resistance conductive film are laminated.

[0265] In this way, without etching the insulating layer 110, by forming a structure in which the upper surface and side surfaces of the semiconductor layer 108 and the insulating layer 103 are covered by the insulating layer 110, when etching the conductive film that becomes the conductive layer 112a or the like, a part of the semiconductor layer 108 or the insulating layer 103 or the like can be prevented from being etched and thinned.

[0266] Note that when processing the conductive layer 112a and the conductive layer 112b, a part of the insulating layer 110 may be etched and thinned.

[0267] Also, when forming the opening 143 shown in FIGS. 13A to 13C, first, before forming the conductive films that will become the conductive layer 112a and the conductive layer 112b, a part of the insulating layer 110 and the insulating layer 103 is etched to form an opening 143 that reaches the conductive layer 106a. Then, a conductive film that will become the conductive layer 112a and the conductive layer 112b is formed on the insulating layer 110 so as to cover the opening 143, and by processing the conductive film, the conductive layer 112a and the conductive layer 112b are formed. Thereby, a conductive layer 112b that is electrically connected to the conductive layer 106a in the opening 143 can be formed.

[0268] 〔Supply Process of Impurity Elements〕 Subsequently, using the conductive layer 112a as a mask, a process of supplying (also referred to as adding or implanting) impurity elements to the semiconductor layer 108 through the insulating layer 110 is performed (FIG. 18A). Thereby, a low-resistance region 108n can be formed in a region of the semiconductor layer 108 that is not covered by the conductive layer 112a. At this time, it is preferable to determine the conditions of the impurity element supply process in consideration of materials such as the conductive layer 112a serving as a mask or the thickness, etc., so that impurity elements are not supplied as much as possible to the region of the semiconductor layer 108 that overlaps with the conductive layer 112a. Thereby, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 112a.

[0269] Examples of the impurity element supply process include plasma processing in an atmosphere containing the impurity element to be supplied. For example, by performing plasma processing in an atmosphere containing hydrogen gas or ammonia gas, hydrogen can be supplied to the semiconductor layer 108 through the insulating layer 110. In particular, it is preferable to perform plasma processing in an atmosphere containing hydrogen gas.

[0270] FIG. 18A schematically shows a state in which impurity elements are supplied to the semiconductor layer 108 through the insulating layer 110 by exposing it to the plasma 140.

[0271] As an apparatus capable of generating plasma 140, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

[0272] Here, after performing the plasma treatment, it is preferable to continuously form the insulating layer 118 without exposing it to the atmosphere. At this time, it is preferable to continuously perform the plasma treatment and the film formation treatment in the same film formation chamber of the film formation apparatus for forming the insulating layer 118. For example, a treatment gas containing hydrogen gas is supplied into the film formation chamber to perform a plasma treatment, and then a film formation gas is supplied into the film formation chamber to form the insulating layer 118. At this time, the plasma treatment and the film formation treatment are preferably performed under the same condition of the substrate temperature (the temperature of the stage holding the substrate).

[0273] In one aspect of the present invention, an impurity element can be supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even when the semiconductor layer 108 has crystallinity, damage to the semiconductor layer 108 during the supply of the impurity element can be reduced, and it is possible to suppress the crystallinity from being impaired. Therefore, it is suitable when the electrical resistance increases due to a decrease in crystallinity.

[0274] Alternatively, as a method for supplying an impurity element, a plasma ion doping method or an ion implantation method can be preferably used. These methods can control the concentration profile in the depth direction with high accuracy by the acceleration voltage of ions, the dose amount, and the like. By using the plasma ion doping method, productivity can be increased. Also, by using an ion implantation method using mass separation, the purity of the supplied impurity element can be increased.

[0275] In the impurity element supply process, it is preferable to control the processing conditions so that the interface between the semiconductor layer 108 and the insulating layer 110, or a portion near the interface in the semiconductor layer 108, or a portion near the interface in the insulating layer 110 has the highest concentration. Thereby, an impurity element having an optimal concentration can be supplied to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0276] Examples of impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0277] As the raw material gas of the impurity element, a gas containing the above impurity element can be used. When supplying boron, typically B 2 H 6 gas or BF 3 gas etc. can be used. Also, when supplying phosphorus, typically PH 3 gas can be used. Further, a mixed gas obtained by diluting these raw material gases with a noble gas may also be used.

[0278] In addition, as the raw material gas, CH 4 、N 2 、NH 3 、AlH 3 、AlCl 3 、SiH 4 、Si 2 H 6 、F 2 、HF、H 2 、(C 5 H 5 ) 2 Mg, and noble gases etc. can be used. Also, the ion source is not limited to gas, and a solid or a liquid heated and vaporized may be used.

[0279] The addition of the impurity element can be controlled by setting conditions such as the acceleration voltage or the dose amount in consideration of the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108.

[0280] 〔Formation of insulating layer 118〕 Subsequently, an insulating layer 118 is formed to cover the insulating layer 110, the conductive layer 112a, the conductive layer 112b, etc. (FIG. 18B).

[0281] When forming the insulating layer 118 by plasma CVD method, if the film formation temperature is too high, impurities contained in the low resistance region 108n etc. may diffuse to the periphery including the channel formation region of the semiconductor layer 108, or the electrical resistance of the low resistance region 108n may increase. Therefore, the film formation temperature of the insulating layer 118 may be determined in consideration of these factors.

[0282] For example, as the film formation temperature of the insulating layer 118, it is preferably, for example, 150 °C or higher and 550 °C or lower, more preferably 160 °C or higher and 500 °C or lower, still more preferably 180 °C or higher and 450 °C or lower, and even more preferably 250 °C or higher and 400 °C or lower. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0283] Also, after forming the insulating layer 118, heat treatment may be performed. In some cases, the low resistance region 108n can be made more stably low resistance by the heat treatment. For example, by performing heat treatment, impurity elements can diffuse appropriately and be locally homogenized, and a low resistance region 108n having an ideal concentration gradient of impurity elements can be formed. Note that if the heat treatment temperature is too high (for example, 500 °C or higher), impurity elements may diffuse into the channel formation region, leading to deterioration of the electrical characteristics or reliability of the transistor.

[0284] The conditions of the heat treatment can refer to the above description.

[0285] In addition, if the heat treatment is not necessary, it may not be performed. Also, here, the heat treatment may not be performed and may be combined with the heat treatment performed in a later process. Also, in the case where there is a treatment at a high temperature in a later process (for example, a film formation process etc.), it may be possible to combine with the heat treatment.

[0286] 〔Formation of the opening 141a, the opening 141b, and the opening 144〕 Subsequently, by etching a part of the insulating layer 118, an opening 144 reaching the conductive layer 112b is formed. Further, by etching a part of the insulating layer 118 and the insulating layer 110, openings 141a and 141b reaching the low-resistance region 108n are formed (FIG. 18C).

[0287] The formation of the opening 144 and the formation of the openings 141a and 141b may be performed simultaneously or separately. When performed simultaneously, it is preferable to etch the insulating layer 110 located at the openings 141a and 141b under conditions where the conductive layer 112b located at the bottom of the opening 144 is difficult to etch.

[0288] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a, 141b, and 144, and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (FIG. 18D).

[0289] Through the above steps, the transistor 100 can be manufactured. For example, when the transistor 100 is applied to a pixel or a driving circuit of a display device, a step of forming one or more of a protective insulating layer, a planarization layer, a pixel electrode, or a wiring may be added thereafter.

[0290] The above is the description of the manufacturing method example.

[0291] In addition, when manufacturing the transistor 100A illustrated in Configuration Example 2, it can be manufactured by making the patterns of the conductive layer 112a and the conductive layer 106a different.

[0292] Also, when fabricating the structure shown in FIG. 15A and the like, the conductive layer 106b and the conductive layer 106c may be formed by processing the same conductive film as the conductive layer 106a, the semiconductor layer 108a may be formed by processing the same metal oxide film as the semiconductor layer 108, the conductive layer 112c may be formed by processing the same conductive film as the conductive layer 112a and the conductive layer 112b, and the conductive layer 120c may be formed by processing the same conductive film as the conductive layer 120a and the conductive layer 120b. Further, the opening 142 and the opening 145 may be formed in the same manner as the opening 143, and the opening 141c, the opening 141d, and the opening 141e may be formed in the same manner as the opening 141a. Thereby, the transistor 100, the transistor 150, and the capacitor 160 can be formed on the same substrate through the same process without increasing the number of processes.

[0293] [Modification Example of Fabrication Method Example] [Modification Example 1] In the above fabrication method example, when processing the conductive layer 112a and the conductive layer 112b, the insulating layer 110 in a region that does not overlap with the conductive layer 112a and the conductive layer 112b may be removed by etching. A schematic cross-sectional view of the transistor fabricated in this way is shown in FIG. 19A.

[0294] The transistor shown in FIG. 19A has a configuration in which the low-resistance region 108n of the semiconductor layer 108 is in contact with the insulating layer 118. At this time, by using an insulating film that can release hydrogen by heating as the insulating layer 118, hydrogen can be suitably supplied to the low-resistance region 108n during the formation process of the insulating layer 118. Alternatively, after the formation of the insulating layer 118, a heat treatment may be performed, or hydrogen can be supplied from the insulating layer 118 to the low-resistance region 108n by the heat applied in a subsequent process. At this time, as the insulating layer 118, an insulating film containing nitrogen such as a silicon nitride film or a silicon oxynitride film can be preferably used. Thereby, the insulating layer 118 can have both the function of releasing hydrogen and the function as a barrier film against water or hydrogen.

[0295] In addition, when a part of the semiconductor layer 108 can be sufficiently reduced in resistance by forming the insulating layer 118 in contact with a part of the semiconductor layer 108 that becomes the low-resistance region 108n, the insulating layer 118 does not necessarily have to be an insulating film capable of releasing hydrogen by heating. At this time, as the insulating layer 118, for example, an insulating film containing oxygen such as a silicon oxide film or a silicon oxynitride film can be used.

[0296] Alternatively, after the formation of the insulating layer 118, the supply process of the above-described impurity element may be performed to supply the impurity element to the low-resistance region 108n through the insulating layer 118. At this time, the insulating layer 118 does not necessarily have to be an insulating film capable of releasing hydrogen by heating.

[0297] [Modification Example 2] Using the above-described manufacturing method example, it is possible to simultaneously manufacture transistors each having only one gate. A schematic cross-sectional view of the transistor manufactured in this way is shown in FIG. 19B.

[0298] The transistor shown in FIG. 19B is mainly different from the transistor 100 in that it does not have a conductive layer 106a functioning as a bottom gate, does not have openings 143, 144, etc., and does not have a conductive layer 112b.

[0299] In addition, FIG. 19C shows a schematic cross-sectional view of a transistor in which the insulating layer 110 is processed so that the upper surface shape thereof substantially coincides with that of the conductive layer 112a, as in the above-described Modification Example 1.

[0300] The above is the description of the modification example.

[0301] The transistors exemplified above can be applied not only to sequential circuits but also to transistors provided in pixels of a display device. At this time, the transistors provided in the sequential circuit and the transistors provided in the pixels of the display device can be manufactured on the same substrate through the same process. Thereby, a display device having high reliability can be manufactured at low cost.

[0302] [Components of the semiconductor device] Hereinafter, the components included in the semiconductor device of the present embodiment will be described.

[0303] [Substrate] There are no major restrictions on the material of the substrate 102, etc., but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, a single-crystalline semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. made of silicon or silicon carbide may be used as the substrate 102. Also, those in which semiconductor elements are provided on these substrates may be used as the substrate 102.

[0304] Further, a flexible substrate may be used as the substrate 102, and a semiconductor device may be directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device. The release layer can be used to separate from the substrate 102 after partially or completely completing the semiconductor device thereon and transfer it to another substrate. At that time, the semiconductor device can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0305] [Conductive film] As materials that can be used for the conductive layers such as the gates, sources, and drains of transistors, and various wirings and electrodes constituting the semiconductor device, metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, gold, silver, zinc, tantalum, manganese, iron, niobium, cobalt, or tungsten, or alloys having these as main components, etc. can be mentioned. Also, films containing these materials can be used as a single layer or in a laminated structure.

[0306] For example, there are a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a three-layer structure in which a titanium film or a titanium nitride film is overlapped with an aluminum film or a copper film laminated thereon, and a titanium film or a titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film is overlapped with an aluminum film or a copper film laminated thereon, and a molybdenum film or a molybdenum nitride film is further formed thereon, etc. In addition, oxides such as indium oxide, tin oxide, or zinc oxide may be used. Further, the use of copper containing manganese is preferable because it enhances the controllability of the shape by etching.

[0307] In addition, oxide conductors or metal oxides such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, and In-Ga-Zn oxide can also be applied to the conductive layer constituting the semiconductor device.

[0308] Here, the oxide conductor (OC: Oxide Conductor) will be described. For example, when oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. The metal oxide that has become a conductor can be referred to as an oxide conductor.

[0309] In addition, as the conductive layer constituting the semiconductor device, a laminated structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy may be used. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced. At this time, it is preferable to apply a conductive film containing an oxide conductor on the side in contact with the insulating layer that functions as a gate insulating film.

[0310] 〔Semiconductor layer〕 When the semiconductor layer 108 is an In-M-Zn oxide, examples of the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M:Zn = 2:2:1, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 10:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, etc. In the above, when two or more elements are included as the element M, the ratio of M in the above atomic ratio shall correspond to the sum of the atomic numbers of the two or more metal elements.

[0311] Further, as the sputtering target, it is preferable to use a target containing a polycrystalline oxide because it is easy to form the semiconductor layer 108 having crystallinity. The atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio].

[0312] When the atomic ratio is described as In:Ga:Zn = 4:2:3 or in the vicinity thereof, when In is 4, it includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When the atomic ratio is described as In:Ga:Zn = 5:1:6 or in the vicinity thereof, when In is 5, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. When the atomic ratio is described as In:Ga:Zn = 1:1:1 or in the vicinity thereof, when In is 1, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0313] Further, the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon in this way, the off-current of the transistor can be reduced.

[0314] Further, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure described later. Among non-single crystal structures, the amorphous structure has the highest density of defect levels, and the CAAC structure has the lowest density of defect levels.

[0315] Hereinafter, CAAC (c-axis aligned crystal) will be described. CAAC represents an example of a crystal structure.

[0316] The CAAC structure is one of crystal structures such as a thin film having a plurality of nano-crystals (crystal regions with a maximum diameter of less than 10 nm). Each nano-crystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nano-crystals are continuously connected without forming grain boundaries with each other. In particular, a thin film having a CAAC structure has a feature that the c-axis of each nano-crystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film.

[0317] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since no distinct crystal grain boundaries can be confirmed in CAAC-OS, it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable.

[0318] Here, in crystallography, with respect to the three axes (crystal axes) of the a-axis, b-axis, and c-axis that make up the unit cell, it is common to take a unit cell with the c-axis as the specific axis. Particularly in crystals with a layered structure, it is common to use the two axes parallel to the plane direction of the layer as the a-axis and b-axis, and the axis intersecting the layer as the c-axis. As a typical example of a crystal with such a layered structure, there is graphite classified into the hexagonal crystal system. The a-axis and b-axis of its unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, InGaZnO 2 O 4 crystals having a 4 4 type crystal structure can be classified into the hexagonal crystal system. The a-axis and b-axis of its unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0319] In the observation image by a transmission electron microscope (TEM), it may not be possible to clearly confirm the crystal part in an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film). The crystal part contained in the microcrystalline oxide semiconductor film often has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the grain boundaries of the nc-OS film.

[0320] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, in the nc-OS film, no regularity is seen in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the whole film. Accordingly, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than that of the crystal part (for example, 1 nm or more and 30 nm or less), a ring-shaped region with high luminance is observed as if drawing a circle, and multiple spots may be observed within the ring-shaped region.

[0321] The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, in the nc-OS film, no regularity is seen in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier density and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility.

[0322] The nc-OS film can be formed by reducing the oxygen flow rate ratio during film formation as compared with the CAAC-OS film. Further, the nc-OS film can also be formed by reducing the substrate temperature during film formation as compared with the CAAC-OS film. For example, since the nc-OS film can be formed even in a state where the substrate temperature is relatively low (for example, a temperature of 130°C or lower) or in a state where the substrate is not heated, it is suitable for use when using a large glass substrate or a resin substrate, etc., and the productivity can be increased.

[0323] An example of the crystal structure of a metal oxide will be described. Using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]), the metal oxide formed by sputtering with the substrate temperature of 100°C or higher and 130°C or lower is likely to have either an nc (nano crystal) structure or a CAAC structure, or a structure in which these are mixed. On the other hand, the metal oxide formed with the substrate temperature at room temperature (R.T.) is likely to have an nc crystal structure. Here, the room temperature (R.T.) mentioned here includes the temperature when the substrate is not intentionally heated.

[0324] [Constitution of Metal Oxide] Hereinafter, the constitution of CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0325] Note that CAAC (c-axis aligned crystal) represents an example of a crystal structure, and CAC (Cloud-Aligned Composite) represents an example of a function or a constitution of a material.

[0326] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is the function of allowing electrons (or holes) serving as carriers to flow, and the insulating function is the function of not allowing electrons serving as carriers to flow. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating the respective functions, both functions can be enhanced to the maximum extent.

[0327] Also, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0328] Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0329] In addition, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to an insulating region and a component having a narrow band gap due to a conductive region. In such a configuration, when carriers flow, the carriers mainly flow in the component having the narrow band gap. Further, the component having the narrow band gap acts complementarily to the component having the wide band gap, and carriers also flow in the component having the wide band gap in conjunction with the component having the narrow band gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0330] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0331] The above is the description of the configuration of the metal oxide.

[0332] The configuration examples illustrated in this embodiment and the corresponding drawings, etc. can be appropriately combined with at least a part of other configuration examples or drawings, etc.

[0333] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0334] (Embodiment 2) In this embodiment, a display device having a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 20A to 20C.

[0335] The display device shown in FIG. 20A includes a pixel section 502, a drive circuit section 504, a protection circuit 506, and a terminal section 507. Note that the protection circuit 506 may not be provided.

[0336] The transistor according to one embodiment of the present invention can be applied to the transistors included in the pixel section 502 or the drive circuit section 504, etc. The transistor according to one embodiment of the present invention may also be applied to the protection circuit 506.

[0337] The pixel section 502 includes pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 includes a circuit for driving a display element.

[0338] The drive circuit section 504 includes drive circuits such as a gate driver 504a that outputs a scan signal to gate lines GL_1 to GL_X and a source driver 504b that supplies a data signal to data lines DL_1 to DL_Y. The gate driver 504a may be configured to include at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. Alternatively, the source driver 504b may be configured using a shift register or the like.

[0339] The sequential circuit according to one embodiment of the present invention can be applied to the gate driver 504a. The sequential circuit according to one embodiment of the present invention may also be applied to the source driver 504b.

[0340] The terminal section 507 refers to a portion provided with terminals for inputting power, a control signal, an image signal, etc. from an external circuit to the display device.

[0341] The protection circuit 506 is a circuit that makes a wiring to which it is connected and another wiring in a conductive state when a potential outside a certain range is applied to the wiring. The protection circuit 506 shown in FIG. 20A is connected to various wirings such as a gate line GL which is a wiring between the gate driver 504a and the pixel circuit 501, or a data line DL which is a wiring between the source driver 504b and the pixel circuit 501. In FIG. 20A, hatching is applied to the protection circuit 506 to distinguish it from the pixel circuit 501.

[0342] Also, the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel portion 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (for example, a driving circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate on which the pixel portion 502 is provided by COG or TAB (Tape Automated Bonding) or the like.

[0343] FIGS. 20B and 20C show an example of the configuration of a pixel circuit applicable to the pixel circuit 501. FIGS. 20B and 20C show the pixel circuit at the m-th row and n-th column (m is a natural number of 1 or more and X or less, n is a natural number of 1 or more and Y or less).

[0344] The pixel circuit 501 shown in FIG. 20B includes a liquid crystal element 570, a transistor 550, and a capacitive element 560. Also, a data line DL_n, a gate line GL_m, a potential supply line VL, etc. are connected to the pixel circuit 501.

[0345] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuits 501 in each row.

[0346] In addition, the pixel circuit 501 shown in FIG. 20C includes a transistor 552, a transistor 554, a capacitor element 562, and a light-emitting element 572. Further, a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, etc. are connected to the pixel circuit 501.

[0347] Note that a potential VDD, which is a high power supply potential, is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a potential VSS, which is a low power supply potential, is applied to the other. The current flowing through the light-emitting element 572 is controlled according to the potential applied to the gate of the transistor 554, whereby the emission luminance from the light-emitting element 572 is controlled.

[0348] The transistor 550 shown in FIG. 20B, or the transistors 552 and 554 shown in FIG. 20C, is preferably provided on the same substrate as the transistors included in the gate driver 504a.

[0349] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other configuration examples, drawings, etc.

[0350] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0351] (Embodiment 3) Hereinafter, a pixel circuit including a memory for correcting the gradation displayed on a pixel and a display device having the same will be described. The transistors illustrated in Embodiment 1 can be applied to the transistors used in the pixel circuit illustrated below.

[0352] [Circuit Configuration] FIG. 21A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. Further, a wiring S1, a wiring S2, a wiring G1, and a wiring G2 are connected to the pixel circuit 400.

[0353] The transistor M1 has its gate connected to the wiring G1, one of its source and drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1, respectively. The transistor M2 has its gate connected to the wiring G2, one of its source and drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401, respectively.

[0354] The circuit 401 is a circuit including at least one display element. Although various elements can be used as the display element, typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be applied.

[0355] Let the node connecting the transistor M1 and the capacitor C1 be the node N1, and the node connecting the transistor M2 and the circuit 401 be the node N2.

[0356] The pixel circuit 400 can hold the potential of the node N1 by turning off the transistor M1. Also, the potential of the node N2 can be held by turning off the transistor M2. Further, with the transistor M2 turned off, by writing a predetermined potential to the node N1 via the transistor M1, the potential of the node N2 can be changed according to the change amount of the potential of the node N1 by capacitive coupling via the capacitor C1.

[0357] Here, a transistor in which an oxide semiconductor exemplified in Embodiment 1 is applied can be applied to one or both of the transistors M1 and M2. Therefore, due to an extremely low off-current, the potential of the node N1 or the node N2 can be held for a long period. When the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or more, etc.), a transistor using a semiconductor such as silicon may be used.

[0358] [Example of driving method] Next, an example of the operation method of the pixel circuit 400 will be described with reference to FIG. 21B. FIG. 21B is a timing chart related to the operation of the pixel circuit 400. Here, for the sake of simplicity of explanation, the effects of various resistances such as wiring resistance, parasitic capacitances such as transistors or wiring, and threshold voltages of transistors are not considered.

[0359] In the operation shown in FIG. 21B, one frame period is divided into a period T1 and a period T2. The period T1 is a period for writing a potential to the node N2, and the period T2 is a period for writing a potential to the node N1.

[0360] 〔Period T1〕 In the period T1, a potential for turning on the transistors is applied to both the wiring G1 and the wiring G2. Also, a potential V ref which is a fixed potential is supplied to the wiring S1, and a first data potential V w is supplied to the wiring S2.

[0361] A potential V ref is applied to the node N1 from the wiring S1 via the transistor M1. Also, a first data potential V w is applied to the node N2 from the wiring S2 via the transistor M2. Therefore, a potential difference V w -V ref is held in the capacitor C1.

[0362] 〔Period T2〕 Subsequently, in the period T2, a potential for turning on the transistor M1 is applied to the wiring G1, and a potential for turning off the transistor M2 is applied to the wiring G2. Also, a second data potential V data is supplied to the wiring S1. A predetermined fixed potential may be applied to the wiring S2, or it may be in a floating state.

[0363] A second data potential V data is applied to the node N1 from the wiring S1 via the transistor M1. At this time, due to capacitive coupling by the capacitor C1, the second data potential V dataAccording to this, the potential of node N2 changes by a potential dV. That is, in circuit 401, a potential obtained by adding the first data potential V w and the potential dV is input. Note that in FIG. 21B, the potential dV is shown as a positive value, but it may be a negative value. That is, the second data potential V data may be lower than the potential V ref .

[0364] Here, the potential dV is generally determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. When the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV becomes a potential close to the second data potential V data .

[0365] In this way, since the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including the display element by combining two types of data signals, it is possible to perform gradation correction within the pixel circuit 400.

[0366] Also, the pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied by the source driver connected to the wiring S1 and the wiring S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Also, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0367] [Application Example] [Example using a liquid crystal element] The pixel circuit 400LC shown in FIG. 21C has a circuit 401LC. The circuit 401LC has a liquid crystal element LC and a capacitor C2.

[0368] One electrode of the liquid crystal element LC is connected to node N2 and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which the potential V com2 is applied. The other electrode of the capacitor C2 is connected to a wiring to which the potential V com1 is applied.

[0369] The capacitor C2 functions as a holding capacitor. Note that the capacitor C2 can be omitted if it is not necessary.

[0370] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example, high-speed display can be realized by overdrive driving, and a liquid crystal material with a high driving voltage can be applied. Also, by supplying a correction signal to the wiring S1 or the wiring S2, gradation can be corrected according to the use temperature, the deterioration state of the liquid crystal element LC, etc.

[0371] 〔Example using a light-emitting element〕 The pixel circuit 400EL shown in FIG. 21D has a circuit 401EL. The circuit 401EL has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0372] The transistor M3 has a gate connected to one of the node N2 and one electrode of the capacitor C2, and one of the source and the drain connected to a wiring to which a potential V H is applied, and the other connected to one electrode of the light-emitting element EL, respectively. The capacitor C2 has the other electrode connected to a wiring to which a potential V com is applied. The light-emitting element EL has the other electrode connected to a wiring to which a potential V L is applied.

[0373] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a holding capacitor. The capacitor C2 can be omitted if not necessary.

[0374] Here, a configuration in which the anode side of the light-emitting element EL is connected to the transistor M3 is shown, but the transistor M3 may be connected to the cathode side. In that case, the values of the potential V H and the potential V L can be appropriately changed.

[0375] By applying a high potential to the gate of transistor M3, a large current can flow through the light-emitting element EL, so that, for example, HDR display or the like can be realized. Further, by supplying a correction signal to wiring S1 or wiring S2, variations in electrical characteristics of transistor M3 or light-emitting element EL or the like can also be corrected.

[0376] Note that the circuit is not limited to the circuits illustrated in FIGS. 21C and 21D, and a configuration in which a transistor or a capacitor or the like is separately added may be used.

[0377] This embodiment can be implemented in appropriate combination with at least a part thereof and other embodiments described in this specification.

[0378] (Embodiment 4) In this embodiment, a display module that can be manufactured using one aspect of the present invention will be described.

[0379] The display module 6000 shown in FIG. 22A includes a display device 6006, a frame 6009, a printed circuit board 6010, and a battery 6011 to which an FPC 6005 is connected between an upper cover 6001 and a lower cover 6002.

[0380] For example, a display device manufactured using one aspect of the present invention can be used as the display device 6006. With the display device 6006, a display module with extremely low power consumption can be realized.

[0381] The upper cover 6001 and the lower cover 6002 can be appropriately changed in shape, dimensions, or the like according to the size of the display device 6006.

[0382] The display device 6006 may have a function as a touch panel.

[0383] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, or the like.

[0384] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, and the like.

[0385] FIG. 22B is a schematic cross-sectional view of the display module 6000 in the case of including an optical touch sensor.

[0386] The display module 6000 has a light emitting part 6015 and a light receiving part 6016 provided on the printed circuit board 6010. Further, it has a pair of light guide parts (light guide part 6017a, light guide part 6017b) in a region surrounded by the upper cover 6001 and the lower cover 6002.

[0387] The display device 6006 is provided so as to overlap with the printed circuit board 6010 or the battery 6011 or the like with the frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide part 6017a and the light guide part 6017b.

[0388] The light 6018 emitted from the light emitting part 6015 passes through the upper part of the display device 6006 by the light guide part 6017a, passes through the light guide part 6017b, and reaches the light receiving part 6016. For example, when the light 6018 is blocked by a detected object such as a finger or a stylus, a touch operation can be detected.

[0389] A plurality of light emitting parts 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving parts 6016 are provided at positions facing the light emitting parts 6015. Thereby, information on the position where the touch operation is performed can be obtained.

[0390]

[0391] The light guide units 6017a and 6017b that control the path of the light 6018 can arrange the light emitting unit 6015 and the light receiving unit 6016 below the display device 6006, and can suppress the external light from reaching the light receiving unit 6016 and causing the touch sensor to malfunction. In particular, when using a resin that absorbs visible light and transmits infrared light, the malfunction of the touch sensor can be more effectively suppressed.

[0392] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0393] (Embodiment 5) In this embodiment, an example of an electronic device to which the display device according to one aspect of the present invention can be applied will be described.

[0394] The electronic device 6500 shown in FIG. 23A is a portable information terminal that can be used as a smartphone.

[0395] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, buttons 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display unit 6502 has a touch panel function.

[0396] The display device according to one aspect of the present invention can be applied to the display unit 6502.

[0397] FIG. 23B is a schematic cross-sectional view including an end portion on the microphone 6506 side of the housing 6501.

[0398] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, and the like are arranged in a space surrounded by the housing 6501 and the protective member 6510.

[0399] On the protective member 6510, the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed by an adhesive layer (not shown).

[0400] Also, in a region outside the display unit 6502, a part of the display panel 6511 is folded back. Further, an FPC 6515 is connected to the folded-back part. An IC 6516 is mounted on the FPC 6515. Also, the FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

[0401] The flexible display panel according to an aspect of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Also, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. Further, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow bezel can be realized.

[0402] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0403] (Embodiment 6) In this embodiment, an electronic device including a display device manufactured using an aspect of the present invention will be described.

[0404] The electronic device exemplified below includes a display device according to an aspect of the present invention in the display unit. Therefore, it is an electronic device that realizes a high resolution. Also, it can be an electronic device that achieves both a high resolution and a large screen.

[0405] For example, an image having a resolution of full high vision, 4K2K, 8K4K, 16K8K, or higher can be displayed on the display unit of the electronic device according to an aspect of the present invention.

[0406] Examples of electronic devices include, in addition to electronic devices with relatively large screens such as television sets, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0407] The electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of an inner wall or outer wall of a house, building, etc., or an interior or exterior of an automobile, etc.

[0408] FIG. 24A is a diagram showing the appearance of a camera 8000 with a viewfinder 8100 attached.

[0409] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. A detachable lens 8006 is attached to the camera 8000.

[0410] Note that the lens 8006 and the housing of the camera 8000 may be integrated.

[0411] The camera 8000 can take an image by pressing the shutter button 8004 or touching the display unit 8002 that functions as a touch panel.

[0412] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, a strobe device, etc. can be connected.

[0413] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc.

[0414] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image, etc. received from the camera 8000 on the display unit 8102.

[0415] The button 8103 has a function as a power button or the like.

[0416] The display device according to an aspect of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0417] FIG. 24B is a diagram showing the appearance of the head-mounted display 8200.

[0418] The head-mounted display 8200 includes a mounting unit 8201, a lens 8202, a main body 8203, a display unit 8204, a cable 8205, and the like. A battery 8206 is built in the mounting unit 8201.

[0419] The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like and can display the received video information on the display unit 8204. Further, the main body 8203 includes a camera and can use information on the movement of the user's eyeball or eyelid as input means.

[0420] In addition, the mounting unit 8201 may be provided with a plurality of electrodes capable of detecting a current flowing along with the movement of the user's eyeball at a position where it touches the user, and may have a function of recognizing the line of sight. Further, it may have a function of monitoring the user's pulse based on the current flowing through the electrodes. In addition, the mounting unit 8201 may include various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204, or a function of changing the video displayed on the display unit 8204 in accordance with the movement of the user's head.

[0421] The display device according to an aspect of the present invention can be applied to the display unit 8204.

[0422] Figures 24C, 24D, and 24E are diagrams showing the appearance of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0423] The user can view the display of the display unit 8302 through the lenses 8305. It is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of immersion. Also, by viewing different images displayed in different regions of the display unit 8302 through the lenses 8305, it is possible to perform three-dimensional display using parallax and the like. Note that the configuration is not limited to having one display unit 8302, and two display units 8302 may be provided, with one display unit arranged for each eye of the user.

[0424] Note that the display device according to one aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to one aspect of the present invention has extremely high definition, even when enlarged using the lenses 8305 as shown in Fig. 24E, it is possible to display a more realistic image without the user being able to visually recognize the pixels.

[0425] The electronic device shown in Figs. 25A to 25G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (including a function for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), a microphone 9008, and the like.

[0426] The electronic devices shown in FIGS. 25A to 25G have various functions. For example, it can have functions such as displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, and the like. Note that the functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have a plurality of display units. Further, the electronic device may be provided with a camera or the like, and may have functions such as shooting a still image or a moving image and storing it in a recording medium (external or built-in to the camera), and displaying the captured image on the display unit.

[0427] Details of the electronic devices shown in FIGS. 25A to 25G will be described below.

[0428] FIG. 25A is a perspective view showing a television device 9100. The television device 9100 can incorporate a large screen, for example, a display unit 9001 of 50 inches or more, or 100 inches or more.

[0429] FIG. 25B is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as, for example, a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Further, the portable information terminal 9101 can display character or image information, etc. on its plurality of surfaces. FIG. 25B shows an example in which three icons 9050 are displayed. Also, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming calls such as e-mails, SNS, and phone calls, titles of e-mails or SNS, sender names, dates and times, remaining battery levels, antenna reception strengths, and the like. Or, icons 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0430] FIG. 25C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of a display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, the user can also confirm the information 9053 displayed at a position where it can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in the breast pocket of the clothing. The user can check the display without taking the mobile information terminal 9102 out of the pocket, and can determine, for example, whether to receive a call.

[0431] FIG. 25D is a perspective view showing a wristwatch-type mobile information terminal 9200. Further, the display surface of the display unit 9001 is provided in a curved shape, and the display can be performed along the curved display surface. Further, the mobile information terminal 9200 can also make a hands-free call by mutually communicating with, for example, a wireless communication-capable headset. Further, the mobile information terminal 9200 can also perform data transmission or charging mutually with other information terminals through a connection terminal 9006. Note that the charging operation may be performed by wireless power supply.

[0432] FIGS. 25E, 25F, and 25G are perspective views showing a foldable mobile information terminal 9201. Further, FIG. 25E shows a state where the mobile information terminal 9201 is unfolded, FIG. 25G shows a folded state, and FIG. 25F is a perspective view of a state in the middle of changing from one of FIG. 25E and FIG. 25G to the other. The mobile information terminal 9201 has excellent portability in the folded state, and excellent display listability due to a seamless wide display area in the unfolded state. The display unit 9001 included in the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0433] FIG. 26A shows an example of a television device. In the television device 7100, a display unit 7500 is incorporated in a housing 7101. Here, a configuration in which the housing 7101 is supported by a stand 7103 is shown.

[0434] The operation of the television apparatus 7100 shown in Fig. 26A can be performed by an operation switch provided in the housing 7101 or a separate remote control unit 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television apparatus 7100 may be operated by touching it. The remote control unit 7111 may have a display unit in addition to operation buttons.

[0435] Note that the television apparatus 7100 may have a television broadcast receiver or a communication device for network connection.

[0436] Fig. 26B shows a notebook personal computer 7200. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. The display unit 7500 is incorporated in the housing 7211.

[0437] Figs. 26C and 26D show an example of a digital signage.

[0438] The digital signage 7300 shown in Fig. 26C has a housing 7301, a display unit 7500, a speaker 7303, etc. Further, it can have an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0439] Fig. 26D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0440] The larger the display unit 7500 is, the more information can be provided at one time, and it is also easier to catch people's eyes. Therefore, for example, it has the effect of enhancing the advertising effect.

[0441] It is preferable that a touch panel is applied to the display unit 7500 so that it can be operated by the user. As a result, it can be used not only for advertising purposes but also for purposes of providing information required by the user, such as route information, traffic information, or guidance information for commercial facilities.

[0442] Also, as shown in FIGS. 26C and 26D, it is preferable that the digital signage 7300 or the digital signage 7400 can be linked by wireless communication with an information terminal 7311 such as a smartphone held by the user. For example, the information of the advertisement displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display of the display unit 7500 can be switched by operating the information terminal 7311.

[0443] Also, a game using the information terminal 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. As a result, an unspecified number of users can participate in the game and enjoy it at the same time.

[0444] The display device according to one aspect of the present invention can be applied to the display unit 7500 in FIGS. 26A to 26D.

[0445] Although the electronic device of the present embodiment is configured to have a display unit, one aspect of the present invention can also be applied to an electronic device that does not have a display unit.

[0446] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

Description of Reference Numerals

[0447] LIN: Signal: RIN: Signal: BDG: Signal: CLK: Signal: OUT: Output Terminal: GOUT: Output Terminal: SROUT: Output Terminal: PWC: Signal: RES: Signal: SP: Signal: C1 to C4: Capacitance: CK1 to CK4: Signal: CLK1 to CLK3: Signal: N, N1, N2: Node: OUT to OUT6: Wiring: PWC1 to PWC4: Signal: RIN1, RIN2: Signal: 10, 10a, 10b, 10c: Sequential Circuit: 11, 11a, 12, 13: Circuit: 14a, 14b: Signal Generation Circuit: 15a, 15b: Wiring: 20: Sequential Circuit: 21 to 26: Transistor: 30, 30a, 30a_n: Sequential Circuit: 30b: Sequential Circuit: 31 to 34: Transistor: 40a, 40b: Drive Circuit: 41 to 47, 51, 52, 60 to 69, 71, 72: Transistor

Claims

[Claim 1] a signal generation circuit, first to seventh transistors, a first capacitor, and first to seventh wirings; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor; the other of the source and the drain of the first transistor is electrically connected to the first wiring to which a first potential is applied; a gate of the first transistor is electrically connected to the second wiring to which a first signal is input; one of a source and a drain of the second transistor is electrically connected to the third wiring to which a second potential is applied; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the fifth transistor; a gate of the second transistor is electrically connected to the fourth wiring to which a second signal is input; one of a source and a drain of the third transistor is electrically connected to a gate of the seventh transistor; the other of the source and the drain of the third transistor is electrically connected to the first wiring; a gate of the third transistor is electrically connected to the fourth wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the seventh transistor; a gate of the fourth transistor is electrically connected to the second wiring; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the sixth transistor; a gate of the fifth transistor is electrically connected to the fifth wiring to which a first pulse signal is supplied; one of a source and a drain of the sixth transistor is electrically connected to the seventh wiring; the other of the source and the drain of the sixth transistor is electrically connected to the sixth wiring to which a second pulse signal is supplied; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the seventh wiring; a first electrode of the first capacitance element is electrically connected to a gate of the sixth transistor; a second electrode of the first capacitance element is electrically connected to the seventh wiring; the first pulse signal has a duty ratio of 1% or less, the second pulse signal is a clock signal; the signal generating circuit has a function of supplying the first pulse signal to the fifth wiring; Semiconductor device.

Images