Chemical solution, etching method, and method of manufacturing semiconductor device

Abstract

To increase the yield of semiconductor devices.SOLUTION: A chemical solution according to an embodiment hereof comprises a mixed acid, and polyethyleneimine which is an organic amine. The mixed acid contains an inorganic acid, an oxidizer, carboxylic acid and water. In the chemical solution, the concentration of the polyethyleneimine is within a range of 0.05-10 wt.%.SELECTED DRAWING: None

Description

Technical Field

[0001] Embodiments relate to a chemical solution, an etching method, and a method for manufacturing a semiconductor device.

Background Art

[0002] A NAND-type flash memory including three-dimensionally stacked memory cells is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the yield of semiconductor devices.

Means for Solving the Problems

[0005] The chemical solution of the embodiment includes a mixed acid and polyethyleneimine which is an organic amine. The mixed acid includes an inorganic acid, an oxidizing agent, a carboxylic acid, and water. The concentration of polyethyleneimine in the chemical solution is within the range of 0.05 wt% to 10 wt%.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing an example of the overall configuration of a semiconductor device according to an embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor device according to an embodiment. [Figure 3] A plan view showing an example of the planar layout of a memory cell array included in a semiconductor device according to an embodiment. [Figure 4] A plan view showing an example of the detailed planar layout in the memory region of a memory cell array included in a semiconductor device according to an embodiment. [Figure 5] A cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure in the memory region of a memory cell array provided in the semiconductor device according to the embodiment. [Figure 6] An enlarged view of region VI in Figure 5, showing an example of a detailed cross-sectional structure in the memory region of a memory cell array provided in the semiconductor device according to the embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a semiconductor device according to the embodiment. [Figure 8] A flowchart showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 10] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 11] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 12] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 13] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 14] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 15] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 16] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor device according to the embodiment. [Figure 17] A schematic diagram showing an example of the cross-sectional structure of a memory cell array after Mo etching in the embodiment. [Figure 18] A table showing the results of shape evaluation of the Mo etching process in the example. [Figure 19] A schematic diagram showing the cross-sectional structure of the memory cell array after Mo etching in the comparative example. [Modes for carrying out the invention]

[0007] Hereinafter, embodiments will be described with reference to the drawings. The embodiments illustrate devices and methods for embodying the technical idea of the invention. The drawings are schematic or conceptual, and dimensions, ratios, etc. of each drawing are not necessarily the same as those in reality. The technical idea of the present invention is not specified by the shape, structure, arrangement, etc. of the components.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. The numbers after the characters constituting the reference numerals are referred to by the reference numerals including the same characters, and are used to distinguish between elements having similar configurations. Similarly, the characters after the numbers constituting the reference numerals are referred to by the reference numerals including the same numbers, and are used to distinguish between elements having similar configurations.

[0009] [Embodiment] The chemical solution according to the embodiment is an etching solution used for etching a molybdenum-containing layer. The chemical solution according to the embodiment is used, for example, for etching a molybdenum-containing layer formed on a high aspect ratio structure in the manufacturing process of the semiconductor device 1. Hereinafter, the chemical solution according to the embodiment and the semiconductor device 1 according to the embodiment will be described in order.

[0010] [1] Composition of Chemical Solution The chemical solution according to the embodiment contains a mixed acid and polyethyleneimine (PEI: Polyethylenimine). The mixed acid contains an inorganic acid, an oxidizing agent, a carboxylic acid, and water.

[0011] The concentration of polyethyleneimine in the chemical solution is within the range of 0.05 wt% to 10 wt%. When the concentration of polyethyleneimine is within this range, there is a corrosion prevention effect on molybdenum, so that the effect of reducing the etching rate is achieved. The concentration of polyethyleneimine is more preferably within the range of 1 wt% to 3 wt%.

[0012] The concentration of inorganic acid in the chemical solution is, for example, within the range of 40 wt% to 80 wt%. When the concentration of inorganic acid is within this range, due to the complexing effect, it has an etching effect. The inorganic acid can be at least one selected from the group consisting of phosphoric acid and sulfuric acid.

[0013] The concentration of oxidizing agent in the chemical solution is, for example, 5 wt% or less. When the concentration of oxidizing agent is within this range, due to the oxidizing effect, it has the effect of making it possible to complex with inorganic acid. The oxidizing agent can be at least one selected from the group consisting of nitric acid and hydrogen peroxide.

[0014] The concentration of carboxylic acid in the chemical solution is, for example, within the range of 0.1 wt% to 45 wt%. When the concentration of carboxylic acid is within this range, due to the interference effect, it has a composition stabilizing effect. The carboxylic acid can be at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid and citric acid.

[0015] The concentration of water in the chemical solution is, for example, within the range of 5 wt% to 30 wt%, preferably 20 wt% or less.

[0016] The average molecular weight of PEI in the chemical solution is from 100 to 1800. Hereinafter, the weight average molecular weight of PEI is also referred to as "PEI molecular weight". In the chemical solution, the concentration of polyethyleneimine is within the range of 0.15 wt% to 0.5 wt%, and the PEI molecular weight is from 100 to 600, or the concentration of polyethyleneimine is within the range of 0.3 wt% to 0.5 wt%, and the PEI molecular weight is from 100 to 1800, which is preferable. Also, in the chemical solution, it is more preferable that the concentration of polyethyleneimine is within the range of 0.3 wt% to 0.5 wt%, and the PEI molecular weight is from 100 to 600.

[0017] The polyethyleneimine contained in the chemical solution according to this embodiment includes, for example, monomer units with ethyleneimine as a repeating unit. The polyethyleneimine may be a polymer consisting only of the above monomer units, a copolymer containing other monomers, or a mixture thereof. In polyethyleneimine, the proportion of the portion composed of monomer units with ethyleneimine as a repeating unit is preferably 95 mol% or more, and more preferably 100 mol%. That is, the polyethyleneimine included as an additive in the chemical solution is most preferably a polymer consisting only of monomer units with ethyleneimine as a repeating unit.

[0018] Whether or not polyethyleneimine is present in a chemical solution can be determined by analysis using infrared spectroscopy (FT-IR) and nuclear magnetic resonance (NMR). Furthermore, the weight-average molecular weight of polyethyleneimine in the chemical solution can be determined by gel permeation chromatography (GPC).

[0019] [2] Configuration of semiconductor device 1 [2-1] Overall configuration of semiconductor device 1 Figure 1 is a block diagram showing an example of the overall configuration of a semiconductor device 1 according to an embodiment. The semiconductor device 1 is a NAND flash memory capable of storing data non-volatilely and is controlled by an external memory controller 2. As shown in Figure 1, the semiconductor device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0020] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cells capable of storing data non-volatilely, and is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0021] The command register 11 holds the command CMD received by the semiconductor device 1 from the memory controller 2. The command CMD includes instructions that cause the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0022] The address register 12 holds the address information ADD received by the semiconductor device 1 from the memory controller 2. The address information ADD includes, for example, the block address BAd, the page address PAD, and the column address CAD. For example, the block address BAd, the page address PAD, and the column address CAD are used for selecting the block BLK, word lines, and bit lines, respectively.

[0023] The sequencer 13 controls the operation of the entire semiconductor device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD held in the command register 11, to perform read operations, write operations, erase operations, etc.

[0024] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PAd held in the address register 12.

[0025] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address Bad held in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0026] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller 2 as read data DAT.

[0027] The semiconductor device 1 and the memory controller 2 may be combined to form a single semiconductor device. For example, an SD card could be one such semiconductor device. TM Examples include memory cards and SSDs (solid state drives).

[0028] [2-2] Circuit configuration of the memory cell array 10 Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array 10 provided in the semiconductor device 1 according to this embodiment. Figure 2 shows one of several block BLKs included in the memory cell array 10. As shown in Figure 2, the block BLK includes, for example, five string units SU0 to SU4.

[0029] Each string unit SU contains multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, as well as selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer to hold data non-volatile. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0030] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL.

[0031] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of multiple selection transistors ST1 in string unit SU0 are connected to selection gate line SGD0. The gates of multiple selection transistors ST1 in string unit SU1 are connected to selection gate line SGD1. The gates of multiple selection transistors ST1 in string unit SU2 are connected to selection gate line SGD2. The gates of multiple selection transistors ST1 in string unit SU3 are connected to selection gate line SGD3. The gates of multiple selection transistors ST1 in string unit SU4 are connected to selection gate line SGD4. The gates of multiple selection transistors ST2 are connected to selection gate line SGS.

[0032] Bit lines BL0 to BLm are each assigned a different column address. Each bit line BL is shared among multiple block BLKs by a NAND string NS that is assigned the same column address. Word lines WL0 to WL7 are provided for each block BLK. Source lines SL are shared, for example, among multiple block BLKs.

[0033] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0034] The circuit configuration of the memory cell array 10 provided in the semiconductor device 1 according to this embodiment may be any other circuit configuration. For example, the number of string units SU included in each block BLK, and the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to any number.

[0035] [2-3] Structure of memory cell array 10 An example of the structure of the memory cell array 10 provided in the semiconductor device 1 according to this embodiment is described below. In the drawings referenced below, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the perpendicular direction to the surface of the semiconductor substrate 20 used to form the semiconductor device 1. Hatching in the plan view is added to make the drawing easier to read and is not necessarily related to the material or characteristics of the components to which the hatching is added. In the cross-sectional view, the illustration of the components is omitted as appropriate to make the drawing easier to read. Also, the components shown in each drawing are simplified as appropriate.

[0036] (Planar layout of memory cell array 10) Figure 3 is a plan view showing an example of the planar layout of a memory cell array 10 provided in a semiconductor device 1 according to an embodiment. Figure 3 shows the regions corresponding to the four blocks BLK0 to BLK3 included in the memory cell array 10. As shown in Figure 3, the planar layout of the memory cell array 10 is divided, for example, in the X direction into a memory region MA and extraction regions HA1 and HA2. The memory cell array 10 also includes, for example, a plurality of slits SLT and a plurality of slits SHE.

[0037] The memory area MA contains multiple NAND strings NS. The memory area MA is sandwiched in the X direction by lead areas HA1 and HA2. Each of the lead areas HA1 and HA2 is used for connections between the stacked wiring (word lines WL and selected gate lines SGD and SGS) and the row decoder module 15. For example, each of the lead areas HA1 and HA2 includes portions (terrace portions) of the selected gate line SGS, word lines WL0 to WL7, and selected gate line SGD that do not overlap with the upper wiring layer (conductor layer). Multiple contacts are provided on the respective terrace portions of the selected gate line SGS, word lines WL0 to WL7, and selected gate lines SGD0 to SGD4 within each block BLK. Contacts for the stacked wiring are provided in lead area HA1 in even-numbered block BLKs, for example, and in lead area HA2 in odd-numbered block BLKs.

[0038] Multiple slit SLTs each have a portion extending along the X direction and are aligned in the Y direction. Each slit SLT crosses the memory area MA and the lead areas HA1 and HA2 in the X direction. Each slit SLT also has a structure in which, for example, an insulator or plate-shaped contact is embedded. Each slit SLT separates adjacent wiring (for example, word lines WL0 to WL7, and selection gate lines SGD and SGS) through it. The aspect ratio of the slit SLTs is, for example, 30 or more.

[0039] Each of the multiple slits SHE has a portion extending along the X direction and is arranged in the Y direction. In this example, four slits SHE are positioned between adjacent slits SLT. Each slit SHE crosses the memory area MA in the X direction, with one end of each slit SHE included in the lead-out area HA1 and the other end included in the lead-out area HA2. Each slit SHE also has a structure in which an insulator is embedded, for example. Each slit SHE separates adjacent wiring (at least the selected gate line SGD) through it.

[0040] In the planar layout of the memory cell array 10 described above, each region separated by the slit SLT corresponds to one block BLK. Furthermore, each region separated by the slit SLT and SHE corresponds to one string unit SU. The memory cell array 10 is arranged in a repeating manner in the Y direction, for example, as shown in Figure 3.

[0041] The planar layout of the memory cell array 10 in the semiconductor device 1 according to this embodiment may be any other layout. For example, the number of slits SHE arranged between adjacent slits SLT can be designed to be any number. The number of string units SU formed between adjacent slits SLT can be changed based on the number of slits SHE arranged between adjacent slits SLT.

[0042] (Planar layout of the memory area MA of the memory cell array 10) Figure 4 is a plan view showing an example of a detailed planar layout in the memory region MA of the memory cell array 10 of the semiconductor device 1 according to the embodiment. Figure 4 shows a region containing one block BLK (i.e., string units SU0 to SU4). As shown in Figure 4, the memory cell array 10 includes multiple memory pillars MP, multiple contacts CV, and multiple bit lines BL in the memory region MA. Each slit SLT also includes contacts LI and spacers SP.

[0043] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 24 rows, in the region between two adjacent slits SLT. Then, for example, counting from the top of the paper, one slit SHE overlaps each of the 5th, 10th, 15th, and 20th memory pillar MPs.

[0044] Multiple bit lines BL each have a portion extending in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are positioned to overlap with one memory pillar MP. One of the multiple bit lines BL overlapping with the memory pillar MP is electrically connected to that memory pillar MP via a contact CV.

[0045] For example, the contact CV between a memory pillar MP in contact with a slit SHE and a bit line BL is omitted. In other words, the contact CV between a memory pillar MP in contact with two different selected gate lines SGD and a bit line BL is omitted. The number and arrangement of memory pillars MP and slit SHE between adjacent slits SLT may be in other configurations and can be changed as appropriate. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0046] Contact LI is a conductor having a portion extending in the X direction. Spacer SP is an insulator provided on the side surface of Contact LI. Contact LI is sandwiched between spacer SP. Contact LI and conductors adjacent to it in the Y direction (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) are separated and insulated by spacer SP.

[0047] (Cross-sectional structure of the memory region MA of the memory cell array 10) Figure 5 is a cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure in the memory region MA of the memory cell array 10 provided in the semiconductor device 1 according to the embodiment. As shown in Figure 5, the memory cell array 10 further includes, for example, a semiconductor substrate 20, conductive layers 21-25, and insulating layers 30-34.

[0048] Specifically, an insulating layer 30 is provided on the semiconductor substrate 20. Although not shown in the diagram, the insulating layer 30 includes circuits corresponding to, for example, a low decoder module 15 and a sense amplifier module 16.

[0049] A conductive layer 21 is provided on the insulating layer 30. The conductive layer 21 is formed, for example, in the shape of a plate extending along the XY plane and is used as a source wire SL. The conductive layer 21 contains, for example, phosphorus-doped silicon.

[0050] An insulating layer 31 is provided on the conductive layer 21. A conductive layer 22 is provided on the insulating layer 31. The conductive layer 22 is formed, for example, in the shape of a plate extending along the XY plane and is used as a selectable gate wire SGS. The conductive layer 22 contains, for example, molybdenum. The conductive layer 22 contains, for example, 99 atom% or more of pure molybdenum.

[0051] An insulating layer 32 and a conductive layer 23 are alternately stacked on a conductive layer 22. The conductive layer 23 is formed in a plate shape that extends along the XY plane, for example. The stacked conductive layers 23 are used as word lines WL0 to WL7, in order from the semiconductor substrate 20 side. The conductive layer 23 contains molybdenum. The conductive layer 23 contains, for example, 99 atom% or more of pure molybdenum.

[0052] An insulating layer 33 is provided on the uppermost conductive layer 23. A conductive layer 24 is provided on the insulating layer 33. The conductive layer 24 is formed, for example, in the shape of a plate extending along the XY plane and is used as a selectable gate wire SGD. The conductive layer 24 contains, for example, molybdenum. The conductive layer 24 contains, for example, 99 atom% or more of pure molybdenum.

[0053] An insulating layer 34 is provided on the conductive layer 24. A conductive layer 25 is provided on the insulating layer 34. The conductive layer 25 is formed in a line shape, for example, extending in the Y direction, and is used as a bit line BL. In other words, in a region not shown, multiple conductive layers 25 are arranged along the X direction. The conductive layer 25 contains, for example, copper.

[0054] Each memory pillar MP extends along the Z direction and penetrates the insulating layers 31-33 and the conductive layers 22-24. The bottom of each memory pillar MP is in contact with the conductive layer 21. The portion where the memory pillar MP intersects with the conductive layer 22 functions as a selection transistor ST2. The portion where the memory pillar MP intersects with one conductive layer 23 functions as one memory cell transistor MT. The portion where the memory pillar MP intersects with the conductive layer 24 functions as a selection transistor ST1.

[0055] Each memory pillar MP also includes, for example, a core member 40, a semiconductor layer 41, and a laminated film 42. The core member 40 is provided extending along the Z direction. For example, the upper end of the core member 40 is included in the layer above the conductive layer 24, and the lower end of the core member 40 reaches the conductive layer 21. The semiconductor layer 41 covers the periphery of the core member 40. At the bottom of the memory pillar MP, a portion of the semiconductor layer 41 is in contact with the conductive layer 21. The laminated film 42 covers the sides and bottom of the semiconductor layer 41, except for the portion where the semiconductor layer 41 and the conductive layer 21 are in contact. The core member 40 is made of an insulating material such as silicon oxide. The semiconductor layer 41 contains, for example, silicon.

[0056] A columnar contact CV is provided on the semiconductor layer 41 within the memory pillar MP. In the illustrated region, two contact CVs corresponding to two of the six memory pillar MPs are shown. In the memory region MA, contact CVs are connected in an area not shown to memory pillar MPs that do not overlap with the slit SHE and to which no contact CVs are connected.

[0057] One conductive layer 25, i.e., one bit line BL, is in contact with contact CV. One contact CV is connected to each of the spaces separated by slits SLT and SHE in one conductive layer 25. In other words, each conductive layer 25 is electrically connected to a memory pillar MP located between adjacent slits SLT and SHE, and to a memory pillar MP located between two adjacent slits SHE.

[0058] The slit SLT has a portion provided, for example, along the XZ plane, and divides the conductive layers 22-24. The contact LI within the slit SLT is provided along the slit SLT. A portion of the upper end of the contact LI is in contact with the insulating layer 34. The lower end of the contact LI is in contact with the conductive layer 21. The contact LI is used, for example, as part of the source wire SL. At least a spacer SP is provided between the contact LI and the conductive layers 22-24. The contact LI and the conductive layers 22-24 are separated and insulated by the spacer SP.

[0059] The slit SHE has a portion that is provided along the XZ plane, for example, and divides at least the conductive layer 24. The upper end of the slit SHE is in contact with the insulating layer 34. The lower end of the slit SHE is in contact with the insulating layer 33. The slit SHE contains an insulator, for example, silicon oxide. The upper end of the slit SHE and the upper end of the slit SLT may or may not be aligned. Also, the upper end of the slit SHE and the upper end of the memory pillar MP may or may not be aligned.

[0060] (Detailed cross-sectional structure of the memory region MA of the memory cell array 10) Figure 6 is an enlarged view of region VI in Figure 5, showing an example of a detailed cross-sectional structure in the memory region MA of the memory cell array 10 provided in the semiconductor device 1 according to the embodiment. Specifically, Figure 6 shows the respective structures of the conductor layer 23 and the memory pillar MP at the point where the conductor layer 23 intersects with the memory pillar MP. As shown in Figure 6, the laminated film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a cover insulating film 45. The conductor layer 23 includes, for example, a conductor 50 and a barrier metal 51. The memory cell array 10 further includes a block insulating film 46.

[0061] The tunnel insulating film 43 is provided on the side surface of the semiconductor layer 41. The insulating film 44 is provided on the side surface of the tunnel insulating film 43. The cover insulating film 45 is provided on the side surface of the insulating film 44. The cover insulating film 45 is divided by a block insulating film 46 at the point where the memory pillar MP and the conductive layer 23 intersect. The block insulating film 46 is provided between the conductive layer 23 and the insulator layer 32, and between the conductive layer 23 and the insulating film 44. The conductor 50 is embedded in a space enclosed on three sides by the block insulating film 46. The conductor 50 and the block insulating film 46 are separated by a barrier metal 51.

[0062] As the tunnel insulating film 43, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride film are used. The cover insulating film 45 contains, for example, silicon oxide. The insulating film 44 contains, for example, silicon nitride. The block insulating film 46 contains, for example, aluminum oxide (Al2O3). The block insulating film 46 is also used as a seed layer for forming the conductor 50. The conductor 50 contains molybdenum (Mo). The conductor 50 may contain impurities. Examples of impurities that may be contained in the conductor 50 include oxygen (O) and hydrogen (H). The barrier metal 51 contains, for example, titanium nitride (TiN).

[0063] The barrier metal 51 may be omitted. The block insulating film 46 may be provided on the side portion of the memory pillar MP instead of the cover insulating film 45. The structure of the conductive layer 22 and the memory pillar MP at the point where the conductive layer 22 and the memory pillar MP intersect, and the structure of the conductive layer 24 and the memory pillar MP at the point where the conductive layer 24 and the memory pillar MP intersect, are the same as the structure of the conductive layer 23 and the memory pillar MP at the point where the conductive layer 23 and the memory pillar MP intersect.

[0064] (Cross-sectional structure of memory pillar MP) Figure 7 is a cross-sectional view along the line VII-VII in Figure 5, showing an example of the cross-sectional structure of a memory pillar MP in a semiconductor device 1 according to an embodiment. Specifically, Figure 7 shows the cross-sectional structure of the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 23. As shown in Figure 7, in the cross-section including the conductive layer 23, the core member 40 is provided in the center of the memory pillar MP. The semiconductor layer 41 surrounds the side surface of the core member 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 46 surrounds the side surface of the insulating film 44. The barrier metal 51 surrounds the side surface of the block insulating film 46. The conductive layer 23 surrounds the side surface of the barrier metal 51.

[0065] The structure of the conductive layer 22 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 22, and the structure of the conductive layer 24 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 24, are the same as the structure of the conductive layer 23 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 23. In each of the memory pillar MPs described above, the semiconductor layer 41 is used as a channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The semiconductor device 1 can conduct current through the memory pillar MP between the bit line BL and the contact LI by turning on the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2.

[0066] [3] Method for manufacturing semiconductor device 1 Figure 8 is a flowchart showing an example of a method for manufacturing the semiconductor device 1 according to the embodiment. Figures 9 to 16 are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the semiconductor device 1 according to the embodiment, and each shows the same region as Figure 5. Below, an example of a manufacturing process for forming the stacked wiring of the memory cell array 10 in the semiconductor device 1 according to the embodiment will be described with appropriate reference to Figure 8. As shown in Figure 8, the method for manufacturing the semiconductor device 1 according to the embodiment involves sequentially executing the processes of steps S10 to S17, for example.

[0067] In step S10, as shown in Figure 9, sacrificial members and insulating layers are alternately stacked. Briefly, an insulating layer 30 including a circuit (not shown) corresponding to a low decoder module 15, etc., is formed on the semiconductor substrate 20. A conductive layer 21 is formed on the insulating layer 30. An insulating layer 31 and a sacrificial member 60 are formed sequentially on the conductive layer 21. Sacrificial members 61 and insulating layers 32 are alternately formed on the sacrificial member 60. An insulating layer 33 and a sacrificial member 62 are formed sequentially on the uppermost sacrificial member 61. An insulating layer 35 is formed on the sacrificial member 62. Sacrificial member 60 is associated with the selected gate line SGS. Sacrificial member 61 is associated with the word line WL. Sacrificial member 62 is associated with the selected gate line SGD. Each of the sacrificial members 60, 61, and 62 is, for example, silicon nitride.

[0068] In step S11, memory holes MH are formed as shown in Figure 10. Specifically, a mask is formed with openings in areas corresponding to multiple memory pillars MP. Then, multiple memory holes MH are formed by anisotropic etching using this mask. The memory holes MH penetrate the insulating layers 31, 32, 33 and 35, as well as the sacrificial members 60, 61 and 62. The bottom of the memory holes MH reaches the conductive layer 21.

[0069] In step S12, memory pillars MP are formed as shown in Figure 11. Specifically, a cover insulating film 45, an insulating film 44, and a tunnel insulating film 43 are sequentially formed on the sides and bottom surfaces of multiple memory holes MH. Then, a portion of the cover insulating film 45, insulating film 44, and tunnel insulating film 43 provided at the bottom of the memory hole MH is removed, and a semiconductor layer 41 and a core member 40 are formed inside the memory hole MH. Next, a portion of the core member 40 provided at the top of the memory hole is removed, and a semiconductor layer 41 is formed in the portion of the core member 40 from which the core member 40 was removed. This forms the structure of multiple memory pillars MP. Subsequently, an insulating layer 36 is formed on the insulating layer 35 and the multiple memory pillars MP. The insulating layer 36 protects the top of the memory pillars MP. The insulating layers 35 and 36 are included in the insulating layer 34 shown in Figure 5.

[0070] In step S13, a slit SLT is formed as shown in Figure 12. Specifically, a mask is formed by photolithography or the like, with an opening in the region corresponding to the slit SLT. Then, anisotropic etching using this mask forms slit SLTs that separate the insulating layers 31, 32, 33, 35, and 36, and the sacrificial members 60, 61, and 62, respectively. The bottom of the slit SLT reaches, for example, the conductive layer 21. After the formation of the slit SLT, a process may be performed to form a protective film on the conductive layer 21 exposed at the bottom of the slit SLT.

[0071] In step S14, as shown in Figure 13, the sacrificial members 60, 61, and 62 are removed. Specifically, in step S14, a wet etching process using hot phosphoric acid or the like is performed. More specifically, the sacrificial members 60, 61, and 62 are selectively removed by supplying hot phosphoric acid or the like through the slit SLT. Although not shown in the figure, the cover insulating film 45 that was provided on the part of each memory pillar MP that was in contact with any of the sacrificial members 60, 61, and 62 is also removed. The structure from which the sacrificial members 60, 61, and 62 have been removed is supported by a plurality of memory pillars MP, etc.

[0072] In step S15, the conductor 50 is formed as shown in Figure 14. Specifically, although not shown in the figure, the block insulating film 46 and the barrier metal 51 are formed in sequence. For the formation of the block insulating film 46, for example, the thermal CVD (Chemical Vapor Deposition) method or the ALD (Atomic Layer Deposition) method is used. Then, the conductor 50 (molybdenum) is embedded in the space where the sacrificial members 60-62 have been removed. For the formation of the molybdenum, for example, the thermal CVD (Chemical Vapor Deposition) method or the ALD (Atomic Layer Deposition) method is used. Note that the block insulating film 46, the barrier metal 51, and the conductor 50 are also formed on the side portions of the slit SLT and on the upper surface portion of the insulating layer 36. At this point, the conductor 50 formed in the space where the sacrificial members 60-62 have been removed is continuously provided and electrically connected.

[0073] In step S16, as shown in Figure 15, an etching process is performed on the conductor 50 (molybdenum). Specifically, a wet etching process is performed using the chemical solution according to the embodiment. In step S16, the conductor 50 formed on the side surface of the slit SLT and the conductor 50 formed on the upper surface of the insulating layer 36 are removed. In step S16, the chemical solution that comes into contact with the conductor 50 through the slit SLT etches the molybdenum at a substantially constant rate, regardless of the height within the slit SLT. In addition, in step S16, it is sufficient that the conductor 50 formed on adjacent wiring layers is separated. As a result, a conductor layer 22 that functions as a selectable gate line SGS, a plurality of conductor layers 23 that function as word lines WL0 to WL7, and a conductor layer 24 that functions as a selectable gate line SGD are formed. Hereinafter, the process in step S16 will be referred to as the "recess process of the multilayer wiring". Furthermore, in the following, the amount of conductor 50 removed on the upper side of the slit SLT (for example, (1) shown in Figure 15) will be referred to as the "top recess amount," and the amount of conductor 50 removed on the lower side of the slit SLT (for example, (2) shown in Figure 15) will be referred to as the "bottom recess amount."

[0074] In step S17, as shown in Figure 16, the slit SLT is filled. Specifically, first, an insulating film (spacer SP) is formed to cover the sides and bottom of the slit SLT. Then, a portion of the spacer SP provided at the bottom of the slit SLT is removed, and a portion of the conductive layer 21 is exposed at the bottom of the slit SLT. Next, a conductor (contact LI) is formed inside the slit SLT, and the conductor formed outside the slit SLT is removed, for example, by CMP (Chemical Mechanical Polishing). After that, multiple grooves parallel to the slit SLT are formed between adjacent slit SLTs in the Y direction, and insulating film is embedded in each groove, thereby forming a slit SHE that divides the conductive layer 24 in the Y direction.

[0075] The manufacturing process of the semiconductor device 1 according to the embodiment described above forms the stacked wiring structure within the memory cell array 10. The series of processes in steps S13 to S17 may be called the “replacement process”. Note that the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between each manufacturing process, or some processes may be omitted or integrated. For example, a process in which a stepped structure of the stacked wiring is formed may be inserted between steps S10 and S11.

[0076] [4] Effects of the embodiment In the semiconductor device manufacturing method according to this embodiment, the use of a chemical solution containing polyethyleneimine in the recess processing of the stacked wiring suppresses the top / bottom difference in the recess amount, thereby improving the yield of the semiconductor device 1. The details of this effect will be explained below.

[0077] A semiconductor device in which memory cells are stacked in three dimensions has, for example, a stacked wiring structure in which conductive layers and insulating layers are stacked alternately. For example, a replacement process using sacrificial members is used to form the stacked wiring. The replacement process is a process in which, after the sacrificial members and insulating layers are stacked alternately, the sacrificial members are replaced with conductors. Briefly speaking, a slit SLT is formed that separates the stacked structure of sacrificial members and insulating layers, and the sacrificial members are selectively removed through the slit SLT. Then, a conductor is embedded in the space where the sacrificial members were removed through the slit SLT. Subsequently, the conductors provided on the sides of the slit SLT are separated for each stacked wiring by an etching process (recess process).

[0078] Tungsten (W) is known as a conductor used in multilayer wiring. However, when tungsten is used in multilayer wiring, device defects can occur due to the generation of fluorine gas during tungsten formation and the resulting warping of the wafer. Therefore, the use of molybdenum as a conductor for multilayer wiring is being considered. Since fluorine gas is not generated during molybdenum formation, as is the case with tungsten, the occurrence of device defects caused by degassing during multilayer wiring formation is suppressed. Furthermore, since molybdenum has lower wiring resistance than tungsten, the use of molybdenum in multilayer wiring can contribute to improving the performance of semiconductor devices.

[0079] As an etching solution for molybdenum (hereinafter referred to as Mo etching solution), a mixed acid containing phosphoric acid, nitric acid, acetic acid, and water is known. However, when a mixed acid is used for etching, the etching rate of molybdenum is fast, which can lead to variations in the amount of molybdenum etched. For example, in the recess treatment of the embodiment, there may be a difference between the recess amount on the top side of the slit SLT and the recess amount on the bottom side of the slit SLT. Such a top / bottom difference in recess amount becomes more pronounced when the aspect ratio of the slit SLT is high (e.g., 30 or more). A large top / bottom difference in recess amount can cause device defects. Furthermore, even if the mixed acid has the same components, if the composition ratio is different, molybdenum etching may not proceed at all.

[0080] Therefore, the chemical solution according to the embodiment has a composition in which polyethyleneimine (PEI) is added to a mixed acid containing an inorganic acid, an oxidizing agent, a carboxylic acid, and water. The chemical solution according to the embodiment has a PEI molecular weight of, for example, 100 to 1800, and the additive concentration is adjusted to within the range of 0.05 wt% to 10 wt%. Etching using the chemical solution according to the embodiment proceeds while protecting the molybdenum surface with the added PEI. As a result, the etching rate of molybdenum with the chemical solution according to the embodiment is suppressed compared to a mixed acid without PEI.

[0081] As a result, the semiconductor device manufacturing method according to the embodiment can suppress the occurrence of top / bottom differences in the recess processing of the multilayer wiring. In other words, the chemical solution according to the embodiment can suppress the top / bottom difference in the recess amount and separate molybdenum for each wiring layer without generating excessively etched portions. Therefore, by using the chemical solution according to the embodiment in the manufacturing process of the semiconductor device 1 (for example, step S16), the yield of the semiconductor device 1 can be improved.

[0082] [5] Others The semiconductor device 1 according to the embodiment described above can be modified in various ways.

[0083] The structure of the memory cell array 10 in the semiconductor device 1 according to this embodiment may be any other structure. For example, the memory pillar MP may have a structure in which two or more pillars are connected in the Z direction. The memory pillar MP may have a structure in which a pillar corresponding to a selection gate line SGD and a pillar corresponding to a word line WL are connected. The memory pillar MP and the bit line BL may be connected by a plurality of contacts connected in the Z direction. A conductive layer may be inserted in the connection portion of the plurality of contacts. The semiconductor layer 41 in the memory pillar MP and the source line SL may be connected via the side surface of the memory pillar MP.

[0084] The drawings used to illustrate the embodiments illustrate a case where the memory pillar MP has the same diameter in the Z direction, but the invention is not limited to this. For example, the memory pillar MP may have a tapered shape or an inverse tapered shape, or it may have a shape with a bulge in the middle (boeing shape). Similarly, the slits SLT and SHE may each have a tapered shape or an inverse tapered shape, or they may have a boeing shape. Furthermore, the cross-sectional structure of the memory pillar MP is not limited to a circle, but may be elliptical or designed to be any shape.

[0085] In embodiments, the interiors of the slit SLT and SHE may be composed of one or more types of insulators. In this case, for example, a contact for the source wire SL (conductor layer 21) is provided in the lead-out region HA. In this specification, the location of the slit SLT may be determined, for example, based on the location of the contact LI. If the slit SLT is composed of an insulator, the location of the slit SLT may be determined by the seam within the slit SLT or by the material remaining in the slit SLT during the replacement process.

[0086] In the embodiment, a case in which a circuit such as a sense amplifier module 16 is provided below the memory cell array 10 has been described, but the invention is not limited to this. For example, the semiconductor device 1 may have a structure in which stacked wiring such as word lines WL is formed on a semiconductor substrate 20, or it may have a structure in which a chip on which the sense amplifier module 16 is provided and a chip on which the memory cell array 10 is provided are bonded together. When the semiconductor device 1 has a chip bonding structure, the configuration corresponding to the semiconductor substrate 20 may be omitted.

[0087] In this specification, “connection” means that they are electrically connected, and does not exclude, for example, the interposition of another element. “Electrically connected” may be via an insulator, as long as it is possible to operate in the same way as if they were electrically connected. “Columnar” means that it is a structure provided within a hole formed in the manufacturing process of the semiconductor device 1. “Same layer structure” means that at least the order in which the layers are formed is the same. “Region” may be considered as a configuration included by the semiconductor substrate 20. For example, if the semiconductor substrate 20 is defined to include a memory region MA and an extraction region HA, then the memory region MA and the extraction region HA are associated with different regions above the semiconductor substrate 20, respectively. “Height” corresponds to, for example, the distance in the Z direction between the configuration under measurement and the semiconductor substrate 20. A configuration other than the semiconductor substrate 20 may be used as the criterion for “height”. “Molybdenum” means metallic molybdenum and includes molybdenum alone.

[0088] In this embodiment, a chemical solution containing polyethyleneimine was shown to be used in the manufacture of a three-dimensional semiconductor device, but the embodiment is not limited to this. The chemical solution according to this embodiment may be used in the manufacture of other semiconductor devices. For example, the chemical solution according to this embodiment may be used to etch a molybdenum-containing layer in a transistor such as a Thin Film Transistor (TFTT).

[0089] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Examples]

[0090] Examples are described below. However, the present invention is not limited to the examples described below. Hereinafter, the process of selectively etching molybdenum will be referred to as "Mo etching."

[0091] [Evaluation of top / bottom difference in Mo etching process] (Preparation of drug solution) The chemical solution according to this embodiment is prepared by mixing phosphoric acid, nitric acid, acetic acid, and PEI aqueous solution in this order. The temperature during preparation of the chemical solution is, for example, room temperature (around 23-24°C). No heating is required for any of the phosphoric acid, nitric acid, acetic acid, and PEI aqueous solution. The time required for preparation of the chemical solution is about 10-20 minutes from the start to the completion of preparation. The PEI aqueous solution is prepared before the preparation of the chemical solution. The PEI aqueous solution is prepared by adding PEI to water at room temperature. Ten types of chemical solutions were used in the example. The PEI concentrations of the ten types of chemical solutions were 0.05 wt%, 0.15 wt%, 0.3 wt%, 0.5 wt%, 0.9 wt%, 1%, 1.5 wt%, 2 wt%, 2.78 wt%, and 3%, respectively.

[0092] (Sample preparation) In the shape evaluation of the Mo etching process in the embodiment, chips cut from three different test lots, LN1, LN2, and LN3, were used. Note that the designs of the three test lots, LN1, LN2, and LN3, are different. Specifically, the number of sacrificial members and insulating layers differs among the wafers of each test lot, LN1, LN2, and LN3. However, in each wafer of test lots LN1, LN2, and LN3, the multiple slits (SLTs) formed on the structure including the sacrificial member and insulating layer stacking structure have a high aspect ratio (>30). Therefore, it is possible to similarly verify the top recess amount and bottom recess amount between chips cut from the wafer of test lot LN1, LN2, and LN3.

[0093] (Evaluation results) In the shape evaluation of the Mo etching process in the embodiment, a cross-sectional image of the memory cell array 10, including the slit SLT, was first acquired for each chip. A Scanning Electron Microscope (SEM) was used to acquire the cross-sectional image of the memory cell array 10. From the acquired cross-sectional image of the memory cell array 10, the top / bottom difference of molybdenum in the side portion of the slit SLT was confirmed. The evaluation results of the top / bottom difference of the Mo etching process are described below with reference to Figures 17 and 18.

[0094] Figure 17 is a schematic diagram showing an example of the cross-sectional structure of the memory cell array 10 after Mo etching in the embodiment. Figure 17(1) shows an example of the cross-sectional structure of the memory cell array 10 when the top / bottom difference is large. Figure 17(2) shows an example of the cross-sectional structure of the memory cell array 10 when the top / bottom difference is small. Hereinafter, the three conductor layers 50 shown in Figure 17 will be referred to as 50A, 50B, and 50C, in order from the layer closest to the top.

[0095] In the example shown in Figure 17(1), the amount of recess due to etching is greater for conductor 50B than for conductor 50C, and greater for conductor A than for conductor 50B. Thus, a large difference in the amount of recess between the top (e.g., conductor 50A) and the bottom (e.g., conductor 50C) corresponds to a large top / bottom difference. In the example, when a shape close to the shape shown in Figure 17(1) was confirmed, the shape evaluation result for that sample was considered "unacceptable," meaning that a top / bottom difference had occurred.

[0096] In the example shown in Figure 17(2), the amount of recess due to etching is approximately equal for each of the conductors 50A, 50B, and 50C. Thus, the difference in recess amount between the top (e.g., conductor 50A) and the bottom (e.g., conductor 50C) is small, which corresponds to a small top / bottom difference. In the example, when a shape close to the shape shown in Figure 17(2) was confirmed, the shape evaluation result for that sample was considered "acceptable," meaning that no top / bottom difference occurred.

[0097] Figure 18 is a table showing the shape evaluation results of the Mo etching treatment in the example, and shows the shape evaluation results based on the lot number, additive concentration, and PEI molecular weight combination. The evaluation results shown in Figure 18 were determined based on the evaluation criteria explained using Figure 17. The “x / y” shown in Figure 18 correspond to the evaluation results. “x” indicates the number of slit SLTs in the cross-sectional image of the sample in which a top / bottom difference occurred. “y” indicates the total number of slit SLTs in the cross-sectional image of the sample in which a top / bottom difference occurred.

[0098] The cross-sectional evaluation result for sample number SN1 with an additive concentration of 0.05 wt% and a PEI molecular weight of 600 was 5 / 5. The cross-sectional evaluation result for sample number SN1 with an additive concentration of 0.05 wt% and a PEI molecular weight of 1800 was also 5 / 5.

[0099] The cross-sectional evaluation result for sample number SN1 with an additive concentration of 0.15 wt% and a PEI molecular weight of 600 was 1 / 5. The cross-sectional evaluation result for sample number SN1 with an additive concentration of 0.15 wt% and a PEI molecular weight of 1800 was 5 / 5.

[0100] The cross-sectional evaluation result for sample number SN1 with an additive concentration of 0.3 wt% and a PEI molecular weight of 600 was 0 / 5. The cross-sectional evaluation result for sample number SN1 with an additive concentration of 0.3 wt% and a PEI molecular weight of 1800 was 1 / 5.

[0101] The cross-sectional evaluation result for sample number SN2 with an additive concentration of 0.3 wt% and a PEI molecular weight of 600 was 9 / 54. The cross-sectional evaluation result for sample number SN2 with an additive concentration of 0.3 wt% and a PEI molecular weight of 1800 was 4 / 18.

[0102] The cross-sectional evaluation results for the combination of sample number SN2, additive concentration of 0.5 wt%, and PEI molecular weight of 600 were 4 / 54. The cross-sectional evaluation results for the combination of sample number SN2, additive concentration of 0.5 wt%, and PEI molecular weight of 1800 were also 4 / 54. The cross-sectional evaluation results for the combination of sample number SN2, additive concentration of 0.5 wt%, and PEI molecular weight of 10000 were 54 / 54.

[0103] The cross-sectional evaluation result for the combination of sample number SN2, additive concentration of 0.9 wt%, and PEI molecular weight of 1800 was 3 / 54.

[0104] The cross-sectional evaluation result for the combination of sample number SN2, additive concentration of 1 wt%, and PEI molecular weight of 600 was 0 / 54.

[0105] The cross-sectional evaluation result for the combination of sample number SN2, additive concentration of 1.5 wt%, and PEI molecular weight of 1800 was 3 / 54.

[0106] The cross-sectional evaluation result for the combination of sample number SN2, additive concentration of 2%, and PEI molecular weight of 600 was 0 / 54.

[0107] The cross-sectional evaluation result for the combination of sample number SN2, additive concentration of 2.78 wt%, and PEI molecular weight of 10000 was 6 / 54.

[0108] The cross-sectional evaluation result for sample number SN2 with an additive concentration of 3 wt% and a PEI molecular weight of 600 was 0 / 54. The cross-sectional evaluation result for sample number SN2 with an additive concentration of 3 wt% and a PEI molecular weight of 1800 was 9 / 54.

[0109] Figure 19 is a schematic diagram showing the cross-sectional structure of the memory cell array after Mo etching in the comparative example. In the comparative example, Mo etching using metal mixed acid was performed on chips cut from wafers of test lot LN3, which is different from test lots LN1 and LN2. In Figure 19, "Mo" indicates a conductor containing molybdenum. "INS" indicates an insulating layer. "SUB" indicates a semiconductor substrate. In the comparative example, the insulating layer INS and sacrificial members are alternately stacked on the semiconductor substrate SUB. Then, after the slit SLT is formed, a replacement process is performed, and Mo etching is performed during this replacement process.

[0110] As shown in Figure 19, in the comparative example, there are areas on the top side where all the molybdenum has been removed (complete molybdenum removal), and areas on the bottom side where molybdenum (Mo remaining) remains on the side of the slit SLT. Thus, in the comparative example, the amount of recess on the top side and the amount of recess on the bottom side are significantly different. In other words, the top / bottom difference in the Mo etching process is large in the comparative example.

[0111] In contrast, as explained using Figures 17 and 18, in Mo etching treatment with added polyethyleneimine, the top / bottom difference is improved by using a chemical solution that combines a predetermined additive concentration and a predetermined PEI molecular weight. Specifically, when the additive concentration is 0.15 wt%, the top / bottom difference when the PEI molecular weight is 600 is better than when the PEI molecular weight is 1800. When the additive concentration is 0.3 wt%, the top / bottom difference when the PEI molecular weight is 600 is better than when the PEI molecular weight is 1800. When the additive concentration is 0.5 wt%, the top / bottom difference when the PEI molecular weight is 600 or 1800 is better than when the PEI molecular weight is 10000. When the PEI molecular weight is 600 and the additive concentration is 1 or higher, no slit SLT exhibiting a top / bottom difference was detected. Furthermore, no slit SLT exhibiting a top / bottom difference was detected when the additive concentration was 0.3 wt%, 1%, 2%, or 3 wt%, and the PEI molecular weight was 600.

[0112] Specifically, for the Mo etching solution, it is preferable that the additive concentration (polyethyleneimine concentration) is in the range of 0.05 wt% to 10 wt%. Furthermore, for the Mo etching solution, it is preferable that the PEI molecular weight (weight-average molecular weight of polyethyleneimine) is between 100 and 1800. Moreover, for the Mo etching solution, it is even more preferable that the additive concentration is in the range of 1 wt% to 3 wt% and the PEI molecular weight is between 100 and 600. The top / bottom difference in the etching process of molybdenum tends to improve as the PEI used as an additive has a low molecular weight and a high concentration. [Explanation of symbols]

[0113] 1...Semiconductor device, 2...Memory controller, 10...Memory cell array, 11...Command register, 12...Address register, 13...Programmable logic controller, 14...Driver module, 15...Raw decoder module, 16...Sense amplifier module, 20...Semiconductor substrate, 21-25...Conductive layer, 30-36...Insulating layer, 40...Core component, 41...Semiconductor layer, 42...Laminated film, 43...Tunnel insulating film, 44...Insulating film, 45...Cover insulating film, 46...Block insulating film, 50...Conductor, 51...Barrier metal, 60-62...Sacrificial component, MA...Memory area, HA...Draw-out area, BL...Bit line, WL...Word line, SGD, SGS...Selection gate line, BLK...Block, SU...String unit, NS...NAND string, MT...Memory cell transistor, ST1, ST2...Selection transistor

Claims

1. A chemical solution containing a mixed acid and polyethyleneimine, which is an organic amine, The mixed acid contains an inorganic acid, an oxidizing agent, a carboxylic acid, and water, The chemical solution has a concentration of the polyethyleneimine in the range of 0.05 wt % to 10 wt %.

2. Used for etching molybdenum-containing layers, The chemical solution according to claim 1.

3. the concentration of the inorganic acid is in the range of 40 wt % to 80 wt %; The concentration of the oxidizing agent is 5 wt % or less, the concentration of the carboxylic acid is in the range of 0.1 wt % to 45 wt %; The concentration of the water is 30 wt% or less. The drug solution according to claim 1 or 2.

4. The weight average molecular weight of the polyethyleneimine is 100 or more and 1800 or less. The chemical solution according to any one of claims 1 to 3.

5. The concentration of the polyethyleneimine is in the range of 1 wt % to 3 wt %, and the weight average molecular weight of the polyethyleneimine is 100 or more and 600 or less. The chemical solution according to any one of claims 1 to 4.

6. The inorganic acid is at least one selected from the group consisting of phosphoric acid and sulfuric acid. The chemical solution according to any one of claims 1 to 4.

7. The oxidizing agent is at least one selected from the group consisting of nitric acid and hydrogen peroxide. The chemical solution according to any one of claims 1 to 5.

8. The carboxylic acid is at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid, and citric acid. The chemical solution according to any one of claims 1 to 6.

9. 1. A method of etching a layer comprising molybdenum, comprising: The etching method uses a chemical solution for etching the molybdenum-containing layer, the chemical solution containing a mixed acid containing an inorganic acid, an oxidizing agent, a carboxylic acid, and water, and polyethyleneimine, which is an organic amine, and the concentration of the polyethyleneimine is in the range of 0.05 wt % to 10 wt %.

10. the concentration of the inorganic acid in the chemical solution is within a range of 40 wt % to 80 wt %; The concentration of the oxidizing agent in the chemical solution is 5 wt % or less, the concentration of the carboxylic acid in the chemical solution is within a range of 0.1 wt % to 45 wt %; The concentration of the water in the chemical solution is 30 wt % or less. The etching method according to claim 9.

11. The weight average molecular weight of the polyethyleneimine in the chemical solution is 100 or more and 1800 or less. The etching method according to claim 9 or 10.

12. the concentration of the polyethyleneimine in the chemical solution is within a range of 1 wt % to 3 wt %, and the weight average molecular weight of the polyethyleneimine is 100 or more and 600 or less; The etching method according to any one of claims 9 to 11.

13. The inorganic acid is at least one selected from the group consisting of phosphoric acid and sulfuric acid. The etching method according to any one of claims 9 to 12.

14. The oxidizing agent is at least one selected from the group consisting of nitric acid and hydrogen peroxide. The etching method according to any one of claims 9 to 13.

15. The carboxylic acid is at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid, and citric acid. The etching method according to any one of claims 9 to 14.

16. forming a structure of alternating sacrificial members and insulating layers; forming a slit that separates the structure; removing the sacrificial member from the structure through the slit; After removing the sacrificial member, forming a conductor to fill the space where the sacrificial member was removed; and etching the conductor provided in the slit after forming the conductor, the conductor includes molybdenum; In the method for manufacturing a semiconductor device, a chemical solution is used for the etching, the chemical solution including a mixed acid containing an inorganic acid, an oxidizing agent, a carboxylic acid, and water, and polyethyleneimine, which is an organic amine and has a concentration in the range of 0.05 wt % to 10 wt %.

17. the concentration of the inorganic acid in the chemical solution is within a range of 40 wt % to 80 wt %; The concentration of the oxidizing agent in the chemical solution is 5 wt % or less, the concentration of the carboxylic acid in the chemical solution is within a range of 0.1 wt % to 45 wt %; The concentration of the water in the chemical solution is 30 wt % or less. The method for manufacturing a semiconductor device according to claim 16.

18. The weight average molecular weight of the polyethyleneimine in the chemical solution is 100 or more and 1800 or less.

18. The method for manufacturing a semiconductor device according to claim 16 or 17.

19. the concentration of the polyethyleneimine in the chemical solution is within a range of 1 wt % to 3 wt %, and the weight average molecular weight of the polyethyleneimine is 100 or more and 600 or less; The method for manufacturing a semiconductor device according to any one of claims 16 to 18.

20. The inorganic acid is at least one selected from the group consisting of phosphoric acid and sulfuric acid.

20. The method for manufacturing a semiconductor device according to claim 16.

21. The oxidizing agent is at least one selected from the group consisting of nitric acid and hydrogen peroxide. The method for manufacturing a semiconductor device according to any one of claims 16 to 20.

22. The carboxylic acid is at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid, and citric acid. The method for manufacturing a semiconductor device according to any one of claims 16 to 21.

Images