Semiconductor device

Abstract

To improve performance of a semiconductor device, and to secure reliability of the semiconductor device.SOLUTION: A semiconductor device comprises a MOSFET 1Q and a cutoff function circuit for detecting an overcurrent flowing to the MOSFET 1Q and restricting the overcurrent. The cutoff function circuit comprises a MOSFET 2Q, a MOSFET 3Q, a resistance element 4Q, and a Schottky barrier diode 5Q. The Schottky barrier diode 5Q comprises gate wiring GW and a drain region ND3. The gate wiring GW is electrically connected to gate electrodes GE1 and GE2 and a drain region ND3. The source electrode SE is electrically connected to source regions NS1 and NS3, body regions PB1 and PB2, and the resistance element 4Q. The source region NS2 is electrically connected to the source region NS3 and the source electrode SE via the resistance element 4Q. The gate electrode GE3 is electrically connected to the source region NS2 by wiring 10.SELECTED DRAWING: Figure 4

Description

Technical Field

[0005] ,

[0004] , , , , ,

[0003]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a semiconductor substrate made of silicon carbide.

Background Art

[0002] 。 In a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), conventionally, a power MOSFET using a silicon (Si) substrate (Si power MOSFET) has been mainstream. However, the electric field strength against dielectric breakdown in silicon carbide (SiC) is approximately one order of magnitude greater than that in Si.

[0003] Therefore, in a power MOSFET using a SiC substrate (SiC power MOSFET), the thickness of the drift layer for maintaining the breakdown voltage can be made approximately 1 / 10 thinner and the impurity concentration of the drift layer can be made about 100 times higher than that in a Si power MOSFET. As a result, in a SiC power MOSFET, theoretically, the element resistance can be reduced by three orders of magnitude or more. Also, since SiC has a bandgap approximately three times larger than that of Si, a SiC power MOSFET can have a lower on-resistance at the same breakdown voltage and can also operate in a high-temperature environment. Therefore, SiC semiconductor devices are expected to have performance superior to Si semiconductor devices.

[0004] As an example of the use of a power MOSFET, two power MOSFETs connected in series are connected to a load, and the potential related to the load is adjusted by alternately switching the on-operation and off-operation of the two power MOSFETs. In one power MOSFET, current flows in the on-state but no voltage is applied, and no current flows but voltage is applied in the off-state. Here, when one power MOSFET is in the on-state, if the other power MOSFET becomes in the on-state due to a failure or malfunction, etc., a short-circuit state occurs in which both current and voltage are conducted to one power MOSFET.

[0005] When a short circuit occurs, the power MOSFET generates heat due to the large current and will be destroyed after a certain amount of time. In that case, the power MOSFET remains in a short-circuit state, which can cause malfunctions or fires in electrical equipment containing the power MOSFET. Therefore, electrical equipment is usually equipped with a protection circuit. This protection circuit protects the power MOSFET from short circuits before it is destroyed. However, it takes some time for the protection circuit to detect the short circuit and complete the interruption of the short circuit in the power MOSFET. During that time, the power MOSFET must withstand the short circuit.

[0006] For example, Patent Document 1 discloses a semiconductor device equipped with an overcurrent limiting circuit for detecting and limiting overcurrents flowing through a power MOSFET. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2003-332446 [Overview of the project] [Problems that the invention aims to solve]

[0008] To improve the performance of power MOSFETs, it is effective to create a low-loss device structure, such as by reducing on-resistance. On the other hand, promoting low loss makes it easier for large currents to flow during a short circuit, thus shortening the time the power MOSFET can withstand a short circuit (short-circuit withstand capability). For example, while Si power MOSFETs had a short-circuit withstand capability of about 10 μsec, SiC power MOSFETs can significantly reduce losses, sometimes resulting in a short-circuit withstand capability of about 2 μsec. In some cases, a device structure with increased losses is deliberately adopted to take such short-circuit withstand capability into consideration.

[0009] Even when an overcurrent limiting circuit, such as the one described in Patent Document 1, is provided to the power MOSFET, there is a problem in that the wiring inductance becomes large in the electrical path leading to the power MOSFET, or in the electrical path between each element constituting the overcurrent limiting circuit. This problem becomes even more pronounced, especially when these current paths are to be realized in a later process.

[0010] When the wiring inductance increases, noise can cause the power MOSFET to malfunction. While a low-pass filter can be used to reduce noise, integration takes time, for example, 3 μsec or more. In such cases, the short-circuit interruption speed of a SiC power MOSFET becomes insufficient.

[0011] Considering the above, if a circuit with a blocking function can be formed within a single semiconductor chip and wiring inductance can be minimized, a power MOSFET with low loss and a short short-circuit withstand capability can be provided. The main objective of this invention is to improve the performance of semiconductor devices (semiconductor chips) and ensure the reliability of semiconductor devices by developing such a SiC power MOSFET.

[0012] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0013] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0014] One embodiment of a semiconductor device includes an n-type semiconductor substrate made of silicon carbide having a front and a back surface, a source electrode, gate wiring and first wiring formed above the front surface of the semiconductor substrate, a p-type first body region formed on the semiconductor substrate on the front surface side, a p-type second body region formed on the semiconductor substrate on the front surface side, a drain electrode formed below the back surface of the semiconductor substrate, a first MOSFET, a second MOSFET, a third MOSFET, a Schottky barrier diode, and a resistive element. Here, the first MOSFET has an n-type first source region formed in the first body region, an n-type first drain region formed on the semiconductor substrate on the back surface of the semiconductor substrate and electrically connected to the drain electrode, and a first gate electrode formed on the front surface of the semiconductor substrate via a first gate insulating film. The second MOSFET has an n-type second source region formed in the second body region, the first drain region, and a second gate electrode formed on the front surface of the semiconductor substrate via a second gate insulating film. Furthermore, the third MOSFET has an n-type third source region formed in the second body region, an n-type third drain region formed in the second body region, and a third gate electrode formed on the surface of the semiconductor substrate via a third gate insulating film. The Schottky barrier diode is constructed by a Schottky junction between the conductive material included in the gate wiring and the third drain region. The gate wiring is electrically connected to the first gate electrode, the second gate electrode, and the third drain region, the source electrode is electrically connected to the first source region, the third source region, the first body region, the second body region, and the resistive element, the second source region is electrically connected to the third source region and the source electrode via the resistive element, and the third gate electrode is electrically connected to the second source region by the first wiring. Furthermore, the second MOSFET, the third MOSFET, the Schottky barrier diode, and the resistive element constitute a cutoff function circuit for detecting and limiting overcurrent flowing through the first MOSFET.

[0015] One embodiment of a semiconductor device includes an n-type semiconductor substrate made of silicon carbide having a front and a back surface, a source electrode, gate wiring and first wiring formed above the front surface of the semiconductor substrate, a p-type first body region formed on the semiconductor substrate on the front surface side, a p-type second body region formed on the semiconductor substrate on the front surface side, a drain electrode formed below the back surface of the semiconductor substrate, a first MOSFET, a third MOSFET, a JFET, a Schottky barrier diode and a resistive element. Here, the first MOSFET has an n-type first source region formed in the first body region, an n-type first drain region formed on the semiconductor substrate on the back surface of the semiconductor substrate and electrically connected to the drain electrode, and a first gate electrode formed on the front surface of the semiconductor substrate via a first gate insulating film. The third MOSFET has an n-type third source region formed in the second body region, an n-type third drain region formed in the second body region, and a third gate electrode formed on the front surface of the semiconductor substrate via a third gate insulating film. Furthermore, the resistive element is composed of a fourth MOSFET, the fourth MOSFET having an n-type second diffusion region formed in the second body region, an n-type third diffusion region formed from the second body region across the semiconductor substrate between the first body region and the second body region, and a fourth gate electrode formed on the surface of the semiconductor substrate via a fourth gate insulating film. Furthermore, the JFET has a first body region, a second body region, a third diffusion region, and the semiconductor substrate between the first body region and the second body region. Furthermore, the Schottky barrier diode is composed of a Schottky junction between a conductive material included in the gate wiring and the third drain region. Furthermore, the gate wiring is electrically connected to the first gate electrode, the fourth gate electrode and the third drain region, the source electrode is electrically connected to the first source region, the third source region, the second diffusion region, the first body region and the second body region, and the third gate electrode is electrically connected to the third diffusion region by the first wiring.Further, the JFET, the third MOSFET, the Schottky barrier diode, and the resistor element constitute a cutoff function circuit for detecting an overcurrent flowing through the first MOSFET and limiting the overcurrent.

Advantages of the Invention

[0016] According to one embodiment, the performance of the semiconductor device can be improved and the reliability of the semiconductor device can be ensured.

Brief Description of the Drawings

[0017] [Figure 1] It is a circuit diagram showing a semiconductor device in Embodiment 1. [Figure 2] It is a perspective view showing a semiconductor device in Embodiment 1. [Figure 3] It is a perspective view showing a semiconductor device in Embodiment 1. [Figure 4] It is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 5] It is a schematic diagram showing problems when a PN diode is used instead of the Schottky barrier diode. [Figure 6] It is a perspective view showing a semiconductor device in Modification 1. [Figure 7] It is a cross-sectional view showing a semiconductor device in Embodiment 2. [Figure 8] It is a graph showing simulation results by the inventors of the present application. [Figure 9] It is a cross-sectional view showing a semiconductor device in Embodiment 3. [Figure 10] It is a graph showing simulation results by the inventors of the present application. [Figure 11] It is a graph showing simulation results by the inventors of the present application. [Figure 12] It is a plan view showing a semiconductor device in Embodiment 4. [Figure 13] It is a plan view showing a semiconductor device in Modification 2. [Figure 14]This is a circuit diagram showing a part of the mechanism in Embodiment 5. [Figure 15] This table shows the simulation results performed by the inventors of the present invention. [Figure 16] This is a perspective view showing a part of the semiconductor device in Embodiment 6. [Figure 17] This is a cross-sectional view showing a part of the semiconductor device in Embodiment 6. [Figure 18] This is a cross-sectional view showing a part of the semiconductor device in Embodiment 6. [Modes for carrying out the invention]

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. Furthermore, in the following embodiments, descriptions of the same or similar parts will not be repeated in principle, except when particularly necessary.

[0019] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical, up-down, height, or thickness direction of a structure. Also, the expression "plan view" used in this application means viewing a surface formed by the X and Y directions from the Z direction.

[0020] (Embodiment 1) <Configuration of semiconductor device> Figure 1 is a circuit diagram showing a semiconductor device 100 in Embodiment 1. The semiconductor device 100 comprises a gate wiring GW, a drain electrode DE, and a source electrode SE, and is connected to an electrical device. The gate wiring GW is connected to the positive terminal of the gate driver voltage Vg_GD of the electrical device via a gate resistor Rg. The drain electrode DE is connected to the positive terminal of the power supply voltage Vcc of the electrical device. The source electrode SE is connected to the negative terminal of the gate driver voltage Vg_GD and the negative terminal of the power supply voltage Vcc.

[0021] The semiconductor device 100 is a semiconductor chip and includes a shut-off function circuit 50 and a MOSFET 1Q. The MOSFET 1Q is a SiC power MOSFET and is the main device of the semiconductor device 100.

[0022] The interruption circuit 50 is a circuit for detecting the overcurrent flowing through MOSFET1Q and limiting that overcurrent. In Embodiment 1, the interruption circuit 50 is composed of MOSFET2Q, MOSFET3Q, resistor 4Q, Schottky barrier diode 5Q, and wiring 10. MOSFET2Q is used as a current detection element, and MOSFET3Q is used as an overcurrent interruption element.

[0023] The structure of the semiconductor device 100 and the electrical connection relationship between the interruption circuit 50 and MOSFET 1Q will be explained below with reference to Figures 2 to 4.

[0024] As shown in Figures 2 and 3, the semiconductor device 100 includes a semiconductor substrate SUB having a front and a back surface. A gate wiring GW, a source electrode SE, and wiring 10 are formed on the upper surface of the semiconductor substrate SUB. The majority of the semiconductor substrate SUB is an active region AR on which the MOSFET 1Q is formed. Although not shown in Figure 2, the majority of the source electrode SE covers the upper part of the active region AR. The wiring 10, a portion of the source electrode SE, and a portion of the gate wiring GW are provided in the shut-off circuit 50, as shown in Figure 3.

[0025] In reality, multiple MOSFETs are formed in the active region AR of the semiconductor device 100, and these are connected in parallel. MOSFET1Q is an equivalent circuit that treats the multiple MOSFETs connected in parallel as a single MOSFET.

[0026] The gate wiring GW has a gate pad area GWa for connecting to an external connection component such as a bonding wire or a clip (copper plate). The source electrode SE also has a source pad area for connecting to an external connection component. By connecting the external connection component to the gate pad area GWa and the source pad area, the semiconductor device 100 is electrically connected to other semiconductor chips, wiring boards, or terminals of electrical equipment.

[0027] Furthermore, a p-type termination region TM is formed on the surface side of the semiconductor substrate SUB. In a plan view, the termination region TM surrounds the MOSFET 1Q and the cutoff function circuit 50.

[0028] As shown in Figure 4, the semiconductor substrate SUB has a low concentration of n-type drift region NV. Here, the semiconductor substrate SUB is an n-type silicon carbide substrate (SiC substrate), and the semiconductor substrate SUB itself constitutes the drift region NV. The drift region NV may also be a laminate of an n-type SiC substrate and an n-type SiC layer grown on the SiC substrate by epitaxial growth while introducing phosphorus (P). In this application, such a laminate will also be described as a semiconductor substrate SUB.

[0029] On the surface side of the semiconductor substrate SUB, two p-type body regions, PB1 and PB2, are formed. These two body regions are physically separated by a drift region NV located between them. Furthermore, body region PB2 is in contact with a termination region TM.

[0030] An n-type source region NS1 is formed in the body region PB1. The source region NS1 has a higher impurity concentration than the drift region NV.

[0031] The body region PB2 has n-type source regions NS2, NS3, ND3, NR1, and NR2. Source regions NS2, NS3, ND3, and NR2 have higher impurity concentrations than the drift region NV and NR1.

[0032] p-type diffusion regions PR are formed in body regions PB1 and PB2. The p-type diffusion regions PR have a higher impurity concentration than body regions PB1 and PB2.

[0033] The gate electrode GE1 is formed on the surface of the semiconductor substrate SUB via the gate insulating film GI1. The gate electrode GE2 is formed on the surface of the semiconductor substrate SUB via the gate insulating film GI2. The gate electrode GE3 is formed on the surface of the semiconductor substrate SUB via the gate insulating film GI3. The gate electrodes GE1 to GE3 are, for example, n-type polycrystalline silicon films. The gate insulating films GI1 to GI3 are, for example, silicon oxide films.

[0034] On the back side of the semiconductor substrate SUB, an n-type drain region ND1 is formed. The drain region ND1 has a higher impurity concentration than the drift region NV. A drain electrode DE is formed beneath the back surface of the semiconductor substrate SUB. The drain electrode DE is electrically connected to the drain region ND1 and the drift region NV, and supplies a drain potential to the drain region ND1. The drain electrode DE consists of a single layer metal film such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film obtained by appropriately stacking these metal films.

[0035] Although not shown in the diagram, the gate wiring GW, source electrode SE, and wiring 10 are formed above the surface of the semiconductor substrate SUB via an interlayer insulating film. Multiple contact holes are formed in the interlayer insulating film. By embedding a portion of each of the gate wiring GW, source electrode SE, and wiring 10 inside the multiple contact holes, the gate wiring GW, source electrode SE, and wiring 10 are electrically connected to each gate electrode and each impurity region.

[0036] The gate wiring GW, source electrode SE, and wiring 10 are made of a conductive material. Such a conductive material consists of, for example, a laminated film of a titanium nitride film and an aluminum film formed on the titanium nitride film. Ohmic contact is established between the gate wiring GW, source electrode SE, and wiring 10 and each gate electrode and each impurity region, except for the Schottky barrier diode 5Q described later. In order to achieve ohmic contact, although not shown in the figures, a silicide film such as a nickel silicide film is formed between the gate wiring GW, source electrode SE, and wiring 10 and each gate electrode and each impurity region.

[0037] In Embodiment 1, either the gate wiring GW, the source electrode SE, or the wiring 10 has a multilayer wiring structure. Specifically, a first interlayer insulating film is formed on top of the semiconductor substrate SUB, and a first layer of conductive material is formed on the first interlayer insulating film. A second interlayer insulating film is formed covering the first layer of conductive material, and a second layer of conductive material is formed on the second interlayer insulating film. A third interlayer insulating film is formed covering the second layer of conductive material, and a third layer of conductive material is formed on the third interlayer insulating film.

[0038] Here, we illustrate a case where the multilayer wiring structure is a three-layer structure. Specifically, the source electrode SE is composed of the first layer of conductive material, the wiring 10 is composed of the first and second layers of conductive material, and the gate wiring GW is composed of the first, second, and third layers of conductive material. However, the number of layers of conductive material constituting the gate wiring GW, source electrode SE, and wiring 10 is not limited to the above configuration and can be changed as appropriate.

[0039] MOSFET1Q has a source region NS1, a drain region ND1, a gate insulating film GI1, and a gate electrode GE1. MOSFET2Q has a source region NS2, a drain region ND1, a gate insulating film GI2, and a gate electrode GE2. MOSFET3Q has a source region NS3, a drain region ND3, a gate insulating film GI3, and a gate electrode GE3.

[0040] The Schottky barrier diode 5Q is constructed by a Schottky junction between the conductive material (titanium nitride film) contained in the gate wiring GW and the drain region ND3. In Embodiment 1, the resistive element 4Q consists of a diffusion region NR1. The diffusion region NR1 has a lower impurity concentration than the source region NS2, source region NS3, drain region ND3, and diffusion region NR2.

[0041] The gate wiring GW is electrically connected to gate electrodes GE1 and GE2 and drain region ND3. The source electrode SE is electrically connected to source regions NS1 and NS3 and diffusion region NR2. In addition, the source electrode SE is electrically connected to body regions PB1 and PB2 via diffusion region PR.

[0042] The resistive element 4Q (diffusion region NR1) is electrically connected to the source electrode SE via the diffusion region NR2. The source region NS2 is electrically connected to the source region NS3 and the source electrode SE via the resistive element 4Q. The gate electrode GE3 is electrically connected to the source region NS2 by the wiring 10.

[0043] <Semiconductor device operation and main effects> Referring to Figure 1, the operation of the semiconductor device 100 will be explained. For example, suppose a load connected to the semiconductor device 100 short-circuits while a positive voltage is applied to the gate wiring GW, causing a large current to flow through MOSFET 2Q. In this case, a portion of the large current flows through MOSFET 2Q and the resistor element 4Q. A voltage drop occurs in the resistor element 4Q, and the potential Vsto of the wiring 10 becomes greater than 0V, causing MOSFET 3Q to turn on. As a result, current flows from the gate wiring GW to the source electrode SE, the gate-source voltage Vgs decreases, and the short-circuit current is suppressed. In other words, the gate-source voltage Vgs can be reduced only when a large current is present, so the short-circuit current can be automatically suppressed.

[0044] Furthermore, in semiconductor device 100, the MOSFET 1Q and the interruption circuit 50 are surrounded by a termination region TM in a plan view. When a high voltage is applied to the drain electrode DE, a high voltage is also applied to the side of the semiconductor device 100, which may cause dielectric breakdown in the lateral direction. The interruption circuit 50 can be formed within a low voltage range inside the termination region TM. Also, since the interruption circuit 50 can be formed near the active region AR, which is to be protected against short circuits, it becomes easier to reduce the wiring inductance.

[0045] The width of MOSFET2Q is approximately 5 μm. The resistance of resistor element 4Q can be arbitrarily set by adjusting the impurity concentration of diffusion region NR1, but the width of resistor element 4Q can also be set to approximately 1 μm. The width of MOSFET3Q is approximately 1 μm. The width of Schottky barrier diode 5Q is approximately 1 μm. Even considering the wiring margin, the wiring length from Schottky barrier diode 5Q to the active region AR (MOSFET1Q) can be set to approximately 10 μm.

[0046] For example, if the semiconductor chip having MOSFET1Q and the semiconductor chip having the interruption function circuit 50 are on separate modules, the wiring length from the interruption function circuit 50 to the gate wiring GW will be at least about 5 cm. Even if the semiconductor chip having MOSFET1Q and the semiconductor chip having the interruption function circuit 50 are on the same module, the wiring length from the interruption function circuit 50 to the gate wiring GW will be at least about 1 cm.

[0047] Therefore, the wiring length of Embodiment 1 can be reduced to about 1 / 1000 of the wiring length of these module configurations. Since the noise electromotive force due to mutual inductance is "V = Mdφ / dt", the noise of Embodiment 1 can be reduced to about 1 / 1000 of the noise of these module configurations.

[0048] As described above, according to Embodiment 1, a semiconductor device 100 with low loss can be provided, such as by reducing on-resistance. At the same time, the wiring inductance can be minimized, and the short-circuit withstand capability can be made, for example, 3 μsec or more. Therefore, the performance of the semiconductor device 100 can be improved and the reliability of the semiconductor device 100 can be ensured.

[0049] Furthermore, the advantages of the Schottky barrier diode 5Q will be explained below using Figure 5. Figure 5 shows the problems that arise when a PN diode is used instead of the Schottky barrier diode 5Q. In this PN diode, the drain region ND3 is used as the cathode, and the p-type anode region PA formed within the drain region ND3 is used as the anode.

[0050] As shown in Figure 5, during a short circuit, a bipolar current flows, which may cause the gate wiring GW and drain electrode DE, which were insulated by the pn junction, to conduct. Also, when a negative bias is applied to the gate wiring GW, the body diode conducts, but since holes can pass through the pn diode, there is a risk that the gate wiring GW and source electrode SE will conduct.

[0051] For example, when the circuit configuration of the interruption function circuit 50 and MOSFET 1Q is configured in the module form described above, the diode may be a Schottky barrier diode or a pn diode. However, when the interruption function circuit 50 and MOSFET 1Q are formed on the same semiconductor substrate SUB as in Embodiment 1, the above-mentioned problems occur, so it is appropriate to use a Schottky barrier diode 5Q.

[0052] (Variation 1) Figure 6 shows Modification 1 of Figure 3 of Embodiment 1. As shown in Figure 3, in Embodiment 1, either the source electrode SE, the gate wiring GW, or the wiring 10 had a multilayer wiring structure. In Modification 1, the source electrode SE, the gate wiring GW, and the wiring 10 are formed in the same layer. That is, the first layer of interlayer insulating film is formed above the semiconductor substrate SUB, and the first layer of conductive material is formed on the first layer of interlayer insulating film. The source electrode SE, the gate wiring GW, and the wiring 10 consist of the first layer of conductive material. Such conductive material consists of, for example, a laminated film of a titanium nitride film and an aluminum film formed on the titanium nitride film.

[0053] When applying a multilayer wiring structure like that in Embodiment 1, the wiring design can be freely performed to reduce the wiring inductance, such as by connecting each element of the interruption function circuit 50 along the shortest path.

[0054] On the other hand, in Modification 1, the source electrode SE, gate wiring GW, and wiring 10 can be designed using only the first layer of conductive material, thus suppressing an increase in manufacturing costs. In Modification 1, the planar area for connecting each element of the shut-off function circuit 50 is slightly larger than in Embodiment 1, and the width of the gate pad area GWa is slightly narrower. However, since the width is about 30 μm, sufficient area is secured for connecting external connection members.

[0055] (Embodiment 2) The semiconductor device in Embodiment 2 will be described below with reference to Figures 7 and 8. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0056] In Embodiment 1, a diffusion region NR1 was used as the resistive element 4Q. In Embodiment 2, a MOSFET (resistive MOS) is used as the resistive element 4Q.

[0057] As shown in Figure 7, this resistive MOS has a diffusion region NR2, a source region NS2, a gate insulating film GI4, and a gate electrode GE4. The gate electrode GE4 is formed on the semiconductor substrate SUB via the gate insulating film GI4. The gate insulating film GI4 is, for example, a silicon oxide film, and the gate electrode GE4 is, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0058] The source region NS2 is electrically connected to the gate electrode GE3 by wiring 10. The diffusion region NR2 is electrically connected to the source electrode SE. The gate electrode GE4 is electrically connected to the gate wiring GW.

[0059] As shown in Figure 8, when a diffusion region NR1 is used as the resistive element 4Q (diffusion layer resistance), the potential Vsto of the wiring 10 rises almost linearly with respect to the drain current Ids. Therefore, the saturation characteristic is gradual.

[0060] On the other hand, when a resistive MOS is used as the resistive element 4Q, the potential Vsto of the wiring 10 rises rapidly when it exceeds the saturation current value of the resistive MOS. Therefore, a nearly flat and steep saturation characteristic is obtained. As a result, the on / off switching of the resistive MOS becomes faster, improving the ability to suppress fault current during abnormal operation. Furthermore, during normal operation, almost no voltage is generated, so there is no adverse effect on MOSFET 1Q. Another advantage is that the designer can easily set the short-circuit current value as the saturation current value of the resistive MOS.

[0061] Furthermore, as shown in Figure 7, MOSFETs 1Q and 2Q may have a trench gate structure. In that case, MOSFETs 1Q and 2Q have a trench TR11. Trench TR1 is formed on the surface side of the semiconductor substrate SUB such that its bottom is located below the body regions PB1 and PB2. Gate insulating films GI1 and GI2 are formed on the surface of the semiconductor substrate SUB inside trench TR1. Gate electrodes GE1 and GE2 are formed on gate insulating films GI1 and GI2 so as to fill the inside of trench TR1.

[0062] In Figure 7, both MOSFET1Q and 2Q have a trench gate structure, but it is also possible for only one of MOSFET1Q or 2Q to have a trench gate structure. In that case, MOSFET1Q and 2Q can be designed individually, and their respective threshold voltages can be designed individually.

[0063] For example, the threshold voltage of MOSFET2Q can be adjusted to make short-channel effects more likely to occur in MOSFET2Q. During abnormal operation, a large voltage such as 1000V is generated, and only at that time does the threshold voltage of MOSFET2Q decrease. This allows a large current to flow during abnormal operation, causing the potential Vsto of wiring 10 to rise rapidly, improving the ability to suppress fault current.

[0064] (Embodiment 3) The semiconductor device in Embodiment 3 will be described below with reference to Figures 9 to 11. Note that the following description will mainly focus on the differences from Embodiment 2, and will omit explanations of points that overlap with Embodiment 1.

[0065] In Embodiment 2, a MOSFET 2Q was used as the element for current detection. In Embodiment 3, a JFET (Junction Field Effect Transistor) 6Q is used as the element for current detection.

[0066] As shown in Figure 9, the JFET 6Q has a body region PB1, a body region PB2, a diffusion region NR3, and a semiconductor substrate SUB (JFET region NVa) between body regions PB1 and PB2. The diffusion region NR3 is formed from the body region PB2 to the JFET region NVa and is electrically connected to the gate electrode GE3 by wiring 10. The diffusion region NR3 has a higher impurity concentration than the drift region NV.

[0067] Furthermore, in Embodiment 3, a MOSFET (resistive MOS) is used as the resistive element 4Q. Note that the resistive MOS in Embodiment 3 has a diffusion region NR3 instead of a source region NS2. When using JFET6Q, the gate electrode GE2 is eliminated, so it is necessary to use a resistive MOS as the resistive element 4Q instead of a diffusion region NR1.

[0068] As shown in Figure 10, in Embodiment 2, when the potential Vsto of the wiring 10 rises, not only does the potential of the gate wiring GW decrease, but the source potential of MOSFET 2Q rises, and the gate-source voltage Vgs of MOSFET 2Q decreases. In that case, the gate-source voltage Vgs of MOSFET 2Q tends to deviate significantly compared to MOSFET 1Q in the active region AR. Therefore, as the interruption function circuit 50 operates, it becomes more difficult to detect the short-circuit current, which presents the problem of difficulty in obtaining excellent interruption characteristics.

[0069] Furthermore, when implementing the cutoff function circuit 50 for MOSFET2Q, which is connected in parallel to MOSFET1Q, in a later process, the gate-source voltage Vgs of MOSFET2Q can be wired so as not to fluctuate because each element is independent. However, when implementing the cutoff function circuit 50 within the same semiconductor substrate SUB, the gate-source voltage Vgs of MOSFET2Q will fluctuate due to the shared body potential. Therefore, a structure is needed that can operate even under the influence of this potential fluctuation.

[0070] As shown in Figure 10, when using MOSFET2Q, in addition to the decrease in the potential of the gate wiring GW, the potential Vsto of wiring 10 increases, resulting in a decrease in the gate-source voltage Vgs of MOSFET2Q compared to MOSFET1Q. As a result, the increase in the drain current Ids of MOSFET2Q is suppressed, and the increase in the potential Vsto of wiring 10 is slowed, which may prevent a sufficient reduction in the gate-source voltage Vgs of MOSFET1Q.

[0071] In Embodiment 3, by using JFET6Q instead of MOSFET2Q, the change in gate-source voltage Vgs can be reduced even when the cutoff function circuit 50 is operating. As shown in Figure 11, in JFET6Q, the gate potential is always 0V (source potential), so only the increase in the potential Vsto of the wiring 10 becomes a fluctuation in the gate-source voltage Vgs of JFET6Q, and the drain current Ids does not decrease compared to MOSFET1Q. As a result, the potential Vsto of the wiring 10 can be effectively increased, and the gate-source voltage Vgs of MOSFET1Q can be suppressed. Furthermore, depending on the design, a negative differential resistance can be realized in the region where the gate-source voltage Vgs is large, in which case the drain current Ids of MOSFET1Q decreases as the gate-source voltage Vgs increases.

[0072] (Embodiment 4) The semiconductor device in Embodiment 4 will be described below with reference to Figure 12. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0073] The extent to which the gate-source voltage Vgs can be suppressed during a short circuit can be calculated from the gate resistance Rg and the characteristics of MOSFET3Q. Let Rsto(Vsto) be the resistance of MOSFET3Q. The gate-source voltage Vgs applied to the MOSFET in a steady state can be calculated as shown in "Equation 1" below.

[0074] Vgs=Vgs_GD × Rsto / (Rg+Rsto) ··· Formula 1

[0075] When a large current flows through MOSFET2Q, the potential Vsto of wiring 10 increases. As a result, the gate-source voltage Vgs of MOSFET3Q increases, which reduces the resistance Rsto of MOSFET3Q, and according to "Equation 1", the gate-source voltage Vgs of MOSFET2Q approaches 0V. Note that if the gate-source voltage Vgs of MOSFET3Q is negative, Schottky barrier diode 5Q acts as an infinitely resistive component, so even if current flows, the gate-source voltage Vgs of MOSFET2Q will not approach 0V.

[0076] Equation 1 shows that the characteristic design of the resistance Rsto of MOSFET3Q must correspond to the gate resistance Rg. For example, assuming that the resistance Rsto changes from 1Ω in an abnormal state to 1000Ω in a normal state when Vgs_GD is 15V, the following applies.

[0077] When Rg is 1Ω, the gate-source voltage Vgs of MOSFET3Q can be varied from 15.0V to 7.5V. Within this range, short-circuit suppression is sufficiently possible.

[0078] When Rg is 1000Ω, the gate-source voltage Vgs of MOSFET3Q can vary from 7.5V to 0.0V. Within this range, there is a risk of unintended suppression of the gate-source voltage Vgs even at low currents.

[0079] When Rg is 0.1Ω, the gate-source voltage Vgs of MOSFET3Q can vary from 15.0V to 14.9V. Within this range, even during a short circuit, the gate-source voltage Vgs can hardly be suppressed.

[0080] Based on the above, the method using MOSFET3Q has the following challenges. First, the resistance Rsto of MOSFET3Q needs to have characteristics of an appropriate order with respect to the gate resistance Rg. Generally, in order to avoid reducing the area of ​​the active region AR, it is desirable to keep the area of ​​the cutoff function circuit 50 small. However, in that case, the channel width of MOSFET3Q becomes several orders of magnitude smaller compared to MOSFET1Q, so the channel resistance becomes larger. That is, the resistance Rsto of MOSFET3Q becomes larger.

[0081] Therefore, it is necessary to devise ways to reduce the channel resistance of MOSFET3Q. Note that this issue is particularly pronounced in SiC power MOSFETs, where the channel resistance is high. Furthermore, since the SiC substrate itself is expensive, reducing the area of ​​the active region AR significantly reduces the cost-effectiveness of the semiconductor device 100.

[0082] Figure 12 shows a plan view of the semiconductor device 100 in Embodiment 4, which is a means for solving the above-mentioned problems.

[0083] Normally, it is not possible to connect to the source electrode SE directly below the gate pad area GWa of the gate wiring GW, so the active area AR cannot be placed there. In other words, the area directly below the gate pad area GWa is an area that is not originally used as the active area AR.

[0084] As shown in Figure 12, in Embodiment 4, the MOSFET 3Q and Schottky barrier diode 5Q are also provided directly below the gate pad region GWa. That is, the body region PB2, gate electrode GE3, drain region ND3, source region NS3, and diffusion region PR are also provided directly below the gate pad region GWa.

[0085] This allows the channel width of MOSFET3Q to be increased without reducing the area of ​​the active region AR. In other words, the channel resistance of MOSFET3Q can be reduced, thus solving the problems associated with the increased resistance of resistor Rsto mentioned above. To put it another way, the interruption circuit 50 can handle a sufficient amount of current, improving its ability to suppress fault current.

[0086] Furthermore, the technology disclosed in Embodiment 4 can be applied not only to Embodiment 1, but also to Embodiments 2 and 3.

[0087] (Modification 2) Figure 13 shows a modified example 2 of Embodiment 4. In modified example 2, the channel width of MOSFET3Q is further increased.

[0088] As shown in Figure 13, the gate electrode GE3 located directly beneath the gate pad region GWa has a meandering shape in plan view. In other words, the gate electrode GE3 located directly beneath the gate pad region GWa has a continuous bent shape in which sections extending in the Y direction and sections extending in the X direction are alternately connected.

[0089] Furthermore, the drain region ND3 and source region NS3, located directly below the gate pad region GWa, are formed along the gate electrode GE3, sandwiching the body region PB2 beneath the gate electrode GE3. This allows for a further increase in the channel width of MOSFET3Q without reducing the area of ​​the active region AR.

[0090] Furthermore, similar to Embodiment 4, the technology disclosed in Modification 2 can be applied not only to Embodiment 1, but also to Embodiments 2 and 3.

[0091] (Embodiment 5) The semiconductor device in Embodiment 5 will be described below with reference to Figures 14 and 15. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0092] As shown in Figure 14, in Embodiment 5, multiple MOSFETs 3Q are provided and are illustrated as MOSFETs 3Qa, 3Qb, and 3Qc connected in parallel. A switch is provided on the wiring 10, and by switching the switch, the connection between the gate electrode GE3 of each of the multiple MOSFETs 3Qa, 3Qb, and 3Qc and the wiring 10 can be switched as needed. A MOSFET 3Q whose connection to the wiring 10 is disconnected by the switch will no longer conduct and will not be included in the calculation of the channel width of the MOSFET 3Q.

[0093] The switch may be formed using other semiconductor elements such as MOSFETs, or it may be realized by cutting the wiring 10 with a laser or the like.

[0094] In this way, by appropriately adjusting the switch state according to the gate resistance Rg during use, a single semiconductor chip design can be adapted to multiple applications, thereby increasing its versatility.

[0095] In other words, when the shut-off function circuit 50 is implemented on the same semiconductor substrate SUB, it is not possible to adjust the specifications by changing electronic components as in the back-end process, which leads to a problem of reduced versatility. For example, in the back-end process, one type of semiconductor chip can be made for 10 types of products, and the specifications of each product can be adapted by changing the electronic components. However, when the shut-off function circuit 50 is implemented on the same semiconductor substrate SUB, it is necessary to make 10 different semiconductor chips. Even with the same semiconductor substrate SUB, if it can accommodate products with various specifications, versatility can be further increased.

[0096] Therefore, in Embodiment 5, the gate widths of the multiple MOSFETs 3Qa, 3Qb, and 3Qc are made different, thereby making the channel widths different and the values ​​of the resistors Rsto different.

[0097] Figure 15 is a graph showing the relationship between the gate-source voltage Vgs of the combined MOSFET3Q and the change in gate resistance Rg when the resistance Rsto of MOSFET3Qc is approximately 10 times greater than the resistance Rsto of MOSFET3Qb, and the resistance Rsto of MOSFET3Qb is also approximately 10 times greater than the resistance Rsto of MOSFET3Qa.

[0098] For example, if Vgs_GD is 15V and the gate resistance Rg is 1Ω, and MOSFET3Q is composed only of MOSFET3Qa, the resistance Rsto will vary from 1Ω (abnormal) to 1000Ω (normal). In this case, the gate-source voltage Vgs of MOSFET3Q can vary from 15.0 to 7.5V. Within this range, short-circuit suppression is sufficiently possible. Furthermore, in this configuration, even when the gate resistance Rg is 10Ω, the gate-source voltage Vgs can vary from 14.9 to 1.4V, and the cutoff circuit 50 can withstand the specifications.

[0099] In the table in Figure 15, the range in which the interruption function circuit 50 can withstand the specifications is shown by a dashed line. Similarly, even if the gate resistance Rg is a different value such as 100Ω or 1000Ω, short circuits can be appropriately suppressed by a combination of multiple MOSFETs 3Qa, 3Qb, and 3Qc. In this way, the versatility of the semiconductor device 100 can be increased in Embodiment 5. Furthermore, the number of MOSFETs 3Q is not limited to three (MOSFETs 3Qa, 3Qb, and 3Qc), but may be four or more, and the more there are, the more various gate resistances Rg can be accommodated.

[0100] Furthermore, the technology disclosed in Embodiment 5 can be applied not only to Embodiment 1 but also to Embodiments 2 to 4.

[0101] (Embodiment 6) The semiconductor device in Embodiment 6 will be described below with reference to Figures 16 to 18. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0102] Figure 16 is a perspective view showing a modified example of MOSFET3Q, which is an overcurrent blocking element. Figure 17 is a cross-sectional view along line AA shown in Figure 16. Figure 18 is a cross-sectional view along line BB shown in Figure 16. Note that in Figure 16, the gate insulating film GI3 and gate electrode GE3 are omitted from the illustration in order to make the configuration of the trench TR2 easier to understand.

[0103] In Embodiment 6, as shown in Figures 16 to 18, a plurality of trenches TR2 are formed in the semiconductor substrate SUB on the surface side of the semiconductor substrate SUB. The MOSFET 3Q has a plurality of trenches TR2, which are located between the drain region ND3 and the source region NS3, and the bottom of each of the plurality of trenches TR2 is located within the body region PB2.

[0104] The gate insulating film GI3 is formed on the surface of the semiconductor substrate SUB within the interior of multiple trenches TR2. The gate electrode GE3 is formed on the gate insulating film GI3 so as to fill the interior of the multiple trenches TR2.

[0105] In other words, the body region PB2 located between each trench TR2 constitutes the channel region of MOSFET3Q. Therefore, in Embodiment 6, when compared with the same planar area as Embodiment 1, the channel width of MOSFET3Q is significantly increased. As a result, the channel resistance of MOSFET3Q can be reduced for the reasons explained in Embodiment 4, thus solving the problems associated with increasing the resistance of resistor Rsto. Consequently, the interruption function circuit 50 can handle an even larger amount of current, further improving its ability to suppress fault current.

[0106] Furthermore, the technology disclosed in Embodiment 6 can be applied not only to Embodiment 1 but also to Embodiments 2 to 5.

[0107] Although the present invention has been specifically described above based on the above embodiments, the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0108] 1Q~3Q, 3a, 3b, 3c MOSFETs 4Q Resistor 5Q Schottky barrier diode 6Q JFET AR Active Area GE1~GE4 gate gate GI1~GI4 Gate Insulation Film GW gate wiring GWa Gatepad Area ND1, ND3 drain region NR1~NR3 Diffusion Region NS1~NS3 Source Area NV drift region NVa JFET area PA anode region PB1, PB2 body area SE source electrode SUB Semiconductor Substrate TM Termination Area TR Trench 10 Wiring 50. Cutoff function circuit 100 Semiconductor Equipment

Claims

1. an n-type semiconductor substrate having a front surface and a back surface and made of silicon carbide; a source electrode, a gate wiring, and a first wiring formed above a surface of the semiconductor substrate; a p-type first body region formed in the semiconductor substrate on a front surface side of the semiconductor substrate; a p-type second body region formed in the semiconductor substrate on the front surface side of the semiconductor substrate; a drain electrode formed under the back surface of the semiconductor substrate; a first MOSFET; and a second MOSFET; and a third MOSFET; and A Schottky barrier diode, A resistive element; Equipped with The first MOSFET is an n-type first source region formed in the first body region; an n-type first drain region formed in the semiconductor substrate on a back surface side of the semiconductor substrate and electrically connected to the drain electrode; a first gate electrode formed on a surface of the semiconductor substrate via a first gate insulating film; and The second MOSFET is an n-type second source region formed in the second body region; the first drain region; a second gate electrode formed on the surface of the semiconductor substrate via a second gate insulating film; and The third MOSFET is an n-type third source region formed in the second body region; an n-type third drain region formed in the second body region; a third gate electrode formed on the surface of the semiconductor substrate via a third gate insulating film; and the Schottky barrier diode is formed by a Schottky junction between a conductive material included in the gate wiring and the third drain region, the gate wiring is electrically connected to the first gate electrode, the second gate electrode, and the third drain region; the source electrode is electrically connected to the first source region, the third source region, the first body region, the second body region, and the resistor element; the second source region is electrically connected to the third source region and the source electrode via the resistive element; the third gate electrode is electrically connected to the second source region by the first wiring; the second MOSFET, the third MOSFET, the Schottky barrier diode, and the resistance element constitute a cutoff function circuit for detecting an overcurrent flowing through the first MOSFET and limiting the overcurrent.

2. 2. The semiconductor device according to claim 1, the semiconductor device further comprising: a p-type termination region formed on the front surface side of the semiconductor substrate so as to surround the first MOSFET and the cutoff function circuit in plan view.

3. 2. The semiconductor device according to claim 1, the resistor element is formed in the second body region and is made of an n-type first diffusion region having an impurity concentration lower than that of the third source region.

4. 2. The semiconductor device according to claim 1, the resistive element is constituted by a fourth MOSFET, The fourth MOSFET is a second n-type diffusion region formed in the second body region; the second source region; a fourth gate electrode formed on the surface of the semiconductor substrate via a fourth gate insulating film; and the second diffusion region is electrically connected to the source electrode; The fourth gate electrode is electrically connected to the gate wiring.

5. 5. The semiconductor device according to claim 4, a first trench formed in the semiconductor substrate on the front surface side of the semiconductor substrate such that a bottom portion of the first trench is located lower than the first body region or the second body region; Further provided with the first MOSFET or the second MOSFET has the first trench; the first gate insulating film or the second gate insulating film is formed on the surface of the semiconductor substrate inside the first trench; The semiconductor device, wherein the first gate electrode or the second gate electrode is formed on the first gate insulating film or the second gate insulating film so as to fill the inside of the first trench.

6. 2. The semiconductor device according to claim 1, the gate wiring has a gate pad region for connection to an external connection member, the third MOSFET and the Schottky barrier diode are also provided directly below the gate pad region.

7. 7. The semiconductor device according to claim 6, the third gate electrode located directly below the gate pad region has a serpentine shape in a plan view, a third drain region and a third source region located directly below the gate pad region, the third drain region and the third source region being formed along the third gate electrode so as to sandwich the second body region below the third gate electrode;

8. 2. The semiconductor device according to claim 1, a plurality of the third MOSFETs are provided, the plurality of third MOSFETs are connected in parallel, the gate widths of the plurality of third MOSFETs are different from one another, a third gate electrode of each of the third MOSFETs and the first wiring can be switched as needed;

9. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the source electrode, the gate wiring, and the first wiring are formed in the same layer.

10. 2. The semiconductor device according to claim 1, a plurality of second trenches formed in the semiconductor substrate on the front surface side of the semiconductor substrate so that the bottoms of the second trenches are located within the second body region; Further provided with the third MOSFET has the plurality of second trenches; the third gate insulating film is formed on the surface of the semiconductor substrate inside the second trenches, the third gate electrode is formed on the third gate insulating film so as to fill the interiors of the second trenches.

11. an n-type semiconductor substrate having a front surface and a back surface and made of silicon carbide; a source electrode, a gate wiring, and a first wiring formed above a surface of the semiconductor substrate; a p-type first body region formed in the semiconductor substrate on a front surface side of the semiconductor substrate; a p-type second body region formed in the semiconductor substrate on the front surface side of the semiconductor substrate; a drain electrode formed under the back surface of the semiconductor substrate; a first MOSFET; and a third MOSFET; and JFET and A Schottky barrier diode, A resistive element; Equipped with The first MOSFET is an n-type first source region formed in the first body region; an n-type first drain region formed in the semiconductor substrate on a back surface side of the semiconductor substrate and electrically connected to the drain electrode; a first gate electrode formed on a surface of the semiconductor substrate via a first gate insulating film; and The third MOSFET is an n-type third source region formed in the second body region; an n-type third drain region formed in the second body region; a third gate electrode formed on the surface of the semiconductor substrate via a third gate insulating film; and the resistive element is constituted by a fourth MOSFET, The fourth MOSFET is a second n-type diffusion region formed in the second body region; a third n-type diffusion region formed from the second body region across the semiconductor substrate between the first body region and the second body region; a fourth gate electrode formed on the surface of the semiconductor substrate via a fourth gate insulating film; and The JFET comprises: the first body region; the second body region; the third diffusion region; the semiconductor substrate between the first body region and the second body region; and the Schottky barrier diode is formed by a Schottky junction between a conductive material included in the gate wiring and the third drain region, the gate wiring is electrically connected to the first gate electrode, the fourth gate electrode, and the third drain region; the source electrode is electrically connected to the first source region, the third source region, the second diffusion region, the first body region, and the second body region; the third gate electrode is electrically connected to the third diffusion region by the first wiring; the JFET, the third MOSFET, the Schottky barrier diode, and the resistance element constitute a cutoff function circuit for detecting an overcurrent flowing through the first MOSFET and limiting the overcurrent.

12. 12. The semiconductor device according to claim 11, the semiconductor device further comprising: a p-type termination region formed on the front surface side of the semiconductor substrate so as to surround the first MOSFET and the cutoff function circuit in plan view.

13. 12. The semiconductor device according to claim 11, a first trench formed in the semiconductor substrate on the front surface side of the semiconductor substrate such that a bottom portion of the first trench is located lower than the first body region; Further provided with the first MOSFET has the first trench; the first gate insulating film is formed on the surface of the semiconductor substrate inside the first trench; the first gate electrode is formed on the first gate insulating film so as to fill the inside of the first trench.

14. 12. The semiconductor device according to claim 11, the gate wiring has a gate pad region for connection to an external connection member, the third MOSFET and the Schottky barrier diode are also provided directly below the gate pad region.

15. 15. The semiconductor device according to claim 14, the third gate electrode located directly below the gate pad region has a serpentine shape in a plan view, a third drain region and a third source region located directly below the gate pad region, the third drain region and the third source region being formed along the third gate electrode so as to sandwich the second body region below the third gate electrode;

16. 12. The semiconductor device according to claim 11, a plurality of the third MOSFETs are provided, the plurality of third MOSFETs are connected in parallel, the gate widths of the plurality of third MOSFETs are different from one another, a third gate electrode of each of the third MOSFETs and the first wiring can be switched as needed;

17. 12. The semiconductor device according to claim 11, a plurality of second trenches formed in the semiconductor substrate on the front surface side of the semiconductor substrate so that the bottoms of the second trenches are located within the second body region; Further provided with the third MOSFET has the plurality of second trenches; the third gate insulating film is formed on the surface of the semiconductor substrate inside the second trenches, the third gate electrode is formed on the third gate insulating film so as to fill the interiors of the second trenches.

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