Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device capable of reducing ON resistance.SOLUTION: A semiconductor device comprises: a silicon carbide layer including a first face and a second face in parallel with a first direction and a second direction which is vertical to the first direction; a first trench and a second trench extending in the first direction; an n-type first region in the silicon carbide layer; a p-type second region between the first region and the first face; an n-type third region between the second region and the first face; a p-type sixth region between the first region and the first trench; and p-type eighth regions which are positioned between the second region and the first trench and between the third region and the first trench and in contact with the sixth region. The eighth region is disposed repeatedly in the first direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, an inverter circuit, a driving device, a vehicle, and an elevator.

Background Art

[0002] Silicon carbide (SiC) is expected as a material for next-generation semiconductor devices. Compared with silicon, silicon carbide has excellent physical properties such as a bandgap of about three times, a breakdown electric field strength of about ten times, and a thermal conductivity of about three times. By utilizing these physical properties, a semiconductor device capable of low-loss and high-temperature operation can be realized.

[0003] In a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) using silicon carbide, it is required to reduce the on-resistance.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing the on-resistance.

Means for Solving the Problems

[0006] The semiconductor device of the embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface, a first trench located within the silicon carbide layer and extending in the first direction on the first surface, a first gate electrode located within the first trench, a first gate insulating layer located between the first gate electrode and the silicon carbide layer, a second trench located within the silicon carbide layer and extending in the first direction on the first surface, and a second gate electrode located within the second trench. An electrode, a second gate insulating layer located between the second gate electrode and the silicon carbide layer, a third trench located within the silicon carbide layer and extending in the first direction on the first surface, with the second trench located between it and the first trench, a third gate electrode located within the third trench, a third gate insulating layer located between the third gate electrode and the silicon carbide layer, an n-type first silicon carbide region located within the silicon carbide layer, and a first silicon carbide region located within the silicon carbide layer and located between the first silicon carbide region and the first surface, A p-type second silicon carbide region located between the trench and the second trench; a p-type third silicon carbide region located within the silicon carbide layer, between the first silicon carbide region and the first surface, and between the second trench and the third trench; an n-type fourth silicon carbide region located within the silicon carbide layer, between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located within the silicon carbide layer, between the third silicon carbide region and the first surface; and a first silicon carbide region located within the silicon carbide layer. A p-type sixth silicon carbide region located between the elementary region and the first trench; a p-type seventh silicon carbide region located within the silicon carbide layer and between the first silicon carbide region and the second trench; a plurality of p-type eighth silicon carbide regions located within the silicon carbide layer, in contact with the sixth silicon carbide region, and located between the first silicon carbide region and the first trench, between the second silicon carbide region and the first trench, and between the fourth silicon carbide region and the first trench, and repeatedly arranged in the first direction; and located within the silicon carbide layer,The device comprises a plurality of p-type ninth silicon carbide regions, which are in contact with the seventh silicon carbide region and located between the first silicon carbide region and the second trench, between the third silicon carbide region and the second trench, and between the fifth silicon carbide region and the second trench, and which are repeatedly arranged in the first direction; a first electrode located on the first surface side with respect to the silicon carbide layer and in contact with the fourth silicon carbide region, the fifth silicon carbide region, the eighth silicon carbide region, and the ninth silicon carbide region; and a second electrode located on the second surface side with respect to the silicon carbide layer. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic plan view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] A diagram showing the crystal structure of a silicon carbide semiconductor. [Figure 6] A schematic cross-sectional view of a semiconductor device, a modified example of the first embodiment. [Figure 7] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 8] A schematic plan view of the semiconductor device according to the second embodiment. [Figure 9] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 10] A schematic cross-sectional view of a semiconductor device, a modified example of the second embodiment. [Figure 11] A schematic diagram of the drive unit of the third embodiment. [Figure 12] A schematic diagram of the vehicle according to the fourth embodiment. [Figure 13] A schematic diagram of the vehicle according to the fifth embodiment. [Figure 14] A schematic diagram of the elevator according to the sixth embodiment. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0009] Also, in the following description, n + , , , ++ ,

[0011] , - ,

[0010] , , , n + , n, n - and, p ++ , p, p - When the notations of, p, p are used, these notations represent the relative levels of the impurity concentrations in each conductivity type. That is, n ++ has a relatively higher n-type impurity concentration than n + , n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p ++ has a relatively higher p-type impurity concentration than p + , p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that the n ++ type, n + type, n - type may be simply described as the n-type, and the p ++ type, p + type, p - type may be simply described as the p-type.

[0010] The impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative level of the impurity concentration can be determined, for example, from the level of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Also, the distance such as the width and depth of the impurity region can be obtained, for example, by SIMS. Also. The distance such as the width and depth of the impurity region can be obtained, for example, from the SCM image.

[0011] The width of the trenches, the spacing between trenches, the depth of the trenches, and the thickness of the insulating layer can be measured, for example, on images from SIMS or a Transmission Electron Microscope (TEM).

[0012] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench located within the silicon carbide layer and extending in the first direction on the first surface; a first gate electrode located within the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench located within the silicon carbide layer and extending in the first direction on the first surface; a second gate electrode located within the second trench; and a position between the second gate electrode and the silicon carbide layer. A second gate insulating layer is placed within the silicon carbide layer, a third trench located within the silicon carbide layer and extending in a first direction on the first surface, with the second trench situated between it and the first trench, a third gate electrode located within the third trench, a third gate insulating layer located between the third gate electrode and the silicon carbide layer, an n-type first silicon carbide region located within the silicon carbide layer, a p-type second silicon carbide region located within the silicon carbide layer and situated between the first silicon carbide region and the first surface, and between the first trench and the second trench, and a first silicon carbide region located within the silicon carbide layer A third p-type silicon carbide region located between the region and the first surface, and between the second trench and the third trench; a fourth n-type silicon carbide region located within the silicon carbide layer, between the second silicon carbide region and the first surface; a fifth n-type silicon carbide region located within the silicon carbide layer, between the third silicon carbide region and the first surface; a sixth p-type silicon carbide region located within the silicon carbide layer, between the first silicon carbide region and the first trench; and a seventh p-type silicon carbide region located within the silicon carbide layer, between the first silicon carbide region and the second trench. , located within the silicon carbide layer, adjacent to the sixth silicon carbide region, between the first silicon carbide region and the first trench, between the second silicon carbide region and the first trench, between the fourth silicon carbide region and the first trench, and multiple p-type eighth silicon carbide regions arranged repeatedly in the first direction, and located within the silicon carbide layer, adjacent to the seventh silicon carbide region, between the first silicon carbide region and the second trench, between the third silicon carbide region and the second trench, between the fifth silicon carbide region and the second trench, and multiple p-type ninth silicon carbide regions arranged repeatedly in the first direction,The device comprises a first electrode located on the side of the first plane relative to the silicon carbide layer and in contact with the fourth, fifth, eighth, and ninth silicon carbide regions, and a second electrode located on the side of the second plane relative to the silicon carbide layer. Furthermore, in a first cross-section perpendicular to the first plane and perpendicular to the first direction, and including one of the eighth silicon carbide regions, the ninth silicon carbide region does not exist; and in a second cross-section parallel to the first cross-section and including one of the ninth silicon carbide regions, the eighth silicon carbide region does not exist.

[0013] Figure 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a trench gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 is an n-channel type MOSFET that uses electrons as carriers.

[0014] Figure 2 is a schematic plan view of the semiconductor device according to the first embodiment. Figure 2 is a plan view of the first plane (F1 in Figure 1) in Figure 1. The first and second directions are parallel to the first plane F1. The second direction is perpendicular to the first direction. Figure 1 is a cross-section AA' of Figure 2. Cross-section AA' is an example of the first cross-section.

[0015] Figure 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 is the BB' section of Figure 2. The BB' section is an example of a second cross-section.

[0016] Figure 4 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 4 is the CC' section of Figure 2.

[0017] The MOSFET 100 comprises a silicon carbide layer 10, a first trench 11, a first gate electrode 12, a first gate insulating layer 13, a second trench 21, a second gate electrode 22, a second gate insulating layer 23, a third trench 31, a third gate electrode 32, a third gate insulating layer 33, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), and an interlayer insulating layer 43.

[0018] Hereinafter, the first trench 11, the second trench 21, and the third trench 31 may be collectively referred to as "trenches." Also, the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 may be collectively referred to as "gate electrodes." Furthermore, the first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33 may be collectively referred to as "gate insulating layers."

[0019] Within the silicon carbide layer 10, n + 50, n of the drain area of ​​type - The drift region 51 of type p (first silicon carbide region), the first body region 52a of type p (second silicon carbide region), the second body region 52b of type p (third silicon carbide region), the third body region 52c of type p, the fourth body region 52d of type p, n + The first source region 53a (fourth silicon carbide region) of type n + The second source region of type 53b (the fifth silicon carbide region), n + The third source region of type 53c, n + The fourth source region of type 53d, p + The first electric field relaxation region 54a (sixth silicon carbide region) of type p + Type 2 electric field relaxation region 54b (7th silicon carbide region), p + Type 3 third electric field relaxation region 54c, p + The first connection region 55a of the type (the eighth silicon carbide region), p + The second connection region of the type 55b (the ninth silicon carbide region), p + A third connection region 55c of the type is provided.

[0020] Hereinafter, the first body region 52a, the second body region 52b, the p-type third body region 52c, and the fourth body region 52d may be collectively referred to as body region 52. Also, the first source region 53a, the second source region 53b, the third source region 53c, and the fourth source region 53d may be collectively referred to as source region 53. Also, the first field relaxation region 54a, the second field relaxation region 54b, and the third field relaxation region 54c may be collectively referred to as field relaxation region 54. Also, the first connection region 55a, the second connection region 55b, and the third connection region 55c may be collectively referred to as connection region 55.

[0021] The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0022] The silicon carbide layer 10 comprises a first surface ("F1" in Figure 1) and a second surface ("F2" in Figure 1). The first surface F1 and the second surface F2 face each other. Hereinafter, the first surface F1 will also be referred to as the front surface, and the second surface F2 as the back surface. Hereinafter, "depth" refers to the depth in the direction toward the second surface F2, with the first surface F1 as the reference point.

[0023] In Figures 1 through 4, the first and second directions are parallel to the first and second planes F1 and F2, respectively. The third direction is perpendicular to the first and second planes F1 and F2.

[0024] Figure 5 shows the crystal structure of a silicon carbide semiconductor. A typical crystal structure of a silicon carbide semiconductor is a hexagonal system, such as 4H-SiC. One of the planes (vertical faces of the hexagonal prism) whose normal axis is the c-axis along the axial direction of the hexagonal prism is the (0001) plane. The plane equivalent to the (0001) plane is called the silicon plane and is denoted as the {0001} plane. Silicon (Si) atoms are arranged on the silicon plane.

[0025] The other plane (the vertex face of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (000-1) plane. The plane equivalent to the (000-1) plane is called the carbon plane and is denoted as the {000-1} plane. Carbon (C) atoms are arranged on the carbon plane.

[0026] On the other hand, the side faces (prismatic faces) of the hexagonal prism are the m faces, or {1-100} faces, which are equivalent to the (1-100) faces. Also, the faces passing through a pair of non-adjacent edges are the a faces, or {11-20} faces, which are equivalent to the (11-20) faces. Both silicon (Si) and carbon (C) are arranged on the m faces and a faces.

[0027] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. That is, it is a surface whose normal is inclined at an angle of 0 to 8 degrees relative to the c-axis in the

[0001] direction. In other words, its off-angle with respect to the (0001) surface is 0 to 8 degrees. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface.

[0028] The (0001) surface is called the silicon surface. The (000-1) surface is called the carbon surface.

[0029] The inclination direction of the first surface F1 and the second surface F2 is, for example, the <11-20> direction. The <11-20> direction is the a-axis direction. In Figure 1, for example, the first direction shown in Figure 2 is coplane with the a-axis direction.

[0030] The first trench 11, the second trench 21, and the third trench 31 are located within the silicon carbide layer 10. The first trench 11, the second trench 21, and the third trench 31 are recesses provided in the silicon carbide layer 10. The first trench 11, the second trench 21, and the third trench 31 extend in the first direction as shown in Figure 2.

[0031] The widths of the first trench 11, the second trench 21, and the third trench 31 in the second direction (w in Figure 2) are smaller than, for example, the distance between the first trench 11 and the second trench 21 (d in Figure 2) and the distance between the second trench 21 and the third trench 31 (d in Figure 2).

[0032] The width of the first trench 11, the second trench 21, and the third trench 31 in the second direction (w in Figure 2) is, for example, 0.2 μm or more and 1 μm or less. More preferably 0.3 μm or more and 0.5 μm or less. The distance between the first trench 11 and the second trench 21 (d in Figure 2) and the distance between the second trench 21 and the third trench 31 (d in Figure 2) is, for example 0.3 μm or more and 2 μm or less. More preferably 0.5 μm or more and 1 μm or less. The depth of the first trench 11, the second trench 21, and the third trench 31 is, for example 0.5 μm or more and 2 μm or less. More preferably 0.7 μm or more and 1.5 μm or less.

[0033] Multiple trenches, including a first trench 11, a second trench 21, and a third trench 31, are repeatedly arranged in a second direction. The repeating pitch of the trenches in the second direction is, for example, 1 μm to 6 μm, more preferably 1.6 μm to 3 μm.

[0034] The second trench 21 is located between the first trench 11 and the third trench 31.

[0035] The angle of inclination of the side surface of the first trench 11 with respect to the m-face or a-face is, for example, 0 degrees or more and 5 degrees or less.

[0036] The first gate electrode 12 is located in the first trench 11. The first gate electrode 12 is located between the source electrode 41 and the drain electrode 42. The first gate electrode 12 extends in a first direction.

[0037] The first gate insulating layer 13 is provided between the first gate electrode 12 and the silicon carbide layer 10. The first gate insulating layer 13 is provided between the first source region 53a, the fourth source region 53d, the first body region 52a, the fourth body region 52d, the first field relaxation region 54a, and the first connection region 55a and the first gate electrode 12.

[0038] The angle of inclination of the side surface of the second trench 21 with respect to the m-face or a-face is, for example, 0 degrees or more and 5 degrees or less.

[0039] The second gate electrode 22 is located in the second trench 21. The second gate electrode 22 is located between the source electrode 41 and the drain electrode 42. The second gate electrode 22 extends in the first direction.

[0040] The second gate insulating layer 23 is provided between the second gate electrode 22 and the silicon carbide layer 10. The second gate insulating layer 23 is provided between the first source region 53a, the second source region 53b, the first body region 52a, the second body region 52b, the second field relaxation region 54b, and the second connection region 55b and the second gate electrode 22.

[0041] The angle of inclination of the side surface of the third trench 31 with respect to the m-face or a-face is, for example, 0 degrees or more and 5 degrees or less.

[0042] The third gate electrode 32 is located in the third trench 31. The third gate electrode 32 is located between the source electrode 41 and the drain electrode 42. The third gate electrode 32 extends in the first direction.

[0043] The third gate insulating layer 33 is provided between the third gate electrode 32 and the silicon carbide layer 10. The third gate insulating layer 33 is provided between the second source region 53b, the third source region 53c, the second body region 52b, the third body region 52c, the third field relaxation region 54c, and the third connection region 55c and the third gate electrode 32.

[0044] The first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 are conductive layers. The first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 are, for example, polycrystalline silicon containing p-type or n-type impurities.

[0045] The first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33 are, for example, silicon oxide films. For the first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33, for example, high-k insulating films (high dielectric constant insulating films such as HfSiON, ZrSiON, and AlON) can be applied. Alternatively, for the first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33, for example, a laminated film of silicon oxide (SiO2) and a high-k insulating film can also be applied.

[0046] The interlayer insulating layer 43 is provided on the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32. The interlayer insulating layer 43 is, for example, a silicon oxide film.

[0047] The source electrode 41 is provided on the surface side of the silicon carbide layer 10.

[0048] The source electrode 41 is electrically connected to the first source region 53a, the second source region 53b, the third source region 53c, and the fourth source region 53d. The source electrode 41 is in contact with the first source region 53a, the second source region 53b, the third source region 53c, and the fourth source region 53d.

[0049] The source electrode 41 is electrically connected to the first connection region 55a, the second connection region 55b, and the third connection region 55c. The source electrode 41 is in contact with the first connection region 55a, the second connection region 55b, and the third connection region 55c.

[0050] The source electrode 41 contains a metal. The metal forming the source electrode 41 is, for example, a layered structure of titanium (Ti) and aluminum (Al). The source electrode 41 may also contain metal silicide or metal carbide in contact with the silicon carbide layer 10.

[0051] The drain electrode 42 is provided on the back side of the silicon carbide layer 10. The drain electrode 42 is provided on the back surface of the silicon carbide layer 10. The drain electrode 42 is in contact with the drain region 50.

[0052] The drain electrode 42 is, for example, a metal or a metal-semiconductor compound. The drain electrode 42 includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0053] n + The drain region 50 is provided on the back side of the silicon carbide layer 10. The drain region 50 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 50 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0054] n - The drift region 51 is provided on the drain region 50. The drift region 51 is provided between the drain region 50 and the surface of the silicon carbide layer 10.

[0055] The drift region 51 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 51 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 18 cm -3 The following applies: The thickness of the drift region 51 in the third direction is, for example, 5 μm or more and 150 μm or less.

[0056] The first p-type body region 52a is provided between the drift region 51 and the surface of the silicon carbide layer 10. The first body region 52a is provided between the first trench 11 and the second trench 21. The first body region 52a is in contact with the first trench 11 and the second trench 21. The first body region 52a is in contact with the first gate insulating layer 13 and the second gate insulating layer 23.

[0057] The p-type second body region 52b is provided between the drift region 51 and the surface of the silicon carbide layer 10. The second body region 52b is provided between the second trench 21 and the third trench 31. The second body region 52b is provided between the second trench 21 and the third trench 31. The second body region 52b is in contact with the second gate insulating layer 23 and the third gate insulating layer 33.

[0058] The body region 52 functions as the channel region of the MOSFET 100. For example, when the MOSFET 100 is turned on, a channel is formed in the region of the body region 52 that is in contact with the gate insulating layer, allowing electrons to flow.

[0059] Body region 52 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in body region 52 is, for example, 5 × 10⁻⁶ 16 cm -3 The above 5 x 10 17 cm -3 The following applies: The depth of the body region 52 is, for example, between 0.2 μm and 1.0 μm.

[0060] n + The first source region 53a of the mold is provided between the first body region 52a and the surface of the silicon carbide layer 10. The first source region 53a is in contact with the source electrode 41. The first source region 53a is in contact with the first trench 11 and the second trench 21. The first source region 53a is in contact with the first gate insulating layer 13 and the second gate insulating layer 23.

[0061] n + The second source region 53b of the mold is provided between the second body region 52b and the surface of the silicon carbide layer 10. The second source region 53b is in contact with the source electrode 41. The second source region 53b is in contact with the second trench 21 and the third trench 31. The second source region 53b is in contact with the second gate insulating layer 23 and the third gate insulating layer 33.

[0062] The n-type impurity concentration in source region 53 is, for example, 1 × 10⁻⁶ 19cm -3 The above 1 x 10 21 cm -3 The following applies: The depth of the source region 53 is shallower than the depth of the body region 52, for example, between 0.1 μm and 0.3 μm. The distance between the drift region 51 and the source region 53 is for example between 0.1 μm and 0.9 μm.

[0063] p + The first electric field relaxation region 54a of the type is provided between the drift region 51 and the first trench 11. The first electric field relaxation region 54a is provided between the drift region 51 and the bottom surface of the first trench 11. The first electric field relaxation region 54a is in contact with the bottom surface of the first trench 11.

[0064] p + The second electric field relaxation region 54b of the type is provided between the drift region 51 and the second trench 21. The second electric field relaxation region 54b is provided between the drift region 51 and the bottom surface of the second trench. The second electric field relaxation region 54b is in contact with the bottom surface of the second trench.

[0065] p + The third electric field relaxation region 54c of the type is provided between the drift region 51 and the third trench 31. The third electric field relaxation region 54c is provided between the drift region 51 and the bottom surface of the third trench 31. The third electric field relaxation region 54c is in contact with the bottom surface of the third trench 31.

[0066] The field relaxation region 54 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the field relaxation region 54 is higher than, for example, the p-type impurity concentration in the body region 52. The p-type impurity concentration in the field relaxation region 54 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0067] The electric field relaxation region 54 can be formed, for example, by forming a trench in the silicon carbide layer 10 and then ion-implanting aluminum (Al) into the silicon carbide layer 10 from the bottom of the trench.

[0068] The potential of the electric field relaxation region 54 is fixed to the potential of the source electrode 41. The potential of the electric field relaxation region 54 is fixed to the source potential. The electric field relaxation region 54 has the function of relaxing the electric field applied to the gate insulating layer at the bottom of the trench.

[0069] p + The first connection region 55a of the type is in contact with the first electric field relaxation region 54a. The first connection region 55a is provided between the drift region 51 and the first trench 11. The first connection region 55a is provided between the first body region 52a and the first trench 11. The first connection region 55a is provided between the first source region 53a and the first trench 11.

[0070] The first connection region 55a is in contact with the side surface of the first trench 11. The first connection region 55a is in contact with, for example, the bottom surface of the first trench 11. The first connection region 55a is in contact with, for example, the first surface F1.

[0071] The first connection region 55a between the first source region 53a and the first trench 11 is in contact with the first trench 11. The first connection region 55a between the first source region 53a and the first trench 11 is in contact with the first gate insulating layer 13.

[0072] The first connection region 55a is in contact with the source electrode 41 on the first surface F1.

[0073] Multiple first connection regions 55a are repeatedly arranged in a first direction. The first connection regions 55a are repeatedly arranged in the first direction at a first pitch (P1 in Figure 2).

[0074] The length of the first connection region 55a in the first direction (L1 in Figure 2) is, for example, 0.5 μm or more and 3 μm or less.

[0075] p +The second connection region 55b of the type is in contact with the second electric field relaxation region 54b. The second connection region 55b is provided between the drift region 51 and the second trench 21. The second connection region 55b is provided between the second body region 52b and the second trench 21. The second connection region 55b is provided between the second source region 53b and the second trench 21.

[0076] The second connection region 55b is in contact with the side surface of the second trench 21. The second connection region 55b is in contact with, for example, the bottom surface of the second trench 21. The second connection region 55b is in contact with, for example, the first surface F1.

[0077] The second connection region 55b between the second source region 53b and the second trench 21 is in contact with the second trench 21. The second connection region 55b between the second source region 53b and the second trench 21 is in contact with the second gate insulating layer 23.

[0078] The second connection region 55b is in contact with the source electrode 41 on the first surface F1.

[0079] Multiple second connection regions 55b are repeatedly arranged in the first direction. The second connection regions 55b are repeatedly arranged in the first direction at a second pitch (P2 in Figure 2).

[0080] The length of the second connection region 55b in the first direction (L2 in Figure 2) is, for example, 0.5 μm or more and 3 μm or less.

[0081] p + The third connection region 55c of the type is in contact with the third electric field relaxation region 54c. The third connection region 55c is provided between the drift region 51 and the third trench 31. The third connection region 55c is provided between the third body region 52c and the third trench 31. The third connection region 55c is provided between the third source region 53c and the third trench 31.

[0082] The third connection region 55c is in contact with the side surface of the third trench 31. The third connection region 55c is in contact with, for example, the bottom surface of the third trench 31. The third connection region 55c is in contact with, for example, the first surface F1.

[0083] The third connection region 55c between the third source region 53c and the third trench 31 is in contact with the third trench 31. The third connection region 55c between the third source region 53c and the third trench 31 is in contact with the third gate insulating layer 33.

[0084] The third connection region 55c is in contact with the source electrode 41 on the first surface F1.

[0085] Multiple third connection regions 55c are repeatedly arranged in the first direction. The third connection regions 55c are repeatedly arranged in the first direction at a first pitch (P1 in Figure 2).

[0086] The length of the third connection region 55c in the first direction is, for example, 0.5 μm or more and 3 μm or less.

[0087] In a first cross-section (Figure 1) perpendicular to the first surface F1 and perpendicular to the first direction, and including one of the first connection regions 55a, the second connection region 55b does not exist. In the first cross-section (Figure 1), between the second trench 21 and the third trench 31, p + No type connection area is provided.

[0088] In the second cross-section (Figure 3), which is parallel to the first cross-section (Figure 1) and includes one of the second connection regions 55b, the first connection region 55a and the third connection region 55c do not exist. In the second cross-section (Figure 3), between the first trench 11 and the second trench 21, p + No type connection area is provided.

[0089] In the third cross-section (Figure 4), which is parallel to the first cross-section (Figure 1) and the second cross-section (Figure 3) and is located between the first cross-section (Figure 1) and the second cross-section (Figure 3), the first connection region 55a, the second connection region 55b, and the third connection region 55c do not exist. In the third cross-section (Figure 4), p + No type connection area is provided.

[0090] The first connection region 55a and the second connection region 55b are arranged alternately in the first direction. The first repeating pitch P1 is equal to, for example, the second repeating pitch P2.

[0091] The first connection region 55a and the second connection region 55b are arranged alternately in a first direction with the same repeating pitch, for example. The repeating pitch of the first connection region 55a and the second connection region 55b in the first direction is, for example, half of the first repeating pitch P1. The repeating pitch of the first connection region 55a and the second connection region 55b in the first direction is, for example, half of the second repeating pitch P2.

[0092] The connection region 55 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the connection region 55 is, for example, higher than the p-type impurity concentration in the body region 52. The p-type impurity concentration in the connection region 55 is, for example, higher than the n-type impurity concentration in the source region 53. The p-type impurity concentration in the connection region 55 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 5 x 10 21 cm -3 The following applies:

[0093] The p-type impurity concentration in the first connection region 55a is higher than, for example, the n-type impurity concentration in the first source region 53a. The p-type impurity concentration in the second connection region 55b is higher than, for example, the n-type impurity concentration in the second source region 53b.

[0094] The connecting region 55 can be formed, for example, by forming a trench in the silicon carbide layer 10 and then ion-implanting aluminum (Al) into the silicon carbide layer 10 from the side of the trench using an oblique ion implantation method.

[0095] The connecting region 55 can be formed, for example, by ion implanting aluminum (Al) into the silicon carbide layer 10 under ion implantation conditions that achieve a p-type impurity concentration higher than the n-type impurity concentration of the source region 53 formed across the entire surface of the first surface F1. By compensating for the n-type impurity concentration in the source region 53, the p-type impurity region that becomes the connecting region 55 can be formed on the first surface F1.

[0096] The connection region 55 has the function of electrically connecting the electric field relaxation region 54 and the source electrode 41. The connection region 55 fixes the electric field relaxation region 54 to the potential of the source electrode 41. The connection region 55 fixes the electric field relaxation region 54 to the source potential.

[0097] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0098] According to the MOSFET 100 of the first embodiment, it is possible to simultaneously achieve reduced on-resistance, improved reliability of the gate insulation layer, and reduced switching loss. These will be described in detail below.

[0099] MOSFET100 employs a trench gate structure in which the gate electrode is located within a trench. By applying a trench gate structure, the channel area per unit area increases, and the on-resistance of MOSFET100 is reduced. For example, if MOSFET100 is miniaturized by reducing the trench width or the trench repeat pitch, the on-resistance of MOSFET100 can be further reduced.

[0100] Furthermore, the MOSFET 100 has an electric field relaxation region 54 at the bottom of the trench. By having the electric field relaxation region 54, the electric field applied to the gate insulating layer at the bottom of the trench is relaxed when the MOSFET 100 is in off operation. Therefore, the reliability of the gate insulating layer is improved.

[0101] For example, if the potential of the electric field relaxation region 54 is floating, the switching loss of the MOSFET increases. For example, if the potential of the electric field relaxation region 54 is floating, the switching loss increases during the turn-off operation of the MOSFET because it takes time to discharge holes from the electric field relaxation region 54.

[0102] The MOSFET 100 has a connection region 55 that electrically connects the electric field relaxation region 54 and the body region 52. Because the MOSFET 100 has the connection region 55, the potential of the electric field relaxation region 54 is fixed to the potential of the source electrode 41. Therefore, for example, during the turn-off operation of the MOSFET, the discharge of holes from the electric field relaxation region 54 is promoted. Thus, the switching loss of the MOSFET 100 can be reduced.

[0103] In the MOSFET 100, the connection region 55 is provided along the side of the trench so as to reach the first surface F1. The connection region 55 is in contact with the source electrode 41 on the first surface F1.

[0104] For example, the first connection region 55a extends along the side surface of the first trench 11 to the first surface F1. The first connection region 55a is in contact with the source electrode 41 on the first surface F1. Since the first connection region 55a is in contact with the first body region 52a, the MOSFET 100 does not need to provide a new connection between the source electrode 41 and the first body region 52a. In other words, the connection between the source electrode 41 and the first connection region 55a also serves as the connection between the source electrode 41 and the first body region 52a.

[0105] Therefore, with MOSFET 100, there is no need to separately provide a connection between the source electrode 41 and the first body region 52a between the first trench 11 and the second trench 21. Thus, it becomes possible to reduce the distance between the first trench 11 and the second trench 21.

[0106] By reducing the distance between the first trench 11 and the second trench 21, the on-resistance of the MOSFET 100 can be further reduced.

[0107] Furthermore, by reducing the distance between the first trench 11 and the second trench 21, the width of the drift region 51 between the first connection region 55a and the second trench 21 is reduced. Therefore, the saturation current when a short circuit occurs in the MOSFET 100 is suppressed. Thus, the short-circuit withstand capability of the MOSFET 100 is improved.

[0108] Furthermore, as shown in Figure 2, in the MOSFET 100, the first connection region 55a and the second connection region 55b are arranged alternately in the first direction. As a result, the current paths of the MOSFET 100 are formed alternately in the first direction. Therefore, heat generation within the MOSFET 100 is distributed without being concentrated in one area. Thus, failure of the MOSFET 100 due to heat generation is suppressed, and the reliability of the MOSFET 100 is improved.

[0109] The inclination angle of the trench side surface with respect to the m-plane is preferably 0 degrees or more and 5 degrees or less. When the inclination direction of the first surface F1 is the <11-20> direction, i.e., the a-axis direction, by making the trench side surface close to the m-plane, it becomes easy to align the plane orientations of two opposing sides of a single trench to similar plane orientations. Therefore, it becomes easy to align the threshold voltages and mobilities of transistors formed on both sides of the trench.

[0110] On the other hand, if the inclination direction of the first surface F1 is the <11-20> direction, i.e., the a-axis direction, and the side surface of the trench is the surface closest to the a-plane, it becomes difficult to align the plane orientations of two opposing sides of a single trench to a similar plane orientation. Therefore, it becomes difficult to align the threshold voltages and mobilities of the transistors formed on both sides of the trench.

[0111] (modified version) Figure 6 is a schematic cross-sectional view of a modified semiconductor device of the first embodiment. Figure 6 corresponds to Figure 1 of the first embodiment.

[0112] The modified MOSFET 101 differs from the MOSFET 100 of the first embodiment in that the first connection region 55a includes a first region 55ax between the drift region 51 and the first trench 11, and a second region 55ay between the first source region 53a and the first trench 11.

[0113] The p-type impurity concentration in the first region 55ax is lower than that in the second region 55ay. For example, the p-type impurity concentration in the first region 55ax is less than or equal to one-tenth of that in the second region 55ay.

[0114] For example, when forming the first connection region 55a by oblique ion implantation from the first side after forming the first trench 11, the second region 55ay can be formed by performing additional ion implantation only on the upper part of the first trench 11.

[0115] In the modified MOSFET 101, the p-type impurity concentration in the portion of the connection region 55 that is in contact with the drift region 51 is reduced. Therefore, the electric field at the bottom of the connection region 55 is relaxed, and the breakdown of the pn junction is suppressed. Consequently, the breakdown voltage of MOSFET 101 is improved.

[0116] As described above, the MOSFETs of the first embodiment and its modified form can simultaneously achieve reduced on-resistance, improved reliability of the gate insulation layer, and reduced switching losses.

[0117] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that a ninth silicon carbide region exists in a first cross-section perpendicular to the first plane and perpendicular to the first direction, and which includes one of the eighth silicon carbide regions. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0118] Figure 7 is a schematic cross-sectional view of the semiconductor device of the second embodiment. The semiconductor device of the second embodiment is a trench gate type vertical MOSFET 200 using silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0119] Figure 8 is a schematic plan view of the semiconductor device according to the second embodiment. Figure 8 is a plan view of the first plane (F1 in Figure 7) in Figure 7. The first and second directions are parallel to the first plane F1. The second direction is perpendicular to the first direction. Figure 7 is a cross-section DD' of Figure 8. The cross-section DD' is an example of the first cross-section.

[0120] Figure 9 is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 9 is the EE' cross-section of Figure 8.

[0121] The MOSFET200 comprises a silicon carbide layer 10, a first trench 11, a first gate electrode 12, a first gate insulating layer 13, a second trench 21, a second gate electrode 22, a second gate insulating layer 23, a third trench 31, a third gate electrode 32, a third gate insulating layer 33, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), and an interlayer insulating layer 43.

[0122] Hereinafter, the first trench 11, the second trench 21, and the third trench 31 may be collectively referred to as "trenches." Also, the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 may be collectively referred to as "gate electrodes." Furthermore, the first gate insulating layer 13, the second gate insulating layer 23, and the third gate insulating layer 33 may be collectively referred to as "gate insulating layers."

[0123] Within the silicon carbide layer 10, n + 50, n of the drain area of ​​type - The drift region 51 of type p (first silicon carbide region), the first body region 52a of type p (second silicon carbide region), the second body region 52b of type p (third silicon carbide region), the third body region 52c of type p, the fourth body region 52d of type p, n+ The first source region 53a (fourth silicon carbide region) of type n + The second source region of type 53b (the fifth silicon carbide region), n + The third source region of type 53c, n + The fourth source region of type 53d, p + The first electric field relaxation region 54a (sixth silicon carbide region) of type p + Type 2 electric field relaxation region 54b (7th silicon carbide region), p + Type 3 third electric field relaxation region 54c, p + The first connection region 55a of the type (the eighth silicon carbide region), p + The second connection region of the type 55b (the ninth silicon carbide region), p + A third connection region 55c of the type is provided.

[0124] Hereinafter, the first body region 52a, the second body region 52b, the p-type third body region 52c, and the fourth body region 52d may be collectively referred to as body region 52. Also, the first source region 53a, the second source region 53b, the third source region 53c, and the fourth source region 53d may be collectively referred to as source region 53. Also, the first field relaxation region 54a, the second field relaxation region 54b, and the third field relaxation region 54c may be collectively referred to as field relaxation region 54. Also, the first connection region 55a, the second connection region 55b, and the third connection region 55c may be collectively referred to as connection region 55.

[0125] As shown in Figure 8, the multiple first connection regions 55a are repeatedly arranged in a first direction. The first connection regions 55a are repeatedly arranged in the first direction at a first pitch (P1 in Figure 8).

[0126] The length of the first connection region 55a in the first direction (L1 in Figure 8) is, for example, 0.5 μm or more and 3 μm or less.

[0127] Multiple second connection regions 55b are repeatedly arranged in the first direction. The second connection regions 55b are repeatedly arranged in the first direction at a second pitch (P2 in Figure 8).

[0128] The length of the second connection region 55b in the first direction (L2 in Figure 8) is, for example, 0.5 μm or more and 3 μm or less.

[0129] Multiple third connection regions 55c are repeatedly arranged in the first direction. The third connection regions 55c are repeatedly arranged in the first direction at a first pitch (P1 in Figure 8).

[0130] In a first cross section (Figure 7) perpendicular to the first surface F1 and perpendicular to the first direction, a second connection region 55b exists in which one of the first connection regions 55a is included. In the first cross section (Figure 7), between the first trench 11 and the second trench 21, and between the second trench 21 and the third trench 31, p + A connection area for the type exists.

[0131] In the second cross-section (Figure 9), which is parallel to the first cross-section (Figure 7) and spaced apart from the first cross-section (Figure 7) in the first direction, the first connection region 55a, the second connection region 55b, and the third connection region 55c do not exist. In the second cross-section (Figure 9), between the first trench 11 and the second trench 21, and between the second trench 21 and the third trench 31, p + No type connection area is provided.

[0132] The first connection region 55a and the second connection region 55b are arranged in parallel in a first direction. The second connection region 55b is located in a second direction relative to the first connection region 55a. The first repeating pitch P1 is equal to the second repeating pitch P2.

[0133] According to the MOSFET 200 of the second embodiment, similar to the MOSFET 100 of the first embodiment, it is possible to simultaneously achieve a reduction in on-resistance, an improvement in the reliability of the gate insulation layer, and a reduction in switching loss.

[0134] (modified version) Figure 10 is a schematic cross-sectional view of a modified semiconductor device of the second embodiment. Figure 10 corresponds to Figure 7 of the second embodiment.

[0135] The modified MOSFET 201 differs from the MOSFET 200 of the second embodiment in that the first connection region 55a includes a first region 55ax between the drift region 51 and the first trench 11, and a second region 55ay between the first source region 53a and the first trench 11.

[0136] The p-type impurity concentration in the first region 55ax is lower than that in the second region 55ay. For example, the p-type impurity concentration in the first region 55ax is less than or equal to one-tenth of that in the second region 55ay.

[0137] For example, when forming the first connection region 55a by oblique ion implantation from the first side after forming the first trench, the second region 55ay can be formed by performing additional ion implantation only on the upper part of the first trench.

[0138] In the modified MOSFET 201, the p-type impurity concentration in the portion of the connection region 55 that is in contact with the drift region 51 is reduced. Therefore, the electric field at the bottom of the connection region 55 is relaxed, and breakdown of the pn junction is suppressed. Consequently, the breakdown voltage of MOSFET 201 is improved.

[0139] As described above, the MOSFETs of the second embodiment and its modified form can simultaneously achieve reduced on-resistance, improved reliability of the gate insulation layer, and reduced switching losses.

[0140] (Third embodiment) The inverter circuit and drive device of the third embodiment is a drive device equipped with the semiconductor device of the first embodiment.

[0141] Figure 11 is a schematic diagram of the drive unit of the third embodiment. The drive unit 1000 comprises a motor 140 and an inverter circuit 150.

[0142] The inverter circuit 150 consists of three semiconductor modules 150a, 150b, and 150c, each using a MOSFET 100 from the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0143] According to the third embodiment, the characteristics of the inverter circuit 150 and the drive unit 1000 are improved by providing a MOSFET 100 with improved characteristics.

[0144] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0145] Figure 12 is a schematic diagram of a vehicle according to the fourth embodiment. The vehicle 1100 of the fourth embodiment is a railway vehicle. The vehicle 1100 includes a motor 140 and an inverter circuit 150.

[0146] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 1100.

[0147] According to the fourth embodiment, the characteristics of the vehicle 1100 are improved by providing a MOSFET 100 with improved characteristics.

[0148] (Fifth embodiment) The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0149] Figure 13 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 1200 of the fifth embodiment is an automobile. The vehicle 1200 includes a motor 140 and an inverter circuit 150.

[0150] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0151] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 1200.

[0152] According to the fifth embodiment, the characteristics of the vehicle 1200 are improved by providing a MOSFET 100 with improved characteristics.

[0153] (Sixth embodiment) The elevator of the sixth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0154] Figure 14 is a schematic diagram of an elevator according to the sixth embodiment. The elevator 1300 of the sixth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoisting machine 616, a motor 140, and an inverter circuit 150.

[0155] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0156] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the hoisting machine 616, causing the cage 610 to rise and fall.

[0157] According to the sixth embodiment, the characteristics of the elevator 1300 are improved by providing a MOSFET 100 with improved characteristics.

[0158] In the first and second embodiments described above, the case of silicon carbide with a 4H-SiC crystal structure was used as an example. However, the present invention can also be applied to silicon carbide with other crystal structures such as 6H-SiC and 3C-SiC.

[0159] In the first and second embodiments, a MOSFET was used as an example of a semiconductor device, but the present invention can also be applied to an Insulated Gate Bipolar Transistor (IGBT). For example, an IGBT can be realized by replacing the region corresponding to the drain region 50 of the MOSFET 100 from n-type to p-type.

[0160] Furthermore, although the third to sixth embodiments were described using the semiconductor device of the first embodiment as an example, it is also possible to apply the semiconductor device of the second embodiment.

[0161] Furthermore, although the third to sixth embodiments described the application of the semiconductor device of the present invention to vehicles and elevators as examples, it is also possible to apply the semiconductor device of the present invention to, for example, a power conditioner for a solar power generation system.

[0162] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0163] 10. Silicon carbide layer 11 The first trench 12 First gate electrode 13. First gate insulating layer 21 The second trench 22 Second gate electrode 23 Second gate insulating layer 31 The Third Trench 32 Third Tetragon 33 Third gate insulating layer 41 Source electrode (first electrode) 42 Drain electrode (second electrode) 51. Drift region (first silicon carbide region) 52a First body region (second silicon carbide region) 52b Second body region (third silicon carbide region) 53a First source region (fourth silicon carbide region) 53b Second source region (fifth silicon carbide region) 54a First electric field relaxation region (sixth silicon carbide region) 54ax, Area 1 54ay Second area 54b Second electric field relaxation region (seventh silicon carbide region) 55a First connection region (eighth silicon carbide region) 55b Second connection region (ninth silicon carbide region) 100 MOSFETs (Semiconductor Devices) 150 Inverter Circuit 200 MOSFETs (Semiconductor Devices) 1000 Drive unit 1100 vehicles 1200 vehicles 1300 Elevator AA' Section, First Section BB' section, second section CC' section, third section DD' Section, First Section F1 First Side F2 Second side

Claims

1. a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench in the silicon carbide layer, the first trench extending in the first direction at the first surface; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench in the silicon carbide layer, the second trench extending in the first direction at the first surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; a third trench present in the silicon carbide layer, extending in the first direction on the first surface, with the second trench located between the third trench and the first trench; a third gate electrode located in the third trench; a third gate insulating layer located between the third gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; a p-type third silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the second trench and the third trench; an n-type fourth silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; an n-type fifth silicon carbide region located in the silicon carbide layer and between the third silicon carbide region and the first surface; a p-type sixth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first trench; a p-type seventh silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second trench; a plurality of p-type eighth silicon carbide regions located in the silicon carbide layer, in contact with the sixth silicon carbide region, and located between the first silicon carbide region and the first trench, between the second silicon carbide region and the first trench, and between the fourth silicon carbide region and the first trench, and repeatedly arranged in the first direction; a plurality of p-type ninth silicon carbide regions located in the silicon carbide layer, in contact with the seventh silicon carbide region, between the first silicon carbide region and the second trench, between the third silicon carbide region and the second trench, and between the fifth silicon carbide region and the second trench, and repeatedly arranged in the first direction; a first electrode located on the first surface side of the silicon carbide layer and in contact with the fourth silicon carbide region, the fifth silicon carbide region, the eighth silicon carbide region, and the ninth silicon carbide region; a second electrode located on the second surface side of the silicon carbide layer; A semiconductor device comprising:

2. the ninth silicon carbide region is absent in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and includes one of the eighth silicon carbide regions; 2. The semiconductor device according to claim 1, wherein the eighth silicon carbide region is absent in a second cross section that is parallel to the first cross section and includes one of the ninth silicon carbide regions.

3. 3. The semiconductor device according to claim 2, wherein the eighth silicon carbide region and the ninth silicon carbide region are absent in a third cross section that is parallel to the first cross section and the second cross section and is located between the first cross section and the second cross section.

4. 2 . The semiconductor device according to claim 1 , wherein the ninth silicon carbide region exists in a first cross section that is perpendicular to the first surface, perpendicular to the first direction, and includes one of the eighth silicon carbide regions.

5. 5. The semiconductor device according to claim 1, wherein the eighth silicon carbide region between the fourth silicon carbide region and the first trench contacts the first trench.

6. 6. The semiconductor device according to claim 1, wherein a p-type impurity concentration of said eighth silicon carbide region is higher than an n-type impurity concentration of said fourth silicon carbide region.

7. the eighth silicon carbide region includes a first region between the first silicon carbide region and the first trench, and a second region between the fourth silicon carbide region and the first trench; 7. The semiconductor device according to claim 1, wherein the first region has a p-type impurity concentration lower than the p-type impurity concentration of the second region.

8. 8. The semiconductor device according to claim 1, wherein the first surface is a surface inclined at an angle of 0 to 8 degrees relative to the (0001) plane toward the a-axis direction, and the first direction is in the same plane as the a-axis direction.

9. 9. The semiconductor device according to claim 1, wherein the inclination angle of the side surface of the first trench with respect to the m-plane is between 0 degrees and 5 degrees.

10. 10. An inverter circuit comprising the semiconductor device according to claim 1.

11. A driving device comprising the semiconductor device according to any one of claims 1 to 9.

12. A vehicle comprising the semiconductor device according to any one of claims 1 to 9.

13. An elevator comprising the semiconductor device according to any one of claims 1 to 9.

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