Semiconductor device

Abstract

A semiconductor device that can be highly integrated or highly integrated is provided. [Solution] A semiconductor device having a first insulator having an opening formed therein, a first conductor disposed in the opening, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, a second conductor on the third oxide and on the first conductor, a third conductor on the fourth oxide, a fifth oxide on the second oxide, a second insulator on the fifth oxide, and a fourth conductor located on the second insulator and overlapping the fifth oxide, wherein the fifth oxide contacts a side surface of the third oxide and a side surface of the fourth oxide, respectively, the conductivity of the third oxide is higher than that of the second oxide, the conductivity of the fourth oxide is higher than that of the second oxide, and the second conductor contacts the top surface of the first conductor.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer, a module, and electronic equipment.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials. Oxide semiconductors include not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals. Among the oxides of multi-component metals, research on In-Ga-Zn oxide (hereinafter also called IGZO) is particularly active.

[0005] Research on IGZO has led to the discovery of CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures in oxide semiconductors, which are neither single-crystal nor amorphous (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 also disclose techniques for fabricating transistors using oxide semiconductors having a CAAC structure. Furthermore, Non-Patent Documents 4 and 5 show that even oxide semiconductors with lower crystallinity than the CAAC and nc structures can contain minute crystals.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-currents (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic have been reported (see Non-Patent Documents 7 and 8). [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] One aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Or, one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Or, one aspect of the present invention is to provide a semiconductor device having a large on-current. Or, one aspect of the present invention is to provide a semiconductor device having high frequency characteristics. Or, one aspect of the present invention is to provide a semiconductor device having good reliability. Or, one aspect of the present invention is to provide a highly productive semiconductor device.

[0009] One aspect of the present invention aims to provide a semiconductor device capable of retaining data for a long period. One aspect of the present invention aims to provide a semiconductor device with a high writing speed of information. One aspect of the present invention aims to provide a semiconductor device with a high degree of design freedom. One aspect of the present invention aims to provide a semiconductor device capable of suppressing power consumption. One aspect of the present invention aims to provide a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention includes a first insulator with an opening formed therein, a first conductor disposed in the opening, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, a second conductor on the third oxide and on the first conductor, a third conductor on the fourth oxide, a fifth oxide on the second oxide, a second insulator on the fifth oxide, and a fourth conductor located on the second insulator and overlapping the fifth oxide. The fifth oxide is in contact with the side surfaces of the third oxide and the fourth oxide respectively. The conductivity of the third oxide is higher than that of the second oxide, and the conductivity of the fourth oxide is higher than that of the second oxide. The second conductor is in contact with the upper surface of the first conductor. It is a semiconductor device.

[0012] Furthermore, one aspect of the present invention includes a first insulator having an opening formed therein, a first conductor disposed within the opening, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, a third oxide, a second conductor on the first conductor, a third conductor on the fourth oxide, a fifth oxide on the second oxide, a second insulator on the fifth oxide, and a fifth oxide located on the second insulator. A semiconductor device having a fourth conductor that overlaps with the second conductor, the third oxide having a first region that does not overlap with the second conductor, the fourth oxide having a second region that does not overlap with the third conductor, the fifth oxide being in contact with the upper surface of the first region and the upper surface of the second region, the conductivity of the third oxide being higher than that of the second oxide, the conductivity of the fourth oxide being higher than that of the second oxide, and the second conductor being in contact with the upper surface of the first conductor.

[0013] Furthermore, the second conductor may have a fifth conductor in contact with its upper surface, and the fifth conductor may be superimposed on at least a portion of the first conductor.

[0014] Furthermore, one aspect of the present invention comprises first to third insulators, first to sixth conductors, first to fifth oxides, a capacitive element, and a transistor, wherein the capacitive element comprises a fifth conductor, a third insulator on the fifth conductor, and a sixth conductor on the third insulator, and the transistor comprises a first insulator with an opening formed therein, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, and on the third oxide, The semiconductor device comprises a second conductor on a first conductor, a third conductor on a fourth oxide, a fifth oxide on the second oxide, a second insulator on the fifth oxide, and a fourth conductor located on the second insulator and overlapping with the fifth oxide, wherein the fifth oxide is in contact with the side surface of the third oxide and the side surface of the fourth oxide, respectively, the conductivity of the third oxide is higher than that of the second oxide, the conductivity of the fourth oxide is higher than that of the second oxide, and the second conductor is in contact with the upper surface of the first conductor.

[0015] Furthermore, one aspect of the present invention comprises first to third insulators, first to sixth conductors, first to fifth oxides, a capacitive element, and a transistor, wherein the capacitive element comprises a fifth conductor, a third insulator on the fifth conductor, and a sixth conductor on the third insulator, and the transistor comprises a first insulator with an opening formed therein, a first conductor disposed in the opening, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, a third oxide, and a second conductor on the first conductor and a third oxide on the fourth oxide. A semiconductor device comprising a conductor, a fifth oxide on a second oxide, a second insulator on the fifth oxide, and a fourth conductor located on the second insulator and overlapping with the fifth oxide, wherein the third oxide has a first region that does not overlap with the second conductor, the fourth oxide has a second region that does not overlap with the third conductor, the fifth oxide is in contact with the upper surface of the first region and the upper surface of the second region, the conductivity of the third oxide is higher than that of the second oxide, the conductivity of the fourth oxide is higher than that of the second oxide, and the second conductor is in contact with the upper surface of the first conductor.

[0016] Furthermore, it is preferable that the capacitive element is formed below the transistor, and that the first conductor is electrically connected to the sixth conductor.

[0017] Furthermore, the first insulator may have a fourth insulator with an opening formed therebelow it, and at least a portion of the fifth conductor, the third insulator, and the sixth conductor may be placed within the opening of the fourth insulator.

[0018] Furthermore, one aspect of the present invention comprises first to fourth insulators, first to seventh conductors, first to fifth oxides, a capacitive element, a first transistor, and a second transistor, wherein the capacitive element comprises a fifth conductor, a third insulator on the fifth conductor, and a sixth conductor on the third insulator, and the first transistor comprises a first insulator with an opening formed therein, a first conductor disposed in the opening, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, and a second conductor on the third oxide and on the first conductor. A semiconductor device comprising an electric body, a third conductor on a fourth oxide, a fifth oxide on a second oxide, a second insulator on the fifth oxide, and a fourth conductor located on the second insulator and overlapping with the fifth oxide, wherein the fifth oxide is in contact with the side surface of the third oxide and the side surface of the fourth oxide, respectively, the conductivity of the third oxide is higher than that of the second oxide, the conductivity of the fourth oxide is higher than that of the second oxide, the second conductor is in contact with the upper surface of the first conductor, and the second transistor comprises a fourth insulator on a silicon substrate and a seventh conductor on the fourth insulator.

[0019] Furthermore, one aspect of the present invention comprises first to fourth insulators, first to seventh conductors, first to fifth oxides, a capacitive element, a first transistor, and a second transistor, wherein the capacitive element comprises a fifth conductor, a third insulator on the fifth conductor, and a sixth conductor on the third insulator, and the first transistor comprises a first insulator with an opening formed therein, a first conductor disposed in the opening, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, a third oxide, and a second conductor on the first conductor, a third conductor on the fourth oxide, and a third oxide on the second oxide. A semiconductor device comprising a fifth oxide, a second insulator on the fifth oxide, and a fourth conductor located on the second insulator and overlapping with the fifth oxide, wherein the third oxide has a first region that does not overlap with the second conductor, the fourth oxide has a second region that does not overlap with the third conductor, the fifth oxide is in contact with the upper surface of the first region and the upper surface of the second region, the conductivity of the third oxide is higher than that of the second oxide, the conductivity of the fourth oxide is higher than that of the second oxide, the second conductor is in contact with the upper surface of the first conductor, and the second transistor comprises a fourth insulator on a silicon substrate and a seventh conductor on the fourth insulator.

[0020] Furthermore, the first transistor may have an eighth conductor in contact with the upper surface of the second conductor, a capacitive element formed above the first transistor, the eighth conductor electrically connected to the fifth conductor, and the second transistor formed below the first transistor, the first conductor electrically connected to the seventh conductor.

[0021] Furthermore, the eighth conductor may have a fifth insulator with an opening formed therein, and at least a portion of the fifth conductor, the third insulator, and the sixth conductor may be placed in the opening of the fifth insulator.

[0022] Furthermore, it is preferable that the third oxide and the fourth oxide each contain zinc.

[0023] Furthermore, the film thicknesses of the third oxide and the fourth oxide are preferably 1 nm or more and 10 nm or less, respectively.

[0024] Furthermore, it is preferable that the third oxide and the fourth oxide each have crystalline properties.

[0025] Furthermore, the second oxide preferably contains In, element M (where M is Al, Ga, Y, or Sn), and Zn. [Effects of the Invention]

[0026] According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high productivity can be provided.

[0027] Alternatively, we can provide semiconductor devices that can retain data for extended periods. Alternatively, we can provide semiconductor devices with high data writing speeds. Alternatively, we can provide semiconductor devices with a high degree of design flexibility. Alternatively, we can provide semiconductor devices that can reduce power consumption. Alternatively, we can provide novel semiconductor devices.

[0028] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0029] [Figure 1] (A)-(C) Top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] (A)-(C) Top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3] (A)(B) Cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 4] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 5] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 6] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 7] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] A diagram illustrating the energy band structure of oxide semiconductors. [Figure 13] (A)(B) A top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 14] (A)(B) A top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 15] (A)(B) A top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 16] (A)-(C) Top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 17]A cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 18] (A)(B) Cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 19] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 20] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 21] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 22] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 23] (A)-(C) A top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 24] A cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 25] A cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 26] A cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 27] (A)(B) Block diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 28] (A)-(H) Circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 29] (A)(B)Schematic diagram of a semiconductor device according to one aspect of the present invention. [Figure 30] (A)-(E) Schematic diagrams of a storage device according to one embodiment of the present invention. [Figure 31] A diagram illustrating a product image that can be used in a semiconductor device according to one embodiment of the present invention. [Figure 32] (A)-(F) Diagrams showing an electronic device according to one aspect of the present invention. [Modes for carrying out the invention]

[0030] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0031] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may be omitted for ease of understanding. Additionally, the same reference numerals may be used across different drawings for identical parts or parts with similar functions, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the hatch patterns may be the same, and no specific reference numeral may be assigned.

[0032] Furthermore, in particular, in top views (also called "plan views") and perspective views, descriptions of some components may be omitted to facilitate understanding of the invention. Also, descriptions of some hidden lines may be omitted.

[0033] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0034] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0035] For example, where it is explicitly stated in this specification that X and Y are connected, this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, predetermined connection relationships, not limited to those shown in the figures or text, are also disclosed in the figures or text.

[0036] Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0037] Furthermore, the functions of the source and drain may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0038] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0039] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0040] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0041] In semiconductors, impurities refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause problems such as an increase in the Density of States (DOS) of the semiconductor or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the semiconductor's properties include, for example, Group 1, Group 2, Group 13, Group 14, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, water can also function as an impurity. In oxide semiconductors, for example, the inclusion of impurities can create oxygen vacancies. When the semiconductor is silicon, impurities that alter the semiconductor's properties include, for example, Group 1, Group 2, Group 13, and Group 15 elements, excluding oxygen and hydrogen.

[0042] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0043] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0044] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0045] In this specification, a barrier film is defined as a film that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. If the barrier film is conductive, it may be referred to as a conductive barrier film.

[0046] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS FET or OS transistor is described, it can be rephrased as a transistor having an oxide or oxide semiconductor.

[0047] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁰ at room temperature. -20 A or less, 1 × 10 at 85℃ -18A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0048] (Embodiment 1) The following describes an example of a semiconductor device having a transistor 200 according to one aspect of the present invention.

[0049] <Example of semiconductor device configuration> Figures 1(A), 1(B), and 1(C) are a top view and a cross-sectional view of a transistor 200 and the area surrounding the transistor 200 according to one embodiment of the present invention.

[0050] Figure 1(A) is a top view of a semiconductor device having a transistor 200. Figures 1(B) and 1(C) are cross-sectional views of the same semiconductor device. Here, Figure 1(B) is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1(A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Similarly, Figure 1(C) is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1(A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the top view of Figure 1(A), some elements have been omitted for clarity.

[0051] A semiconductor device according to one aspect of the present invention includes an insulator 214 on a substrate (not shown), a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 274 on the insulator 282, and an insulator 281 on the insulator 274. The insulators 214, 280, 282, 274, and 281 function as interlayer films. A conductor 247 is provided that is electrically connected to the transistor 200 and functions as a plug. A conductor 240 (conductor 240a and conductor 240b) is also provided that is electrically connected to the transistor 200 and functions as a plug. An insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. Furthermore, conductors 246 (conductors 246a and 246b) are provided on the insulator 281 and on the conductor 240, electrically connected to the conductor 240 and functioning as wiring.

[0052] Furthermore, an insulator 241a is provided in contact with the inner wall of the opening of insulators 272, 273, 280, 282, 274, and 281, a first conductor of conductor 240a is provided in contact with its side surface, and a second conductor of conductor 240a is provided further inside. Also, an insulator 241b is provided in contact with the inner wall of the opening of insulators 272, 273, 280, 282, 274, and 281, a first conductor of conductor 240b is provided in contact with its side surface, and a second conductor of conductor 240b is provided further inside. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 281 can be made to be approximately the same. Note that the present invention is shown as a configuration in which the first conductor and the second conductor of conductor 240 are stacked, but the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or as a laminated structure of three or more layers. Furthermore, the first conductor of the conductor 247 is provided in contact with the inner wall of the opening of the insulators 214, 216, 222, and 224, and the second conductor of the conductor 247 is provided further inside. While the present invention describes a configuration in which the first and second conductors of the conductor 247 are laminated, the present invention is not limited to this. For example, the conductor 247 may be provided as a single layer or as a laminated structure of three or more layers. When a structure has a laminated structure, ordinal numbers may be assigned to distinguish the layers in order of formation.

[0053] [Transistor 200] As shown in Figure 1, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243a and an oxide 243b on the oxide 230b, and a conductive material in contact with a portion of the upper surface of the insulator 224, the side of the oxide 230a, the side of the oxide 230b, the side of the oxide 243a, and the upper surface of the oxide 243a. The material comprises body 242a, a conductor 242b in contact with a portion of the upper surface of insulator 224, the side surface of oxide 230a, the side surface of oxide 230b, the side surface of oxide 243b, and the upper surface of oxide 243b, oxide 230c on oxide 230b, insulator 250 on oxide 230c, conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with oxide 230c, insulator 272 in contact with a portion of the upper surface of insulator 224, the side surface of conductor 242a, the upper surface of conductor 242a, the side surface of conductor 242b, and the upper surface of conductor 242b, and insulator 273 on insulator 272. Furthermore, oxide 230c is in contact with the side surface of oxide 243a and the side surface of oxide 243b, respectively. The conductor 260 has conductor 260a and conductor 260b, with conductor 260a positioned to enclose the bottom and sides of conductor 260b. Here, as shown in Figure 1(B), the top surface of conductor 260 is positioned to substantially coincide with the top surface of insulator 250 and the top surface of oxide 230c. In addition, insulator 282 is in contact with the top surfaces of conductor 260, oxide 230c, insulator 250, and insulator 280, respectively.

[0054] Furthermore, openings are formed in the insulators 214, 216, 222, and 224, and the conductor 247 is arranged within these openings. At least a portion of the upper surface of the conductor 247 is exposed from the insulator 224, and it is preferable that the upper surface of the conductor 247 and the upper surface of the insulator 224 substantially coincide. In addition, the conductor 247 may be configured not to overlap with oxides 230a and 230b.

[0055] Here, the conductor 247 is electrically connected to circuit elements such as switches, transistors, capacitive elements, inductors, resistive elements, and diodes, as well as wiring, electrodes, or terminals, which are located in a layer below the insulator 214. For example, the conductor 247 may be configured to be electrically connected to the gate of a transistor located in a layer below the insulator 214. Alternatively, for example, the conductor 247 may be configured to be electrically connected to one of the electrodes of a capacitive element located in a layer below the insulator 214.

[0056] Furthermore, the conductor 242b is placed on the oxide 243b and the conductor 247. The conductor 242b is in contact with at least a portion of the upper surface of the conductor 247. By connecting the conductor 242b and the conductor 247 in this way, the electrical resistance between the source or drain of the transistor 200 and the conductor 247 can be reduced. In addition, by not superimposing the conductor 247 with the oxides 230a and 230b, and instead covering the upper surface of the conductor 247 with the conductor 242b, the electrical resistance between the source or drain of the transistor 200 and the conductor 247 can be further reduced.

[0057] This configuration improves the frequency characteristics and electrical characteristics of the semiconductor device, including transistor 200.

[0058] Furthermore, it is preferable that at least a portion of circuit elements such as switches, transistors, capacitive elements, inductors, resistive elements, and diodes, wiring, electrodes, or terminals that are electrically connected to the conductor 247 are superimposed on the oxide 230. This reduces the area occupied by the transistor 200, the circuit elements, wiring, electrodes, or terminals in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0059] The conductor 242b may be provided in contact with the side surface of oxide 243b, the side surface of oxide 230a, and the side surface of oxide 230b.

[0060] Furthermore, although Figures 1(A) and 1(B) show a configuration in which conductor 247 is provided below conductor 242b, the semiconductor device shown in this embodiment is not limited to this. For example, conductor 247 may be provided below conductor 242a, or conductor 247 may be provided below both conductor 242a and conductor 242b.

[0061] Furthermore, it is preferable that insulators 222, 272, 273, and 282 have a function to suppress the diffusion of at least one of the hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). It is also preferable that insulators 222, 272, 273, and 282 have a function to suppress the diffusion of at least one of the oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, it is preferable that insulators 222, 272, 273, and 282 have lower permeability to oxygen and hydrogen, or both, than insulator 224. It is preferable that insulators 222, 272, 273, and 282 have lower permeability to oxygen and hydrogen, or both, than insulator 250. It is preferable that insulators 222, 272, 273, and 282 have lower permeability to oxygen and hydrogen, or both, than insulator 280.

[0062] As shown in Figure 1(B), it is preferable that the insulator 272 is in contact with the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, and the top surface of the insulator 224. It is also preferable that the insulator 273 is in contact with the insulator 272. As a result, the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulators 272 and 273.

[0063] Furthermore, it is preferable that the oxide 230 comprises an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230c disposed on the oxide 230b, with at least a portion of it in contact with the upper surface of the oxide 230b.

[0064] In the transistor 200, a configuration is shown in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers may be provided. Also, in the transistor 200, the conductor 260 is shown as a two-layer stacked structure. However, the present invention is not limited to this. For example, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers.

[0065] Here, the conductor 260 functions as the gate electrode of the transistor, while the conductors 242a and 242b function as the source electrode or drain electrode, respectively. The transistor 200 is formed in a self-aligning manner such that the conductor 260, which functions as the gate electrode, fills an opening formed by the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0066] Furthermore, it is preferable that the transistor 200 uses a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) which includes the channel formation region.

[0067] The transistor 200, which uses an oxide semiconductor in the channel formation region, exhibits extremely low leakage current (off-current) in the non-conductive state, thus enabling the provision of a low-power semiconductor device. Furthermore, since oxide semiconductors can be deposited using methods such as sputtering, they can be used in transistors 200 that constitute highly integrated semiconductor devices.

[0068] For example, as oxide 230, metal oxides such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. In particular, element M should be aluminum, gallium, yttrium, or tin. Alternatively, In-Ga oxide or In-Zn oxide may be used as oxide 230.

[0069] Furthermore, in transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may deteriorate if impurities and oxygen vacancies are present in the region where the channel is formed within the oxide semiconductor. Also, if oxygen vacancies are present in the region where the channel is formed within the oxide semiconductor, the transistor tends to exhibit normally-on characteristics. Therefore, it is preferable to reduce oxygen vacancies in the region where the channel is formed as much as possible. For example, oxygen can be supplied to the oxide 230 via an insulator 250 or the like to compensate for the oxygen vacancies. This makes it possible to provide a transistor that suppresses fluctuations in electrical properties, has stable electrical properties, and has improved reliability.

[0070] Furthermore, as shown in Figure 1(B), in the transistor 200, oxide 243 (oxide 243a and oxide 243b) is arranged between the upper surface of oxide 230b and the lower surface of conductor 242 (conductors 242a and 242b). Since the conductor 242 and most of the oxide 230 do not come into contact, the absorption of oxygen from the oxide 230 by the conductor 242 can be reduced. In other words, by preventing the oxidation of the conductor 242, the decrease in the conductivity of the conductor 242 can be suppressed. Therefore, it is preferable that oxide 243 has the function of suppressing the oxidation of the conductor 242.

[0071] Furthermore, it is preferable that the oxide 243 is conductive. Placing the conductive oxide 243 between the conductor 242, which functions as a source electrode and a drain electrode, and the oxide 230b is preferable because it reduces the electrical resistance between the conductor 242 and the oxide 230b. This configuration can improve the electrical characteristics and reliability of the transistor 200. Note that the oxide 243 may have a crystalline structure.

[0072] As oxide 243, an oxide containing zinc can be used. For example, zinc oxide, gallium zinc oxide, indium zinc oxide, indium gallium zinc oxide, etc. can be used. Alternatively, indium oxide, indium tin oxide, etc. may be used. Furthermore, oxide 243 is preferably a metal oxide with high bond energy between metal atoms and oxygen atoms. Furthermore, the conductivity of oxide 243 is preferably higher than that of oxide 230 (oxide 230a, oxide 230b, and oxide 230c). Furthermore, the film thickness of oxide 243 is preferably 1 nm to 10 nm, and more preferably 1 nm to 5 nm. Furthermore, oxide 243 is preferably crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be suitably suppressed. For example, if oxide 243 has a crystalline structure such as hexagonal, the release of oxygen from oxide 230 can be suppressed.

[0073] In one aspect of the present invention, the transistor 200 has a structure in which the insulator 282 and the insulator 250 are in direct contact, as shown in Figures 1(B) and 1(C). This structure makes it difficult for oxygen contained in the insulator 280 to be absorbed by the conductor 260. Therefore, the oxygen contained in the insulator 280 can be efficiently injected into the oxides 230a and 230b via the oxide 230c, thereby reducing oxygen deficiencies in the oxides 230a and 230b and improving the electrical characteristics and reliability of the transistor 200. Furthermore, the incorporation of impurities such as hydrogen contained in the insulator 280 into the insulator 250 can be suppressed, thus reducing adverse effects on the electrical characteristics and reliability of the transistor 200. As the insulator 282, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be used. Silicon nitride is particularly preferred as the insulator 282. This silicon nitride can effectively block impurities that may enter from the outside (e.g., hydrogen, water, etc.).

[0074] It is preferable that the insulators 272 and 273 have the function of suppressing the permeation of impurities such as hydrogen and water, and oxygen.

[0075] Figure 3(A) is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1(A), and is also a cross-sectional view of the source region or drain region of transistor 200 in the channel width direction. As shown in Figure 3(A), the top surface and side surfaces of the conductor 242b are covered with insulators 272 and 273, respectively, so that the diffusion of impurities such as hydrogen and water, as well as oxygen, into the conductor 242b from the side surfaces and the top surface of the conductor 242b can be suppressed. Therefore, the diffusion of oxygen into the conductor 242b from its surroundings can be suppressed, and thus the oxidation of the conductor 242b can be suppressed. The same effect is also observed for the conductor 242a. Furthermore, the diffusion of impurities such as hydrogen and water into oxide 230a and oxide 230b from the side surfaces of oxide 230a and oxide 230b can be suppressed. For example, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used as the insulator 272. For example, aluminum oxide or hafnium oxide can be used as the insulator 273.

[0076] Figure 3(B) is a cross-sectional view of the area indicated by the dashed line A7-A8 in Figure 1(A), and is also a cross-sectional view in the channel width direction of the conductor 240b, which is electrically connected to the transistor 200 and functions as a plug. As shown in Figure 3(B), the conductor 240b is provided in contact with the upper surface of the conductor 242b. Since the insulator 241b is arranged on the side surface of the conductor 240b, the diffusion of impurities such as hydrogen and water, as well as oxygen, from the insulator 280 to the conductor 240b can be suppressed. The same effect is also present for the conductor 240a.

[0077] As shown in Figures 1(A)(B) and 3(B), it is preferable that the conductor 240b is provided superimposed on at least a portion of the conductor 247. This reduces the area occupied by the conductor 240b and the conductor 247 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0078] Furthermore, as shown in Figure 1(C), with reference to the bottom surface of the insulator 224, it is preferable that the height of the bottom surface of the conductor 260 in the region where the oxide 230a and oxide 230b and the conductor 260 do not overlap is lower than the height of the bottom surface of the oxide 230b. Also, the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230b and the conductor 260 do not overlap is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0079] Thus, the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, making it easier for the electric field of the conductor 260 to act on the entire oxide 230b in the channel formation region. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0080] Based on the above, it is possible to provide a miniaturized or highly integrated semiconductor device. Alternatively, it is possible to provide a semiconductor device having a transistor with a large on-current. Alternatively, it is possible to provide a semiconductor device having a transistor with high frequency characteristics. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and improves reliability. Alternatively, it is possible to provide a semiconductor device having a transistor with a small off-current.

[0081] The following describes the detailed configuration of a semiconductor device having a transistor 200 according to one aspect of the present invention.

[0082] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Furthermore, it is preferable that the conductor 205 is embedded in the insulators 214 and 216.

[0083] Here, the conductor 260 may function as the first gate (also called the top gate) electrode. Also, the conductor 205 may function as the second gate (also called the bottom gate) electrode. In that case, the Vth of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking them. In particular, by applying a negative potential to conductor 205, it is possible to make the Vth of transistor 200 greater than 0V and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0084] Furthermore, as shown in Figure 1(A), the conductor 205 should be larger than the size of the region of the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in Figure 1(C), it is preferable that the conductor 205 extends to the region outside the end that intersects the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the oxide 230 via an insulator. Alternatively, by making the conductor 205 larger, it may be possible to mitigate local charging (called charge-up) in the plasma processing of the manufacturing process after the formation of the conductor 205. However, one aspect of the present invention is not limited to this. The conductor 205 only needs to be superimposed on the oxide 230 located between at least the conductor 242a and the conductor 242b.

[0085] With the above configuration, the channel formation region can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0086] Furthermore, the conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Also, the conductor 205b is preferably a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is shown as two layers, it may also be a multilayer structure of three or more layers.

[0087] Insulators 214, 272, and 281 preferably function as barrier insulating films that suppress the ingress of impurities such as water or hydrogen into the transistor 200 from the substrate side or from above. Therefore, it is preferable to use insulating materials for insulators 214, 272, and 281 that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use insulating materials that have the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable).

[0088] For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. This makes it possible to suppress the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200 side above insulator 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in insulator 224, etc., towards the substrate side above insulator 214. Furthermore, it is possible to suppress the diffusion of impurities such as water or hydrogen from insulator 280, and / or conductor 246, etc., which are positioned above insulator 272, towards the transistor 200 side.

[0089] Furthermore, it may be preferable to lower the resistivity of insulators 214, 272, and 281. For example, the resistivity of insulators 214, 272, and 281 may be approximately 1 × 10⁻⁶. 13By setting the resistivity to Ωcm, insulators 214, 272, and 281 may be able to mitigate the charge-up of conductors 205, 242, or 260 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 214, 272, and 281 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0090] Furthermore, the insulator 214 may have a multilayer structure. For example, a multilayer structure of an aluminum oxide film and a silicon nitride film is preferable for the insulator 214. The aluminum oxide film can supply oxygen to the area below the insulator 214. In addition, the silicon nitride film can suppress the diffusion of impurities such as hydrogen and water that diffuse from the substrate side to the transistor 200 side.

[0091] Furthermore, it is preferable that insulators 216, 280, and 274 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide may be used as insulators 216, 280, and 274.

[0092] Insulators 222 and 224 function as gate insulators.

[0093] Here, it is preferable that the insulator 224 in contact with the oxide 230 desorbs oxygen by heating. In this specification, the oxygen that is desorbed by heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be silicon oxide or silicon oxynitride, etc., as appropriate. By providing an oxygen-containing insulator in contact with the oxide 230, the oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0094] As the insulator 224, specifically, it is preferable to use an oxide material in which some oxygen is desorbed by heating. An oxide that desorbs oxygen by heating means that, in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0095] The insulator 222 preferably functions as a barrier insulating film that suppresses the mixing of impurities such as water or hydrogen into the transistor 200 from the substrate side. For example, it is preferable that the insulator 222 has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, etc. with the insulator 222 and the insulator 272, it is possible to suppress the intrusion of impurities such as water or hydrogen from the outside into the transistor 200.

[0096] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (The above oxygen is difficult to permeate.) For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, it is possible to reduce the diffusion of the oxygen possessed by the oxide 230 to the lower side of the insulator 222, which is preferable. Also, it is possible to suppress the reaction of the conductor 205 with the oxygen possessed by the insulator 224 and the oxide 230.

[0097] The insulator 222 may be an insulator containing an oxide of either or both aluminum and hafnium, which are insulating materials. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the incorporation of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0098] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the above insulators.

[0099] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0100] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials.

[0101] The conductor 247, like the conductor 205, may have a configuration comprising a first conductive layer and a second conductive layer disposed inside the first conductive layer. The first conductive layer of the conductor 247 is preferably made of a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Furthermore, the second conductive layer of the conductor 247 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 247 is shown as having two layers, it may also have a multilayer structure of three or more layers.

[0102] Furthermore, similar to the conductor 240, an insulator may be provided on the side surface of the conductor 247 to suppress the diffusion of impurities such as hydrogen and water, as well as oxygen, similar to the insulator 241.

[0103] Oxide 230 comprises oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. Having oxide 230a below oxide 230b suppresses the diffusion of impurities from structures formed below oxide 230a to oxide 230b. Furthermore, having oxide 230c on oxide 230b suppresses the diffusion of impurities from structures formed above oxide 230c to oxide 230b.

[0104] Furthermore, it is preferable that oxide 230 has a layered structure made up of oxides with different atomic ratios of each metal atom. Specifically, it is preferable that the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 230a is greater than the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 230b. Also, it is preferable that the atomic ratio of element M to In in the metal oxide used for oxide 230a is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. In addition, oxide 230c can be any metal oxide that can be used for oxide 230a or oxide 230b.

[0105] Furthermore, it is preferable that the oxide 230b is crystalline. For example, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor), which will be described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0106] Furthermore, it is preferable that the energy at the lower end of the conduction band of oxide 230a and oxide 230c is higher than the energy at the lower end of the conduction band of oxide 230b. In other words, it is preferable that the electron affinity of oxide 230a and oxide 230c is smaller than the electron affinity of oxide 230b.

[0107] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junctions of oxide 230a, oxide 230b, and oxide 230c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c.

[0108] Specifically, for oxide 230a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. For oxide 230b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 1:1:1 may be used. For oxide 230c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Furthermore, specific examples of layered structures for oxide 230c include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0109] In this case, the main carrier pathway is oxide 230b. By configuring oxide 230a and oxide 230c as described above, the defect level density at the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c, can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain high on-current and high frequency characteristics. Furthermore, when oxide 230c is made into a multilayer structure, in addition to the effect of reducing the defect level density at the interface between oxide 230b and oxide 230c as described above, it is expected that the constituent elements of oxide 230c will be suppressed from diffusing to the insulator 250 side. More specifically, by making oxide 230c into a multilayer structure and positioning an oxide that does not contain In on top of the multilayer structure, it is possible to suppress In that could diffuse to the insulator 250 side. Since insulator 250 functions as a gate insulator, if In diffuses, it will result in a defect in the transistor's characteristics. Therefore, by making oxide 230c into a multilayer structure, it is possible to provide a highly reliable semiconductor device.

[0110] For oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. For example, it is preferable to use one with an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large energy gap in this way, the off-current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0111] The electron affinity or energy level Ec at the bottom of the conduction band can be determined from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg, as shown in Figure 12. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) instrument. The energy gap Eg can be measured, for example, using a spectroscopic ellipsometer.

[0112] On the oxide 230b, oxide 243 is provided, and on the oxide 243, conductors 242 (conductors 242a and 242b) that function as source electrodes and drain electrodes are provided. The film thickness of conductor 242 may be, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.

[0113] As the conductor 242, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0114] The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper surface of the oxide 230c. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable.

[0115] Similar to insulator 224, it is preferable that insulator 250 be formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as insulator 250 in contact with the upper surface of oxide 230c, oxygen can be effectively supplied to the channel formation region of oxide 230b. Also, similar to insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in insulator 250 is reduced. The film thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0116] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0117] Furthermore, the metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0118] Specifically, metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used. In particular, it is preferable to use insulators containing oxides of aluminum, hafnium, or both, such as aluminum oxide, hafnium oxide, or oxides containing aluminum and hafnium (hafnium aluminate).

[0119] Alternatively, the metal oxide may function as part of the gate electrode. In this case, it is preferable to provide an oxygen-containing conductive material on the channel-forming region side. By providing an oxygen-containing conductive material on the channel-forming region side, oxygen released from the conductive material is more easily supplied to the channel-forming region.

[0120] In particular, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0121] Although the conductor 260 is shown as a two-layer structure in Figure 1, it may also be a single-layer structure or a laminated structure of three or more layers.

[0122] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0123] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0124] Furthermore, it is preferable that the conductor 260b be made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 260 functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive material.

[0125] The insulator 280 preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0126] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Furthermore, the upper surface of the insulator 280 may be flattened.

[0127] The insulator 282 preferably functions as a barrier insulating film that suppresses the incorporation of impurities such as water or hydrogen into the insulator 280 from above. As the insulator 282, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used.

[0128] Furthermore, it is preferable to provide an insulator 274, which functions as an interlayer film, on top of the insulator 282. Similar to the insulator 224, it is preferable that the insulator 274 has a reduced concentration of impurities such as water or hydrogen in its film.

[0129] It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure.

[0130] Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen for the conductors that are in contact with the insulators 281, 274, 282, 280, 273, and 272. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. The conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen may be used in a single layer or in a laminate. By using such a conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a and 240b. In addition, it is possible to suppress the mixing of impurities such as water or hydrogen from the layer above the insulator 281 into the oxide 230 through the conductors 240a and 240b.

[0131] For example, insulators such as aluminum oxide, silicon nitride, or silicon oxide nitride may be used as insulators 241a and 241b. Since insulators 241a and 241b are provided in contact with insulators 272 and 273, it is possible to suppress the incorporation of impurities such as water or hydrogen from insulator 280, etc., into the oxide 230 through conductors 240a and 240b. Furthermore, it is possible to prevent oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0132] Furthermore, conductors 246 (conductors 246a and 246b) that function as wiring may be placed in contact with the upper surfaces of conductors 240a and 240b. It is preferable that the conductors 246 be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductors may also be in a laminated structure, for example, a laminate of titanium, titanium nitride, and the conductive material. The conductors may also be formed to be embedded in openings provided in the insulator.

[0133] In the semiconductor device shown in Figure 1, a conductor 240b, an insulator 241b, and a conductor 246b are provided, but a configuration without these elements is also possible.

[0134] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0135] <Circuit board> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0136] <insulator> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0137] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0138] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0139] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0140] Furthermore, the electrical properties of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxide nitride, or silicon nitride can be used.

[0141] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0142] <Conductive material> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0143] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0144] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0145] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0146] <Metal oxides> It is preferable to use a metal oxide that functions as an oxide semiconductor as the oxide 230. Below, metal oxides applicable to the oxide 230 according to the present invention will be described.

[0147] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, or tin. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0148] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M can be aluminum, gallium, yttrium, or tin, for example. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, it is sometimes permissible to use a combination of multiple of the aforementioned elements as element M.

[0149] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0150] [Structure of metal oxides] Oxide semiconductors (metal oxides) can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0151] CAAC-OS has a c-axis orientation and a crystal structure in which multiple nanocrystals are linked in the ab-plane direction, resulting in a strained structure. The strain refers to the region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement, within the region where multiple nanocrystals are linked.

[0152] Nanocrystals are based on a hexagonal structure, but they are not necessarily regular hexagons and may have non-regular hexagonal shapes. Furthermore, under strain, they may have lattice arrangements such as pentagons and heptagons. In CAAC-OS, however, it is difficult to observe clear grain boundaries (also called grain boundaries) even near strain. This indicates that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is because CAAC-OS can tolerate strain due to factors such as the sparse arrangement of oxygen atoms in the ab-plane and the change in interatomic bond distances caused by the substitution of metal elements.

[0153] Furthermore, CAAC-OS tends to have a layered crystalline structure (also called a layered structure) in which layers containing indium and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are stacked. Note that indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be represented as the (In,M,Zn) layer. Similarly, when indium in the In layer is substituted with element M, it can also be represented as the (In,M) layer.

[0154] CAAC-OS is a highly crystalline metal oxide. On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Also, the crystallinity of metal oxides can decrease due to the inclusion of impurities or the formation of defects, so CAAC-OS is less susceptible to impurities and defects (oxygen vacancies (V OAlso known as oxygen vacancy, it can be said to be a metal oxide with low levels of (etc.). Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0155] nc-OS exhibits periodicity in atomic arrangement within minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). Furthermore, nc-OS lacks regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed across the entire film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors.

[0156] Furthermore, indium-gallium-zinc oxide (IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes adopt a stable structure when formed into the nanocrystals described above. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, smaller crystals (for example, the nanocrystals described above) may be structurally more stable than larger crystals (here, crystals of several millimeters or several centimeters).

[0157] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. In other words, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0158] Oxide semiconductors (metal oxides) can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0159] In one embodiment of the present invention, there are no particular limitations on the structure of the oxide semiconductor (metal oxide), but it is preferable that it has crystalline properties. For example, oxide 230 can have a CAAC-OS structure, and oxide 243 can have a hexagonal crystalline structure. By having oxide 230 and oxide 243 have the above crystalline structures, a semiconductor device with high reliability can be made.

[0160] [impurities] Here, we will explain the effects of various impurities in metal oxides.

[0161] Furthermore, if a metal oxide contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using metal oxides containing alkali metals or alkaline earth metals in the channel formation region tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of alkali metals or alkaline earth metals in the metal oxide obtained by SIMS (concentration obtained by secondary ion mass spectrometry (SIMS)) should be reduced to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0162] Furthermore, hydrogen contained in metal oxides can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms, generating electrons. Therefore, transistors using metal oxides containing hydrogen tend to exhibit normally-on characteristics.

[0163] Therefore, it is preferable that the hydrogen content in the metal oxide be reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶.20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 The impurities should be less than [amount missing]. By using metal oxides with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0164] It is preferable to use a highly crystalline thin film as the metal oxide used in the semiconductor of a transistor. Using such a thin film can improve the stability or reliability of the transistor. Examples of such thin films include thin films of single-crystal metal oxides or thin films of polycrystalline metal oxides. However, forming thin films of single-crystal metal oxides or polycrystalline metal oxides on a substrate requires high-temperature or laser heating processes. Therefore, the manufacturing cost increases, and throughput also decreases.

[0165] Non-Patent Documents 1 and 2 reported the discovery of an In-Ga-Zn oxide with a CAAC structure (referred to as CAAC-IGZO) in 2009. These documents reported that CAAC-IGZO has c-axis orientation, clearly defined grain boundaries, and can be formed on a substrate at low temperatures. Furthermore, transistors using CAAC-IGZO were reported to possess excellent electrical properties and reliability.

[0166] Furthermore, in 2013, an In-Ga-Zn oxide with an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Literature 3). It was reported that nc-IGZO has periodicity in the atomic arrangement in minute regions (for example, regions between 1 nm and 3 nm), and that no regularity is observed in the crystal orientation between different such regions.

[0167] Non-patent documents 4 and 5 show the changes in average crystal size of thin films of CAAC-IGZO, nc-IGZO, and low-crystallinity IGZO after electron beam irradiation. In the low-crystallinity IGZO thin film, crystalline IGZO of about 1 nm was observed even before electron beam irradiation. Therefore, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, it has been shown that CAAC-IGZO thin films and nc-IGZO thin films have higher stability against electron beam irradiation compared to low-crystallinity IGZO thin films. Therefore, it is preferable to use CAAC-IGZO thin films or nc-IGZO thin films as semiconductors for transistors.

[0168] Transistors using metal oxides exhibit extremely low leakage current in the non-conductive state; specifically, the off-current per 1 μm of channel width is yA / μm(10 -24 Non-patent document 6 shows that the order is on the order of A / μm. For example, a low-power CPU that takes advantage of the low leakage current characteristic of transistors using metal oxides has been disclosed (see Non-patent document 7).

[0169] Furthermore, applications of transistors using metal oxides to display devices have been reported, taking advantage of their low leakage current characteristic (see Non-Patent Document 8). In display devices, the displayed image switches dozens of times per second. The number of image switches per second is called the refresh rate. The refresh rate is also sometimes called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is considered to be a cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device to reduce the number of image rewrites. In addition, it is possible to reduce the power consumption of the display device by driving with a reduced refresh rate. This driving method is called idling stop (IDS) driving.

[0170] The discovery of CAAC and nc structures has contributed to improving the electrical properties and reliability of transistors using metal oxides with CAAC or nc structures, as well as reducing manufacturing costs and increasing throughput. Furthermore, research is underway on the application of these transistors to display devices and LSIs, taking advantage of their low leakage current characteristics.

[0171] <Method for fabricating semiconductor devices> Next, the manufacturing method of the semiconductor device having the transistor 200 according to the present invention, as shown in Figure 1, will be explained using Figures 4 to 11. In Figures 4 to 11, (A) in each figure shows a top view. (B) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. (C) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the top view (A) of each figure, some elements have been omitted for clarity.

[0172] First, a substrate (not shown) is prepared, and an insulator 214 is deposited on the substrate. The insulator 214 can be deposited using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD).

[0173] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo-CVD (Photo-CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0174] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0175] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in advantages such as the ability to deposit extremely thin films, deposit films on structures with high aspect ratios, deposit films with fewer defects such as pinholes, deposit films with excellent coverage, and deposit films at low temperatures. The ALD method also includes the PEALD (Plasma Enhanced ALD) method, which utilizes plasma. Using plasma allows for deposit films at even lower temperatures, which is sometimes preferable. It should be noted that precursors used in the ALD method may contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other deposition methods. The quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0176] Unlike film deposition methods where particles emitted from a target or other source are deposited, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and offer good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method.

[0177] CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases during film deposition. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0178] In this embodiment, silicon nitride is deposited as the insulator 214 by CVD. By using an insulator such as silicon nitride, which is impermeable to copper, as the insulator 214, even if a diffusive metal such as copper is used in the conductor layer below the insulator 214 (not shown), it is possible to suppress the diffusion of the metal into the layer above the insulator 214.

[0179] Next, an insulator 216 is deposited on the insulator 214. The insulator 216 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0180] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening includes, for example, grooves and slits. In some cases, the term "opening" refers to the region in which the opening is formed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if a silicon oxide film is used for the insulator 216 in which grooves are formed, then a silicon nitride film, an aluminum oxide film, or a hafnium oxide film may be used for the insulator 214.

[0181] After the opening is formed, a conductive film that will become the conductor 205 is deposited. It is desirable that the conductive film contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be formed. The conductive film that will become the conductor 205 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0182] In this embodiment, the conductive film that becomes the conductor 205 is made of multiple layers. First, tantalum nitride is deposited by sputtering, and titanium nitride is laminated on top of the tantalum nitride. By using such a metal nitride as the lower layer of the conductive film that becomes the conductor 205, even if a highly diffusible metal such as copper is used as the upper layer conductive film that becomes the conductor 205, it is possible to prevent the metal from diffusing out of the conductor 205.

[0183] Next, a conductive film is formed on top of the conductive film that will become the conductor 205. This conductive film can be formed using methods such as plating, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film on top of the conductive film that will become the conductor 205.

[0184] Next, by performing a CMP (Chemical Polishing) treatment, the upper layer of the conductive film that will become the conductor 205, as well as a portion of the lower layer of the conductive film that will become the conductor 205, are removed, exposing the insulator 216. As a result, the conductive film that will become the conductor 205 remains only in the opening. This makes it possible to form a conductor 205 with a flat upper surface. Note that in some cases, a portion of the insulator 216 may be removed by this CMP treatment (see Figure 4).

[0185] From here, a different method for forming the conductor 205 will be described below.

[0186] A conductive film, which will become the conductor 205, is deposited on the insulator 214. The conductive film that will become the conductor 205 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. Furthermore, the conductive film that will become the conductor 205 can be a multilayer film. In this embodiment, tungsten is deposited as the conductive film that will become the conductor 205.

[0187] Next, a conductive film that will become the conductor 205 is processed using lithography to form the conductor 205.

[0188] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, electron beams or ion beams can be used instead of the aforementioned light. When using electron beams or ion beams, a mask is not required. To remove the resist mask, dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching can be performed.

[0189] Alternatively, a hard mask made of an insulator or conductor may be used instead of a resist mask. When using a hard mask, an insulating film or conductive film that will become the hard mask material is formed on the conductive film that will become the conductor 205, a resist mask is formed on top of that, and a hard mask of the desired shape can be formed by etching the hard mask material. The etching of the conductive film that will become the conductor 205 may be performed after removing the resist mask, or it may be performed while the resist mask is still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching the conductive film that will become the conductor 205. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0190] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power supplies of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0191] Next, an insulating film that will become an insulator 216 is deposited on the insulator 214 and the conductor 205. The insulating film that will become an insulator 216 can be deposited using sputtering, CVD, MBE, PLD, or ALD, etc. In this embodiment, silicon oxide is deposited as the insulating film that will become an insulator 216 by the CVD method.

[0192] Here, it is preferable that the thickness of the insulating film that becomes the insulator 216 is greater than or equal to the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, then the thickness of the insulating film that becomes the insulator 216 is between 1 and 3. In this embodiment, the thickness of the conductor 205 is 150 nm, and the thickness of the insulating film that becomes the insulator 216 is 350 nm.

[0193] Next, the insulating film that will become the insulator 216 is subjected to CMP (chemical mechanical polishing) treatment to remove a portion of the insulating film that will become the insulator 216, exposing the surface of the conductor 205. This makes it possible to form a conductor 205 and an insulator 216 with flat top surfaces. The above describes different methods for forming the conductor 205. Figure 2 shows an example of a semiconductor device having a transistor 200 in which the conductor 205 and insulator 216 have been formed as described above.

[0194] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205. It is preferable to deposit an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the formation of oxygen vacancies in the oxide 230.

[0195] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0196] Next, an insulator 224 is deposited on the insulator 222. The insulator 224 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0197] Next, openings are formed in insulators 224, 222, 216, and 214. While wet etching may be used to form the openings, dry etching is preferable for microfabrication.

[0198] After the opening is formed, a conductive film that will become the conductor 247 is deposited. It is desirable that the conductive film contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be formed. The conductive film that will become the conductor 247 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0199] Next, a CMP (Chemical Polymer Measure) treatment is performed to remove a portion of the conductive film that will become the conductor 247, exposing the insulator 224. As a result, the conductive film that will become the conductor 247 remains only in the opening. This makes it possible to form a conductor 247 with a flat top surface. Note that this CMP treatment may remove a portion of the insulator 224 (see Figure 4).

[0200] Next, it is preferable to perform a heat treatment. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by a heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0201] In this embodiment, the material is treated in a nitrogen atmosphere at a temperature of 400°C for 1 hour, followed by a continuous treatment in an oxygen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 224.

[0202] Furthermore, the heat treatment may be performed after the insulator 222 has been formed. The heat treatment conditions described above can be used for this heat treatment.

[0203] Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use a device that has a power supply that generates high-density plasma using microwaves, for example. Alternatively, the substrate side may have a power supply that applies RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. By appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, heating treatment does not need to be performed.

[0204] Here, aluminum oxide may be deposited on the insulator 224, for example, by sputtering, and CMP may be performed on the aluminum oxide until it reaches the insulator 224. Performing CMP can planarize and smooth the surface of the insulator 224. Placing the aluminum oxide on the insulator 224 and performing CMP makes it easier to detect the end point of CMP. In addition, CMP may polish a part of the insulator 224, causing the film thickness of the insulator 224 to become thinner, but this can be corrected by adjusting the film thickness during the deposition of the insulator 224. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent deterioration of the coverage rate of the oxide film deposited later and prevent a decrease in the yield of the semiconductor device. Furthermore, depositing aluminum oxide on the insulator 224 by sputtering is preferable because it allows oxygen to be added to the insulator 224.

[0205] Next, an oxide film 230A, which will become oxide 230a, and an oxide film 230B, which will become oxide 230b, are sequentially deposited on the insulator 224 and the conductor 247 (see Figure 4). It is preferable to deposit the oxide films continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to the oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0206] The oxide films 230A and 230B can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0207] For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above In-M-Zn oxide target can be used.

[0208] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen in the sputtering gas for the oxide film 230A should be 70% or more, preferably 80% or more, and more preferably 100%.

[0209] Furthermore, when forming the oxide film 230B by sputtering, if the oxygen content in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can obtain relatively high field-effect mobility.

[0210] In this embodiment, oxide film 230A is formed by sputtering using a target with an In:Ga:Zn ratio of 1:1:0.5 (2:2:1) or 1:3:4. Oxide film 230B is formed by sputtering using a target with an In:Ga:Zn ratio of 4:2:4.1 or 1:1:1. Note that each oxide film should be formed according to the desired properties of oxide 230 by appropriately selecting the deposition conditions and atomic ratios.

[0211] Next, a heat treatment may be performed. The heat treatment conditions described above can be used. The heat treatment can remove impurities such as water and hydrogen from the oxide film 230A and oxide film 230B. In this embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere, followed by a continuous treatment at a temperature of 400°C for 1 hour in an oxygen atmosphere.

[0212] Next, an oxide film 243A is deposited on the oxide film 230B. The oxide film 243A can be deposited using sputtering, CVD, MBE, PLD, or ALD (see Figure 4).

[0213] Next, oxide films 230A, 230B, and 243A are processed into island-like structures to form oxides 230a, 230b, and 243B (see Figure 5). Here, at least a portion of the upper surface of the conductor 247 is exposed from oxide films 230A, 230B, and 243A. Alternatively, oxide films 230A, 230B, and 243A do not overlap with the conductor 247. Although not shown in the figures, in this step, the film thickness of the region of the insulator 224 that does not overlap with oxide 230a may become thinner.

[0214] Furthermore, oxides 230a, 230b, and oxide layer 243B are formed so that at least a portion of them overlaps with the conductor 205. It is also preferable that the sides of oxides 230a, 230b, and oxide layer 243B are approximately perpendicular to the upper surface of the insulator 222. Having the sides of oxides 230a, 230b, and oxide layer 243B approximately perpendicular to the upper surface of the insulator 222 allows for smaller area and higher density when providing multiple transistors 200. Alternatively, the angle between oxides 230a, 230b, and oxide layer 243B and the upper surface of the insulator 222 may be low. In that case, the angle between the sides of oxides 230a, 230b, and oxide layer 243B and the upper surface of the insulator 222 is preferably 60° or more and less than 70°. This shape improves the coverage of the insulator 272 and other materials in subsequent processes, reducing defects such as porosity.

[0215] The oxide film and conductive film can be processed using lithography. Furthermore, either dry etching or wet etching methods can be used for this process. Dry etching is suitable for microfabrication.

[0216] Next, a conductive film 242A is deposited on the insulator 224, oxide 230a, oxide 230b, and oxide layer 243B. The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, or ALD (see Figure 5).

[0217] Next, the conductive film 242A is processed into island-like structures to form the conductive layer 242B (see Figure 6). Here, the conductive layer 242B is made to be in contact with at least a portion of the upper surface of the conductor 247. Alternatively, the conductive layer 242B is made to cover the upper surface of the conductor 247. Although not shown in the figures, in this step, the film thickness of the insulator 224 in areas that do not overlap with the conductive layer 242B may become thinner.

[0218] Furthermore, it is preferable that there is a curved surface between the side surface and the top surface of the conductive layer 242B. In other words, it is preferable that the ends of the side surface and the ends of the top surface are curved (hereinafter also referred to as rounded). For example, at the end of the conductive layer 242B, the radius of curvature of the curved surface is 3 nm to 10 nm, preferably 5 nm to 6 nm. By not having corners at the ends, the coverage of the film in subsequent film formation processes is improved.

[0219] The conductive film can be processed using lithography. Furthermore, either dry etching or wet etching methods can be used for this process. Dry etching is suitable for microfabrication.

[0220] Next, an insulating film 272A is deposited on the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B (see Figure 6).

[0221] The insulating film 272A can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, silicon nitride, silicon oxide, or aluminum oxide can be deposited by sputtering.

[0222] Next, an insulating film 273A is deposited on the insulating film 272A. The insulating film 273A can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. For example, it is preferable to deposit an aluminum oxide film by ALD or sputtering. In this embodiment, an aluminum oxide film is deposited by ALD (see Figure 6).

[0223] Next, an insulating film that will become the insulator 280 is deposited on the insulating film 273A. The insulating film that will become the insulator 280 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figure 7).

[0224] Next, a portion of the insulator 280, a portion of the insulating film 273A, a portion of the insulating film 272A, a portion of the conductive layer 242B, and a portion of the oxide layer 243B are processed to form an opening that reaches the oxide 230b. Preferably, the opening is formed so as to overlap with the conductor 205. The formation of the opening creates oxide 243a, oxide 243b, conductor 242a, conductor 242b, insulator 272, and insulator 273 (see Figure 7).

[0225] Furthermore, the processing of a portion of the insulator 280, a portion of the insulating film 273A, a portion of the insulating film 272A, a portion of the conductive layer 242B, and a portion of the oxide layer 243B may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by a dry etching method, a portion of the insulating film 273A may be processed by a wet etching method, and a portion of the insulating film 272A, a portion of the conductive layer 242B, and a portion of the oxide layer 243B may be processed by a dry etching method.

[0226] Conventional processes such as dry etching can cause impurities, such as etching gases, to adhere to or diffuse into the surface or interior of oxide 230a and oxide 230b. Examples of such impurities include fluorine and chlorine.

[0227] To remove the aforementioned impurities, cleaning is performed. Cleaning methods include wet cleaning using cleaning solutions, plasma treatment using plasma, or cleaning by heat treatment, and these cleaning methods may be combined as appropriate.

[0228] For wet cleaning, a cleaning treatment may be performed using an aqueous solution of oxalic acid, phosphoric acid, ammonia water, or hydrofluoric acid diluted with carbonated water or distilled water. Alternatively, ultrasonic cleaning using distilled water or carbonated water may be performed.

[0229] Next, a heat treatment may be performed. The heat treatment may be carried out under reduced pressure, and the oxide film 230C may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of oxide 230b can be removed, and the moisture and hydrogen concentrations in oxide 230a and oxide 230b can be further reduced. The heat treatment temperature is preferably between 100°C and 400°C. In this embodiment, the heat treatment temperature is set to 200°C (see Figure 8).

[0230] Here, it is preferable that the oxide film 230C is provided so as to be in contact with at least a portion of the side surface of oxide 230a, a portion of the side surface and a portion of the top surface of oxide 230b, a portion of the side surface of oxide 243, a portion of the side surface of conductor 242, a portion of the side surface of insulator 272, a portion of the side surface of insulator 273, and a portion of the side surface of insulator 280. By being surrounded by oxide 243, insulator 272, and oxide film 230C, the decrease in conductivity due to oxidation of conductor 242 in subsequent processes can be suppressed.

[0231] The oxide film 230C can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. Depending on the desired properties of oxide film 230C, the oxide film 230C can be deposited using the same deposition method as oxide film 230A or oxide film 230B. In this embodiment, oxide film 230C is deposited by sputtering using a target with an In:Ga:Zn ratio of 1:3:4 or 4:2:4.1.

[0232] Furthermore, the oxide film 230C may be layered. For example, it may be deposited by sputtering using a target with an In:Ga:Zn ratio of 4:2:4.1 [atomic ratio], and then continuously deposited using a target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio].

[0233] In particular, during the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxides 230a and 230b. Therefore, the proportion of oxygen in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%.

[0234] Next, a heat treatment may be performed. The heat treatment may be carried out under reduced pressure, and the insulating film 250A may be continuously deposited without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, and oxide film 230C can be further reduced. The heat treatment temperature is preferably between 100°C and 400°C (see Figure 9).

[0235] The insulating film 250A can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. Preferably, silicon oxidnitride is deposited as the insulating film 250A by the CVD method. The deposition temperature for the insulating film 250A is preferably 350°C or higher and less than 450°C, particularly around 400°C. Depositing the insulating film 250A at 400°C allows for the formation of an insulator with fewer impurities.

[0236] Next, conductive films 260Aa and 260Ab are deposited. The conductive films 260Aa and 260Ab can be deposited using sputtering, CVD, MBE, PLD, or ALD. For example, CVD is preferred. In this embodiment, conductive film 260Aa is deposited using the ALD method, and conductive film 260Ab is deposited using the CVD method (see Figure 10).

[0237] Next, the oxide film 230C, insulating film 250A, conductive film 260Aa, and conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, thereby forming the oxide 230c, insulator 250, and conductor 260 (conductor 260a and conductor 260b) (see Figure 11).

[0238] Here, the conductor 242 is arranged so as to be surrounded by oxide 243, insulator 272, and oxide 230c, which makes it possible to suppress the decrease in conductivity due to oxidation of the conductor 242.

[0239] Next, a heat treatment may be performed. In this embodiment, the treatment is carried out at a temperature of 400°C for 1 hour in a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and the insulator 280.

[0240] Next, insulating films that will become insulators 282 may be formed on the conductor 260, the oxide 230c, the insulator 250, and the insulator 280. The insulating films that will become insulators 282 can be formed using sputtering, CVD, MBE, PLD, or ALD. For example, it is preferable to form aluminum oxide as the insulating film that will become insulators 282 by sputtering. Forming the insulators 282 in contact with the upper surface of the conductor 260 in this way is preferable because it is possible to suppress the absorption of oxygen contained in the insulators 280 into the conductor 260 during the subsequent heat treatment (see Figure 11).

[0241] Next, a heat treatment may be performed. In this embodiment, the treatment is carried out at a temperature of 400°C for 1 hour in a nitrogen atmosphere. This heat treatment allows the oxygen added by the film formation of the insulator 282 to be injected into the insulator 280. Furthermore, this oxygen can be injected into oxides 230a and 230b via oxide 230c.

[0242] Next, an insulating film that will become the insulating film 274 may be deposited on the insulating film 282. The insulating film that will become the insulating film 274 can be deposited using sputtering, CVD, MBE, PLD, or ALD (see Figure 11).

[0243] Next, an insulating film to become the insulating film 281 may be deposited on the insulating film 274. The insulating film to become the insulating film 281 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. As the insulating film to become the insulating film 281, for example, silicon nitride is preferably deposited by sputtering (see Figure 11).

[0244] Next, openings reaching the conductors 242a and 242b are formed in insulators 272, 273, 280, 282, 274, and 281. These openings can be formed using lithography.

[0245] Next, an insulating film to form the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241. The conductive film can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film to form the insulator 241. For example, it is preferable to deposit aluminum oxide or silicon nitride by the ALD method. Anisotropic etching can be performed by, for example, dry etching. By configuring the side walls of the opening in this way, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed next can be prevented. In addition, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0246] Next, a conductive film that will become the conductors 240a and 240b is formed. The conductive film that will become the conductors 240a and 240b preferably has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The formation of the conductive film that will become the conductor 240 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0247] Next, by performing CMP processing, a part of the conductive film that will become the conductors 240a and 240b is removed to expose the insulator 281. As a result, conductors 240a and 240b with a flat upper surface can be formed by the remaining conductive film only in the above opening (see FIG. 1). Note that a part of the insulator 281 may be removed by the CMP processing.

[0248] Next, a conductive film that will become the conductor 246 is formed. The formation of the conductive film that will become the conductor 246 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0249] Next, the conductive film that will become the conductor 246 is processed by a lithography method to form a conductor 246a that contacts the upper surface of the conductor 240a and a conductor 246b that contacts the upper surface of the conductor 240b (see FIG. 1).

[0250] As described above, a semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 4 to 11, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device according to the present embodiment.

[0251] According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Or, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Or, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Or, according to one aspect of the present invention, a semiconductor device with a small off-current can be provided. Or, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Or, according to one aspect of the present invention, a highly productive semiconductor device can be provided.

[0252] <Modified Example of Semiconductor Device> Hereinafter, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, which is different from that shown in the previous <Configuration Example of Semiconductor Device>, will be described with reference to FIGS. 13 to 23.

[0253] In the semiconductor device shown in FIGS. 13 to 23, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device (see FIG. 1) shown in the <Configuration Example of Semiconductor Device>. In this section, the materials described in detail in the <Configuration Example of Semiconductor Device> can be used for the constituent materials of the transistor 200.

[0254] <Modified Example 1 of Semiconductor Device> FIGS. 13(A) and 13(B) are a top view and a cross-sectional view of a semiconductor device having a transistor 200 and a capacitor element 100 according to one aspect of the present invention.

[0255] In FIG. 13, FIG. 13(A) shows a top view. Further, FIG. 13(B) is a cross-sectional view corresponding to the portion indicated by the one-dot chain line A1 - A2 shown in FIG. 13(A), and is also a cross-sectional view in the channel length direction of the transistor 200. In the top view of FIG. 13(A), some elements are omitted for clarity of the drawing.

[0256] The semiconductor device shown in Figure 13 includes a capacitive element 100 and a transistor 200 on the capacitive element 100. The semiconductor device shown in Figure 13 differs from the semiconductor device shown in Figure 1 in that the capacitive element 100 is provided beneath the conductor 247. The transistor 200 shown in Figure 13 is the same as the transistor 200 shown in Figure 1, except that it does not have a conductor 240b, an insulator 241b, and a conductor 246b.

[0257] The capacitive element 100 includes an insulator 114 on an insulator 116, an insulator 140 on an insulator 114, a conductor 110 disposed in an opening formed in the insulators 114 and 140, an insulator 130 on the conductor 110 and 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and 130. Here, at least a portion of the conductor 110, the insulator 130, and the conductor 120 are disposed in the opening formed in the insulators 114 and 140.

[0258] The conductor 110 functions as the lower electrode of the capacitive element 100, the conductor 120 functions as the upper electrode of the capacitive element 100, and the insulator 130 functions as the dielectric of the capacitive element 100. In the openings of the insulators 114 and 140, the upper electrode and lower electrode of the capacitive element 100 face each other with the dielectric in between, not only on the bottom surface but also on the sides, which allows for a large capacitance per unit area. Furthermore, the deeper the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, miniaturization or high integration of semiconductor devices can be promoted.

[0259] Insulators 114 and 150 may be made of any insulator suitable for use in insulator 280. Insulators 116 and 140 preferably function as etching stoppers when forming the opening in insulator 114, and may be made of any insulator suitable for use in insulator 214.

[0260] The shape of the openings formed in the insulators 114 and 140 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. In this case, it is preferable that the area overlapping between the opening and the transistor 200 is large when viewed from above. By adopting such a configuration, the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.

[0261] The conductor 110 is positioned in contact with the openings formed in the insulators 140, 114, and 116. Preferably, the upper surface of the conductor 110 substantially coincides with the upper surface of the insulator 140. The conductor 110 is preferably formed using the ALD method or the CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0262] The insulator 130 is positioned to cover the conductor 110 and the insulator 140. The insulator 130 is made of, for example, hafnium oxide, hafnium silicate (HfSi x O y (x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0), nitrogen-added hafnium aluminate (HfAl x O y N z It is preferable to use a high-k material such as (x>0, y>0, z>0) or yttrium oxide. By using such a high-k material, the capacitance of the capacitive element 100 can be sufficiently secured even if the insulator 130 is made thicker. By making the insulator 130 thicker, the leakage current that occurs between the conductor 110 and the conductor 120 can be suppressed. Furthermore, it is preferable to deposit the insulator 130 using, for example, the ALD method or the CVD method.

[0263] Furthermore, the insulator 130 may be laminated with a material with high dielectric strength (a material with a low dielectric constant), such as silicon oxynitride, to form the insulator 130. Examples of materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or resin. By laminating the insulator 130 in this way, the capacitive element 100 can secure sufficient capacitance by having a high-k material insulator, and its dielectric strength can be improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 100. Furthermore, if sufficient capacitance can be secured for the capacitive element 100, the insulator 130 may be composed solely of a material with high dielectric strength.

[0264] The conductor 120 is positioned to fill the openings formed in the insulators 140 and 114. The conductor 247 is in contact with the upper surface of the conductor 120 through an opening in the insulator 150. The conductor 120 is preferably formed using an ALD method or a CVD method; for example, any conductor suitable for the conductor 205 may be used.

[0265] The capacitive element 100 described above may require high-temperature heat treatment exceeding 700°C during the manufacturing process. If such high-temperature heat treatment is performed after the formation of the transistor 200, the oxide 230 may be affected by the diffusion of impurities such as hydrogen or water, or oxygen, which could degrade the electrical characteristics of the transistor 200.

[0266] However, as shown in this modified example, by forming the transistor 200 on top of the capacitive element 100, the thermal history during the manufacturing process of the capacitive element 100 does not affect the transistor 200. This prevents deterioration of the electrical characteristics of the transistor 200 and makes it possible to provide a semiconductor device with stable electrical characteristics.

[0267] In this modified example, the conductor 242b and the conductor 120 are electrically connected via the conductor 247, but this modification is not limited to this. For example, the capacitive element 100 may be provided such that the upper surface of the conductor 120 is exposed from the insulator 224, and the upper surface of the conductor 120 is in contact with the conductor 242b.

[0268] <Modified example of a semiconductor device 2> Figures 14(A) and 14(B) are a top view and a cross-sectional view of a semiconductor device having a transistor 200 and a capacitive element 100a according to one aspect of the present invention.

[0269] In Figure 14, Figure 14(A) shows a top view of the layer containing the insulator 140 (insulator 140a and insulator 140b). Figure 14(B) is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 14(A), and is also a cross-sectional view of the transistor 200 in the channel length direction.

[0270] The semiconductor device shown in Figure 14 differs from the semiconductor device shown in Figure 13 in that the shape of the capacitive element 100a is different from that of the capacitive element 100. The capacitive element 100a has insulators 114a, 114b, 140a, 140b, conductor 110a, 130a, and 120a. Here, insulators 114a and 114b correspond to insulator 114, insulators 140a and 140b correspond to insulator 140, conductor 110a corresponds to conductor 110, insulator 130a corresponds to insulator 130, and conductor 120a corresponds to conductor 120, so further details can be found in the above.

[0271] In the capacitive element 100a, columnar insulators 114b and 140b are formed inside the openings of the insulators 114a and 140a. Also on the side surfaces of the columnar insulators 114b and 140b, the conductor 110a and the conductor 120a face each other via the insulator 130a. As a result, not only the side surfaces of the insulators 114a and 140a but also the side surfaces of the insulators 114b and 140b can form the capacitive element 100a. Therefore, the capacitive element 100a can have a capacitance larger than that of the capacitive element 100 with an occupied area comparable to that of the capacitive element 100.

[0272] <Modified Example 3 of Semiconductor Device> FIG. 15(A) and FIG. 15(B) are a top view and a cross-sectional view of a semiconductor device having transistors 200a and 200b according to one aspect of the present invention.

[0273] In FIG. 15, FIG. 15(A) shows a top view. Also, FIG. 15(B) is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1 - A2 shown in FIG. 15(A), and is also a cross-sectional view in the channel length direction of the transistors 200a and 200b. In the top view of FIG. 15(A), some elements are omitted for clarity of the drawing.

[0274] In the semiconductor device shown in FIG. 15, the transistors 200a and 200b have the same structure as the transistor 200, respectively, except that the conductor 205, the oxides 230a, 230b, 243, the conductor 242, the conductor 240, the insulator 241, and the conductor 246 are shared by the transistors 200a and 200b. Therefore, the details can be referred to the above.

[0275] As shown in FIGS. 15(A) and 15(B), by configuring the transistors 200a and 200b to share the conductor 240, the occupied area in the top view per transistor element can be reduced, so that the semiconductor device can be further highly integrated.

[0276] In this modified example, a configuration is described in which transistor 200a has a conductor 247a and transistor 200b has a conductor 247b, but the invention is not limited to this configuration. For example, similar to the configuration shown in Figure 13, a capacitive element electrically connected via the conductor 247a may be provided below transistor 200a, and furthermore, a capacitive element electrically connected via the conductor 247b may be provided below transistor 200b.

[0277] <Modification 4 of semiconductor device> The semiconductor devices shown in Figures 16 to 18 are semiconductor devices having transistors 200 with a different shape than the transistor 200 shown in Figure 1.

[0278] Figure 16(A) is a top view of a semiconductor device having a transistor 200. Figures 16(B) and 16(C) are cross-sectional views of the same semiconductor device. Here, Figure 16(B) is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 16(A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 16(C) is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 16(A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the top view of Figure 16(A), some elements have been omitted for clarity. Figure 17 is an enlarged view of the vicinity of the channel formation region of the transistor 200 in Figure 16(B). Figure 18(A) is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 16(A), and is also a cross-sectional view of the source region or drain region of the transistor 200 in the channel width direction. Furthermore, Figure 18(B) is a cross-sectional view of the area indicated by the dashed line A7-A8 in Figure 16(A), and is also a cross-sectional view in the channel width direction of the conductor 240b, which is electrically connected to the transistor 200 and functions as a plug.

[0279] The semiconductor device shown in Figure 16, etc., comprises an insulator 214 on a substrate (not shown), a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 274 on the insulator 282, and an insulator 281 on the insulator 274. Insulators 214, 280, 282, 274, and 281 function as interlayer films. A conductor 247 is provided that is electrically connected to the transistor 200 and functions as a plug. Conductors 240 (conductors 240a and 240b) are also provided that are electrically connected to the transistor 200 and function as plugs. Insulators 241 (insulators 241a and 241b) are provided in contact with the side surface of the conductor 240 that functions as a plug. Furthermore, conductors 246 (conductors 246a and 246b) are provided on the insulator 281 and on the conductor 240, electrically connected to the conductor 240 and functioning as wiring.

[0280] As shown in Figure 16, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243a and an oxide 243b on the oxide 230b, and a conductive material in contact with a portion of the upper surface of the insulator 224, the side of the oxide 230a, the side of the oxide 230b, the side of the oxide 243a, and the upper surface of the oxide 243a. The insulator comprises body 242a, a conductor 242b in contact with a part of the upper surface of the insulator 224, the side surface of oxide 230a, the side surface of oxide 230b, the side surface of oxide 243b, and the upper surface of oxide 243b, oxide 230c on oxide 230b, an insulator 250 on oxide 230c, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with oxide 230c, an insulator 272 in contact with a part of the upper surface of the insulator 224, the side surface of conductor 242a, the upper surface of conductor 242a, the side surface of conductor 242b, and the upper surface of conductor 242b, and an insulator 273 on the insulator 272. Furthermore, oxide 230c is in contact with the upper surface of the region where the side surface of oxide 243a does not overlap with the conductor 242a, and with the upper surface of the region where the side surface of oxide 243b does not overlap with the conductor 242b.

[0281] Here, oxide 243a has a region that does not overlap with conductor 242a, and oxide 243b has a region that does not overlap with conductor 242b. That is, oxides 243a and 243b are provided so that they have portions that protrude into the opening provided in the insulator 280. In this respect, the transistor 200 shown in Figure 16 differs from the transistor shown in Figure 1. For other structures of the semiconductor device shown in Figure 16, the corresponding structure shown in Figure 1 can be considered.

[0282] Figure 17 is an enlarged view of the vicinity of the channel formation region of transistor 200 in Figure 16(B). As shown in Figure 17, the opposing sides of oxide 243a and oxide 243b are located inward from the opposing sides of conductor 242a and conductor 242b. Therefore, the distance between the source electrode and the drain electrode of transistor 200, i.e., the channel length (L), is determined by the distance between oxide 243a and oxide 243b. The distance between oxide 243a and oxide 243b can be shorter than the width of the opening provided in the insulator 280 and the distance between conductor 242a and conductor 242b. In other words, the opening provided in the insulator 280 can be made larger, so even when the channel length of transistor 200 is shortened, the oxide 230c, insulator 250, and conductor 260 can be easily embedded.

[0283] For example, if the channel length (L) of transistor 200 is 20 nm, then if the width of the region of oxide 243 that does not overlap with conductor 242 can be set to 20 nm, then the width of the opening formed in insulator 280 can be set to 60 nm. Similarly, if the width of the region of oxide 243 that does not overlap with conductor 242 can be set to 5 nm, then the width of the opening formed in insulator 280 can be set to 30 nm. Furthermore, a portion of oxide 243 and a portion of conductor 260 can be superimposed. Also, for example, if the length (L') between conductor 242a and conductor 242b shown in Figure 17 is 60 nm, then the channel length (L) can be less than 60 nm, preferably 30 nm or less, and more preferably 5 nm or more and 10 nm or less.

[0284] Here, in oxide 230b, region 234 functions as a channel-forming region, region 231a functions as either a source region or a drain region, and region 231b functions as the other source region or drain region.

[0285] Furthermore, Figure 18(A) is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 16(A), and is also a cross-sectional view of the source region or drain region of transistor 200 in the channel width direction. As shown in Figure 18(A), the top surface and side surfaces of the conductor 242b are covered with insulators 272 and 273, respectively, so that the diffusion of impurities such as hydrogen and water, as well as oxygen, into the conductor 242b from the side surfaces and the top surface of the conductor 242b can be suppressed. Therefore, the diffusion of oxygen into the conductor 242b from its surroundings can be suppressed, and thus the oxidation of the conductor 242b can be suppressed. The same effect is also observed for the conductor 242a. In addition, the diffusion of impurities such as hydrogen and water into oxide 230a and oxide 230b from the side surfaces of oxide 230a and oxide 230b can be suppressed. For example, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used as the insulator 272. For example, aluminum oxide or hafnium oxide can be used as the insulator 273.

[0286] Figure 18(B) is a cross-sectional view of the area indicated by the dashed line A7-A8 in Figure 16(A), and is also a cross-sectional view in the channel width direction of the conductor 240b, which is electrically connected to the transistor 200 and functions as a plug. As shown in Figure 18(B), the conductor 240b is provided in contact with the upper surface of the conductor 242b. Since the insulator 241b is placed on the side surface of the conductor 240b, the diffusion of impurities such as hydrogen and water, as well as oxygen, from the insulator 280 to the conductor 240b can be suppressed. The same effect is also present for the conductor 240a.

[0287] As shown in Figures 16(A)(B) and 18(B), it is preferable that the conductor 240b is provided superimposed on at least a portion of the conductor 247. This reduces the area occupied by the conductor 240b and the conductor 247 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0288] Next, the manufacturing method of the semiconductor device having the transistor 200 shown in Figure 16 will be explained using Figures 19 to 23. In Figures 19 to 23, (A) in each figure shows a top view. (B) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. (C) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the top view (A) of each figure, some elements have been omitted for clarity.

[0289] First, as described above, the manufacturing process for semiconductor devices is carried out using the methods shown in Figures 4 to 6.

[0290] Next, an insulating film that will become the insulator 280 is deposited on the insulating film 273A. The insulating film that will become the insulator 280 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figure 19).

[0291] Next, a portion of the insulator 280, a portion of the insulating film 273A, a portion of the insulating film 272A, and a portion of the conductive layer 242B are processed to form an opening that exposes the oxide layer 243B. It is preferable that the opening be formed so as to overlap with the conductor 205. The formation of the opening creates the conductor 242a, the conductor 242b, the insulator 272, and the insulator 273. In addition, the formation of the opening may reduce the thickness of a portion of the oxide layer 243B (see Figure 19).

[0292] Furthermore, the processing of a portion of the insulator 280, a portion of the insulating film 273A, a portion of the insulating film 272A, and a portion of the conductive layer 242B may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by a dry etching method, a portion of the insulating film 273A may be processed by a wet etching method, and a portion of the insulating film 272A and a portion of the conductive layer 242B may be processed by a dry etching method.

[0293] Next, a dummy film 265A is formed on the insulator 280 and inside the opening (see Figure 20). The dummy film 265A needs to be formed on the sidewall of the opening, and the distance between oxide 243a and oxide 243b, i.e., the channel length (L), is determined by the thickness of the dummy film. For this reason, it is preferable to form the dummy film 265A using the ALD method or CVD method, which have high coverage and allow for relatively easy fine-tuning of the film thickness. The dummy film 265A should be formed such that the film thickness on the sidewall of the opening is between 5 nm and 20 nm, and can be appropriately set according to the electrical characteristics required for the transistor 200. For example, if the film thickness of the dummy film 265A on the sidewall of the opening is 5 nm, the channel length can be made 10 nm shorter than the width of the opening, and if the film thickness of the dummy film 265A on the sidewall of the opening is 20 nm, the channel length can be made 40 nm shorter than the width of the opening. Furthermore, since the dummy film 265A will ultimately be removed, it is preferable to use a film that is easy to microfabricate and also easy to remove.

[0294] Next, anisotropic etching is performed on the dummy film 265A to form the dummy film 265, leaving only the portion of the dummy film 265A that is in contact with the side wall of the opening (see Figure 21). At this time, the width of the dummy film 265 is preferably 5 nm or more and 20 nm or less. The width of the dummy film 265 depends on the film thickness at the side wall of the opening of the dummy film 265A. If the width of the dummy film 265 is shorter than the film thickness at the side wall of the opening of the dummy film 265A, the dummy film 265A can be made thicker, so the film thickness is not limited to the value described above.

[0295] Next, the oxide layer 243B is etched using the dummy film 265 as a mask to form oxide 243a and oxide 243b (see Figure 22). Note that the etching of the dummy film 265 and the etching of the oxide layer 243B may be performed consecutively. In addition, a portion of the upper surface of oxide 230b exposed between oxide 243a and oxide 243b may be removed.

[0296] At this time, the oxide layer 243B is processed using the dummy film 265 as a mask to form oxide 243a and oxide 243b. Thus, the openings formed in the insulator 280 are superimposed on the region between the conductors 242a and 242b, and the region between oxide 243a and oxide 243b. This allows the conductor 260 to be self-aligned between the conductors 242a and 242b, and between oxide 243a and oxide 243b in a later process.

[0297] In this embodiment, a method for forming the oxide layer 243B using a dummy film 265 is illustrated, but the embodiment is not limited thereto. For example, after forming the oxide layer 243B, a patterning process may be performed to form a resist mask, and the oxide layer 243B may be processed with the resist mask to form oxide 243a and oxide 243b.

[0298] Next, the dummy film 265 is selectively removed using isotropic etching (see Figure 23). For isotropic etching, for example, wet etching or etching using a reactive gas can be used. In this way, the distance between oxide 243a and oxide 243b can be made shorter than the length of the channel in the direction of the opening.

[0299] Conventional processes such as dry etching can cause impurities, such as etching gases, to adhere to or diffuse into the surface or interior of oxide 230a and oxide 230b. Examples of such impurities include fluorine and chlorine.

[0300] To remove the aforementioned impurities, cleaning is performed. Cleaning methods include wet cleaning using cleaning solutions, plasma treatment using plasma, or cleaning by heat treatment, and these cleaning methods may be combined as appropriate.

[0301] For wet cleaning, a cleaning treatment may be performed using an aqueous solution of oxalic acid, phosphoric acid, ammonia water, or hydrofluoric acid diluted with carbonated water or distilled water. Alternatively, ultrasonic cleaning using distilled water or carbonated water may be performed.

[0302] The semiconductor device manufacturing process can be carried out using the methods shown in Figures 8 to 11, as described above. In this way, the semiconductor device shown in Figure 16 can be manufactured. The configurations and methods shown in the above-mentioned modified examples can be used in appropriate combination with other configurations and methods shown in this embodiment.

[0303] The configurations and methods described in this embodiment can be used in appropriate combination with the configurations and methods described in other embodiments.

[0304] (Embodiment 2) In this embodiment, one form of a semiconductor device will be described with reference to Figures 24 to 26.

[0305] [Storage device 1] Figure 24 shows an example of a semiconductor device (memory device) using a capacitive element according to one aspect of the present invention. In the semiconductor device according to one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above both the transistor 300 and the transistor 200. It is preferable that at least a portion of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. This reduces the area occupied by the capacitive element 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0306] Furthermore, the transistor 200 described in the previous embodiment can be used as the transistor 200, and the capacitive element 100 described in the previous embodiment can be used as the capacitive element 100. Therefore, the description of the previous embodiment can be used with respect to the transistor 200, the capacitive element 100, and the layer containing them. However, in the memory device 1, unlike the previous embodiment, the capacitive element 100 is provided on top of the transistor 200.

[0307] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Because transistor 200 has a small off-current, it can be used in a memory device to retain stored data for a long period of time. In other words, because refresh operations are not required, or are performed very infrequently, the power consumption of the memory device can be significantly reduced.

[0308] In the memory device shown in Figure 24, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and wiring 1005 is electrically connected to the other electrode of the capacitive element 100. In the following, the node connected to the gate of transistor 300, the other of the source and drain of transistor 200, and one of the electrodes of the capacitive element 100 may be referred to as node FG.

[0309] The memory device shown in Figure 24 has the characteristic that the potential of the gate (node ​​FG) of transistor 300 can be maintained by switching transistor 200, thereby enabling the writing, holding, and reading of information.

[0310] Furthermore, the memory devices shown in Figure 24 can be arranged in a matrix to form a memory cell array.

[0311] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region.

[0312] Here, an insulator 315 is placed on the semiconductor region 313, and a conductor 316 is placed on the insulator 315. Furthermore, the transistor 300 formed in the same layer is electrically isolated by an insulator 312 that functions as an element isolation insulating layer. The insulator 312 can be an insulator similar to the insulator 326 described later. The transistor 300 may be either a p-channel or n-channel type.

[0313] The substrate 311 preferably contains a semiconductor such as a silicon-based semiconductor in the region where the channel of the semiconductor region 313 is formed, the region near it, the source region, or the low-resistance region 314a and low-resistance region 314b, and preferably contains single-crystal silicon. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, the transistor 300 may be made into a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, etc.

[0314] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0315] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0316] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use metallic materials such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0317] In Figure 24, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It is also possible to have an insulator in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0318] Note that the transistor 300 shown in Figure 24 is just one example, and its structure is not limited to this example. Any appropriate transistor can be used depending on the circuit configuration and driving method.

[0319] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0320] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have embedded conductive elements such as conductors 328 and 330 that are electrically connected to the capacitive element 100 or the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0321] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0322] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 24, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0323] Similarly, insulators 210, 212, 214, 216, 222, and 224 have conductors 247 and conductors (conductor 205) that constitute the transistor 200 embedded in them. Conductor 247 functions as a plug or wiring that electrically connects to the capacitive element 100, transistor 200, or transistor 300. For example, conductor 247 is electrically connected to conductor 316, which functions as the gate electrode of transistor 300.

[0324] Furthermore, insulators 114, 140, 130, 150, and 154 on the insulator 281 have conductors 112 and conductors (conductors 120 and 110) that constitute the capacitive element 100 embedded in them. Conductor 112 functions as a plug or wiring that electrically connects transistor 200 or transistor 300 to conductor 152, which functions as a terminal. In addition, an insulator 156 is provided on top of insulators 154 and conductor 152.

[0325] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0326] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0327] For example, it is preferable that insulators 320, 322, 326, 352, 354, and insulators 212, 114, 150, and 156 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxide nitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0328] Furthermore, the resistivity of the insulator provided above or below the conductor 152 is 1.0 × 10⁻⁶. 12 Ωcm or greater: 1.0 × 10 15 Ωcm or less, preferably 5.0 × 10⁻⁶ 12 Ωcm or greater: 1.0 × 10 14 Ωcm or less, more preferably 1.0 × 10⁻⁶ 13 Ωcm or more, 5.0 × 10 13 It is preferable that the resistivity is Ωcm or less. By setting the resistivity of the insulator provided above or below the conductor 152 to the above range, the insulator can disperse the charge accumulated between the wiring of the transistor 200, transistor 300, capacitive element 100, and conductor 152, while maintaining its insulating properties, thereby suppressing characteristic defects and electrostatic discharge damage to the transistor and the memory device having the transistor caused by the charge, which is preferable. Silicon nitride or silicon nitride oxide can be used as such an insulator. For example, the resistivity of the insulator 154 may be set to the above range.

[0329] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 324, 350, 210, and 154 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0330] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0331] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0332] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, 247, 112, and 152, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0333] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used in the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0334] For example, in Figure 24, an insulator 276 may be provided between the insulator 280 having excess oxygen and the conductor 245. Here, the conductor 245 corresponds to the conductor 240 shown in the previous embodiment, and the insulator 276 corresponds to the insulator 241 shown in the previous embodiment. By providing the insulator 276 and the insulator 272 in contact, the conductor 245 and the transistor 200 can be sealed by an insulator having barrier properties.

[0335] In other words, by providing the insulator 276, it is possible to suppress the absorption of excess oxygen in the insulator 280 by the conductor 245. Furthermore, by having the insulator 276, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 245.

[0336] Here, the conductor 245 functions as a plug or wire that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300. For example, the conductor 245 electrically connects the conductor 242b, which functions as the other half of the source and drain of the transistor 200, and the conductor 110, which functions as one of the electrodes of the capacitive element 100, via the conductor 246.

[0337] The above is a description of the configuration example. By using this configuration, it is possible to suppress fluctuations in electrical characteristics and improve reliability in semiconductor devices using transistors having oxide semiconductors. Alternatively, it is possible to provide a transistor having an oxide semiconductor with a large on-current. Alternatively, it is possible to provide a transistor having an oxide semiconductor with a small off-current. Alternatively, it is possible to provide a semiconductor device with reduced power consumption.

[0338] [Storage device 2] Figure 25 shows an example of a storage device using a semiconductor device according to one aspect of the present invention. The storage device shown in Figure 25 has a transistor 200, a transistor 300, and a capacitive element 100, similar to the semiconductor device shown in Figure 24. However, the storage device shown in Figure 25 differs from the storage device shown in Figure 24 in that the capacitive element 100 is located below the transistor 200, and the transistors 200 and 300 are not electrically connected via the conductor 247.

[0339] In one embodiment of the present invention, the semiconductor device has a transistor 200 located above the transistor 300, and a capacitive element 100 located below the transistor 200. Preferably, at least a portion of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. This reduces the area occupied by the capacitive element 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0340] Furthermore, the above-mentioned capacitive element 100, transistor 200, and transistor 300 can be used as the capacitive element 100, transistor 200, and transistor 300. Therefore, the above description can be taken into consideration regarding the capacitive element 100, transistor 200, transistor 300, and the layer containing them.

[0341] In the memory device shown in Figure 25, wiring 2001 is electrically connected to the source of transistor 300, wiring 2002 is electrically connected to the drain of transistor 300, and wiring 2007 is electrically connected to the gate of transistor 300. Wiring 2003 is electrically connected to one of the source and drain of transistor 200, wiring 2004 is electrically connected to the first gate of transistor 200, and wiring 2006 is electrically connected to the second gate of transistor 200. The other of the source and drain of transistor 200 is electrically connected to one of the electrodes of capacitive element 100, and wiring 2005 is electrically connected to the other electrode of capacitive element 100.

[0342] The memory device shown in Figure 25 has the characteristic that it can retain the charge stored on one of the electrodes of the capacitive element 100 by switching the transistor 200, thereby enabling the writing, retention, and reading of information.

[0343] Furthermore, the memory devices shown in Figure 25 can be arranged in a matrix to form a memory cell array.

[0344] Since the layer containing transistor 300 has a structure similar to that of the memory device shown in Figure 24, the structure below the insulator 354 can be considered in reference to the above description.

[0345] An insulator 360 is placed on top of an insulator 354, an insulator 362 is placed on top of an insulator 360, an insulator 364 is placed on top of an insulator 362, and an insulator 114 is placed on top of an insulator 364. Insulator 360 may be any insulator that can be used for insulator 350, etc. Insulators 362 and 364 may be any insulator that can be used for insulator 352, etc.

[0346] An opening is formed in the insulator 364, and the conductor 366 is placed inside this opening. The conductor 366 is in contact with the lower surface of the conductor 110. In other words, the conductor 366 functions as wiring that connects to the other electrode of the capacitive element 100. The conductor 366 can be made of an insulator that can be used for the conductor 356, etc.

[0347] Furthermore, insulators 360, 362, 364, 114, 140, 130, and 150 have conductors 112 and conductors (conductors 120 and 110) that constitute the capacitive element 100 embedded in them. Conductor 112 functions as a plug or wiring that electrically connects transistor 300 and conductor 152, which functions as a terminal.

[0348] The layer containing the transistor 200 on the insulator 150 has a structure similar to the memory device shown in Figure 24, so the above description can be taken into consideration. However, the transistor 200 in the memory device shown in Figure 25 does not have a conductor 240b. Also, a conductor 152 is placed on top of the conductor 245, and an insulator 156 is placed on top of the conductor 152 and the insulator 281.

[0349] Furthermore, the conductor 247 functions as a plug or wire for electrical connection to the capacitive element 100, the transistor 200, or the transistor 300. For example, the conductor 247 is electrically connected to the conductor 120, which functions as the other electrode of the capacitive element 100.

[0350] [Storage device 3] Figure 26 shows an example of a storage device using a semiconductor device according to one aspect of the present invention. The storage device shown in Figure 26 has a transistor 400 in addition to the semiconductor device having transistors 200, 300, and capacitive element 100 shown in Figure 24.

[0351] Transistor 400 can control the second gate voltage of transistor 200. For example, the first and second gates of transistor 400 are diode-connected to the source, and the source of transistor 400 is connected to the second gate of transistor 200. In this configuration, when the negative potential of the second gate of transistor 200 is maintained, the voltage between the first gate and source of transistor 400 and the voltage between the second gate and source become 0V. In transistor 400, the drain current is very small when the second gate voltage and the first gate voltage are 0V, so the negative potential of the second gate of transistor 200 can be maintained for a long time even without supplying power to transistors 200 and 400. As a result, a memory device having transistors 200 and 400 can retain its contents for a long period of time.

[0352] Therefore, in Figure 26, wire 1001 is electrically connected to the source of transistor 300, and wire 1002 is electrically connected to the drain of transistor 300. Also, wire 1003 is electrically connected to one of the source and drain of transistor 200, wire 1004 is electrically connected to the gate of transistor 200, and wire 1006 is electrically connected to the back gate of transistor 200. Furthermore, the gate of transistor 300, and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitive element 100, and wire 1005 is electrically connected to the other electrode of capacitive element 100. Wire 1007 is electrically connected to the source of transistor 400, wire 1008 is electrically connected to the gate of transistor 400, wire 1009 is electrically connected to the back gate of transistor 400, and wire 1010 is electrically connected to the drain of transistor 400. Here, wires 1006, 1007, 1008, and 1009 are electrically connected.

[0353] Furthermore, the memory device shown in Figure 26 can be configured as a memory cell array by arranging it in a matrix, similar to the memory device shown in Figure 24. Note that one transistor 400 can control the second gate voltage of multiple transistors 200. Therefore, it is preferable to have fewer transistors 400 than transistors 200.

[0354] In the storage device shown in Figure 24, the capacitive element 100 is cylindrical, but the present invention is not limited to this. For example, as shown in Figure 26, the capacitive element 100 may be planar.

[0355] <Transistor 400> Transistor 400 is a transistor formed in the same layer as transistor 200 and can be manufactured in parallel. Transistor 400 includes a conductor 460 (conductors 460a and 460b) that functions as a first gate electrode, a conductor 405 (conductors 405a and 405b) that functions as a second gate electrode, insulators 222, 224 and 450 that function as a gate insulating layer, an oxide 430c having a region in which a channel is formed, conductors 442a, 443a, 431a and 431b that function as either a source or a drain, conductors 442b, 443b, 432a and 432b that function as the other source or drain, and a conductor 440 (conductors 440a and 440b).

[0356] In transistor 400, conductor 405 is in the same layer as conductor 205. Oxide 431a, oxide 432a, and oxide 230a are in the same layer, and oxide 431b, oxide 432b, and oxide 230b are in the same layer. Conductor 442 is in the same layer as conductor 242. Oxide 443 is in the same layer as oxide 243. Oxide 430c is in the same layer as oxide 230c. Insulator 450 is in the same layer as insulator 250. Conductor 460 is in the same layer as conductor 260.

[0357] Furthermore, structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing an oxide film that becomes oxide 230c.

[0358] Oxide 430c, which functions as the active layer of transistor 400, has reduced oxygen deficiency and reduced impurities such as hydrogen or water, similar to oxide 230. This allows the threshold voltage of transistor 400 to be greater than 0V, the off-current to be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V to be very small.

[0359] <Dicing line> The following describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when extracting multiple semiconductor devices as chips by dividing a large-area substrate into individual semiconductor elements. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0360] Here, for example, as shown in Figure 26, it is preferable to design the region where the insulator 272 and the insulator 222 are in contact to form a dicing line. That is, an opening is provided in the insulator 224 near the region that will become a dicing line, which is provided on the outer edge of the memory cell having multiple transistors 200 and the transistor 400. In addition, the insulator 272 is provided so as to cover the side surface of the insulator 224.

[0361] In other words, the insulator 222 and the insulator 272 are in contact at the opening provided in the insulator 224. For example, the insulator 222 and the insulator 272 may be formed using the same material and method. By providing the insulator 222 and the insulator 272 using the same material and method, the adhesion can be improved. For example, it is preferable to use aluminum oxide.

[0362] This structure allows the insulator 224, transistor 200, and transistor 400 to be enclosed by the insulator 222 and the insulator 272. Since the insulator 222 and the insulator 272 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region on which the semiconductor elements shown in this embodiment are formed, it is possible to prevent impurities such as hydrogen or water from entering from the side of the divided substrate and diffusing into transistors 200 and 400.

[0363] Furthermore, this structure prevents excess oxygen from insulator 224 from diffusing to the outside of insulators 272 and 222. Therefore, excess oxygen from insulator 224 is efficiently supplied to the oxide in which the channel in transistor 200 or transistor 400 is formed. This oxygen reduces oxygen deficiencies in the oxide in which the channel in transistor 200 or transistor 400 is formed. As a result, the oxide in which the channel in transistor 200 or transistor 400 is formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of transistor 200 or transistor 400 can be suppressed and reliability can be improved.

[0364] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0365] (Embodiment 3) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described with reference to Figures 27 and 28. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.

[0366] <Example of storage device configuration> Figure 27(A) shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0367] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The wiring mentioned above is the wiring connected to the memory cells of the memory cell array 1470, which will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to access.

[0368] The storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The storage device 1400 also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and WDATA is input to the write circuit.

[0369] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0370] The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row.

[0371] Although Figure 27(A) shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 27(B), the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0372] Figure 28 illustrates an example of a memory cell configuration that can be applied to the memory cell MC described above.

[0373] [DOSRAM] Figures 28(A) to (C) show examples of the circuit configuration of a DRAM memory cell. In this specification, a DRAM using a 1OS transistor, 1 capacitance element type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 28(A) has a transistor M1 and a capacitance element CA. The transistor M1 has a gate (sometimes called a front gate) and a back gate.

[0374] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitive element CA is connected to wiring CAL.

[0375] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL functions as wiring for applying a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0376] Here, the memory cell 1471 shown in Figure 28(A) corresponds to the memory device shown in Figure 25. In other words, transistor M1 corresponds to transistor 200, capacitive element CA corresponds to capacitive element 100, wiring BIL corresponds to wiring 2003, wiring WOL corresponds to wiring 2004, wiring BGL corresponds to wiring 2006, and wiring CAL corresponds to wiring 2005. Note that the transistor 300 shown in Figure 25 corresponds to the transistor provided in the peripheral circuit 1411 of the memory device 1400 shown in Figure 27(B).

[0377] Furthermore, the memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of transistor M1 is connected to wiring WOL instead of wiring BGL, as shown in memory cell 1472 in Figure 28(B). Alternatively, the memory cell MC may be a memory cell composed of a single-gate transistor, i.e., a transistor M1 without a back gate, as shown in memory cell 1473 in Figure 28(C).

[0378] When the semiconductor device shown in the above embodiment is used as a memory cell 1471, etc., transistor 200 can be used as transistor M1 and capacitive element 100 can be used as capacitive element CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 1471, 1472, and 1473.

[0379] Furthermore, in DOSRAM, by configuring the sense amplifier to overlap the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance and thus the memory cell retention capacity can be reduced.

[0380] [NOSRAM] Figures 28(D) to (H) show an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 1474 shown in Figure 28(D) has a transistor M2, a transistor M3, and a capacitance element CB. The transistor M2 has a front gate (sometimes simply called a gate) and a back gate. In this specification, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 may be called NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0381] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0382] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. It is preferable to apply a low-level potential to wiring CAL when writing data, during data holding, and when reading data. Wiring BGL functions as wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0383] Here, the memory cell 1474 shown in Figure 28(D) corresponds to the memory device shown in Figure 24. In other words, transistor M2 corresponds to transistor 200, capacitive element CB corresponds to capacitive element 100, transistor M3 corresponds to transistor 300, wiring WBL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, wiring CAL corresponds to wiring 1005, wiring RBL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0384] Furthermore, the memory cell MC is not limited to memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of transistor M2 is connected to wiring WOL instead of wiring BGL, as shown in memory cell 1475 in Figure 28(E). Alternatively, the memory cell MC may be configured such that the memory cell MC is composed of a single-gate transistor, i.e., a transistor M2 without a back gate, as shown in memory cell 1476 in Figure 28(F). Alternatively, the memory cell MC may be configured such that wiring WBL and wiring RBL are combined into a single wiring BIL, as shown in memory cell 1477 in Figure 28(G).

[0385] When the semiconductor device shown in the above embodiment is used as a memory cell 1474, etc., transistor 200 can be used as transistor M2, transistor 300 as transistor M3, and capacitive element 100 as capacitive element CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be made very low. As a result, the written data can be held by transistor M2 for a long time, and the frequency of memory cell refresh can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0386] Furthermore, transistor M3 may be a transistor having silicon in its channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be n-channel or p-channel. Si transistors may have higher field-effect mobility than OS transistors. Therefore, a Si transistor may be used as transistor M3, which functions as a readout transistor. Also, by using a Si transistor for transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the occupied area of ​​the memory cell and enabling high integration of the memory device.

[0387] Furthermore, transistor M3 may be an OS transistor. If OS transistors are used for transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.

[0388] Figure 28(H) also shows an example of a gain cell type memory cell with 3 transistors and 1 capacitance element. The memory cell 1478 shown in Figure 28(H) has transistors M4 to M6 and a capacitance element CC. The capacitance element CC is provided as appropriate. The memory cell 1478 is electrically connected to wiring BIL, RWL, WWL, BGL, and GNDL. Wiring GNDL is wiring that provides a low level potential. Note that the memory cell 1478 may be electrically connected to wiring RBL and WBL instead of wiring BIL.

[0389] Transistor M4 is an OS transistor with a back gate, and the back gate is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a back gate.

[0390] Transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively. Alternatively, transistors M4 to M6 may be OS transistors; in this case, the memory cell array 1470 can be configured using only n-type transistors.

[0391] When the semiconductor device shown in the above embodiment is used as a memory cell 1478, transistor 200 can be used as transistor M4, transistors 300 can be used as transistors M5 and M6, and capacitive element 100 can be used as capacitive element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made very low.

[0392] The configuration of the peripheral circuit 1411 and the memory cell array 1470 shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary.

[0393] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0394] (Embodiment 4) In this embodiment, Figure 29 shows an example of a chip 1200 on which the semiconductor device of the present invention is mounted. Multiple circuits (systems) are mounted on the chip 1200. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC).

[0395] As shown in Figure 29(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog processing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0396] The chip 1200 is provided with bumps (not shown) and connects to the first surface of the printed circuit board (PCB) 1201, as shown in Figure 29(B). In addition, multiple bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connect to the motherboard 1203.

[0397] The motherboard 1203 may be equipped with storage devices such as DRAM 1221 and flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for the flash memory 1222.

[0398] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The memory can be the aforementioned NOSRAM or DOSRAM. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing and multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit and a multiply-accumulate operation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption.

[0399] Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed on the GPU 1212.

[0400] The analog arithmetic unit 1213 includes one or both an A / D (analog-to-digital) conversion circuit and a D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the above-mentioned sum-of-accumulate circuit.

[0401] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0402] Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface).

[0403] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.

[0404] The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost.

[0405] A PCB 1201 equipped with a chip 1200 having a GPU 1212, a motherboard 1203 equipped with DRAM 1221, and flash memory 1222 can be called a GPU module 1204.

[0406] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of operations such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN). Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 as an AI system module.

[0407] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0408] (Embodiment 5) This embodiment describes application examples of a memory device using the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment can be applied to memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment can be applied to various removable memory devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figure 30 schematically shows several configuration examples of removable memory devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memory.

[0409] Figure 30(A) is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1105 on the circuit board 1104.

[0410] Figure 30(B) is a schematic diagram of the external appearance of an SD card, and Figure 30(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. By providing a memory chip 1114 on the back side of the circuit board 1113, the capacity of the SD card 1110 can be increased. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor devices shown in the above embodiment can be incorporated into the memory chip 1114 on the circuit board 1113.

[0411] Figure 30(D) is a schematic diagram of the external appearance of the SSD, and Figure 30(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. Semiconductor devices as shown in the above embodiment can be incorporated into the memory chips 1154 on the circuit board 1153.

[0412] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0413] (Embodiment 6) In this embodiment, a product image applicable to a semiconductor device according to one aspect of the present invention, and specific examples of electronic devices, will be described with reference to Figures 31 and 32.

[0414] First, Figure 31 shows a product image that can be used in a semiconductor device according to one embodiment of the present invention. Region 501 in Figure 31 represents a high temperature characteristic (High T operate), region 502 represents a high frequency characteristic (High f operate), region 503 represents a low off-mode characteristic (Ioff), and region 504 represents the overlapping region of regions 501, 502, and 503.

[0415] Furthermore, to satisfy region 501, it can be roughly satisfied by using silicon carbide or gallium nitride or other carbides or nitrides as the channel formation region of the semiconductor device. Similarly, to satisfy region 502, it can be roughly satisfied by using single-crystal silicon or crystalline silicon or other silides as the channel formation region of the semiconductor device. Finally, to satisfy region 503, it can be roughly satisfied by using oxide semiconductors or metal oxides as the channel formation region of the semiconductor device.

[0416] A semiconductor device according to one aspect of the present invention can be suitably used, for example, in products within the range shown in region 504.

[0417] In conventional products, it was difficult to satisfy all of regions 501, 502, and 503. However, a semiconductor device according to one aspect of the present invention has crystalline OS in the channel formation region. When crystalline OS is present in the channel formation region, it is possible to provide a semiconductor device and electronic device that satisfy high temperature characteristics, high frequency characteristics, and low off-peak characteristics.

[0418] Products within the scope of area 504 include, for example, electronic devices such as low-power, high-performance CPUs, and automotive electronic devices that require high reliability in high-temperature environments.

[0419] More specifically, a semiconductor device according to one aspect of the present invention can be used as a processor such as a CPU or GPU, or as a chip. Figure 32 shows a specific example of an electronic device equipped with a processor such as a CPU or GPU, or as a chip according to one aspect of the present invention.

[0420] <Electronic Equipment and Systems> A GPU or chip according to one aspect of the present invention can be mounted in various electronic devices. Examples of electronic devices include, for example, television equipment, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices. Furthermore, by providing an integrated circuit or chip according to one aspect of the present invention in an electronic device, artificial intelligence can be mounted in the electronic device.

[0421] An electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, the display unit can display images, information, etc. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0422] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0423] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on. An example of an electronic device is shown in Figure 32.

[0424] [mobile phone]

[0425] Figure 32(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0426] The information terminal 5500 can execute applications utilizing artificial intelligence by applying a chip according to one aspect of the present invention. Examples of applications utilizing artificial intelligence include applications that recognize conversations and display the content of those conversations on the display unit 5511, applications that recognize characters, figures, etc., entered by the user on the touch panel provided on the display unit 5511 and display them on the display unit 5511, and applications that perform biometric authentication such as fingerprints and voiceprints.

[0427] [Information Terminal 1] Figure 32(B) shows a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display 5302, and a keyboard 5303.

[0428] The desktop information terminal 5300, like the information terminal 5500 described above, can run applications utilizing artificial intelligence by applying a chip according to one embodiment of the present invention. Examples of applications utilizing artificial intelligence include design support software, document editing software, and automatic menu generation software. Furthermore, the desktop information terminal 5300 can be used to develop new artificial intelligence.

[0429] In the above, smartphones and desktop information terminals were used as examples of electronic devices and illustrated in Figures 32(A) and (B), respectively. However, information terminals other than smartphones and desktop information terminals can also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0430] [electric appliances] Figure 32(C) shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0431] By applying a chip according to one aspect of the present invention to an electric refrigerator 5800, an electric refrigerator 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5800 can have functions such as automatically generating menus based on the ingredients stored in the electric refrigerator 5800 and their expiration dates, and automatically adjusting the temperature to suit the ingredients stored in the electric refrigerator 5800.

[0432] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0433] [Game console] Figure 32(D) shows a portable game console 5200, which is an example of a game console. The portable game console has a casing 5201, a display unit 5202, buttons 5203, etc.

[0434] By applying a GPU or chip according to one aspect of the present invention to a portable game console 5200, a portable game console 5200 with low power consumption can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0435] Furthermore, by applying a GPU or chip according to one aspect of the present invention to the portable game console 5200, a portable game console 5200 with artificial intelligence can be realized.

[0436] Normally, the progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the game's program. However, by applying artificial intelligence to the 5200 handheld game console, it becomes possible to express things that are not limited to the game's program. For example, it becomes possible to express changes in the content of questions asked by the player, the game's progress, the time, and the behavior of characters appearing in the game.

[0437] Furthermore, when playing games that require multiple players on the 5200 handheld game console, artificial intelligence can be used to create anthropomorphic game players. By using AI-generated game players as opponents, it becomes possible to play the game even by a single player.

[0438] Figure 32(D) shows a portable game console as an example of a game console, but the game consoles to which the GPU or chip of one aspect of the present invention is applied are not limited to this. Examples of game consoles to which the GPU or chip of one aspect of the present invention is applied include home game consoles, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0439] [Mobile] A GPU or chip according to one aspect of the present invention can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0440] Figure 32(E1) shows an example of a mobile vehicle, automobile 5700, and Figure 32(E2) shows the area around the windshield inside the automobile. In Figure 32(E2), display panels 5701, 5702, and 5703 mounted on the dashboard are shown, as well as a display panel 5704 mounted on the pillar.

[0441] Display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, and more. Furthermore, the display items and layout on the display panels can be changed as needed to suit the user's preferences, enhancing the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0442] The display panel 5704 can display images from an imaging device (not shown) installed in the vehicle 5700, thereby compensating for the blind spots obstructed by the pillars. In other words, by displaying images from an imaging device installed on the outside of the vehicle 5700, blind spots can be compensated for, and safety can be enhanced. Furthermore, by displaying images that compensate for the parts that are not visible, safety checks can be performed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0443] A GPU or chip according to one aspect of the present invention can be applied as a component of artificial intelligence, and for example, the chip can be used in an autonomous driving system for an automobile 5700. The chip can also be used in systems that perform tasks such as road guidance and hazard prediction. Display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0444] Although automobiles are described above as an example of a mobile device, mobile devices are not limited to automobiles. For example, mobile devices can also include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and by applying a chip according to one aspect of the present invention to these mobile devices, a system utilizing artificial intelligence can be provided.

[0445] [Broadcasting System] A GPU or chip according to one aspect of the present invention can be applied to a broadcasting system.

[0446] Figure 32(F) schematically illustrates data transmission in a broadcasting system. Specifically, Figure 32(F) shows the path from radio waves (broadcast signals) transmitted from broadcasting station 5680 to television receiving devices (TVs) 5600 in each household. The TV 5600 is equipped with a receiving device (not shown), and the broadcast signal received by antenna 5650 is transmitted to the TV 5600 via this receiving device.

[0447] In Figure 32(F), antenna 5650 is shown as a UHF (Ultra High Frequency) antenna, but antennas such as BS / 110°CS antennas and CS antennas can also be used as antenna 5650.

[0448] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting. Radio tower 5670 amplifies the received radio wave 5675A and transmits radio wave 5675B. Each household can receive radio wave 5675B with antenna 5650 and watch terrestrial TV broadcasts on TV 5600. Note that the broadcasting system is not limited to terrestrial broadcasting as shown in Figure 32(F), but may also include satellite broadcasting using artificial satellites, data broadcasting via fiber optic lines, etc.

[0449] The broadcasting system described above may also be an artificial intelligence-based broadcasting system by applying a chip according to one aspect of the present invention. When broadcasting data is transmitted from the broadcasting station 5680 to the TVs 5600 in each home, the broadcasting data is compressed by an encoder, and when the antenna 5650 receives the broadcasting data, the broadcasting data is restored by a decoder in the receiving device included in the TV 5600. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, it is possible to recognize display patterns included in the displayed image. It is also possible to perform in-frame prediction using artificial intelligence. Furthermore, for example, when receiving low-resolution broadcasting data and displaying the broadcasting data on a high-resolution TV 5600, image interpolation processing such as upconversion can be performed in the restoration of the broadcasting data by the decoder.

[0450] The broadcasting system utilizing artificial intelligence described above is suitable for ultra-high-definition television (UHDTV: 4K, 8K) broadcasting, where the amount of broadcast data increases.

[0451] Furthermore, as an application of artificial intelligence on the TV5600 side, for example, a recording device equipped with artificial intelligence may be provided in the TV5600. By configuring it in this way, the recording device can be programmed to learn the user's preferences, enabling it to automatically record programs that match the user's preferences.

[0452] The electronic devices described in this embodiment, their functions, examples of artificial intelligence applications, and their effects can be appropriately combined with descriptions of other electronic devices.

[0453] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of Symbols]

[0454] 100: Capacitive element, 100a: Capacitive element, 110: Conductor, 110a: Conductor, 112: Conductor, 114: Insulator, 114a: Insulator, 114b: Insulator, 116: Insulator, 120: Conductor, 120a: Conductor, 130: Insulator, 130a: Insulator, 140: Insulator, 140a: Insulator, 140b: Insulator, 150: Insulator, 152: Conductor, 154: Insulator, 156: Insulator, 200: Transistor ,200a:transistor, 200b:transistor, 205:conductor, 205a:conductor, 205b:conductor, 210:insulator, 212:insulator, 214:insulator, 216:insulator, 222:insulator, 224:insulator, 230:oxide, 230a:oxide, 230A:oxide film, 230b:oxide, 230B:oxide film, 230c:oxide, 230C:oxide film, 231a:region, 231b:region, 234 : Region, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242A: Conductive film, 242b: Conductor, 242B: Conductive layer, 243: Oxide, 243a: Oxide, 243A: Oxide film, 243b: Oxide, 243B: Oxide layer, 245: Conductor, 246: Conductor, 246a: Conductor, 246b: Conductor, 247: Conductor, 247a: Conductor, 247b: Conductor, 250: Insulator, 250A: Insulating film, 260: Conductor, 260a: Conductor, 260Aa: Conductive film, 260Ab: Conductive film, 260b: Conductor, 265: Dummy film, 265A: Dummy film, 272: Insulator, 272A: Insulating film, 273: Insulator, 273A: Insulating film, 274: Insulator, 276: Insulator, 280: Insulator, 281: Insulator, 282: Insulator

Claims

1. a first insulator having an opening in which a first conductor is disposed, and a transistor located on the first insulator; The transistor a first oxide overlying the first insulator; a second oxide located on the first oxide; and one of a source electrode and a drain electrode having a region in contact with a side surface of the first oxide and a side surface of the second oxide; a gate electrode located on the second oxide; one of the source electrode and the drain electrode is provided at a position overlapping with the first conductor; the gate electrode is provided in an opening formed in a second insulator located above one of the source electrode and the drain electrode; a third oxide is located between the gate electrode and the second oxide in a region overlapping with the opening of the second insulator;

2. a first insulator having an opening in which a first conductor is disposed, and a transistor located on the first insulator; The transistor a first oxide semiconductor located on the first insulator; a second oxide semiconductor located on the first oxide semiconductor; one of a source electrode and a drain electrode having a region in contact with a side surface of the first oxide semiconductor and a side surface of the second oxide semiconductor; a gate electrode located on the second oxide semiconductor; one of the source electrode and the drain electrode is provided at a position overlapping with the first conductor; the gate electrode is provided in an opening formed in a second insulator located above one of the source electrode and the drain electrode; a third oxide semiconductor is located between the gate electrode and the second oxide semiconductor in a region overlapping with an opening in the second insulator.

3. a first insulator having an opening in which a first conductor is disposed, and a transistor located on the first insulator; The transistor a first oxide semiconductor located on the first insulator; a second oxide semiconductor located on the first oxide semiconductor; a first oxide and a second oxide located on the second oxide semiconductor; one of a source electrode and a drain electrode having a region in contact with a side surface of the first oxide semiconductor, a side surface of the second oxide semiconductor, and a side surface and an upper surface of the second oxide semiconductor; a gate electrode located on the second oxide semiconductor; one of the source electrode and the drain electrode is provided at a position overlapping with the first conductor; the gate electrode is provided in an opening formed in a second insulator located above one of the source electrode and the drain electrode; a third oxide semiconductor is located between the gate electrode and the second oxide semiconductor in a region overlapping with an opening in the second insulator.

4. a first insulator having an opening in which a first conductor is disposed, and a transistor located on the first insulator; The transistor a first oxide overlying the first insulator; a second oxide located on the first oxide; and one of a source electrode and a drain electrode having a region in contact with a side surface of the first oxide and a side surface of the second oxide; a gate electrode located on the second oxide; one of the source electrode and the drain electrode has a region in contact with an upper surface of the first conductor; the gate electrode is provided in an opening formed in a second insulator located above one of the source electrode and the drain electrode; a third oxide is located between the gate electrode and the second oxide in a region overlapping with the opening of the second insulator;

5. a first insulator having an opening in which a first conductor is disposed, and a transistor located on the first insulator; The transistor a first oxide semiconductor located on the first insulator; a second oxide semiconductor located on the first oxide semiconductor; one of a source electrode and a drain electrode having a region in contact with a side surface of the first oxide semiconductor and a side surface of the second oxide semiconductor; a gate electrode located on the second oxide semiconductor; one of the source electrode and the drain electrode has a region in contact with an upper surface of the first conductor; the gate electrode is provided in an opening formed in a second insulator located above one of the source electrode and the drain electrode; a third oxide semiconductor is located between the gate electrode and the second oxide semiconductor in a region overlapping with an opening in the second insulator.

6. a first insulator having an opening in which a first conductor is disposed, and a transistor located on the first insulator; The transistor a first oxide semiconductor located on the first insulator; a second oxide semiconductor located on the first oxide semiconductor; a first oxide and a second oxide located on the second oxide semiconductor; one of a source electrode and a drain electrode having a region in contact with a side surface of the first oxide semiconductor, a side surface of the second oxide semiconductor, and a side surface and an upper surface of the second oxide semiconductor; a gate electrode located on the second oxide semiconductor; one of the source electrode and the drain electrode has a region in contact with an upper surface of the first conductor; the gate electrode is provided in an opening formed in a second insulator located above one of the source electrode and the drain electrode; a third oxide semiconductor is located between the gate electrode and the second oxide semiconductor in a region overlapping with an opening in the second insulator.

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