Semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics, which has stable electric characteristics.SOLUTION: A transistor 100A includes: a semiconductor layer 108 that contains a metal oxide; a first insulation layer 103; a second insulation layer 110; a third insulation layer 116 that contains a nitride; and a first conductive layer 112. The first insulation layer includes: a first region 103a that is overlapped with the semiconductor layer, and has a convex shape; and a second region 103b that is not overlapped with the semiconductor layer, and is thinner than the first region. The second insulation layer is provided so as to cover an upper surface of the second region, a side surface of the first region, and the semiconductor layer. The first conductive layer is provided on the second insulation layer, and includes a part where a lower surface on the second region is located lower than the lower surface of the semiconductor layer. The semiconductor layer includes: a third region that is overlapped with the second insulation layer and the first conductive layer; and a fourth region 108N that is not overlapped with the first conductive layer nor the second insulation layer. The third insulation layer 116 is provided so as to be in contact with the fourth region of the semiconductor layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and a , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof A semiconductor device functions by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used for transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called the mobility A semiconductor device having improved mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed by using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. The company plans to improve some of its production facilities for transistors using polycrystalline silicon and amorphous silicon. This allows the use of metal oxide transistors, which reduces capital investment. The field effect mobility of the transistor is higher than that of amorphous silicon, so the driver circuit It is possible to realize a high-performance display device having the above-mentioned structure.

[0005] In addition, Patent Document 2 discloses that aluminum, boron, and gallium are added to the source and drain regions. The group consisting of lithium, indium, titanium, silicon, germanium, tin, and lead. An oxide semiconductor film having a low-resistance region containing at least one of these as a dopant is used. A thin film transistor having the same structure is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-7399 A [Patent Document 2] JP 2011-228622 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a semiconductor device capable of passing a large current. Another object of the present invention is to provide a semiconductor device having stable electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. One of the objectives of the project is to

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from descriptions in the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a third insulating layer, A semiconductor device having a first conductive layer. The semiconductor layer is provided on the first insulating layer. The first insulating layer has a shape in which a part overlapping with the semiconductor layer protrudes in the thickness direction. a first region overlapping the semiconductor layer, and a second region not overlapping the semiconductor layer and thinner than the first region; The second insulating layer is disposed on the top surface of the second region, the side surface of the first region, and the top surface of the semiconductor layer. The first conductive layer is disposed on the second insulating layer and covers the front and side surfaces. The lower surface of the semiconductor layer in the region 2 has a portion located lower than the lower surface of the semiconductor layer. a third region overlapping the second insulating layer and the first conductive layer; and a second region overlapping the first conductive layer and the second insulating layer. and a fourth region that does not overlap with the third insulating layer. The third insulating layer is in contact with the fourth region of the semiconductor layer. The semiconductor layer includes a metal oxide, and the third insulating layer includes a nitride.

[0010] In the above, the first insulating layer has a thickness in the first region that is 1. It is preferably 2 to 10 times.

[0011] In the above, the first insulating layer has a side surface of the first region that contacts the lower end of the semiconductor layer. It is preferable that the gradient change continuously from the first region to the second region.

[0012] In the above, the upper surface of the first conductive layer is located lower than the lower surface of the semiconductor layer. It is preferred that the .alpha.-amino acid has a moiety.

[0013] In the above, the semiconductor layer is composed of a first metal oxide film and a second metal oxide film. In this case, the second metal oxide film preferably has a layered structure in which the first metal oxide film and the second metal oxide film are layered in this order. It is preferable that the second metal oxide film has higher crystallinity than the first metal oxide film.

[0014] Alternatively, in the above, the semiconductor layer comprises a first metal oxide film and a second metal oxide film. In this case, the first metal oxide film is preferably located on the first region, and the second The metal oxide film is in contact with the side surface of the first region and the side surface and the top surface of the first metal oxide film. It is preferable that the second metal oxide film is provided so as to be thicker than the first metal oxide film. It is preferable that the crystallinity is high.

[0015] In the above, the third insulating layer is made of aluminum, titanium, tantalum, or tungsten. It is preferable that the alloy contains one or more elements selected from the group consisting of ruthenium, chromium, and ruthenium, and nitrogen. In this case, it is preferable that metallic indium is present in the fourth region of the semiconductor layer. stomach.

[0016] Alternatively, in the above, the third insulating layer may contain silicon, nitrogen, and hydrogen. preferable.

[0017] In the above, the channel length in the region of the first conductive layer overlapping with the semiconductor layer is The length in the direction is preferably 2 μm or more and 3 μm or less.

[0018] In the above, the channel width direction in the region of the semiconductor layer covered with the first conductive layer is The length in the direction is preferably 1 μm or more and 100 μm or less.

[0019] Another embodiment of the present invention is a method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer including an oxide; A second step of forming a metal oxide film on the insulating layer of the first step, and a resist mask on the metal oxide film. A resist mask is formed, and a part of the metal oxide film that is not covered by the resist mask is etched to form a semiconductor a third step of forming a dielectric layer and exposing a portion of the first insulating layer; The portion of the first insulating layer that is not covered by the semiconductor layer is etched to thin it, and the first region overlapping the semiconductor layer is thinned. a fourth step of forming a first region that does not overlap with the semiconductor layer and a second region that does not overlap with the semiconductor layer; a fifth step of removing a second layer covering the semiconductor layer, the side surface of the first region, and the top surface of the second region; a first conductive layer having a lower surface lower than a lower surface of the semiconductor layer and disposed on the second insulating layer; a sixth step of forming a conductive layer in contact with a portion of the semiconductor layer that is not covered by the first conductive layer; and a seventh step of performing a heat treatment after forming the first layer containing a nitride. A method for fabricating a semiconductor device.

[0020] In the above, the first layer is made of aluminum, titanium, tantalum, tungsten, The alloy is formed so as to contain one or more elements selected from chromium and ruthenium, and nitrogen. is preferred.

[0021] Alternatively, in the above, the first layer is formed so as to contain silicon, nitrogen, and hydrogen. It is preferable that Effect of the Invention

[0022] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. It is possible to provide a semiconductor device capable of passing a current. Alternatively, a highly reliable semiconductor device can be provided. A display device can be provided.

[0023] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief description of the drawings]

[0024] [Figure 1] (A), (B), and (C) are examples of semiconductor device configurations. [Diagram 2] (A) and (B) Examples of semiconductor device configurations. [Diagram 3] (A), (B), and (C) are examples of semiconductor device configurations. [Figure 4] (A) and (B) Examples of semiconductor device configurations. [Diagram 5] (A), (B), and (C) are examples of semiconductor device configurations. [Figure 6] 1A and 1B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 7] 1A and 1B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 8] 1A and 1B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 9] 1A and 1B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 10] 1A and 1B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 11] (A), (B), and (C) are top views of the display device. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] FIG. [Figure 15] FIG. [Figure 16](A) Block diagram of the display device, (B) and (C) circuit diagrams. [Figure 17] (A), (C), and (D) are circuit diagrams of the display device, and (B) is a timing chart. [Figure 18] (A) and (B) Example of display module configuration. [Figure 19] (A) and (B) Examples of electronic device configurations. [Figure 20] (A) to (E) Examples of electronic device configurations. [Figure 21] (A) to (G) Examples of electronic device configurations. [Figure 22] (A) to (D) Examples of electronic device configurations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0026] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component is May be exaggerated for clarity.

[0027] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the This is added to avoid confusion and is not intended to limit the number.

[0028] In addition, in this specification, the words "above" and "below" that indicate the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0029] In this specification, the functions of the source and drain of a transistor are different. When using polarity transistors, or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are often used interchangeably. It is possible to do so.

[0030] In this specification, the channel length direction of a transistor is the direction between the source region and the drain region. This refers to one of the directions parallel to the line that connects the two gate regions at the shortest distance. That is, the channel length The direction corresponds to one of the directions of current flow through the semiconductor layer when the transistor is in the on state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction are determined as one. This may not be possible.

[0031] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0032] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and The term "insulating film" may sometimes be used interchangeably.

[0033] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source gs is the threshold voltage V th (For p-channel transistors, V th Higher than (i) This refers to a state of being.

[0034] In this specification, a display panel, which is one aspect of a display device, displays (outputs) images on a display surface. Therefore, the display panel is one aspect of an output device.

[0035] In the present specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). inted Circuit) or TCP (Tape Carrier Packa ge) or COG (Chip On Gauge) connectors attached to the board. Display module is a device that has ICs mounted using a method such as display glass. It may be called a display panel, a display unit, or simply a display panel.

[0036] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images, etc. on a display surface. The function of displaying information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. The touch panel also functions as a touch sensor that detects the touch of the touch panel. A card is one form of input / output device.

[0037] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with touch function. A display panel and a touch sensor panel may be used. It may also be configured to have a touch sensor function inside or on the surface.

[0038] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. It may be called a touch panel module, a display module, or simply a touch panel. be.

[0039] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to one embodiment of the present invention will be described. I will explain it below.

[0040] One aspect of the present invention is a semiconductor layer in which a channel is formed on a first insulating layer; A gate insulating layer is formed on the gate insulating layer, and a conductive layer (a first conductive layer) that functions as a gate electrode is formed on the gate insulating layer. The semiconductor layer is a metal oxide ( Hereinafter, it is preferable that the insulating film 100 includes an oxide semiconductor.

[0041] The first insulating layer has a first region overlapping the semiconductor layer and a second region other than the first region. In addition, the first insulating layer has a thickness in the first region greater than a thickness in the second region. The first region has a protrusion protruding in the thickness direction from the second region. The layer is disposed over the raised portion of the first region of the first insulating layer.

[0042] In addition, the side surface of the first region of the first insulating layer (i.e., the outer edge of the protrusion) is tapered. In this case, it is preferable that the angle between the side surface of the first region and the top surface of the second region is: More than 90° and less than 180°, preferably 100° or more and 170° or less, more preferably The angle is set to 110° or more and 160° or less. This allows the gate insulating layer covering the side surface of the first region to Since the covering property can be improved, the thickness of this portion can be prevented from becoming thin.

[0043] The side surface of the first region of the first insulating layer extends from the portion in contact with the lower end of the semiconductor layer to the second It is preferable that the shape of the semiconductor layer is such that the gradient changes continuously from the upper to the lower regions. A gate insulating layer covering the gate electrode and the first insulating layer, and a coating layer for the first layer, etc., which will be described later The performance can be further improved.

[0044] The gate insulating layer and the gate electrode are formed in a semiconductor layer in the channel width direction of the transistor. the top and side surfaces of the body layer, and the side surfaces of the first region and the top surface of the second region of the first insulating layer. At this time, the lower surface of the gate electrode in the portion overlapping with the second region is It is preferable that the first region is located below the lower surface of the semiconductor layer. When a voltage is applied to the electrode, the electric field generated is generated not only from the top side of the semiconductor layer, but also from the side and The electric field acts from the diagonally downward direction and electrically surrounds the semiconductor layer. Therefore, it is possible to more effectively apply an electric field for inducing a channel in the semiconductor layer. This improves the field effect mobility of the transistor and increases the on-state current. do.

[0045] The difference in thickness between the first region and the second region of the first insulating layer is determined in consideration of the thickness of the gate insulating layer, etc. The difference in thickness between the first and second regions can be controlled by considering at least the gate. The thickness of the gate insulating layer is set to be larger than that of the gate insulating layer. When a layer other than the first layer is provided, the second region is processed to be thin, taking into consideration the thickness of the layer. is preferred.

[0046] For example, the thickness of the first region is 1.2 times or more, preferably 1.5 times, the thickness of the second region. More preferably, the ratio is 2 times or more, and even more preferably, the ratio is 2.5 times or more, and the ratio is 10 times or less. It can be a thickness.

[0047] Alternatively, the difference between the thickness of the first region and the thickness of the second region is equal to or greater than 1 time the thickness of the gate insulating layer. Preferably, the ratio is 1.2 or more, more preferably 1.5 or more, and even more preferably 2 or more. It is preferable that the first insulating layer is processed so that the difference is 20 times or less.

[0048] An example of a method for forming the first insulating layer will be described. First, a film is formed on an insulating film that will become the first insulating layer. A metal oxide film that will become a semiconductor layer is formed, and a resist mask is formed on the metal oxide film. A part of the metal oxide film that is not covered with the resist mask is etched to form a semiconductor layer. Next, the portion of the insulating film that will become the first insulating layer that is not covered by the resist mask is etched. By thinning the semiconductor layer by etching, a first region overlapping the semiconductor layer and a second region having a thickness smaller than the first region are formed. A thin second region can be formed. At this time, the etching is performed so that the second region does not disappear. It is important to keep the timing

[0049] The first insulating layer has a laminated structure in which two or more insulating films are laminated, and the second region is One or more insulating films located on the insulating layer may be removed.

[0050] Here, the metal oxide film is etched by wet etching to form a first insulating layer. For etching the insulating film, it is preferable to use an anisotropic dry etching method. The metal oxide film and the insulating film that will become the first insulating layer are continuously formed by dry etching. The etching may be performed by

[0051] The region of the semiconductor layer covered by the gate electrode functions as a channel forming region. The regions not covered by the gate electrode function as source or drain regions, forming a channel shape. It is preferable that the region has a lower resistance than the formed region (hereinafter, also referred to as a low resistance region). A second insulating layer capable of reducing the resistance of the semiconductor layer is provided in a portion of the semiconductor layer that is not covered by the gate electrode. It is preferable that the first insulating layer (also referred to as the third insulating layer) is provided in contact with the first insulating layer.

[0052] For example, the low resistance region of the semiconductor layer is in a state where a first layer is formed to cover the low resistance region. It is preferable that the resistance of the region is reduced by performing a heat treatment at .

[0053] The first layer may be made of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. A film containing at least one metal element such as aluminum or arsenic can be used. It is preferable that the metal contains at least one of aluminum, titanium, tantalum, and tungsten. A nitride containing at least one of these metal elements, or a nitride containing at least one of these metal elements An oxide containing the following can be suitably used.

[0054] For example, nitrides such as aluminum nitride film, aluminum titanium nitride film, and titanium nitride film A film or an oxide film such as an aluminum titanium oxide film can be preferably used. Alternatively, a metal film such as a tungsten film or a titanium film may be used.

[0055] For example, when an aluminum titanium nitride film is used, the composition formula is AlTiN x (x is greater than 0 (real number less than 3) or the composition formula is AlTi x N y (x is a real number greater than 0 and less than or equal to 2, It is more preferable to use a film that satisfies the following condition: y is a real number greater than 0 and less than or equal to 4.

[0056] In addition, the higher the temperature of the heat treatment, the more the resistance of the low resistance region is reduced, which is preferable. The temperature of the heat treatment may be determined in consideration of the heat resistance of the gate electrode. For example, 150° C. 500°C or higher, preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher The temperature can be 450° C. or less, and more preferably 300° C. or more and 400° C. or less. For example, by setting the heat treatment temperature at around 350°C, production equipment using large glass substrates can be used. Therefore, semiconductor devices can be produced with a high yield.

[0057] In a state where the first layer is provided in contact with a part of the semiconductor layer, a heat treatment is performed to form a layer in the semiconductor layer. The oxygen is absorbed into the first layer, and many oxygen vacancies are formed in the semiconductor layer. This makes it possible to form a low resistance region with an extremely low resistance.

[0058] The low resistance region thus formed has the characteristic that it is difficult for the resistance to increase during subsequent processing. For example, heat treatment in an atmosphere containing oxygen, film formation in an atmosphere containing oxygen, etc. Even if the above process is performed, there is no risk of impairing the conductivity of the low resistance region, so the electrical properties are good and A highly reliable transistor can be realized.

[0059] In addition, in the case where the first layer after the heat treatment has electrical conductivity, the first layer after the heat treatment On the other hand, if the first layer has insulating properties, it is preferable to leave it. By doing so, the first layer can function as a protective insulating film (third insulating layer).

[0060] In particular, the above-mentioned aluminum nitride or aluminum titanium nitride film has excellent insulating properties. Since it is a film, it is preferable to leave it.

[0061] Alternatively, the low resistance region may be a region that contains more hydrogen than the channel formation region. This allows the low resistance region to have a lower resistance than the channel formation region. As a result, the carrier density in the channel formation region is extremely low, and the source and drain regions Since the resistance of the semiconductor layer is extremely low, a transistor with excellent electrical characteristics can be realized.

[0062] As a method for supplying hydrogen to the low resistance region, for example, a film containing hydrogen (the first layer) is used. It is preferable to provide the insulating layer (3) in contact with a part of the semiconductor layer and perform the heat treatment in that state. This allows the hydrogen concentration in the low resistance region to be higher than that in the channel formation region. do.

[0063] The first layer is preferably an insulating film containing, for example, silicon, hydrogen, and nitrogen. More specifically, hydrogen-containing silicon nitride film formed by plasma CVD is preferred. It is preferable to use a silicon nitride (SiN:H) film.

[0064] The method of supplying hydrogen to the low resistance region is not limited to the above. For example, Examples of methods include ion doping, ion implantation, and heat treatment in an atmosphere containing hydrogen. Hydrogen may be supplied to the semiconductor layer by the method described above.

[0065] Here, the first insulating layer is preferably a film capable of releasing oxygen when heated. At this time, a first region located in the lower part of the semiconductor layer is heated to form a channel formation region of the semiconductor layer. It is possible to supply oxygen to the area.

[0066] Furthermore, the first layer (third insulating layer) not only covers the low resistance region of the semiconductor layer, but also a first region located outside the low resistance region of the semiconductor layer in the channel length direction of the transistor; It is preferable that the first layer is provided so as to cover the side surface of the first region of the insulating layer. Since the first region has a property of being difficult to transmit oxygen, the oxygen contained in the first region is absorbed outward from the side surface. This prevents a large amount of oxygen from diffusing into the channel formation region of the semiconductor layer. This reduces the carrier density in the channel formation region, resulting in a highly reliable transistor. A transistor can be realized.

[0067] A transistor according to one embodiment of the present invention having such a structure has favorable electrical characteristics and high reliability. It is a highly reliable transistor.

[0068] A more specific example will be described below with reference to the drawings.

[0069] [Configuration example 1] FIG. 1A is a top view of a transistor 100, and FIG. 1B is a top view of the transistor 100 shown in FIG. FIG. 1C is a cross-sectional view taken along the dashed line A1-A2 shown in FIG. It corresponds to a cross-sectional view taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as an insulating layer) are omitted in the figure. The direction of the line A1-A2 corresponds to the channel length direction, and the direction of the dashed line B1-B2 corresponds to the channel width direction. In addition, the top views of the transistors in the following drawings are the same as those in FIG. , some of the components are omitted in the illustration.

[0070] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating The insulating layer 116 is a dielectric layer 118. The insulating layer 118 is a dielectric layer 116. The insulating layer 118 is a dielectric layer 118. The insulating layer 116 is a dielectric layer. The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The layer 114 and the conductive layer 112 are, in this order, a part of the semiconductor layer 108 and a part of the insulating layer 103. The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are laminated to cover the portion. The insulating layer 116 is provided so that the upper surface shapes of the insulating layer 116 and the insulating layer 116 are substantially the same in plan view. The top and side surfaces of the conductive layer 112, the side surfaces of the metal oxide layer 114, and the top and side surfaces of the insulating layer 110 The insulating layer 103 is provided to cover the upper and side surfaces of the semiconductor layer 108 and the surface of the insulating layer 103 . An insulating layer 118 is provided over insulating layer 116 .

[0071] In this specification, the term "approximately coincident upper surface shapes" means that there is at least a slight difference between the layers. For example, the upper and lower layers have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where a part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0072] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The portion of the semiconductor layer 108 that overlaps with the conductive layer 112 serves as a channel formation region. The transistor 100 has a gate electrode provided on the semiconductor layer 108. , a so-called top-gate transistor.

[0073] As shown in FIGS. 1A and 1B, the transistor 100 is formed on an insulating layer 118. The conductive layer 120a and the conductive layer 120b may be included. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. are the openings 141a and 141b provided in the insulating layer 118 and the insulating layer 116, respectively. It is electrically connected to a region 108N, which will be described later, via 41b.

[0074] The semiconductor layer 108 preferably comprises a metal oxide.

[0075] For example, the semiconductor layer 108 may be made of indium and M (where M is gallium, aluminum, or silicon). Boron, Yttrium, Tin, Copper, Vanadium, Beryllium, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, and magnesium; and zinc. In particular, M is aluminum, gallium, yttrium, or It is preferable to use one or more elements selected from tin.

[0076] In particular, the semiconductor layer 108 is made of an oxide containing indium, gallium, and zinc. It is preferable.

[0077] The semiconductor layer 108 may be a layer having a different composition, a layer having a different crystallinity, or a layer having a different impurity concentration. Alternatively, a laminate structure in which different layers are laminated may be used.

[0078] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained therein from diffusing into the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, A material that is less permeable to oxygen and hydrogen than 0 can be used.

[0079] When the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper, However, the metal oxide layer 114 prevents oxygen from diffusing from the insulating layer 110 to the conductive layer 112. Even when the conductive layer 112 contains hydrogen, the conductive layer 112 can be prevented from Therefore, it is possible to prevent hydrogen from diffusing into the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0080] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0081] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a gate film or the like since the driving voltage can be reduced.

[0082] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). Conductive oxides such as silicon-doped indium tin oxide (ITSO) In particular, conductive oxides containing indium are preferred because of their high conductivity. .

[0083] The metal oxide layer 114 may be made of an oxide material containing at least one of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use the same structure as the semiconductor layer 108 as the metal oxide layer 114. By applying metal oxide films formed using sputtering targets, equipment can be standardized This is preferable because it allows

[0084] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. When a metal oxide material containing gallium is used, the composition of gallium is higher than that of the material used for the semiconductor layer 108. When a material having a high content is used for the metal oxide layer 114, the blocking property against oxygen is improved. In this case, the semiconductor layer 108 is preferably a metal oxide layer. By using a material with a higher indium content than the material used in 114, The field effect mobility of the transistor 100 can be improved.

[0085] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering device, it is formed in an atmosphere containing oxygen gas. This allows oxygen to be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0086] The semiconductor layer 108 has a channel forming region that overlaps with the conductive layer 112 via the insulating layer 110. The semiconductor layer 108 has a pair of regions 108N that sandwich the channel formation region. The region 108N is a region having a lower resistance than the channel formation region, and the transistor 10 0 source or drain region.

[0087] The insulating layer 103 has a region 103a overlapping with the semiconductor layer 108 and a region 103b overlapping with the semiconductor layer 108. The insulating layer 103 has a region 103a that is thicker than the region 103b. The region 103a has a shape that protrudes in the thickness direction.

[0088] The region 103a of the insulating layer 103 is thicker than the region 103b. The side surface of the region 103a (the outer edge of the protruding portion of the insulating layer 103) is in contact with the lower end of the semiconductor layer 108. It is preferable that the region 103b has a tapered shape from the region 103b. It is preferable that the angle between the side surface of 103a and the upper surface of the region 103b is an obtuse angle. Specifically, the angle between the side surface of the region 103a and the top surface of the region 103b is greater than 90°. Less than 180°, preferably 100° to 170°, more preferably 110° to 160° 0° or less. This allows the film (e.g. For example, the insulating layer 110, the metal oxide layer 114, the conductive layer 112, the insulating layer 116, etc. This allows the particles to rise, making it difficult for low-density areas (also called porosity) to form. The reliability of the transistor 100 can be improved.

[0089] Furthermore, the side surface of the region 103a is such that the upper end portion (the portion in contact with the lower end portion of the semiconductor layer 108) The shape has a continuous gradient from the upper surface of the region 103b to the upper surface of the region 103b. In this way, it is preferable that the side surface of the region 103a has a gently curved shape and the region 1 The side surface of region 103a and the upper surface of region 103b are continuously connected to each other, so that insulating layer 1 This can further improve the coverage of the film located above 03.

[0090] As shown in FIG. 1C, in the channel width direction, an insulating layer 110, a metal oxide layer 11 4, and the conductive layer 112 are formed on the top and side surfaces of the semiconductor layer 108 and the region of the insulating layer 103. It is provided to cover the side surface of 103a and the upper surface of region 103b.

[0091] FIG. 2(A) is an enlarged view of a portion of FIG. 1(C). In FIG. 2(A), the thicknesses t1 to t4 are shown. and heights h1 to h4, respectively.

[0092] The thickness t1 is the thickness of the region 103a, and the thickness t2 is the thickness of the region 103b. The thickness t3 is the thickness of the insulating layer 110 and the metal oxide layer 103b in the portion overlapping the region 103b. The thickness t4 is the total thickness of the insulating layer 114 in the portion overlapping the region 103b. 110, the metal oxide layer 114, and the conductive layer 112.

[0093] Here, if the difference between the thickness of the region 103a and the thickness of the region 103b is d1, then "d In this case, as shown in FIG. 2(A), the difference d1 is expressed as the thickness t It is preferable that the difference d1 is greater than the thickness t4. I wish.

[0094] On the other hand, the heights h1 to h4 are each based on the height of the bottom surface of the region 103a of the insulating layer 103. The height h1 is the height of the lower surface of the semiconductor layer 108 (the height between the insulating layer 103 and the semiconductor layer 108 The height h2 is the height of the upper surface ( When the insulating layer 103 and the insulating layer 110 are in contact with each other, the height h 3 is a bottom surface of the conductive layer 112 (conductive layer 112 and metal The height h4 is the height of the interface between the region 1 and the oxide layer 114. The upper surface of the conductive layer 112 (where the conductive layer 112 and the insulating layer 116 overlap) in the portion overlapping with 03b If they are in contact, this is the height of their interface.

[0095] At this time, as shown in FIG. 2A, the height h1 of the lower surface of the semiconductor layer 108 is The height h1 is preferably greater than the height h3 of the bottom surface of the conductive layer 112. It is more preferable that the height is higher than the height h4.

[0096] As shown in FIG. 2B, the difference d1 between the thickness of the region 103a and the thickness of the region 103b The insulating layer 110, the metal oxide layer 114, and the conductive layer 115 are overlapped with the region 103b. 2B, the thickness of the semiconductor layer 112 may be smaller than the thickness t4 of the semiconductor layer 112. The height h1 of the lower surface of 108 may be less than the height h4 of the upper surface of the conductive layer 112.

[0097] With this configuration, the conductive layer 112 is disposed in the channel width direction. It is recommended that the mounting position be located not only on the top surface of 08, but also on the side and diagonally below the bottom end. With such a structure, the conductive layer 112 can be electrically isolated by an electric field generated when a voltage is applied to the conductive layer 112. , the semiconductor layer 108 can be electrically surrounded, thereby increasing the on-current of the transistor 100. It can be done.

[0098] In general, by designing the ratio of channel width W to channel length L (W / L ratio) to be large, In this case, the on-state current of the transistor can be increased. Without modifying these designs, i.e., without increasing the channel width W, It is possible to improve the field effect mobility of the transistor and increase the on-current.

[0099] The channel width W of a transistor is set according to the characteristics required when it is incorporated into a circuit. However, when applied to a pixel circuit or a driving circuit of a display device, The channel width W is set to 1 μm or more and 100 μm or less, preferably 1.2 μm or more and 50 μm or less, more preferably Even if the thickness is preferably 1.5 μm or more and 30 μm or less, an extremely large current can be passed. The channel width W is not limited to this, and may be greater than 100 μm depending on the required characteristics. It may be possible to do so.

[0100] In addition, the transistor 100 can have high field-effect mobility and on-state current. The channel length L can be set relatively large, which reduces the variation in transistor characteristics and reduces the The channel length L of a transistor is the same as the channel width W. It may be set according to the required characteristic values, for example, in the pixel circuits and drive circuits of a display device. In the case of application, the channel length L is set to 1 μm or more and 20 μm or less, preferably 1.2 μm. It is preferable to set the thickness to 1.5 μm or more and 15 μm or less, and more preferably to set the thickness to 1.5 μm or more and 10 μm or less. In particular, the channel length L is set to 1.5 μm or more and 5 μm or less, preferably 2 μm or more and 3 μm or less. This reduces the variation in the channel length L within the substrate surface, thereby increasing the production yield. The channel length L is not limited to this, and can be set to 20 μm or more depending on the required characteristics. It may be larger than.

[0101] In this specification, the channel length direction of a transistor is the direction between the source region and the drain region. This refers to one of the directions parallel to the line that connects the two gate regions at the shortest distance. That is, the channel length The direction corresponds to one of the directions of current flow through the semiconductor layer when the transistor is in the on state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction are determined as one. This may not be possible.

[0102] Here, the channel length L of the transistor 100 is the length of the region overlapping with the semiconductor layer 108. The channel width of the transistor 100 is defined as the length of the conductive layer 112 in the channel length direction. is the length of the semiconductor layer 108 in the channel width direction in the region covered by the conductive layer 112. That's right.

[0103] As shown in FIG. 1B, an insulating layer 116 is provided in contact with a region 108N of the semiconductor layer 108. Since the insulating layer 116 is in contact with both the semiconductor layer 108 and the conductive layer 112, the insulating layer 116 has insulating properties. It is preferred that the compound has the formula:

[0104] The insulating layer 116 in contact with the region 108N may be an insulating film containing a nitride. By providing an insulating layer 116 containing nitride in contact with the region 108N, the conductive layer 116 of the region 108N can be formed. Furthermore, when the insulating layer 116 is in contact with the region 108N, the heat treatment is performed. Heat treatment is preferable because it promotes a further reduction in resistance.

[0105] Examples of nitrides that can be used for the insulating layer 116 include silicon nitride and gallium nitride. It is particularly preferred to use nitrides of semiconductor materials or metal nitrides such as aluminum nitride. For example, silicon nitride has a blocking effect against hydrogen and oxygen, so it is difficult to This prevents both the diffusion of hydrogen from the semiconductor layer to the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside. This makes it possible to realize a highly reliable transistor.

[0106] In addition, when metal nitrides are used, aluminum, titanium, tantalum, tungsten, quartz, etc. It is preferable to use nitrides of chromium or ruthenium. In particular, nitrides of aluminum or titanium are used. For example, aluminum is used as a sputtering target. The nitride alumina was formed by reactive sputtering using a nitrogen-containing gas as the deposition gas. The aluminum film is extremely thin, and can be formed by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the deposition gas. The film has extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen. Therefore, an insulating film containing such a metal nitride is provided in contact with a semiconductor layer. By doing so, not only can the resistance of the semiconductor layer be reduced, but oxygen is also released from the semiconductor layer. In addition, the diffusion of hydrogen into the semiconductor layer can be effectively prevented.

[0107] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the thickness of the layer is 5 nm or more. Even with such a thin film, hydrogen and oxygen This allows the compound to have both high blocking properties against elements and a function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer may be any thickness, but in consideration of productivity, it is preferably 500 nm or less. It is preferable that the thickness is 200 nm or less, and more preferably 50 nm or less.

[0108] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is greater than 0 A membrane is used that satisfies the following: x is a real number less than or equal to 2, preferably, x is a real number greater than 0.5 and less than or equal to 1.5. This makes it possible to obtain a film having excellent insulating properties and excellent thermal conductivity. Therefore, it is possible to improve the dissipation of heat generated when the transistor 100 is driven. Cut.

[0109] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like is used as the insulating layer 116. It is possible.

[0110] By providing such an insulating layer 116 in contact with the region 108N, the insulating layer 116 The oxygen in the region 108N can be absorbed, and oxygen vacancies can be formed in the region 108N. In this case, when a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 and the region 108N Between the insulating layer 116 and the insulating layer 116, a layer containing an oxide of a metal element (for example, aluminum) is provided. It may be formed.

[0111] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, the region 1 In the vicinity of the interface of the insulating layer 116 of the 08N, there is a region where indium in a metallic state is precipitated, and In some cases, a region with a high indium concentration is formed. The presence of such a region is For example, X-ray Photoelectron Spectroscopy (XPS) This may be possible using analytical methods such as autoscopy.

[0112] In this way, the region 108N is a region that contains more oxygen vacancies than the channel formation region. Therefore, the resistance of the region can be lower than that of the channel formation region. Furthermore, by using an insulating film containing a metal oxide as the insulating layer 116, the insulation of the region 108N is improved. A region where highly conductive indium is precipitated is formed near the interface on the layer 116 side, and It can be a resistive area.

[0113] Alternatively, the insulating layer 116 may be a film that functions as a hydrogen source for the region 108N. For example, the insulating layer 116 may be a film that releases hydrogen when heated. It is preferable to provide such an insulating layer 116 in contact with the region 108N. By carrying out a heat treatment later, hydrogen can be supplied to the region 108N to reduce the resistance. do.

[0114] The insulating layer 116 is formed by using a gas containing hydrogen as a deposition gas. This prevents water from entering the region 108N during the formation of the insulating layer 116. The material can be supplied effectively.

[0115] The insulating layer 116 may be made of, for example, silicon nitride, silicon nitride oxide, or silicon oxide nitride. An insulating film such as aluminum nitride or aluminum nitride oxide can be used.

[0116] By the heat treatment during and after the formation of the insulating layer 116, the region 108N Hydrogen is supplied to the region 108N. The supplied hydrogen combines with oxygen vacancies in the region 108N, forming carriers This can create a region with a higher carrier concentration and lower resistance than the channel formation region. Region 108N may be formed.

[0117] The insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 are formed of an oxide. It is preferable to use a film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An oxide film such as a tungsten film can be used. Oxygen released from the insulating layer 103 or the insulating layer 110 during heat treatment in the process is transported to the semiconductor layer 1 The oxygen vacancies in the semiconductor layer 108 can be reduced by supplying the oxygen to the channel formation region of the semiconductor layer 108. .

[0118] As shown in FIG. 1B, the insulating layer 116 is formed on the side surface of the region 103a of the insulating layer 103. It is preferable that the insulating layer 103 is provided so as to cover the insulating layer 103. The element can be supplied to the semiconductor layer 108 from the region 103a of the insulating layer 103. Therefore, in order to prevent oxygen from being desorbed from the side surface of the region 103a due to heating, the side surface is covered with an oxygen mask. The insulating layer 116 is used to cover the semiconductor device. It is more preferable that the layer 116 also covers the upper surface of the region 103b of the insulating layer 103. As a result, oxygen released from the insulating layer 103 can be effectively supplied to the semiconductor layer 108. This reduces the carrier density in the channel formation region of the semiconductor layer 108. This makes it possible to improve the reliability of the transistor 100.

[0119] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon nitride, silicon nitride oxide, silicon oxynitride, and aluminum oxide. Hafnium, Aluminum Oxide Nitride, Aluminum Nitride, Hafnium Oxide, Hafnium Aluminum The insulating layer 118 can be formed of an inorganic insulating material such as polycarbonate. In this case, an organic resin material can be used as the insulating layer 118. .

[0120] In this example, a laminated structure of an insulating layer 116 and an insulating layer 118 is used as the protective layer. However, if the insulating layer 118 is unnecessary, it may not be provided. A laminated structure may also be used.

[0121] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described. I will explain it below.

[0122] The oxygen vacancies formed in the channel formation region of the semiconductor layer 108 affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, the oxygen Hydrogen bonds to the vacancies and can become a carrier source. When this occurs, the electrical characteristics of the transistor 100 change, typically resulting in a shift in the threshold voltage. Therefore, in the channel formation region, the fewer oxygen vacancies the better. .

[0123] Therefore, in one embodiment of the present invention, the insulating film in the vicinity of the channel formation region of the semiconductor layer 108 is Specifically, the insulating layer 110 located above the channel formation region and the insulating layer 111 located below the channel formation region The insulating layer 103 and the insulating film 104 are formed by the heat during the manufacturing process. By transferring oxygen from the insulating layer 110 to the channel formation region, the oxygen in the channel formation region is It is possible to reduce the element deficiency.

[0124] In addition, the semiconductor layer 108 preferably has a region in which the atomic ratio of In is greater than the atomic ratio of M. The higher the atomic ratio of In, the more the field effect mobility of the transistor can be improved. Cut.

[0125] In the case of a metal oxide film containing In, Ga, and Zn, the bonding strength between In and oxygen is Since the bonding strength is weaker than that of oxygen, when the atomic ratio of In is large, oxygen is trapped in the metal oxide film. In addition, even if the metal element shown in M ​​is used instead of Ga, the same problem occurs. When there are many oxygen vacancies in the metal oxide film, the electrical characteristics of the transistor deteriorate. This can result in reduced performance and reduced reliability.

[0126] However, in one embodiment of the present invention, the channel formation region of the semiconductor layer 108 containing a metal oxide Since a large amount of oxygen can be supplied to the region, metal oxide materials with a large In atomic ratio are used. This makes it possible to achieve extremely high field-effect mobility and stable electrical characteristics. Therefore, it is possible to realize a transistor that has high reliability.

[0127] For example, the atomic ratio of In is 1.5 times or more, or 2 times or more, or Preferably, the metal oxide has a concentration of 1000 or more times the surface area of ​​the metal oxide, 3 times or more, 3.5 times or more, or 4 times or more. It is possible.

[0128] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn=4:2. It is preferable that the ratio of the numbers of In, M, and Zn atoms is 3 or about 3. It is preferable that the composition ratio of In:M:Zn is 5:1:6 or in the vicinity thereof. The composition of the alloy may be such that the ratio of the numbers of In, M, and Zn atoms is approximately equal. A material in which the ratio of the numbers of n, M, and Zn atoms is In:M:Zn=1:1:1 or close to that. It may include fees.

[0129] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this in a driver, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-mentioned high field effect mobility transistor is used as a source driver (especially the source It can be used for a demultiplexer connected to the output terminal of a shift register of a driver. As a result, a display device with a small number of connected wires can be provided.

[0130] Even if the semiconductor layer 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M, However, when the crystallinity of the semiconductor layer 108 is high, the field effect mobility may be reduced. The crystallinity of 108 can be measured, for example, by X-ray diffraction (XRD). Analyze using a transmission electron microscope (TEM) or This can be analyzed using a 3D electron microscope.

[0131] Here, the channel formation region of the semiconductor layer 108 has a low impurity concentration and a low defect level density. By reducing the oxygen vacancies, the carrier density in the film can be reduced. A transistor using such a metal oxide film in a channel formation region of a semiconductor layer has a threshold The electrical characteristics where the voltage is negative (also called normally on) are rare. In addition, a transistor using such a metal oxide film has a characteristic of having a significantly small off-state current. It is possible.

[0132] When a metal oxide film with high crystallinity is used for the semiconductor layer 108, the semiconductor layer 108 is easily processed. Damage caused during the formation of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, by using a metal oxide film with a relatively low crystallinity for the semiconductor layer 108, This improves the electrical conductivity and enables the realization of a transistor with high field effect mobility.

[0133] The semiconductor layer 108 is a c-axis aligned cryostat (CAAC) layer. Metal oxide film with stal structure, nc (nano crystal) structure Metal oxide films or metal oxide films with a mixture of CAAC and nc structures can be used. preferable.

[0134] By adopting such a configuration, the transistor 100 has excellent electrical characteristics and high reliability. This can be achieved.

[0135] Hereinafter, a configuration example of a transistor having a partly different configuration from the above configuration example 1 will be described. In the following, explanations of parts that overlap with the above-mentioned configuration example 1 may be omitted. In the drawings shown below, parts having the same functions as the above configuration example are shown with hatched patterns. In some cases, the lines are the same and no code is added.

[0136] [Configuration example 2] FIG. 3A is a top view of a transistor 100A, and FIG. 3B is a top view of a transistor 100B. 3(C) is a cross-sectional view of the channel length direction of transistor 100A, and FIG. 3(D) is a cross-sectional view of the channel width direction of transistor 100A. 4 is a cross-sectional view in the direction.

[0137] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 is a channel forming region of the semiconductor layer 108. , and has a region overlapping with the conductive layer 112.

[0138] In the transistor 100A, the conductive layer 106 is a first gate electrode (bottom gate electrode). The conductive layer 112 functions as a second gate electrode (also called a top gate electrode). A part of the insulating layer 103 functions as a first gate insulating layer. and a portion of the insulating layer 110 functions as a second gate insulating layer.

[0139] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 106 In the following description, for ease of explanation, the semiconductor layer 10 The portion of the conductive layer 112 of the conductive layer 110 of the first embodiment is sometimes called a channel formation region. The portion that does not overlap with the layer 112 but overlaps with the conductive layer 106 (the portion including the region 108N) is also A channel can be formed.

[0140] As shown in FIGS. 3A and 3C, the conductive layer 106 is made of a metal oxide layer 114 and an insulating layer. The conductive layer 112 is electrically connected to the insulating layer 103 through an opening 142 provided in the insulating layer 103 and the conductive layer 112 . In this way, the conductive layer 106 and the conductive layer 112 can be given the same potential. It is possible to do so.

[0141] The conductive layer 106 may be made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. In addition, the conductive layer 106 is preferably made of a high melting point metal such as tungsten or molybdenum. By using a material containing this, processing at a higher temperature can be carried out in a subsequent step.

[0142] As shown in FIGS. 3A and 3C, the conductive layer 112 and It is preferable that the conductive layer 106 protrudes outward beyond the end of the semiconductor layer 108. At this time, as shown in FIG. 3C, the entire semiconductor layer 108 in the channel width direction is covered with the insulating layer 11. 0 and the insulating layer 103, the conductive layer 112 and the conductive layer 106 cover the conductive layer 106.

[0143] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by a pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 are electrically surrounded by the same material. It is preferable to apply a potential to the semiconductor layer 108 in order to induce a channel in the semiconductor layer 108. Since the electric field can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0144] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistor 100A, and a signal for driving the transistor 100A is applied to the other gate electrode. At this time, a potential is applied to one electrode of the transistor 100A. It is also possible to control the threshold voltage when the second electrode is driven by the first electrode.

[0145] This concludes the description of configuration example 2.

[0146] [Configuration example 3] FIG. 4A is a cross-sectional view of a transistor 100B in the channel length direction, and FIG. FIG. 3A is a cross-sectional view of the transistor 100B in the channel width direction. Therefore, it is omitted.

[0147] The transistor 100B has a semiconductor layer 101 formed on the insulating layer 103 side instead of the semiconductor layer 108. The semiconductor layer 8a and the semiconductor layer 108b are stacked in the semiconductor layer 8a. The main difference is with Transistor 100A.

[0148] The semiconductor layers 108a and 108b are formed of, for example, metal oxides having different compositions. For example, when an In-Ga-Zn oxide is used, In, M, and the ratio of the number of Zn atoms is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3: 4. Sputtering target with In:M:Zn=1:3:2 or a similar ratio It is preferable to use a film formed by selecting from the films formed by the steps 1 to 5.

[0149] Metal oxide films with different crystallinity may be laminated. In that case, the same oxide target is used. By using different deposition conditions, the films can be formed continuously without being exposed to the air. is preferred.

[0150] At this time, a metal oxide film having an nc structure is used as the semiconductor layer 108a. The layer structure 108b may be a laminate structure using a metal oxide film having a CAAC structure. Alternatively, both the semiconductor layer 108a and the semiconductor layer 108b may be made of a metal oxide having an nc structure. A film may be used for the semiconductor layer 108a and the semiconductor layer 108b. The functions of metal oxides that can be used and the composition of the materials are described later in the section on CAC (Cloud-Accelerated Coupling). The Aligned Composite can be used.

[0151] For example, the oxygen flow rate during deposition of the first metal oxide film is set to be equal to or lower than the oxygen flow rate during deposition of the second metal oxide film. The oxygen flow rate ratio is set to be smaller than that during deposition of the first metal oxide film. During the film formation, oxygen is not allowed to flow. This prevents oxygen from being introduced during the formation of the second metal oxide film. In addition, the first metal oxide film is more effective in supplying the element than the second metal oxide film. The film has lower crystallinity and higher electrical conductivity than the first film. The second metal oxide film is made to have higher crystallinity than the first metal oxide film, so that the semiconductor layer 1 Damage during processing of 08 and during deposition of the insulating layer 110 can be suppressed.

[0152] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably, it is 0% or more and 20% or less, typically, it is 10%. The oxygen flow rate during the formation of the second metal oxide film is set to 50% or more and 100% or less. Preferably, the ratio is 60% or more and 100% or less, more preferably, 80% or more and 100% or less, and even more preferably, The ratio is preferably 90% or more and 100% or less, and typically 100%. The first and second metal oxide films may be formed under different conditions such as pressure, temperature, and power. By keeping all other conditions the same except for the oxygen flow rate, the time required for the film formation process can be shortened. This is preferable.

[0153] [Configuration example 4] FIG. 5A is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. FIG. 3A is a cross-sectional view of the transistor 100C in the channel width direction. Therefore, it is omitted.

[0154] The transistor 100C is the same as that illustrated in the above-described Configuration Example 3, except that the shape of the semiconductor layer 108b is different. The main difference between the transistor 100 and the transistor 100B is as follows.

[0155] The semiconductor layer 108b is in contact with the conductive layer 112, the metal oxide layer 114, and the insulating layer 110. For example, the semiconductor layer 108b is formed by etching the conductive layer 112 and the like. The insulating film can be formed by processing the insulating film using a resist mask for this purpose.

[0156] The semiconductor layer 108b is formed on the upper and side surfaces of the semiconductor layer 108a and the region 103a of the insulating layer 103. The insulating layer 104 is provided so as to cover the side surfaces of the region 103a and a part of the upper surface of the region 103b.

[0157] When a film having a higher crystallinity than the semiconductor layer 108a is used as the semiconductor layer 108b, the thickness In particular, the metal oxide having the CAAC structure can reduce the oxygen diffusion in the direction. The metal oxide film has low oxygen diffusivity in the c-axis direction of the crystal part contained in the metal oxide film. Furthermore, the metal oxide film having the CAAC structure has the following characteristics: The film is formed so that the c-axis of the crystal part contained therein is oriented in a direction approximately perpendicular to the surface on which the film is formed. This becomes possible.

[0158] FIG. 5(C) shows an enlarged view of the area Q surrounded by the dashed line in FIG. 5(B). As shown in FIG. 1, the crystalline semiconductor layer 108b is formed on the upper and side surfaces of the semiconductor layer 108a, It is provided so as to cover the side surface of region 103a of insulating layer 103 and the upper surface of region 103b.

[0159] In FIG. 5C, the semiconductor layer 108b includes the The orientation of the c-axis of the crystal and the layer 108L constituting the layered crystal portion shown by the dashed line are shown in schematic form. As shown in FIG. 1, the crystalline portion of the semiconductor layer 108b is aligned along the c-axis (i.e., The direction perpendicular to the layer of the layered crystal part is oriented approximately perpendicular to the surface on which the layer is formed. do.

[0160] In this manner, as shown in FIG. 5C, the semiconductor layer 108b is formed in the region 103 of the insulating layer 103. b and the side surface of the semiconductor layer 108a are covered, In addition, the diffusion of oxygen from the region 103b can be suppressed. This can prevent oxygen from diffusing to the outside from the side surface of the layer 108a. The oxygen vacancies in the semiconductor layer 108a can be effectively reduced, and a highly reliable transistor can be realized. .

[0161] The above is a description of the configuration example.

[0162] [Example of manufacturing method] A manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100A illustrated in the above configuration example will be taken as an example for explanation.

[0163] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device are formed by sputtering. Chemical Vapor Deposition (CVD) method , vacuum deposition, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be a plasma-enhanced chemical vapor deposition (PEC) method. There are methods such as the VD (Plasma Enhanced CVD) method and the thermal CVD method. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). c CVD) method.

[0164] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife, slit coat, roll coat, curtain coat, knife coat It can be formed by the above method.

[0165] In addition, when processing the thin films that constitute the semiconductor device, photolithography and other methods are used. In addition, nanoimprinting, sandblasting, lift-off, The thin film may be processed by a method such as a masking method using a metal mask. The island-shaped thin film may be directly formed by the film method.

[0166] There are two typical photolithography methods. A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the mask after forming a photosensitive thin film. Then, development is performed to process the thin film into a desired shape.

[0167] In the photolithography method, the light used for exposure is, for example, i-line (wavelength 365 nm), Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may be performed by immersion lithography. Using extreme ultraviolet (EUV) and X-rays, Also, instead of light for exposure, an electron beam can be used. The use of light, X-rays or electron beams is preferable because it allows extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is not necessary.

[0168] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as the above can be used.

[0169] 6A to 10B show steps in the manufacturing process of the transistor 100A. The cross sections in the channel length direction and the channel width direction are shown side by side.

[0170] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a first gate electrode. A conductive layer 106 is formed to function as a conductive layer.

[0171] [Formation of insulating layer 103] Next, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 6(A)). The insulating layer 103 may be formed by using a PECVD method, an ALD method, a sputtering method, or the like. can be done.

[0172] The insulating layer 103 can be formed to a thickness corresponding to the region 103a to be formed later. The thickness of 03 can be set to a thickness that will not disappear in the subsequent thinning process.

[0173] After the insulating layer 103 is formed, a process of supplying oxygen to the insulating layer 103 may be performed. For example, a plasma treatment or a heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen may be introduced into the insulating layer 103 by plasma ion doping or ion implantation. may be supplied.

[0174] [Formation of Semiconductor Layer 108] Next, a metal oxide film 108f, which will later become the semiconductor layer 108, is formed on the insulating layer 103. (Figure 6(B)).

[0175] The metal oxide film is formed by a sputtering method using a metal oxide target. is preferred.

[0176] In addition, when forming a metal oxide film, in addition to oxygen gas, an inert gas (e.g., helium Gas such as argon gas, xenon gas, etc. may be mixed. The higher the ratio of oxygen gas in the total deposition gas (hereinafter referred to as the oxygen flow ratio), the better the deposition efficiency. This can improve the crystallinity of the metal oxide film, resulting in highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. The transistor may be a transistor having a gate insulating film.

[0177] When the semiconductor layer 108 has a laminated structure, the same sputtering target is used to produce the same composition. By continuously forming the films in the film chamber, it is possible to obtain a good interface, which is preferable. The deposition conditions for each metal oxide film were varied under different pressures, temperatures, power, etc. However, by keeping the conditions other than the oxygen flow rate the same, the time required for the film formation process can be shortened. In addition, when metal oxide films having different compositions are laminated, the air is preferably It is preferable to form the films successively without exposing them to heat.

[0178] The metal oxide film is classified into two types: a metal oxide film having a CAAC structure and a metal oxide film having an nc structure. The deposition conditions are set so that the metal oxide film has a mixture of CAAC structure and nc structure. It is preferable to set the film forming conditions so that the metal oxide film to be formed has the CAAC structure. The deposition conditions for the nc structure depend on the composition of the sputtering target used. Since the composition of the material varies, the substrate temperature, oxygen flow rate, pressure, power, etc. are adjusted appropriately according to the composition. Just set it.

[0179] The deposition conditions for the metal oxide film are as follows: the substrate temperature is from room temperature to 450° C. The substrate temperature is preferably from room temperature to 300° C., more preferably from room temperature to 200° C., and even more preferably For example, the substrate 102 may be a large glass substrate or a resin substrate. When using a grease substrate, productivity is increased by setting the film formation temperature to room temperature or higher and lower than 140°C. In addition, the substrate temperature is set to room temperature or is not intentionally heated. By forming a film, the crystallinity can be reduced.

[0180] In addition, before the metal oxide film is formed, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a process for removing components or a process for supplying oxygen into the insulating layer 103. For example, the heat treatment is performed at a temperature of 70° C. or more and 200° C. or less in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. By performing plasma treatment containing nitrogen oxide gas, organic substances on the surface of the insulating layer 103 can be suitably removed. After such a treatment, the surface of the insulating layer 103 can be heated without being exposed to the air. It is preferable to deposit the metal oxide films successively.

[0181] Then, a resist mask 115 is formed on the metal oxide film 108f. The part of the metal oxide film 108f that is not covered by the mask 115 is etched. Then, a semiconductor layer 108 is formed (FIG. 7(A)).

[0182] Metal oxide films are processed using either wet etching or dry etching. Either or both may be used.

[0183] [Thinning of insulating layer 103] Next, the part of the insulating layer 103 that is not covered by the resist mask 115 is thinned by etching. The region 103a is formed into a film and has a portion overlapping the semiconductor layer 108, and the region 103b is formed into a film and has a portion overlapping the semiconductor layer 108. A region 103b is formed that is not folded and has a thickness smaller than that of the region 103a.

[0184] The insulating layer 103 is preferably etched by a dry etching method. For example, An anisotropic dry etching method can be used. At this time, the part that will become the region 103b The etching conditions and etching time are set so that the etching is not lost. The side surface of the region 103a of the insulating layer 103 has a curved shape with a continuously changing gradient. It is preferable to optimize the etching conditions so that the etching temperature is reduced.

[0185] Here, the insulating layer 103 has a laminated structure of two insulating films with different etching rates. By applying a film with a high etching rate to the upper insulating film, only the upper insulating film is etched. The region 103b may be formed by etching. The insulating films may contain different elements. Alternatively, a film containing SiO 2 may be used, with a denser film being applied to the insulating film located underneath.

[0186] In this example, the metal oxide film 108f is etched and the insulating layer 103 is thinned. Although the method of performing etching and etch separately has been described, it is possible to perform these processes in a single etching process. Alternatively, the same etching may be performed on both the metal oxide film 108f and the insulating layer 103. The etching method (preferably dry etching method) is used, and the etching is performed in the same etching apparatus without exposing it to the atmosphere. Alternatively, the processes may be performed successively using different etchants.

[0187] After the insulating layer 103 has been thinned, the resist mask 115 is removed.

[0188] Here, after the metal oxide film is formed and processed into the semiconductor layer 108, or after the insulating layer 103 is To remove hydrogen or water in the metal oxide film or semiconductor layer 108 after the thinning process. The temperature of the heat treatment is typically 150° C. or higher than the distortion point of the substrate. or between 250°C and 450°C, or between 300°C and 450°C. can.

[0189] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in air, the substrate may be heated in an atmosphere containing oxygen. It is preferable that the mixture does not contain hydrogen, water, etc. The heat treatment is carried out using an electric furnace, an RTA device, etc. By using an RTA device, the heat treatment time can be shortened.

[0190] [Formation of insulating film 110f and metal oxide film 114f] Next, the insulating film 110f and the metal oxide film 110f are formed on the insulating layer 103 and the semiconductor layer 108. Form 14f.

[0191] The insulating film 110f is a film that will later become the insulating layer 110. For example, the insulating film 110f may be For example, an oxide film such as a silicon oxide film or a silicon oxynitride film is deposited by a plasma enhanced chemical vapor deposition apparatus. It is preferable to form the layer by using a plasma enhanced CVD (PECVD) apparatus or simply a plasma enhanced CVD (plasma enhanced chemical vapor deposition) apparatus. It is also preferable to form the insulating film by using a PECVD method using microwaves.

[0192] The metal oxide film 114f is a film that will later become the metal oxide layer 114. It is preferable that 4f is formed by, for example, a sputtering method in an atmosphere containing oxygen. This makes it possible to supply oxygen to the insulating film 110f when the metal oxide film 114f is formed. Cut.

[0193] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. When forming the film by a sputtering method using a target, the above method can be used. Cut.

[0194] The metal oxide film 114f is formed by reactive spat deposition using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, An aluminum oxide film can be formed.

[0195] When the metal oxide film 114f is formed, the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating layer 1 The oxygen supplied during the experiment can be increased by, for example, 5 0% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 10% or less, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure to 0% and to make the oxygen partial pressure as close to 100% as possible.

[0196] In this manner, the metal oxide film 114f is formed by the sputtering method in an atmosphere containing oxygen. By forming the metal oxide film 114f, oxygen is supplied to the insulating film 110f during the formation of the metal oxide film 114f. At the same time, oxygen can be prevented from being released from the insulating film 110f. It is possible to trap a large amount of oxygen in the film 110f. As a result, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, and the Oxygen vacancies can be reduced, and highly reliable transistors can be realized.

[0197] In addition, by performing a heat treatment after the formation of the metal oxide film 114f, the insulating film 110f is Oxygen may be supplied to the semiconductor layer 108. The heat treatment may be performed using one or more of nitrogen, oxygen, and a rare gas. The reaction can be carried out at a temperature of 200° C. or higher and 400° C. or lower in an atmosphere containing

[0198] Next, the metal oxide film 114f, the insulating film 110f, and a part of the insulating layer 103 are etched. By this, an opening reaching the conductive layer 106 is formed. 112 and the conductive layer 106 can be electrically connected through the opening.

[0199] [Formation of Conductive Film 112f] Next, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f ( FIG. 8(A). The conductive film 112f is formed by sputtering a metal or alloy target. It is preferable to form the film by a sputtering method.

[0200] [Formation of insulating layer 110, metal oxide layer 114, and conductive layer 112] Then, a resist mask is formed over the conductive film 112f. In the unetched area, the conductive film 112f, the metal oxide film 112c, and the like are removed by anisotropic etching. The film 114f and the insulating film 110f are etched, and the resist mask is removed (FIG. 8(B) )).

[0201] The conductive film 112f, the metal oxide film 114f, and the insulating film 110f are etched by the same etching. The etching conditions may be different, or the etching conditions or techniques may be different. For example, the conductive film 112f and the metal The oxide film 114f is etched first, and then the insulating film 110f is etched under different etching conditions. By etching, damage to the semiconductor layer 108 due to etching can be reduced. do.

[0202] [Formation of insulating layer 116 and region 108N] Next, an insulating layer 116 is formed in contact with the exposed region of the semiconductor layer 108 (FIG. 9(A) )).

[0203] The insulating layer 116 may be made of aluminum, titanium, tantalum, tungsten, chromium, or A film containing at least one metal element such as ruthenium is formed. It is preferable that the material contains at least one of tungsten, tantalum, and tungsten. Nitrides containing at least one of these metal elements, or compounds containing at least one of these metal elements As an insulating film, an oxide such as aluminum titanium nitride can be preferably used. Nitride films such as titanium nitride film, aluminum nitride film, titanium aluminum oxide film, etc. An oxide film of the above can be suitably used.

[0204] Here, the insulating layer 116 is formed by sputtering using nitrogen gas or oxygen gas as a deposition gas. It is preferable to form the film by the method described above. By controlling the flow rate of the film forming gas, The film quality can be easily controlled.

[0205] Next, a heat treatment is performed. By the heat treatment, the area of ​​the semiconductor layer 108 in contact with the insulating layer 116 is The resistance of the region is reduced, and a low-resistance region 108N is formed in the semiconductor layer 108 (FIG. 9B). .

[0206] The heat treatment is preferably carried out in an inert gas atmosphere such as nitrogen or a rare gas. The higher the processing temperature, the more preferable. However, the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, etc. For example, the temperature can be set to 120° C. or higher and 500° C. or lower, preferably 15 0°C or higher and 450°C or lower, more preferably 200°C or higher and 400°C or lower, and even more preferably 2 The temperature can be 50°C or higher and 400°C or lower. For example, the heat treatment temperature can be about 350°C. By achieving this, it is possible to produce semiconductor devices with a high yield rate using production equipment that uses large glass substrates. It is possible.

[0207] In this case, the insulating layer 116 is not removed, so the heat treatment can be performed after the insulating layer 116 is formed. It may be performed at any stage, such as at the time of the heating process or at the time of the heat treatment.

[0208] By the heat treatment, oxygen in the semiconductor layer 108 is extracted into the insulating layer 116. The oxygen vacancies are generated. The oxygen vacancies are bonded to hydrogen in the semiconductor layer 108, The carrier concentration increases, and the resistance of the region 108N in contact with the insulating layer 116 decreases.

[0209] Alternatively, the metal elements contained in the insulating layer 116 may be diffused into the semiconductor layer 108 by the heat treatment. By doing so, a part of the semiconductor layer 108 may be alloyed, resulting in a lower resistance.

[0210] Alternatively, nitrogen or hydrogen contained in the insulating layer 116, or nitrogen contained in the atmosphere of the heat treatment, When elements such as silicon are diffused into the semiconductor layer 108 by heat treatment, the resistance of these elements decreases. There are also cases where this is the case.

[0211] The region 108N of the semiconductor layer 108, which has a low resistance due to such a complex action, is extremely The region 108N thus formed is a stable low-resistance region. Even if a process in which oxygen is supplied is performed, it is difficult for the resistance to increase again. .

[0212] In this embodiment, the insulating layer 11 having insulating properties is used as the layer for forming the region 108N. 6 is used in the example described above, but a conductive film is provided in contact with the region that will become the region 108N. In this case, after the formation of the region 108N, The conductive film can be oxidized or nitrided to be insulated, to form the insulating layer 116. Alternatively, the film may be removed after the region 108N is formed, and the insulating layer 116 may not be provided. It may also be composed of.

[0213] Alternatively, a process of supplying hydrogen to the exposed region of the semiconductor layer 108 may be performed, In the following, a region 108N may be formed in contact with the exposed region of the semiconductor layer 108. Hydrogen is supplied by forming the insulating layer 116 containing hydrogen.

[0214] The insulating layer 116 may be formed by a plasma CVD method using a deposition gas containing hydrogen. For example, silicon nitride is formed by using a deposition gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen is contained in the film. Also, during the deposition process, the exposed portion of the semiconductor layer 108 may contain It becomes possible to supply hydrogen.

[0215] After the insulating layer 116 is formed, a heat treatment is performed to release hydrogen from the insulating layer 116. It is preferable that a part of the nitrogen, oxygen, In an atmosphere containing one or more of the rare gases, the temperature is 150° C. or higher and 450° C. or lower, preferably 200° C. It is preferable to carry out the treatment at a temperature of 0.degree. C. or higher and 400.degree. C. or lower.

[0216] By supplying hydrogen in this manner, a region 108N having extremely low resistance is formed in the semiconductor layer 108. The region 108N has a higher carrier concentration than the channel formation region. These are also called regions with high oxygen vacancies, regions with high hydrogen concentrations, or regions with high impurity concentrations. It is possible to do so.

[0217] In addition, the channel of the semiconductor layer 108 is formed from the insulating layer 110 and the insulating layer 103 by the heat treatment. Oxygen can be supplied to the formation region.

[0218] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed on the insulating layer 116 (FIG. 10(A)).

[0219] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, the region 1 Depending on the impurity contained in O8N, the impurity may form a channel formation region of the semiconductor layer 108. As a result, the resistance of the channel formation region may decrease, There is a risk that the electrical resistance of the region 108N may increase. The film formation temperature of 118 is, for example, 150° C. or higher and 400° C. or lower, preferably 180° C. or higher. The temperature is preferably 360° C. or lower, and more preferably 200° C. or higher and 250° C. or lower. By forming the 118 film at low temperature, good performance was achieved even for transistors with short channel lengths. Electrical properties can be imparted.

[0220] After the insulating layer 118 is formed, heat treatment may be performed.

[0221] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118 and a part of the insulating layer 116 are etched to form an opening 114 reaching the region 108N. 41a and an opening 141b are formed.

[0222] [Formation of Conductive Layer 120a and Conductive Layer 120b] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 10(B)).

[0223] Through the above steps, the transistor 100A can be manufactured.

[0224] The above is a description of the modified example of the manufacturing method.

[0225] [Components of Semiconductor Devices] Next, components included in the semiconductor device of this embodiment will be described in detail.

[0226] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates A plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. are used as the substrate 102. In addition, the substrate 102 may be a substrate on which a semiconductor element is provided. It may be used.

[0227] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100, etc. The release layer may be removed from the substrate 10 after a part or all of a semiconductor device is completed thereon. 2 and can be transferred to another substrate. 00 etc. can be transferred to substrates with poor heat resistance or flexible substrates.

[0228] [Insulating layer 103] The insulating layer 103 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating layer 103 can be formed by appropriately using a photo-induced laser deposition (PLD) method or the like. The insulating film can be formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the semiconductor layer 108, at least a semiconductor A region in contact with the insulating layer 108 is preferably formed using an oxide insulating film. It is preferable to use a film that releases oxygen when heated.

[0229] The insulating layer 103 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The above may be used, and the layer may be formed as a single layer or a multilayer.

[0230] In addition, the insulating layer 103 may have a film other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When the above-mentioned film is used, a pretreatment such as an oxygen plasma treatment is performed on the surface in contact with the semiconductor layer 108. and oxidizing the surface or the vicinity of the surface.

[0231] [Conductive Film] The conductive layer 112 and the conductive layer 106 function as a gate electrode, and a source electrode or drain electrode. A conductive layer 120a functions as one of the drain electrodes, and a conductive layer 120b functions as the other drain electrode. b: chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium tungsten, manganese, nickel, iron, cobalt, or any of the above. The alloys are made of the above metal elements or alloys combining the above metal elements. Each of them can be formed.

[0232] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. Alternatively, an oxide conductor or a metal oxide film may be used.

[0233] Here, an oxide conductor (OC) will be described. For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. When the metal oxide is heated, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. The metal oxide that has been made conductive can be called an oxide conductor.

[0234] In addition, the conductive layer 112 and the like may be a conductive film containing the oxide conductor (metal oxide) or a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating film that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0235] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is preferable to use one or more of the above. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and is resistant to copper, oxygen, and hydrogen. Since the barrier layer 104 has a high barrier property and releases little hydrogen from itself, it is preferable that the barrier layer 104 is in contact with the semiconductor layer 108. It can be suitably used as a conductive film or a conductive film in the vicinity of the semiconductor layer 108 .

[0236] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for the transistor 100, etc., is formed by PECVD. The insulating layer 110 can be formed by a sputtering method or the like. Silicon oxide film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film tungsten oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, Magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film, or more The insulating layer 110 may have a laminated structure of two layers or three or more layers. The above laminated structure may also be used.

[0237] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film. It is more preferable to have a region containing oxygen in excess of the stoichiometric composition. The insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed by the above-mentioned method, and the insulating layer 110 after the film formation is subjected to a heat treatment in an oxygen atmosphere. Alternatively, an oxide film is formed on the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by, for example, forming a film therein.

[0238] In addition, the insulating layer 110 is made of a material having a higher dielectric constant than silicon oxide or silicon oxynitride. Materials such as hafnium oxide can also be used. This allows the thickness of the insulating layer 110 to be increased. It is possible to suppress leakage current caused by tunnel current. In particular, hafnium oxide, which has crystallinity, is It is preferable because it has a higher relative dielectric constant than crystalline hafnium oxide.

[0239] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The sputtering target used in the present invention must have an atomic ratio of In equal to or greater than that of M. The atomic ratio of the metal elements in such a sputtering target is preferably In:M :Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2: 4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn= 5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. .

[0240] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 having crystallinity can be easily formed. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. For example, the sputtering used for the semiconductor layer 108 may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], the film is formed. The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. There may be cases where this occurs.

[0241] In addition, when the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, When the atomic ratio of Ga is 4, the atomic ratio of Ga is 1 to 3, and the atomic ratio of Zn is 2. The atomic ratio of In:Ga:Zn is 5:1:6 or less. When describing it as being in the vicinity of , when the atomic ratio of In is 5, the atomic ratio of Ga is 0. The atomic ratio of Zn is greater than 1 and less than 2, and includes the case where the atomic ratio of Zn is greater than 5 and less than 7. When describing that the atomic ratio of In:Ga:Zn is 1:1:1 or close to that, When the atomic ratio of Ga is 1, the atomic ratio of Zn is 0.1 or more and 2 or less. This includes cases where the numerical ratio is greater than 0.1 and less than 2.

[0242] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0243] In addition, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure is, for example, This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure described below. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0244] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0245] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystal structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which the film is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0246] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. The crystallinity may be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). The physical properties of an oxide semiconductor having an OS are stable. The oxide semiconductor used is heat resistant and highly reliable.

[0247] In crystallography, the three axes that make up a unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the lattice. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis that intersects the layers is the Generally, the c-axis is taken as the c-axis. A typical example of a crystal with such a layered structure is Graphite is classified as a hexagonal crystal, and the a- and b-axes of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The InGaZnO4 crystal can be classified as a hexagonal system, and the a-axis and The a- and b-axes are parallel to the plane of the layer, and the c-axis is perpendicular to the layers (i.e., the a- and b-axes).

[0248] An oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film) is shown in the TEM image. In some cases, it may not be possible to clearly identify the crystal parts in the microcrystalline oxide semiconductor film. The crystal part has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, microcrystals with sizes of 1 nm to 10 nm or 1 nm to 3 nm are often An oxide semiconductor film having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) film In addition, the grain boundaries of the nc-OS film can be clearly seen in the TEM images. There may be cases where this is not possible.

[0249] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that in the crystalline region. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam of 50 nm or more (for example) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron beam diffraction) is performed using the electron beam shown below, a circle is drawn. A bright area (ring-shaped) was observed, and multiple spots were detected within the ring-shaped area. In some cases, spurts of light may be observed.

[0250] The nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the S-film, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has The defect density of the nc-OS film is higher than that of the CAAC-OS film. Compared to OS films, the carrier density and electron mobility may be higher. A transistor including an -OS film can exhibit high field-effect mobility.

[0251] The nc-OS film is formed with a smaller oxygen flow rate than the CAAC-OS film. In addition, the nc-OS film can be formed at a low temperature compared to the CAAC-OS film. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is relatively low (for example, below 130°C) or the board is not heated. Since it can form films even in small spaces, it is suitable for large glass substrates and resin substrates, and is easy to produce. It can improve sexuality.

[0252] An example of the crystal structure of a metal oxide will be described. In the following, In-Ga-Zn oxide Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). A metal oxide film formed by the ring method will be described as an example. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is either the nc (nano crystal) structure or the CAAC structure. On the other hand, the substrate temperature is set to room temperature (RT). Metal oxides formed by sputtering tend to have an nc crystal structure. Room temperature (RT) as used herein includes the temperature at which the substrate is not intentionally heated.

[0253] [Metal oxide composition] The following describes a CAC (C This paper explains the configuration of the Multicloud Aligned Composite Operating System (MSO).

[0254] In this specification, CAAC (c-axis aligned crystal l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Shows an example.

[0255] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has a function of insulating in part and a function of semiconductor in the whole material. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a layer, the conductive function is to allow the flow of electrons (or holes) that serve as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the function of the material and the function of the material complement each other, the material can be switched (On / Off). The function of ff can be given to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the functions are separated. By combining them, the functions of both can be maximized.

[0256] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0257] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than one millimeter.

[0258] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide gap component due to the insulating region and a conductive region. In this configuration, when the carrier flows, In addition, carriers mainly flow in the narrow gap component. The component with a gap acts complementary to the component with a wide gap to produce a narrow gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field effect mobility can be obtained.

[0259] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a composite matrix.

[0260] The above is a description of the components.

[0261] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0262] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain about this.

[0263] [Configuration example] FIG. 11A shows a top view of a display device 700. The display device 700 includes a sealant 712. The first substrate 701 and the second substrate 705 are bonded together by a bonding agent. 1, the second substrate 705, and the area sealed by the sealant 712. 1, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided. The pixel portion 702 is provided with a plurality of display elements.

[0264] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. Through the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 Various signals are supplied to each of these.

[0265] A plurality of gate driver circuit sections 706 may be provided. The path portion 706 and the source driver circuit portion 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip may be mounted on the first substrate 70. 1, or can be mounted on FPC716.

[0266] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0267] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light emitting element. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, etc. are used. The light emitting element can be LED (Light Emitting Diode). Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs and semiconductor lasers. MEMS (Micro Electro Mechanical Systems) using the optical interferometry or optical interference method l Systems) elements, microcapsule type, electrophoretic type, electrowet type Display elements using the electronic powder method or the like can be used. It is also possible.

[0268] The display device 700A shown in FIG. 11B has a flexible substrate instead of the first substrate 701. A display device to which a resin layer 743 is applied and which can be used as a flexible display This is an example.

[0269] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in the region P1 in FIG. 11B, the pixel section 702 and the resin layer 743 The pair of gate driver circuit sections 706 are connected to the pixel section 7 The gate driver circuit section 706 is provided on both sides of the pixel section 702. The recess is provided along a circular arc-shaped contour at the recess.

[0270] The resin layer 743 has a protruding shape at the portion where the FPC terminal portion 708 is provided. In addition, a part of the resin layer 743 including the FPC terminal portion 708 is disposed on the back side in the region P2 in FIG. By folding back a part of the resin layer 743, the FPC 716 can be attached to the pixel area. With the display device 700A placed behind the display device 702, the display device 700A can be mounted on the electronic device. This allows for space saving for electronic devices.

[0271] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. The source driver circuit section 704 in 00A includes a protection circuit, a buffer circuit, a demultiplexer, The configuration may include at least one of a crosstalk circuit, etc.

[0272] The display device 700B shown in FIG. 11C is suitable for use in electronic devices having a large screen. For example, television sets, monitors, personal computers, etc. Computers (including notebooks and desktops), tablets, digital signage It can be suitably used in the following cases:

[0273] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuits. The sensor 722 has a first section 722.

[0274] The source driver ICs 721 are each attached to an FPC 723. In addition, the FPCs 723 are each connected to the substrate 701 at one terminal and to the printed circuit board 72 at the other terminal. 4. By bending the FPC 723, the printed circuit board 724 is It can be mounted on the back side of the pixel section 702 in the electronic device, thereby saving space in the electronic device. It is possible to achieve this.

[0275] On the other hand, the gate driver circuit section 722 is formed on the substrate 701. It is possible to realize electronic devices with narrow bezels.

[0276] With this configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can also be applied to the above display devices. In addition, the resolution is 4K2K, 8K4K, etc. It is possible to realize a display device with extremely high resolution.

[0277] [Cross-section example] The following describes a configuration in which a liquid crystal element is used as a display element, and a configuration in which an EL element is used. 12 to 15. Note that FIGS. 12 to 14 are the same as FIG. 11(A 11(B) is a cross-sectional view taken along the dashed line QR shown in FIG. 12 and 13 are cross-sectional views of the display device 700A taken along dashed line ST. 14 and 15 show a configuration using an EL element. do.

[0278] [Description of common parts of the display device] The display device shown in FIG. 12 to FIG. 15 includes a wiring portion 711, a pixel portion 702, and a The wiring section 711 includes a driver circuit section 704 and an FPC terminal section 708. 7 and a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. The absence of element 790 is shown.

[0279] The transistor 750 and the transistor 752 are the transistors exemplified in the first embodiment. can be applied.

[0280] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The retention time of the image signal can be extended, and the interval between writing the image signal can be set to be longer. Since the frequency of refresh operations can be reduced, this has the effect of reducing power consumption.

[0281] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a display device. By using this in a device, the switching transistor in the pixel section and the driver circuit section In other words, the transistors can be formed on the same substrate, such as a silicon wafer. It is also possible to adopt a configuration that does not use a driving circuit formed by the above-mentioned method, and the number of parts of the display device can be reduced. In addition, by using a transistor capable of high speed operation in the pixel portion, It is possible to provide high quality images.

[0282] The capacitor 790 shown in FIG. 12, FIG. 14, and FIG. 15 is a third capacitor included in the transistor 750. The lower electrode is formed by processing the same film as the gate electrode in 1, and the same metal oxide as the semiconductor layer is and an upper electrode formed by processing a material. The upper electrode is a source electrode of the transistor 750. The resistance of the gate electrode is reduced in the same manner as the source and drain regions. A part of an insulating film that functions as a first gate insulating layer of the transistor 750 is provided on the That is, the capacitor 790 has an insulating film that functions as a dielectric film sandwiched between a pair of electrodes. The upper electrode is a layered structure in which the source electrode and drain electrode of the transistor are formed. The electrodes are connected to wiring obtained by processing the same film as the electrodes.

[0283] In addition, a planarization insulating layer is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0284] A transistor 750 included in the pixel portion 702 and a transistor 751 included in the source driver circuit portion 704 A transistor having a different structure from the transistor 752 may be used. For example, A top-gate transistor is applied to one side and a bottom-gate transistor is applied to the other side. The gate driver circuit section 706 may also be configured using a source driver. This is similar to the driver circuit section 704.

[0285] The signal line 710 is the same as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by line resistance and enables display on a large screen.

[0286] The FPC terminal portion 708 includes wiring 760, a part of which functions as a connection electrode, and an anisotropic conductive film 78. The wiring 760 is connected to the FPC 710 via an anisotropic conductive film 780. In this example, the wiring 760 is electrically connected to a terminal of the transistor 750, The source electrode and drain electrode 752 are formed from the same conductive film.

[0287] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used as the first substrate 701. When using a substrate that can be used for the first substrate 701, water or water may be provided between the first substrate 701 and the transistor 750, etc. It is preferable to provide an insulating layer having a barrier property against elements.

[0288] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and insulating films in contact with these are provided. A border membrane 734 is provided.

[0289] [Example of the configuration of a display device using a liquid crystal element] The display device 700 shown in FIG. 12 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 772 is provided on the substrate 705 side and functions as a common electrode. The conductive layer is electrically connected to a source electrode or a drain electrode of the transistor 750. A pixel electrode 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0290] The conductive layer 772 is formed using a material that transmits visible light (hereinafter also referred to as a light-transmitting material). ), or a material having reflectivity (hereinafter also referred to as a reflective material) can be used. As the light-transmitting material, for example, an oxide material containing indium, zinc, tin, etc. may be used. As the reflective material, for example, a material containing aluminum, silver, or the like may be used.

[0291] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive type. In the case of a liquid crystal display device of the transmission type, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0292] The display device 700 shown in FIG. 13 includes a liquid crystal element 77 of a horizontal electric field type (for example, an FFS mode). 5 is formed on a conductive layer 772 with an insulating layer 773 interposed therebetween, the insulating layer 773 serving as a common electrode. A conductive layer 774 is provided. An electric field is generated between the conductive layer 772 and the conductive layer 774, The alignment state of the liquid crystal layer 776 can be controlled.

[0293] In FIG. 13, a holding container is formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0294] Although not shown in FIGS. 12 and 13, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members may be used. , and light sources such as a backlight and a sidelight can be provided as appropriate.

[0295] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, etc. Crystal (PDLC: Polymer Dispersed Liquid Crystal) , Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When the lateral electric field mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0296] The liquid crystal element modes are Twisted Nematic (TN) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optical Compensated Birefri) ngence) mode, ECB (Electrically Controlled B irefringence mode, guest-host mode, etc. can be used.

[0297] In addition, the liquid crystal layer 776 is made of a polymer dispersed liquid crystal or a polymer network liquid crystal. A scattering type liquid crystal can also be used. In this case, a black and white display is performed without providing the color film 736. Alternatively, a colored film 736 may be used to perform color display.

[0298] In addition, as a driving method for liquid crystal elements, a time-series additive color mixing method is used to display colors. A split display method (also called a field sequential driving method) may be applied. In this case, the color film 736 may not be provided. For example, it is necessary to provide sub-pixels that exhibit the respective colors R (red), G (green), and B (blue). This has the advantage of improving the aperture ratio of pixels and increasing the definition.

[0299] [Display device using light-emitting element] The display device 700 shown in FIG. 14 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound, has inorganic compounds such as quantum dots.

[0300] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, etc.

[0301] In the display device 700 shown in FIG. 14, a conductive layer 772 is provided on a planarization insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. Note that the light-emitting element 782 emits light toward the conductive layer 772. A bottom emission structure in which light is emitted from the bottom of the conductive layer 772 and the conductive film 788 can be used. It may also be a dual emission structure.

[0302] The colored film 736 is provided at a position overlapping the light emitting element 782, and the light shielding film 738 is an insulating film. 730, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by painting. In some cases, the colored film 736 may not be provided.

[0303] FIG. 15 shows a configuration of a display device that can be suitably applied to a flexible display. FIG. 15 is a cross-sectional view taken along dashed line ST in the display device 700A shown in FIG. 11(B). FIG.

[0304] A display device 700A shown in FIG. 15 includes a support substrate 74 instead of the substrate 701 shown in FIG. 5, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated. The resistor 750, the capacitor element 790, and the like are provided on an insulating layer 744 provided on a resin layer 743. It is being done.

[0305] The support substrate 745 is a substrate that contains organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The resin layer 74 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. 3 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferably thinner than the supporting substrate 745 .

[0306] 15 includes a protective layer 702 instead of the substrate 705 shown in FIG. 40. The protective layer 740 is attached to the sealing film 732. A glass substrate or a resin film can be used as the protective layer 740. , polarizing plates, scattering plates, and other optical components, input devices such as touch sensor panels, and the like. A configuration in which two or more of these are stacked may be applied.

[0307] In addition, the EL layer 786 of the light-emitting element 782 is an island on the insulating film 730 and the conductive layer 772. The EL layer 786 is formed so that each subpixel emits a different light. In this way, color display can be achieved without using the color film 736. A protective layer 741 is provided to cover the light emitting element 782. The protective layer 741 protects the light emitting element 782 from inclusions such as water. The protective layer 741 has a function of preventing diffusion of impurities. It is also preferable to use a laminated structure including at least one inorganic insulating film and at least one organic insulating film. preferable.

[0308] 15 shows a bendable region P2. In the region P2, the support substrate 7 45, in addition to the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. The bendable region P2 is provided with as little inorganic insulating film as possible, and is provided with a conductive material containing a metal or an alloy. By laminating only layers containing organic materials, cracks do not occur when the material is bent. In addition, by not providing the support substrate 745 in the region P2, A portion of the display device 700A can be bent with a small radius of curvature.

[0309] [Example of configuration in which an input device is provided on a display device] In addition, an input device is provided to the display device 700 or the display device 700A shown in FIG. 12 to FIG. An example of the input device is a touch sensor.

[0310] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, infrared type, etc. Various methods can be used, such as a pressure-sensitive, optical, or pressure-sensitive method. Or, two or more of these can be used. may be used in combination.

[0311] The touch panel is configured as a so-called in-cell type, in which the input device is formed inside a pair of substrates. A touch panel of the type, an input device is formed on the display device 700, so-called an on-cell type touch panel. or a so-called out-cell type touch panel that is attached to the display device 700. There are some.

[0312] The configuration examples shown in this embodiment and the corresponding drawings are at least partially It can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0313] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0314] (Embodiment 3) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. The explanation will be given using A), (B), and (C).

[0315] The display device shown in FIG. 16A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 505. 6 and a terminal portion 507. Note that the protection circuit 506 may be omitted. .

[0316] The transistors in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also use the transistor of one embodiment of the present invention. may be applied.

[0317] The pixel section 502 is a multi-layered pixel array arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The pixel circuit 501 includes a number of pixel circuits 501 for driving a number of display elements.

[0318] The driving circuit unit 504 includes a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. a source driver 504a, which supplies data signals to the data lines DL_1 to DL_Y; The gate driver 504a includes at least a shift register The source driver 504b may be, for example, a plurality of analog switches. Also, the source driver 504 is configured using a shift register, etc. b may be constructed.

[0319] The terminal unit 507 is a terminal for inputting power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals are provided for connecting the power supply to the power source.

[0320] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, Various wiring such as the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501, Connected.

[0321] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver 504a or the source driver 505 may be provided on the same substrate. The substrate 04b is a substrate formed separately (for example, a substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film). The drive circuit board is mounted on the COG or TAB (Tape Automated Bonding) The circuit board may be mounted on the substrate by using a method such as the above.

[0322] In addition, the pixel circuits 501 shown in FIG. 16(A) may be, for example, The configuration shown in FIG.

[0323] The pixel circuit 501 shown in FIG. 16B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_ m, a potential supply line VL, etc. are connected.

[0324] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0325] The pixel circuit 501 shown in FIG. 16C includes transistors 552 and 554 and a capacitance element. The pixel circuit 501 includes a data line DL_n , the scanning line GL_m, the potential supply line VL_a, the power supply line VL_b, etc. are connected to the pixel electrodes GL_m, GL_m.

[0326] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. A low power supply potential VSS is applied to the gate of the transistor 554. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 5 The brightness of the light emitted from 72 is controlled.

[0327] The configuration examples shown in this embodiment and the corresponding drawings are at least partially It can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0328] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0329] (Embodiment 4) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0330] [Circuit configuration] 17A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0331] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, The other end is connected to one electrode of the capacitor C1. The gate of the transistor M2 is G2, one of the source and drain is the wiring S2, and the other is the other electrode of the capacitance C1, and 401 and 402, respectively.

[0332] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) ems) elements, etc. can be applied.

[0333] The node connecting the transistor M1 and the capacitor C1 is designated as N1, and the transistor M2 and the circuit 40 are designated as Let N2 be the node connecting to 1.

[0334] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. In addition, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via transistor M1, capacitive coupling via capacitor C1 This makes it possible to change the potential of the node N2 in response to a change in the potential of the node N1.

[0335] Here, in one or both of the transistors M1 and M2, The transistor using an oxide semiconductor, which is exemplified in 1, can be used. Therefore, the potentials of the nodes N1 and N2 can be maintained for a long period of time due to the extremely low off-current. In addition, when the period for which the potential of each node is held is short (specifically, when the frame In cases where the system frequency is 30 Hz or more, transistors using semiconductors such as silicon A meter may also be used.

[0336] [Driving method example] Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. 4B is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, we have not included various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The effects of the transistor threshold voltage, etc. are not taken into account.

[0337] In the operation shown in FIG. 17B, one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0338] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the line S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supplies.

[0339] The node N1 is connected to a potential V ref is given. In addition, the node N2 is supplied with a first data potential V w is given. Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0340] [Period T2] In the next period T2, a potential is applied to the wiring G1 to turn on the transistor M1. A potential for turning off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. It may also be used as a ping.

[0341] A second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N That is, the first data potential Vw and the potential In FIG. 17B, dV is a positive value. However, it may be negative. That is, the potential V data is the potential V re f It may be lower.

[0342] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes the second Data potential V data The potential becomes close to

[0343] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential to be supplied to the line 401 can be generated, the gray scale correction can be performed within the pixel circuit 400. It will be possible to do so.

[0344] In addition, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when liquid crystal elements are used, overdriving is possible. It is possible to realize drive such as a spring.

[0345] [Example of application] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 17C includes a circuit 401LC. has a liquid crystal element LC and a capacitance C2.

[0346] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the Potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0347] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0348] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Achieving high-speed display through overdrive operation and using liquid crystal materials with high drive voltage In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0349] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 17D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0350] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the One of the drains is a wiring to which a potential VH is applied, and the other is one electrode of the light-emitting element EL. The capacitor C2 is connected to the other electrode at potential V com Connect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0351] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0352] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value of can be changed appropriately.

[0353] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or the wiring S2, the transistor It is also possible to correct the variations in the electrical characteristics of M3 and the light-emitting element EL.

[0354] In addition, the circuit is not limited to the circuits shown in FIG. 17(C) and (D), and may include other transistors, capacitors, etc. may be added.

[0355] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0356] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. I will explain this in more detail.

[0357] The display module 6000 shown in FIG. 18(A) includes an upper cover 6001 and a lower cover 6002. A display device 6006, a frame 6009, and a printer 6002 are connected to the FPC 6005. The semiconductor device has a support substrate 6010 and a battery 6011.

[0358] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0359] The upper cover 6001 and the lower cover 6002 are adapted to the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0360] The display device 6006 may have a function as a touch panel.

[0361] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0362] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. It has a signal processing circuit, a battery control circuit, etc. good.

[0363] FIG. 18B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. It is.

[0364] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guiding portions (light guiding portion 6017a, light guiding portion 6017b).

[0365] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are disposed on top of the light guide unit 6011. 017a and fixed to light guiding portion 6017b.

[0366] Light 6018 emitted from the light emitting portion 6015 is guided to the display device 600 by the light guiding portion 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0367] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information on the position where the touch operation was performed.

[0368] The light emitting unit 6015 may be a light source such as an LED element, and in particular, may be a light source that emits infrared rays. It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that can receive light and convert it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0369] The light guiding portion 6017a and the light guiding portion 6017b transmit light 6018. The light receiving unit 6016 can be disposed under the display device 6006, and external light is received by the light receiving unit 601. 6, which prevents the touch sensor from malfunctioning. If a resin that transmits wires is used for the light guides 6017a and 6017b, the touch sensor will not malfunction. This allows for more effective suppression of movement.

[0370] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0371] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described. Reveal.

[0372] The electronic device 6500 shown in FIG. 19(A) is a mobile device that can be used as a smartphone. It is a portable information terminal.

[0373] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, and a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0374] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0375] FIG. 19(B) is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0376] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. In the space surrounded by the protective member 6510, a display panel 6511, an optical member 6512, and a The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. There are.

[0377] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The panel 6513 is secured to the panel 6512 by an adhesive layer (not shown).

[0378] In addition, in an area outside the display portion 6502, a part of the display panel 6511 is folded back. The folded part is connected to the FPC6515. The 6515 is equipped with IC 6516. The FPC 6515 is a printed circuit board 6 517.

[0379] A flexible display panel according to one embodiment of the present invention is applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. 1 is extremely thin, so it can accommodate a large-capacity battery 6518 while keeping the thickness of the electronic device to a minimum. Also, a part of the display panel 6511 can be folded back and an FPC can be attached to the back side of the pixel area. By arranging the connection part with 6515, electronic devices with narrow bezels can be realized.

[0380] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0381] (Embodiment 7) In this embodiment, an electronic device including a display device manufactured according to one embodiment of the present invention will be described. I will explain this in more detail.

[0382] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to provide an electronic device that is compatible with both.

[0383] The display unit of the electronic device according to one embodiment of the present invention may be a display device that supports, for example, full high definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0384] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices that can be used for personal computers, digital cameras, digital video cameras, digital photo frames, mobile phones, etc. Examples of the portable electronic device include mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0385] An electronic device to which one aspect of the present invention is applied is installed on the inner or outer wall of a house or building, the interior of a car, etc. The sensor can be installed along a flat or curved surface of a housing or exterior.

[0386] FIG. 20A shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0387] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0388] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0389] The camera 8000 can be operated by pressing the shutter button 8004 or by using a touch panel. By touching the display portion 8002, an image can be captured.

[0390] The housing 8001 has a mount having electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as a

[0391] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0392] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The Finder 8100 is attached to the Camera 8000. The information can be displayed on the display unit 8102 .

[0393] The button 8103 has a function such as a power button.

[0394] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied to a camera having a built-in viewfinder. It may be La 8000.

[0395] FIG. 20B is a diagram showing the external appearance of the head mounted display 8200.

[0396] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0397] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0398] In addition, the attachment part 8201 is provided with a flow sensor that flows in accordance with the movement of the user's eyeball at a position where the device touches the user. A plurality of electrodes capable of detecting a current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse rate of the user by measuring the current flowing through the electrodes. In addition, the mounting part 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function for displaying the user's biological information, and the head of the user may have a function for displaying the user's biological information. The display portion 8204 may have a function of changing an image displayed on the display portion 8204 in accordance with the user's movement.

[0399] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0400] 20(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, and a backlight. The optical element has a band-shaped fixture 8304 and a pair of lenses 8305.

[0401] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The present invention is not limited to a configuration in which one display unit 8302 is provided, but may be configured in such a way that two display units 8302 are provided and one of the display units is One display unit may be arranged for each eye.

[0402] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the image is magnified using the lens 8305, the pixels are not visible to the user, and the image is more This makes it possible to display images with a higher sense of reality.

[0403] The electronic device shown in FIG. 21A to FIG. 21G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0404] The electronic devices shown in FIGS. 21A to 21G have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) a function for controlling processing by a wireless communication function, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data, etc. The electronic device may have a variety of functions, but is not limited to these. Also, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external It has the functions of storing the captured image on a memory card (built into the camera or the internal memory) and displaying the captured image on the display. It is okay to do so.

[0405] The electronic devices shown in FIGS. 21A to 21G will be described in detail below.

[0406] FIG. 21A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more or 100 inches or more It is possible to incorporate.

[0407] FIG. 21B is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. In the example shown in FIG. 9, three icons 9050 are displayed. 051 can be displayed on another surface of the display unit 9001. , notifications of incoming e-mails, SNS, phone calls, etc., subject of e-mails and SNS, sender Name, date, time, battery level, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where 51 is displayed.

[0408] FIG. 21C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example in which information 9053 and information 9054 are displayed on different sides is shown. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check information 9053 displayed in a position that can be observed from above 2. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0409] 21(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can communicate with, for example, a wireless headset. Therefore, a hands-free call is also possible. The device 9006 can transmit data to and from other information terminals and can also charge the device. The charging operation may be performed by wireless power supply.

[0410] 21(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 21E shows the portable information terminal 9201 in an unfolded state, and FIG. 21G shows the portable information terminal 9201 in a folded state. Figure 21(F) shows the state where the two are changing from Figure 21(E) to Figure 21(G). The portable information terminal 9201 is highly portable when folded and is unfolded and is in a perspective view. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. For example, the display unit 9001 is curved with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0411] FIG. 22A shows an example of a television device. A television device 7100 includes a housing 7 A display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0412] The television device 7100 shown in FIG. 22A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or a display unit 75 A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control operation device 7111 may have a display unit in addition to the operation buttons.

[0413] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0414] FIG. 22B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, The display unit 7500 is assembled in the housing 7211. It is embedded in the

[0415] Figure 22 (C) and (D) show digital signage. An example of a sub-sign is shown below.

[0416] The digital signage 7300 shown in FIG. 22C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0417] FIG. 22(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0418] The larger the display 7500, the more information can be provided at once, and the closer it is to the human eye. Since it is easy to attach to the skin, it has the effect of increasing the effectiveness of advertising, for example.

[0419] It is preferable that a touch panel be applied to the display unit 7500 so that a user can operate it. This will enable the use of the information not only for advertising purposes, but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide users with information they are looking for.

[0420] Also, as shown in FIG. 22(C) and (D), the digital signage 7300 or the digital The signage 7400 is connected wirelessly to an information terminal 7311 such as a smartphone carried by a user. For example, the advertisement displayed on the display unit 7500 may be The information is displayed on the screen of the information terminal 7311, and the information terminal 7311 is operated. In this way, the display on the display unit 7500 can be switched.

[0421] In addition, the Digital Signage 7300 or Digital Signage 7400 can be equipped with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0422] The display device of one embodiment of the present invention is applied to the display portion 7500 in FIGS. It is possible.

[0423] Although the electronic device of the present embodiment has a display unit, the present invention can be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above-mentioned semiconductor device.

[0424] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0425] 100, 100A to 100C: transistor, 102: substrate, 103: insulating layer, 103a , b: region, 106: conductive layer, 108, 108a, b: semiconductor layer, 108f: metal oxide Film, 108L: layer, 108N: region, 110: insulating layer, 110f: insulating film, 112: conductive layer, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide film, 115: resist Masks, 116, 118: insulating layers, 120a, 120b: conductive layers, 141a, b, 1 42: Opening

Claims

[Claim 1] a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer, a second conductive layer, and a metal oxide layer; the semiconductor layer is provided on the first insulating layer, the first insulating layer has a first region protruding in a thickness direction; the semiconductor layer overlaps with the first region, the second insulating layer has an upper surface of a second region other than the first region of the first insulating layer, a side surface of the first region, an upper surface of the semiconductor layer, and a region in contact with the side surface of the semiconductor layer; the metal oxide layer is provided on the second insulating layer; the first conductive layer is provided on the metal oxide layer; the first conductive layer has a region in which a lower surface of the first conductive layer on the second region is located at a position lower than a lower surface of the semiconductor layer; the semiconductor layer has a third region that does not overlap with the first conductive layer, the metal oxide layer, and the second insulating layer; the third insulating layer has a region in contact with an upper surface of the third region; the semiconductor layer and the metal oxide layer include a metal oxide containing indium and gallium; the metal oxide layer has a higher gallium composition than the semiconductor layer; the semiconductor layer has a first metal oxide film and a second metal oxide film on the first metal oxide film; the second metal oxide film has higher crystallinity than the first metal oxide film; the third insulating layer comprises a nitride; Semiconductor device.

Images