Semiconductor device

Abstract

To provide a semiconductor device that uses an oxide semiconductor and that can achieve microfabrication while maintaining good characteristics.SOLUTION: A semiconductor device comprises: an oxide semiconductor layer; a source electrode and a drain electrode contacted with the oxide semiconductor layer; a gate electrode overlapped with the oxide semiconductor layer; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. Each of the source electrode and the drain electrode includes: a first conductive layer; and a second conductive layer that has a region extending in a channel length direction from an end part of the first conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technical field of the invention relates to semiconductor devices. Here, the term "semiconductor device" refers to a device that utilizes the characteristics of semiconductors. This generally refers to elements and devices that function by [Background technology]

[0002] Metal oxides exist in a wide variety of forms and are used for a variety of purposes. Indium oxide is well known. It is a material that has been used as a transparent electrode material for liquid crystal display devices. do.

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using various metal oxides in the channel formation region are already known (e.g. , Patent Documents 1 to 4, Non-Patent Document 1, etc.).

[0004] By the way, not only single-component oxides but also multi-component oxides are known as metal oxides. For example, InGaO3(ZnO) with homologous phase m (m: natural number) is In, Ga and It is known as a multi-element oxide semiconductor containing Zn (for example, Non-Patent Document 2 and Non-Patent Document (See Reference 4, etc.).

[0005] In addition, oxide semiconductors made of the above-mentioned In-Ga-Zn oxides are also thin-film transistors. It has been confirmed that the method can be applied to the channel formation region of a transistor (for example, see Patent Document 5, Non-Patent Documents 5 and 6, etc. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Special Publication No. 60-198861 [Patent Document 2] Special Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Special Publication No. 2000-150900 [Patent Document 5] Japanese Patent Publication No. 2004-103957

Non-licensed documents

[0007]

Non-patent document 1

Non-patent document 2

Non-patent document 3

[0008] By the way, the speed of transistors, the power consumption of transistors, and the cost reductions, etc. In order to achieve this, miniaturization of transistors is essential.

[0009] When miniaturizing transistors, defects that occur during the manufacturing process become a major problem. For example, the source electrode and the drain electrode are electrically connected to the channel forming region. However, due to factors such as a decrease in coverage that accompanies miniaturization, disconnections and connection failures may occur.

[0010] Furthermore, when transistors are miniaturized, the short channel effect also occurs. The effect is a decrease in electrical characteristics that becomes apparent as transistors are miniaturized (reduced channel length (L)). The short channel effect occurs when the effect of the electric field of the drain electrode extends to the source electrode. Specific examples of short channel effects include a decrease in threshold voltage, In particular, transistors using oxide semiconductors have the following problems: It is known that the off-state current is smaller at room temperature than that of silicon transistors. This is because there are few carriers generated by thermal excitation, i.e., the carrier density is small. In transistors using materials with such low carrier density, the threshold There is a tendency for short channel effects such as voltage drop to occur.

[0011] In view of the above, one embodiment of the disclosed invention provides a semiconductor device that achieves miniaturization while suppressing defects. Another object of the present invention is to provide a semiconductor device that achieves miniaturization while maintaining good characteristics. One of the objectives is to [Means for solving the problem]

[0012] One embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer, a source electrode and a drain electrode which are in contact with the oxide semiconductor layer, a gate electrode overlapping the oxide semiconductor layer; and a gate electrode between the oxide semiconductor layer and the gate electrode. and a gate insulating layer provided between the source electrode and the drain electrode. a second conductive layer having a region extending in a channel length direction from an end of the first conductive layer; The semiconductor device includes:

[0013] In the above semiconductor device, the first conductive layer and the second conductive layer are preferably tapered. I wish.

[0014] In the above semiconductor device, a sidewall insulating layer is provided on the second conductive layer. It is preferable to do so.

[0015] Another embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer and a source a gate electrode overlapping the oxide semiconductor layer; and a gate insulating layer provided between the source electrode and the drain electrode. a first conductive layer and a second conductive layer having a higher resistance than the first conductive layer, In the semiconductor device, a first insulating film is provided in contact with an oxide semiconductor layer.

[0016] Another embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer and a source a gate electrode overlapping the oxide semiconductor layer; and a gate insulating layer provided between the source electrode and the drain electrode. a first conductive layer and a second conductive layer having a higher resistance than the first conductive layer, and the first conductive layer is in contact with the oxide semiconductor layer.

[0017] In the above semiconductor device, the second conductive layer is preferably a metal nitride.

[0018] In the above semiconductor device, the second conductive layer has a thickness of 5 nm to 15 nm. preferable.

[0019] Another embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer having a channel formation region and a The source electrode and the drain electrode are in contact with the gate electrode and the channel region. a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; In the drain electrode and the gate electrode, the regions in contact with the channel formation region of the oxide semiconductor layer are The semiconductor device has a higher resistance than other regions.

[0020] In the above semiconductor device, the source electrode or the drain electrode has an end portion A semiconductor layer is in contact with the oxide semiconductor layer and is disposed between the source electrode or the drain electrode and the oxide semiconductor layer. It is preferable that the insulating layer is provided on the substrate.

[0021] Here, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. For example, A display device, a memory device, an integrated circuit, and the like can be included in the semiconductor device.

[0022] In addition, the terms "above" and "below" in this specification and the like refer to the positional relationship of components "directly above" or "below." For example, "gate electrode on a gate insulating layer" is not limited to "directly under". ", it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation and are not to be specifically mentioned. Except in certain cases, this also includes those with the top and bottom reversed.

[0023] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as an integral part.

[0024] In addition, the functions of the "source electrode" and "drain electrode" can be changed by adopting transistors with different polarities. These may be reversed when the load is increased or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source electrode" and "drain electrode" are interchangeable. It is possible to use it.

[0025] In addition, in this specification, "electrically connected" means "something that has some electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects. For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as Effect of the Invention

[0026] According to one embodiment of the disclosed invention, it is possible to obtain one or both of the following effects: be.

[0027] First, the source electrode and the drain electrode are formed as a laminated structure of a first conductive layer and a second conductive layer, By providing a region in the second conductive layer that extends in the channel length direction from the end of the first conductive layer, Therefore, the coverage is improved when forming a semiconductor layer on the source electrode and the drain electrode. This prevents connection failures and other problems from occurring.

[0028] Second, in the vicinity of the region of the source electrode or the drain electrode that contacts the channel forming region By making the region a high resistance region, the electric field between the source electrode and the drain electrode can be relaxed. This makes it possible to suppress short channel effects such as a decrease in threshold voltage.

[0029] These effects will eliminate the problems associated with miniaturization, resulting in: It becomes possible to make the transistor size sufficiently small. By making the size smaller, the area occupied by a semiconductor device using a transistor is reduced, and the area of ​​a substrate or This increases the number of semiconductor devices per package, thereby reducing the manufacturing cost per semiconductor device. In addition, as semiconductor devices become smaller, the functionality can be improved with the same size. In addition, the reduction in channel length can lead to an increase in the operating speed. In other words, according to one embodiment of the disclosed invention, By achieving miniaturization of transistors using nitride semiconductors, various associated effects will be realized. It is possible to obtain results.

[0030] In this way, according to one embodiment of the disclosed invention, it is possible to suppress defects or to obtain good characteristics. It is possible to provide a semiconductor device that achieves miniaturization while maintaining the same quality. [Brief description of the drawings]

[0031] [Figure 1] FIG. [Diagram 2] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Diagram 3] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 4] FIG. [Diagram 5] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 6] 1 is an example of a circuit diagram of a semiconductor device. [Figure 7] 1 is an example of a circuit diagram of a semiconductor device. [Figure 8] 1 is an example of a circuit diagram of a semiconductor device. [Figure 9] Examples of electronic devices. [Figure 10] FIG. 13 is a cross-sectional view showing a model of a transistor used in calculations. [Figure 11] FIG. 13 is a graph showing the relationship between channel length L (nm) and threshold voltage shift amount ΔVth (V). [Figure 12] FIG. 13 is a graph showing the relationship between channel length L (nm) and threshold voltage shift amount ΔVth (V). [Figure 13] FIG. 13 is a graph showing the relationship between channel length L (nm) and threshold voltage shift amount ΔVth (V). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof are not limited to those described above without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the above may be modified in various ways. The present invention should not be construed as being limited to the description of the embodiments.

[0033] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0034] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0035] (Embodiment 1) In this embodiment, an example of a structure of a semiconductor device according to one embodiment of the disclosed invention and a manufacturing process thereof will be described. This will be described with reference to FIGS.

[0036] <Configuration Example of Semiconductor Device> 1A to 1D show cross-sectional structures of transistors as examples of semiconductor devices. 1A to 1D show a top view of a transistor according to one embodiment of the disclosed invention. 1 shows a p-gate type transistor.

[0037] The transistor 160 illustrated in FIG. 1A includes a first conductive layer 142a and a second conductive layer 142b over a substrate 100. The source electrode is formed by stacking a first conductive layer 142b and a second conductive layer 145a in order. The drain electrode is formed by stacking an insulating layer 143 on the source electrode. a, an insulating layer 143b provided on the drain electrode, and an insulating layer 143a and an insulating layer 143 b, and a gate electrode 143 provided on the oxide semiconductor layer 144. The semiconductor device has an insulating layer 146 and a gate electrode 148 disposed on the gate insulating layer 146. .

[0038] In the transistor 160 illustrated in FIG. 1A, the second conductive layer 145a is a first conductive layer The region extends from the end of 142a in the channel length direction (direction in which carriers flow). In this case, the second conductive layer 145a is in contact with at least a channel formation region of the oxide semiconductor layer 144. In addition, the second conductive layer 145b is located at a position slightly larger than the end of the first conductive layer 142b by a channel length. The second conductive layer 145b and the oxide semiconductor layer 144 have a region extending in the direction of the insulating film 141. At the very least, it is in contact with the channel formation region.

[0039] More specifically, the second conductive layer 145a is located at a channel length greater than the end of the first conductive layer 142a. It has an area extending toward the drain electrode in the direction of carrier flow. In addition, the second conductive layer 145b is disposed in a direction parallel to the source electrode 141 from the end of the first conductive layer 142b in the channel length direction. It has an elongated region toward the electrode.

[0040] Difference between the transistor 170 illustrated in FIG. 1B and the transistor 160 illustrated in FIG. The first difference is whether or not the insulating layers 143a and 143b are present. The second conductive layer 145a and the second conductive layer 145b are in contact with the upper surfaces and ends of the second conductive layer 145a and the second conductive layer 145b. A nitride semiconductor layer 144 is provided.

[0041] In the transistor 170 illustrated in FIG. 1B, similarly to the transistor 160, The conductive layer 145a has a region extending in the channel length direction from the end of the first conductive layer 142a. The second conductive layer 145b is located in the channel length direction from the end of the first conductive layer 142b. It has an elongated region.

[0042] Difference between the transistor 180 shown in FIG. 1C and the transistor 160 shown in FIG. The first is the stacking order of the first conductive layer 142a and the second conductive layer 145a, and The stacking order of the first conductive layer 42b and the second conductive layer 145b is shown in FIG. The source electrode is formed by sequentially stacking a second conductive layer 145a and a first conductive layer 142a. a drain electrode in which a second conductive layer 145b and a first conductive layer 142b are laminated in this order; is.

[0043] In the transistor 180 illustrated in FIG. 1C, the second conductive layer 145a is The second conductive layer 142a has an area extending in the channel length direction from the end of the conductive layer 142a. 45b has a region extending in the channel length direction from the end of the first conductive layer 142b. Therefore, the insulating layer 143a is formed on the second conductive layer 145a so that the first conductive layer 142a The first conductive layer 142a is provided in contact with a region extending in the channel length direction from the end of the first conductive layer 142a. In addition, the insulating layer 143b is formed such that the second conductive layer 145b is adjacent to the first conductive layer 142. b in the channel length direction and in contact with the first conductive layer 142b. It is being done.

[0044] Difference between the transistor 190 shown in FIG. 1D and the transistor 180 shown in FIG. The first difference is whether or not the insulating layers 143a and 143b are present. In the first conductive layer 142a, the first conductive layer 142b, and the second conductive layer 145a, The region extending in the channel length direction from the end of the first conductive layer 142a and the region extending in the channel length direction from the end of the second conductive layer 14 5b, which is in contact with a region extending in the channel length direction from an end of the first conductive layer 142b. An oxide semiconductor layer 144 is provided therebetween.

[0045] In the transistor 190 illustrated in FIG. 1D, the second conductive layer 145a is The second conductive layer 145a has a region extending in the channel length direction from the end of the second conductive layer 142a. and at least a channel formation region of the oxide semiconductor layer 144. The first conductive layer 145b has a region extending in the channel length direction from the end of the first conductive layer 142b. The second conductive layer 145b and at least a channel formation region of the oxide semiconductor layer 144 are adjacent.

[0046] <Example of the transistor manufacturing process> An example of a manufacturing process of the transistor shown in FIG. 1 will be described below with reference to FIGS. .

[0047] <Fabrication process of transistor 160 or transistor 170> First, the transistor 160 shown in FIG. 1A is fabricated using FIG. An example of the process will be described. Note that the transistor 170 shown in FIG. The manufacturing process of the transistor 160 can be taken into consideration, except that 43a and 143b are not provided. Therefore, detailed description will be omitted.

[0048] A first conductive film is formed on a substrate 100 having an insulating surface, and the conductive film is selectively etched. Then, the first conductive layers 142a and 142b are formed (see FIG. 2(A)). The film thickness is, for example, 50 nm to 500 nm.

[0049] There is no particular limitation on the substrate that can be used for the substrate 100. It is necessary to have heat resistance sufficient to withstand heat treatment. For example, glass substrates, Substrates such as ceramic substrates, quartz substrates, and sapphire substrates can be used. If it has a surface, it can be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. It is also possible to use compound semiconductor substrates such as silicon germanium and SOI substrates. The substrate 100 may have a semiconductor element formed thereon. An undercoat film may be provided.

[0050] The first conductive film is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The first conductive film can be formed by a method such as the above. Elements selected from chromium, copper, tantalum, titanium, molybdenum, and tungsten, or Nitrides of these elements, alloys containing the above elements, etc. can be used. The material is made of either tungsten, zirconium, or beryllium, or a combination of these. In addition, titanium, tantalum, tungsten, molybdenum, Materials made of elements selected from chromium, neodymium, and scandium, or a combination of these elements Fees may also be used.

[0051] The first conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, , a single layer structure of a titanium film, a single layer structure of an aluminum film containing silicon, A two-layer structure with a titanium film laminated, a three-layer structure with a titanium film, an aluminum film, and a titanium film laminated When the first conductive film has a single-layer structure, the first conductive film may have a tapered shape. The advantage of this is that it is easy to process the source and drain electrodes having the same structure.

[0052] The first conductive film may be formed using a conductive metal oxide. The materials are indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0053] The etching of the first conductive film is performed so that the first conductive layer 142a and the first conductive layer 142 It is preferable that the end of b is tapered. Here, the taper angle α1 and and β1 are the distances from the ends of the first conductive layer 142a and the first conductive layer 142b to the substrate surface, respectively. The angle between the side surfaces of the portion is preferably, for example, 30° to 60° (see FIG. 2(A)). )reference).

[0054] Next, a second conductive film 1 is formed so as to cover the first conductive layers 142a and 142b and the substrate 100. The thickness of the second conductive film 145 is 3 nm to 30 nm, preferably 5 nm. Up to 15 nm.

[0055] The second conductive film 145 can be formed of the same material and by the same film formation method as the first conductive film. That is, the material of the second conductive film can be aluminum, chromium, copper, tantalum, titanium, etc. Elements selected from the group consisting of tungsten, molybdenum, and tungsten, and their nitrides, The alloys containing manganese, magnesium, zirconium, borium, etc. can be used. Alternatively, a combination of two or more of these materials may be used. Minium, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a combination of elements selected from the group consisting of tungsten, cadmium, and zinc may be used. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide In2O3-SnO2, sometimes abbreviated as ITO), indium tin oxide In2O3-ZnO, or these metal oxide materials with silicon Alternatively, a conductive metal oxide containing silicon oxide or silicon oxide may be used.

[0056] The second conductive film 145 is made of a material having a higher resistance than the first conductive layers 142a and 142b. It is preferable to use a material having a high conductivity. In the oxide semiconductor layer, a region of the oxide electrode that is in contact with a channel formation region is thicker than the other region. The high resistance of the MOSFET reduces the electric field between the source and drain electrodes, which reduces the short channel effect. The conductive material used for the second conductive film 145 is, for example, For example, metal nitrides such as titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride. The second conductive film 145 is preferably a source electrode or a drain electrode. Since the second conductive film 145 becomes a part of the doped electrode and comes into contact with the oxide semiconductor layer, It is preferable to use a material that does not chemically react when in contact with the conductor layer. It is also preferable in this respect.

[0057] Next, an insulating film 143 is formed on the second conductive film 145 to a thickness of 50 nm to 300 nm, preferably In most cases, the thickness is 100 nm to 200 nm (see FIG. 2A). In this case, a silicon oxide film is formed as the insulating film 143. As shown in the case of the transistor 170, the insulating film 143 is not necessarily formed. However, when the insulating film 143 is provided, the source electrode or drain electrode In this case, it becomes easier to control the contact area (contact area, etc.) with the oxide semiconductor layer. This makes it easier to control the resistance of the gate or drain electrode, effectively suppressing the short channel effect. In addition, by providing the insulating film 143, the gate electrode to be formed later can be formed. , it is possible to reduce the parasitic capacitance between the source electrode and the drain electrode.

[0058] Next, a mask is formed on the insulating film 143, and the insulating film 143 is etched using the mask. As a result, insulating layers 143a and 143b are formed (see FIG. 2B). The etching of 3 can be performed by wet etching or dry etching. A combination of wet etching and dry etching may be used. The etching conditions (etching gas and etching method) are adjusted to suit the material so that the etching can be performed smoothly. The etching conditions (etching solution, etching time, temperature, etc.) shall be set appropriately. In order to process the channel length (L) finely, it is preferable to use dry etching. The etching gas used for dry etching is, for example, sulfur hexafluoride (SF6), trifluoromethane (THF), etc. Fluorine-containing gases such as nitrogen fluoride (NF3), trifluoromethane (CHF3), or , a mixture of carbon tetrafluoride (CF4) and hydrogen, etc. can be used, and rare gases (helium ( He), argon (Ar), xenon (Xe), carbon monoxide, or carbon dioxide, etc. You can do that.

[0059] Next, the second conductive film 145 is etched using the mask used for etching the insulating film 143. By this, second conductive layers 145a and 145b are formed (see FIG. 2(C)). Before etching the second conductive film 145, the mask is removed, and the insulating layer 143a and The second conductive film 145 may be etched using the insulating layer 143b as a mask. In the case where the insulating layer is not provided, as shown in the transistor 170 of FIG. A mask may be formed directly on the conductive film 145 to etch the second conductive film. The etching of the conductive film 145 is performed on the ends of the second conductive layer 145a and the second conductive layer 145b. In the case where the insulating film 143 is provided, the insulating layer It is preferable that the ends of the insulating layer 143a and the insulating layer 143b are also tapered. Here, the taper angles α2 and β2 are the angles of the second conductive layer 145a with respect to the substrate surface. At the angle formed by the side surfaces of the second conductive layer 145b, the insulating layer 143a, and the insulating layer 143b at the end For example, it is preferable that the angle is 30° or more and 60° or less.

[0060] The second conductive film 145 is etched by wet etching or dry etching. Alternatively, wet etching and dry etching may be used in combination. The etching conditions (etching gas, etc.) can be adjusted to suit the material so that the desired shape can be etched. The etching solution, etching time, temperature, etc. shall be set appropriately. In order to finely process the channel length (L) of the MOSFET, it is preferable to use dry etching. The etching gas used for etching the second conductive film 145 is, for example, chlorine. (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrafluoride ( CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), etc. can be used. A mixture of two or more selected from the above may be used. In addition, the etch of the second conductive film 145 may be performed using a gas such as argon (Ar) or oxygen. The etching can be performed successively using the same gas as that for etching the insulating film 143.

[0061] This etching process results in a first conductive layer 142a and a second conductive layer 145a being laminated. The source electrode is a first conductive layer 142b and a second conductive layer 145b. By appropriately adjusting the mask used for etching, the first conductive layer 14 A second conductive layer 145a having a region extending in the channel length direction from the end of 2a, or The second conductive layer 142b has a region extending in the channel length direction from the end of the first conductive layer 142b. 45b can be formed.

[0062] The channel length (L) of the transistor 160 is determined by dividing the length between the bottom end of the second conductive layer 145a and the bottom end of the second conductive layer 145b. The channel length (L) is determined by the distance between the bottom end of the first conductive layer 145b and the bottom end of the second conductive layer 145b. The thickness of the star 160 varies depending on the application, but may be, for example, 10 nm to 1000 nm, preferably 20 It can be from 400 nm to 400 nm.

[0063] In addition, when forming a transistor having a channel length (L) of less than 25 nm, the insulating film 143 and When performing exposure to form a mask used for etching the second conductive film 145, the thickness of the mask is set to several nm to several Extreme ultraviolet rays with a short wavelength of 10 nm are used. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is also possible to make the channel length (L) of the transistor used sufficiently small, It is possible to increase the operating speed. In addition, miniaturization reduces the power consumption of semiconductor devices. It is also possible to reduce it.

[0064] In addition, in the second conductive layer, a region extending in the channel length direction from the end of the first conductive layer is This has the effect of improving coverage in the subsequent oxide semiconductor layer and gate insulating layer formation steps. In the second conductive layer 145a, the first conductive layer 142a is formed on the first conductive layer 142a. The length of the region in the channel length direction (L S ) in the second conductive layer 145b, The length in the channel length direction of the region extending in the channel length direction from the end of the first conductive layer 142b ( L D ) are not necessarily the same. However, for example, if transistor 160 is placed on the same substrate, If multiple transistors are provided, the L S and L D The sum of these values ​​is approximately constant.

[0065] Next, an oxide semiconductor layer 144 is sputtered on the insulating layers 143a and 143b and the substrate 100. The oxide semiconductor layer 144 is formed by a deposition method (see FIG. 2D). The thickness of the oxide semiconductor layer 1 is preferably 5 nm to 30 nm, and more preferably 5 nm to 15 nm. 44 is a second conductive layer 145a, a second conductive layer 145b, and at least a channel forming region. They are in contact at .

[0066] Here, the second conductive layers 145a and 145b are closer to the ends of the first conductive layers 142a and 142b. By having a region extending in the channel length direction, the ends of the source electrode and the drain electrode Therefore, the step in the oxide semiconductor layer 144 can be made gentle. This improves the covering property and prevents breakage.

[0067] The source electrode and the drain electrode of the transistor 160 to be manufactured are formed by the second conductive layer 1. Only the ends of the second conductive layer 145a and the second conductive layer 145b are in contact with the oxide semiconductor layer 144. As a result, the top surfaces of the source electrode and the drain electrode are also in contact with the oxide semiconductor layer. In this way, the contact area of ​​the source electrode can be significantly reduced compared to the case where the source electrode is In addition, by reducing the contact area between the drain electrode and the oxide semiconductor layer 144, The contact resistance at the source and drain electrodes can be increased, and the electric field between the source and drain electrodes can be reduced. The technical idea of ​​the disclosed invention is to provide a source electrode and a drain electrode. Since the purpose of the present invention is to form a high resistance region in the second region, the source electrode and the drain electrode are strictly the second The oxide semiconductor layer 144 is formed only at the end portions of the first conductive layer 145a and the second conductive layer 145b. For example, the second conductive layer 145a and the second conductive layer 145b may be A part of the oxide semiconductor layer 144 may be in contact with the oxide semiconductor layer 144 .

[0068] The oxide semiconductor layer 144 is made of a quaternary metal oxide such as In-Sn-Ga-Zn-O or a ternary The In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. , Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides. It can be formed using In-O, Sn-O, Zn-O, or other materials.

[0069] Among them, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. Since it is possible to sufficiently reduce the field current and the field effect mobility is high, It is suitable as a semiconductor material for use in devices.

[0070] A representative example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0, m: non-natural number). Also, M is used instead of Ga, and I nMO3(ZnO) m (m>0, m: non-natural number) Here, M is gallium (Ga), aluminum (Al), iron (Fe), or nickel. (Ni), manganese (Mn), cobalt (Co), etc. For example, M is Ga, Ga and Al, Ga and Fe, Ga and and Ni, Ga and Mn, Ga and Co, etc. can be applied. It should be noted that this is derived from the crystal structure and is merely one example.

[0071] The oxide semiconductor layer 144 is formed by sputtering with a target of In:Ga: The composition formula is Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] A metal oxide target having a composition ratio of In2O3 Metal oxide target with a composition ratio of Ga2O3:ZnO=1:1:1 [molar ratio] and gold with a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio]. Metal oxide targets and In2O3:Ga2O3:ZnO=1:0:2 [molar ratio] A metal oxide target having a composition ratio can also be used.

[0072] In this embodiment, the oxide semiconductor layer 144 having an amorphous structure is made of In-Ga-Zn-O based metal. The layer is formed by sputtering using a metal oxide target.

[0073] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more. More preferably, the relative density is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form the oxide semiconductor layer 144 with a dense structure.

[0074] The oxide semiconductor layer 144 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration is reduced to 10 ppb or less. It is.

[0075] When the oxide semiconductor layer 144 is formed, for example, a processing object is placed in a processing chamber kept in a reduced pressure state. The object (here, a structure including a substrate 100) is held, and the temperature of the object to be processed is kept at 100° C. or higher and 55° C. or lower. The workpiece is heated to a temperature below 0°C, preferably between 200°C and 400°C. Or The temperature of the object to be treated during the formation of the oxide semiconductor layer 144 may be room temperature. While removing moisture from the treatment chamber, a sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor layer 144 is formed using the get. By forming the oxide semiconductor layer 144, impurities contained in the oxide semiconductor layer 144 can be reduced. In addition, damage caused by sputtering can be reduced. For this purpose, it is preferable to use an adsorption type vacuum pump. A pump such as a suction pump or a titanium sublimation pump can be used. A cryopump or similar device may be used to evacuate the gas. Since hydrogen, water, and the like can be removed from the treatment chamber, the oxide semiconductor layer 144 The concentration of impurities in the

[0076] The conditions for forming the oxide semiconductor layer 144 include, for example, the distance between the processing object and the target. The diameter was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was oxygen (oxygen 100%) atmosphere, or argon (100% argon) atmosphere, or oxygen and argon In addition, a pulsed direct current (DC) power source is used. By using this, powdery substances (also called particles or dust) generated during film formation can be reduced, and the film thickness can be improved. The oxide semiconductor layer 144 has a thickness of, for example, 3 nm to 3 The thickness of the oxide semiconductor layer 144 is set to 0 nm, preferably 5 nm to 15 nm. By using this, it is possible to suppress the short channel effect that accompanies miniaturization. The appropriate thickness varies depending on the oxide semiconductor material used and the application of the semiconductor device. The thickness can be selected depending on the material used and the application.

[0077] Before the oxide semiconductor layer 144 is formed by a sputtering method, argon gas is introduced. Then, a reverse sputtering process is performed to generate plasma by sputtering the insulating layer 143a, 143b. In this case, the reverse sputtering is the same as the normal sputtering. In the ion beam sputtering, instead of bombarding the sputtering target with ions, the ions are directed at the surface to be treated. This is a method of modifying a surface by bombarding it with ions. The method of collision is to apply a high frequency voltage to the treatment surface side in an argon atmosphere. In addition, nitrogen and helium are used instead of argon. An atmosphere of sodium, oxygen, etc. may also be used.

[0078] After that, the oxide semiconductor layer 144 is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (including water and a hydroxyl group) from the oxide semiconductor layer 144. ) is removed, the structure of the oxide semiconductor layer is adjusted, and the defect level in the energy gap is reduced. The temperature of the first heat treatment can be, for example, 300° C. or more and less than 550° C., or 40 The temperature must be between 0℃ and 500℃.

[0079] The heat treatment is carried out, for example, by placing the workpiece in an electric furnace using a resistance heating element, and heating the workpiece in a nitrogen atmosphere. The heat treatment can be performed under conditions of 450° C. and 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the air. Do not allow leakage or contamination with water or hydrogen.

[0080] The heat treatment device is not limited to an electric furnace, and may be heat conducted from a medium such as a heated gas or heat radiation. For example, a device that heats the workpiece by LRTA (Lamp Ra pid Thermal Annealing Equipment, GRTA (Gas Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a light bulb. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. Inert gases such as rare gases or nitrogen that do not react with the workpiece during heat treatment are used. Used.

[0081] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and left for several minutes. After the heating, the workpiece may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA processing allows high-temperature heat treatment in a short time. The present invention can be applied even under temperature conditions exceeding 100°C. During the treatment, inert gas is used instead of oxygen. By performing the first heat treatment in an atmosphere containing oxygen, This is because it is possible to reduce defect levels in the energy gap caused by oxygen vacancies. .

[0082] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing 1,2-dichloroethane (CO), which is the main component, and does not contain water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into heat treatment equipment Purity should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0083] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming the oxide semiconductor layer 144 that is close to the It is possible to realize the above.

[0084] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. The heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the formation of an oxide semiconductor layer, after the formation of a gate insulating layer, or after the formation of a gate electrode. It is also possible to carry out the dehydration treatment at a timing such as after the dehydration treatment. The hydrogenation treatment may be carried out not only once but also multiple times.

[0085] Next, the gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144 (see FIG. 2E). Here, the second conductive layers 145a and 145b are connected to the ends of the first conductive layers 142a and 142b. By having a region extending in the channel length direction, Therefore, the step in the covering portion of the gate insulating layer 146 can be made gentle. This improves the covering property and prevents breakage.

[0086] The gate insulating layer 146 can be formed by using a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (Hf SixOy(x>0, y>0)), nitrogen-doped hafnium silicate (HfSix OyNz(x>0, y>0, z>0)), nitrogen doped hafnium aluminate (H It is preferable to form the sine wave array so as to include fAlxOyNz (x>0, y>0, z>0), etc. The gate insulating layer 146 may have a single layer structure or a stacked layer structure. The thickness is not particularly limited, but when miniaturizing a semiconductor device, the operation of the transistor For example, when silicon oxide is used, the thickness is 1n. The thickness m can be set to 100 nm or more, and preferably 10 nm or more and 50 nm or less.

[0087] As mentioned above, making the gate insulating layer thinner reduces gate leakage caused by the tunnel effect, etc. To solve the gate leakage problem, the gate insulating layer 146 is doped with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0 , y>0), nitrogen-doped hafnium silicate (HfSixOyNz(x>0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAlxOyNz( It is recommended to use high-k materials such as x>0, y>0, z>0. By using an igh-k material for the gate insulating layer 146, the electrical characteristics are ensured while the gate It is possible to increase the film thickness to suppress leakage. and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, alumina oxide, Alternatively, it may have a laminated structure with a film containing any one of aluminum and the like.

[0088] After the gate insulating layer 146 is formed, a second thermal annealing is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0 and 350°C. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. In addition, when the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 By supplying oxygen to the oxide semiconductor layer 144, oxygen vacancies in the oxide semiconductor layer 144 are compensated for, so that the oxide semiconductor layer 144 becomes an i-type (intrinsic semiconductor) or Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0089] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not particularly limited. For example, the second heat treatment may be performed after the formation of the gate electrode. Alternatively, a second heat treatment may be performed after the first heat treatment. The first heat treatment may be combined with the second heat treatment, or the second heat treatment may be combined with the first heat treatment. It's okay to let them sleep.

[0090] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide The semiconductor layer 144 is highly purified so that it contains as few impurities as possible other than its main components. As a result, the hydrogen concentration in the oxide semiconductor layer 144 can be increased to 5×10 19 atoms / cm 3 Less than 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 In addition, the carrier of the oxide semiconductor layer 144 can be The carrier density is calculated by dividing the carrier density in a typical silicon wafer (1×10 14 / cm 3 degree) A sufficiently small value (e.g., 1×10 12 / cm 3Less than 1, more preferably .45×10 10 / cm 3 This allows the off-state current to be For example, the off-state current of the transistor 160 at room temperature (here, unit transistor The value per channel width (1 μm) is 100zA / μm (1zA (zeptoampere) is 1 ×10 -21 A) or less, and preferably, 10zA / μm or less.

[0091] Next, a semiconductor layer 144 is formed over the gate insulating layer 146. A gate electrode 148 is formed in the region where the gate electrode 148 is to be formed (see FIG. 2(F)). After a conductive film is formed on the insulating layer 146, the conductive film is selectively etched. The conductive film to be the gate electrode 148 can be formed by a method such as sputtering. The film can be formed by using a PVD method such as a plasma CVD method. The same applies to the case of a source electrode or a drain electrode, and the descriptions therefor can be taken into consideration. However, the work function of the material of the gate electrode 148 is approximately equal to the electron affinity of the oxide semiconductor layer 144. If the size of the transistor is 100 nm or less, the threshold voltage of the transistor will decrease when the transistor is miniaturized. Therefore, the gate electrode 148 is provided with a It is preferable to use a material having a work function larger than the electron affinity. Examples of such materials include tungsten, platinum, gold, and silicon that has been given p-type conductivity.

[0092] Through the above steps, the transistor 160 including the oxide semiconductor layer 144 is completed.

[0093] <Fabrication process of transistor 180 or transistor 190> Next, a process for manufacturing the transistor 180 shown in FIG. 1C will be described with reference to FIGS. An example of the process will be described. Note that the transistor 190 shown in FIG. The manufacturing process of the transistor 180 can be taken into consideration, except that the transistor 143a and the transistor 143b are not included. Therefore, detailed description will be omitted.

[0094] A second conductive film 145 is formed on the substrate 100. The second conductive film 145 has a thickness of 3 nm. Next, a second conductive film 145 is formed on the second conductive film 145. A first conductive film is formed and selectively etched to form a first conductive layer 142. Then, the first conductive layers 142a and 142b and the second conductive film 142a and 142b are formed. An insulating film 143 is formed on the film 145 (see FIG. 3A).

[0095] In addition, when the first conductive film is formed on the second conductive film, the second conductive film and the first conductive film The materials for the second conductive layer and the second conductive layer are selected so that the etching selectivity can be obtained. It is preferable that the film is made of a material having a higher resistance than the first conductive film. A titanium nitride film is formed as the second conductive film 145, and a tungsten film is formed as the first conductive film. It forms a film or molybdenum film and combines carbon tetrafluoride (CF4), chlorine (Cl2) and oxygen (O2 ), carbon tetrafluoride (CF4) and oxygen (O2) mixed gas, sulfur hexafluoride (S F6), chlorine (Cl2) and oxygen (O2) mixed gas, or sulfur hexafluoride (SF6) The first conductive film is etched using a mixed gas of SiO2 and oxygen (O2), thereby forming a first conductive film. Layers 142a and 142b are to be formed.

[0096] In addition, as shown in FIG. 1D for a transistor 190, the insulating film 143 is not necessarily Although it is not necessary to form the insulating film 143, the insulating film 143 is provided to prevent the gate electrode from being damaged. , it is possible to reduce the parasitic capacitance between the source electrode and the drain electrode.

[0097] Next, in the same manner as in the process shown in FIG. 2B, a mask is formed on the insulating film 143. The insulating film 143 is etched using the etching agent to form insulating layers 143a and 143b. (See FIG. 3(B)).

[0098] Next, in the same manner as in the process shown in FIG. 2(C), the insulating layer 143a and the insulating layer 143b are etched. The second conductive film 145 is etched using the mask used for etching, to form the second conductive film. The second conductive film 145 is then formed on the insulating film 144. Before etching, the mask is removed, and the insulating layer 143a and the insulating layer 143b are used as a mask. The second conductive film 145 may be etched using the above-mentioned etching method. The etching gases used are, for example, chlorine (Cl2), boron trichloride (BCl3), tetrachloride (TbCl4), etc. Silicon chloride (SiCl4), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), trifluoride Nitrogen (NF3), etc. can be used, and a mixture of multiple selected gases from these can be used. Also, rare gases (helium (He), argon (Ar)) may be added. In addition, as shown in FIG. 1D, when an insulating layer is not provided, A mask may be formed directly on the conductive film 145 and the second conductive film may be etched.

[0099] Next, in the same manner as in the process shown in FIG. 2(D), the insulating layers 143a and 143b and the substrate 100 are An oxide semiconductor layer 144 is formed on the insulating film 140 by a sputtering method (see FIG. 3D). The oxide semiconductor layer 144 includes at least the second conductive layer 145a and the second conductive layer 145b. The oxide semiconductor layer 144 is in contact with both of the first and second insulating layers 141 and 142 in the channel formation region. It is desirable to carry out a heat treatment (first heat treatment).

[0100] Next, in the same manner as in the step shown in FIG. 2E, a gate insulating layer in contact with the oxide semiconductor layer 144 is After the gate insulating layer 146 is formed, a heat treatment (second It is desirable to carry out heat treatment of the above mentioned conditions.

[0101] Next, similarly to the step shown in FIG. 2F, an oxide semiconductor A gate electrode 148 is formed in a region of the layer 144 that overlaps with the channel forming region (FIG. 3(F)). reference).

[0102] Through the above steps, a transistor 180 including the oxide semiconductor layer 144 is completed.

[0103] In the transistors 160, 170, 180, and 190 shown in this embodiment, the first conductor The source electrode and the drain electrode are formed by stacking a first conductive layer and a second conductive layer. The first conductive layers 142a and 142b extend beyond the ends of the first conductive layers 142a and 142b in the channel length direction. This makes it possible to eliminate the step at the ends of the source electrode and the drain electrode. Since the thermal expansion of the oxide semiconductor layer 144 and the gate insulating layer 146 can be gradual, It is possible to improve coverage and prevent connection failures.

[0104] In addition, in the transistors 160, 170, 180, and 190 shown in this embodiment, In the source electrode or drain electrode, the vicinity of the region in contact with the channel forming region is defined as a high resistance region. By making the region, the electric field between the source electrode and the drain electrode can be relaxed, and the transistor It is possible to suppress the short channel effect that accompanies the reduction in the size of the transistor.

[0105] In this way, in one embodiment of the disclosed invention, problems associated with miniaturization can be solved. As a result, it becomes possible to make the transistor size sufficiently small. By making the transistor size sufficiently small, the area occupied by a semiconductor device using the transistor is small. This reduces the size of the substrate, increasing the number of semiconductor devices that can be fabricated per substrate. In addition, the manufacturing cost is reduced because the semiconductor device is miniaturized. In addition, the channel length can be reduced, and a semiconductor device with improved functionality can be realized. This can provide the effects of increasing the operation speed and reducing power consumption. According to one embodiment of the present invention, a transistor including an oxide semiconductor can be miniaturized. It is possible to obtain various associated effects.

[0106] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0107] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the disclosed invention, which is different from that in the first embodiment, will be described. The structure and manufacturing process thereof will be described with reference to FIGS.

[0108] <Configuration Example of Semiconductor Device> The transistor 280 shown in FIG. 4 is an example of a semiconductor device. The stacking order of the transistor 280 corresponds to that of the transistor 180 shown in FIG. The difference in transistor 180 is that the second conductive layer 245a is A sidewall insulating layer 252a is provided on a region extending in the channel length direction from the second The conductive layer 245b of the region extending in the channel length direction from the end of the first conductive layer 242b The difference is that a sidewall insulating layer 252b is provided thereon.

[0109] The transistor 280 shown in FIG. 4 includes a second conductive layer 245a and a first conductive layer 245b disposed on a substrate 200. The source electrode is formed by stacking a first conductive layer 242a, a second conductive layer 245b and a first conductive layer 245c. 42b are laminated in order to form a drain electrode, and an insulating layer 243a is provided on the source electrode, An insulating layer 243b is provided on the drain electrode, and a The oxide semiconductor layer 244 and the gate insulating layer 245 are provided on the oxide semiconductor layer 244. 246 and a gate electrode 248 provided on the gate insulating layer 246.

[0110] In the transistor 280 shown in FIG. 4, the second conductive layer 245a is a) extending in the channel length direction, and the second conductive layer 245a and the oxide The second conductive layer 242 is in contact with at least the channel forming region of the semiconductor layer 244. 45b has a region extending in the channel length direction from the end of the first conductive layer 242b. The second conductive layer 245b is in contact with at least a channel formation region of the oxide semiconductor layer 244. is.

[0111] More specifically, the second conductive layer 245a is located at a channel length greater than the end of the first conductive layer 242a. It has an area extending toward the drain electrode in the direction of carrier flow. In addition, the second conductive layer 245b is disposed in a direction parallel to the source electrode 241 from the end of the first conductive layer 242b in the channel length direction. It has an elongated region toward the electrode.

[0112] Furthermore, the transistor 280 shown in FIG. 4 has a first conductive layer 245a. A sidewall insulating layer 252 is formed on a region extending from an end of the layer 242a in the channel length direction. a, and in the second conductive layer 245b, a channel length from the end of the first conductive layer 242b A sidewall insulating layer 252b is provided on the region extending in the direction. The insulating layer 252a is formed on at least the channel formation region of the oxide semiconductor layer 244 and the second conductive layer. The insulating layer 243a is provided in contact with the first conductive layer 245a, the first conductive layer 242a, and the insulating layer 243a. In the sidewall insulating layer 252a, at least a region in contact with the oxide semiconductor layer 244 is The sidewall insulating layer 252b is formed on the oxide semiconductor layer 2. At least the channel forming region of 44, the second conductive layer 245b, the first conductive layer 242b, and The sidewall insulating layer 252b is provided in contact with the insulating layer 243b. At least a part of the region in contact with the oxide semiconductor layer 244 has a curved shape.

[0113] Example of a process for manufacturing the transistor 280 Next, an example of a manufacturing process of the transistor 280 will be described with reference to FIGS. He explains.

[0114] First, a second conductive film 245 is formed on the substrate 200. Next, Then, a first conductive film 242 is formed, and an insulating film 243 is formed on the first conductive film 242 (FIG. 5(A)).

[0115] Here, the substrate 200 can be made of the same material as the substrate 100 shown in the first embodiment. The second conductive film 245 can be formed using the same material as the second conductive film 145 described in the first embodiment. The first conductive film 242 can be formed by using the material and the film forming method. The second conductive film can be formed using the same material and film formation method as the first conductive film shown in the embodiment 1. For details, the description in embodiment 1 can be referred to.

[0116] However, the etching selectivity between the first conductive film 242 and the second conductive film 245 is ensured. In this embodiment, a titanium nitride film is used as the second conductive film 245. A tungsten film or a molybdenum film is formed as the first conductive film 242. do.

[0117] Next, a mask is formed on the insulating film 243, and the insulating film 243 is etched using the mask. By this, the insulating layers 243a and 243b are formed. , wet etching or dry etching can be used, wet etching The insulating film can be etched into a desired shape by using a combination of dry etching and etchant. In order to achieve this, the etching conditions (etching gas, etching solution, etching time, etc.) are adjusted according to the material. However, the channel length (L) of the transistor is slightly changed. For fine processing, it is preferable to use dry etching. The etching gases used are, for example, sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3 ), trifluoromethane (CHF3), or other fluorine-containing gases, such as carbon tetrafluoride (C Mixtures of F4 and hydrogen can be used, and rare gases (helium (He), argon ( Ar), xenon (Xe), carbon monoxide, carbon dioxide, or the like may be added.

[0118] Next, the first conductive film 242 is etched using the mask used for etching the insulating film 243. By this, the first conductive layers 242a and 242b are formed (see FIG. 5(B)). When etching the first conductive film 242, etching with the second conductive film 245 is performed. The etching material used is one that ensures a selectivity of the first conductive film 242. Before the etching, the mask is removed, and the insulating layer 243a and the insulating layer 243b are used as a mask to perform the second etching. The first conductive film 242 may be etched.

[0119] In this embodiment, the etching gas for etching the first conductive film 242 is A mixture of carbon tetrafluoride (CF4), chlorine (Cl2) and oxygen (O2), A mixture of fluorine (CF4) and oxygen (O2), sulfur hexafluoride (SF6), chlorine (Cl2) and acid Mixture of sulfur hexafluoride (SF6) and oxygen (O2), or mixture of sulfur hexafluoride (SF6) and oxygen (O2) shall be used.

[0120] By providing the insulating layers 243a and 243b, the source electrode and the drain electrode to be formed later can be This makes it easier to control the contact area (contact area, etc.) between the silicon electrode and the oxide semiconductor layer. The resistance of the source and drain electrodes can be easily controlled, effectively suppressing the short channel effect. In addition, by providing the insulating layers 243a and 243b, The parasitic capacitance between the gate electrode and the source and drain electrodes is reduced. It is possible.

[0121] Next, an insulating layer 243a, 243b and the exposed second conductive film 245 are covered with an insulating film. The insulating film 252 is formed by a CVD method or a sputtering method (see FIG. 5C). The insulating film 252 can be formed using silicon oxide, silicon nitride, It is preferable to form the insulating film so as to contain silicon oxynitride, aluminum oxide, or the like. The insulating film 252 may have a single-layer structure or a multi-layer structure.

[0122] Next, the exposed area of ​​the second conductive film 245 (the first conductive layer 242a and the first conductive layer 242 Sidewall insulating layers 252a and 252b are formed on the region between the first and second insulating layers 252a and 252b (FIG. 5(D)). The sidewall insulating layers 252a and 252b are formed by applying a highly anisotropic etch to the insulating film 252. By performing a etching process, it is possible to form the film in a self-aligned manner. Dry etching is preferable as the etching method. For example, etching gas is tritium. Gases containing fluorine, such as fluoromethane (CHF3), can be used, and helium (H In addition, a rare gas such as argon (Ar) or argon (Ar) may be added. Therefore, reactive ion etching (RIE) is used, which applies a high frequency voltage to the substrate. preferable.

[0123] Next, the second conductive film 245 is selected using the sidewall insulating layers 252a and 252b as a mask. Selective etching is performed to form second conductive layers 245a and 245b (see FIG. 5(E)). This etching process results in the second conductive layer 245a and the first conductive layer 242a being stacked. The source electrode is a layered structure including a second conductive layer 245b and a first conductive layer 242b. The second conductive film 245 is etched without removing the sidewall insulating layer 2. Except for using 52a and 252b as masks, the same procedure as in the first embodiment is repeated using FIG. 2(C). This can be done in a similar manner to that shown.

[0124] The channel length (L) of the transistor 280 is determined by the distance between the bottom end of the second conductive layer 245a and the bottom end of the second conductive layer 245b. The channel length (L) is determined by the distance between the bottom end of the layer 245b and the bottom end of the transistor 2. Although it depends on the application of 80, for example, it is 10 nm to 1000 nm, preferably 20 nm or less. It can be up to 400 nm.

[0125] Note that in the manufacturing process of the transistor described in this embodiment, the sidewall insulating layer 252a The second conductive film 245 is etched using the second conductive film 252b. In the first conductive layer 245a, a region extending in the channel length direction from the end of the first conductive layer 242a The length of the channel in the direction of length (L S ) and the chamfer at the bottom surface of the sidewall insulating layer 252a. Similarly, in the second conductive layer 245b, the length of the first conductive layer 245b is approximately the same as that of the first conductive layer 245c. The length in the channel length direction of the region extending in the channel length direction from the end of the conductive layer 242b (L D ) The length of the sidewall insulating layer 252b in the channel length direction at the bottom surface thereof is approximately equal to that of the sidewall insulating layer 252b. The sidewall insulating layers 252a and 252b are formed by etching the insulating film 252. Since the L S ) or (L D ) is the thickness of the insulating film 252 In other words, by controlling the thickness of the insulating film 252, the transistor 280 For example, the channel length (L) of the transistor 280 can be finely adjusted. It is also possible to adjust the channel length (L) to be finer than the minimum processing dimension of the exposure equipment used to form the mask. Therefore, the desired channel length (L) of the transistor 280 and the first conductive layer 2 The thickness of the insulating film 252 is determined according to the resolution of the exposure device used to process the layers 42a and 242b. It is enough to set it.

[0126] Next, the insulating layers 243a, 243b and the sidewall insulating layers 252a, 252b are covered with The oxide semiconductor layer 24 is formed in contact with the second conductive layer 245a and the second conductive layer 245b. 4, and a gate insulating layer 246 is formed on the oxide semiconductor layer 244. A region over the insulating layer 246 overlapping with a region that will be a channel formation region of the transistor 280 A gate electrode 248 is formed in the region (see FIG. 5(F)).

[0127] The oxide semiconductor layer 244 is formed using a material and a method similar to those of the oxide semiconductor layer 144 described in Embodiment 1. The oxide semiconductor layer 244 can be formed by a thermal treatment (first For details, please refer to the description of the first embodiment. can be done.

[0128] The gate insulating layer 246 is formed of the same material and by the same method as the gate insulating layer 146 shown in the first embodiment. After the gate insulating layer 246 is formed, the insulating layer 246 is formed in an inert gas atmosphere. It is preferable to perform the heat treatment (second heat treatment) under a low temperature or oxygen atmosphere. For details, see Please refer to the description of embodiment 1.

[0129] The gate electrode 248 is formed by forming a conductive film on the gate insulating layer 246 and then selectively insulating the conductive film. The gate electrode 248 can be formed by selectively etching the gate electrode 248. It can be formed using the same material and method as the gate electrode 148 shown in the first embodiment.

[0130] The source electrode of the transistor 280 is connected to the first conductive layer 245a. The oxide semiconductor layer 244 The drain electrode is in contact with the first conductive layer 245b. The end of the region extending in the channel length direction beyond the end of 42b is in contact with the oxide semiconductor layer 244. In this manner, the second conductive layer 242a, 242b has a smaller thickness than the first conductive layers 242a, 242b. The layers 245a and 245b are in contact with the oxide semiconductor layer 244 at their ends, forming a source electrode In addition, the contact area between the drain electrode and the oxide semiconductor layer 244 can be reduced. Therefore, the contact resistance at the contact interface can be increased. Even if the channel length (L) of 80 is shortened, the electric field between the source electrode and the drain electrode is relaxed. In addition, the second conductive layer can be made to have a higher conductivity than the first conductive layer. By using a highly resistive material, the contact resistance can be increased more effectively. The technical idea of ​​the disclosed invention is to provide a highly resistive source electrode and a highly resistive drain electrode. Since the source electrode and the drain electrode are formed in the second conductive layer 2, It is necessary that the oxide semiconductor layer 244 is in contact with the oxide semiconductor layer 244 only at the ends of the second conductive layer 245a and the second conductive layer 245b. There is none.

[0131] In the above manner, the transistor 280 including the oxide semiconductor layer 244 can be manufactured. .

[0132] The channel length (L) of the transistor 280 in this embodiment is determined by the sidewall insulating layer 2 This can be precisely controlled by adjusting the thickness of the insulating film 252 for forming 52a and 252b. Therefore, by appropriately setting the thickness of the insulating film 252, The channel length (L) can be reduced, and the miniaturization of semiconductor devices can be easily achieved.

[0133] In the transistor 280 described in this embodiment, the first conductive layer 245a is In the region extending from the end of the layer 242a in the channel length direction and in the second conductive layer 245b In addition, a side wall is formed in a region extending from an end of the first conductive layer 242b in the channel length direction. The insulating layer 252a and the sidewall insulating layer 252b are provided. , the coverage of the oxide semiconductor layer 244 and the gate insulating layer 246 is improved, and the occurrence of connection failure and the like is prevented. It can be suppressed.

[0134] Further, in the transistor 280 described in this embodiment, the first conductive layer 245a is A region extending in the channel length direction from the end of the layer 242a is provided, and the second conductive layer 245 b is provided with a region extending in the channel length direction from the end of the first conductive layer 242b, and an oxide semiconductor The vicinity of the region of the conductor layer 244 that contacts the channel forming region is made into a high resistance region. By reducing the electric field between the source and drain electrodes, short-channel effects such as lowering the threshold voltage can be improved. The effects can be suppressed.

[0135] In this way, in one embodiment of the disclosed invention, problems associated with miniaturization can be solved. As a result, it becomes possible to make the transistor size sufficiently small. By making the transistor size sufficiently small, the area occupied by a semiconductor device using the transistor is small. This reduces the size of the substrate, increasing the number of semiconductor devices that can be fabricated per substrate. In addition, the manufacturing cost is reduced because the semiconductor device is miniaturized. In addition, the channel length can be reduced, and a semiconductor device with improved functionality can be realized. This can provide the effects of increasing the operation speed and reducing power consumption. According to one embodiment of the present invention, a transistor including an oxide semiconductor can be miniaturized. It is possible to obtain various associated effects.

[0136] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0137] (Embodiment 3) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIG. Here, an example of a memory device will be described. In order to indicate that the transistor includes an oxide semiconductor, the symbol OS is also used. There are cases.

[0138] In the semiconductor device shown in FIG. 6(A-1), a first wiring (1st Line) and a transistor The source electrode of the transistor 300 is electrically connected to the second wiring (2nd Line). The drain electrode of the transistor 300 is electrically connected to the third wiring (3 The RD Line and one of the source electrode and the drain electrode of the transistor 310 are connected to each other. The fourth line and the gate electrode of the transistor 310 are electrically connected to each other. The gate electrode of the transistor 300 and the The other of the source electrode or the drain electrode of the transistor 310 is electrically connected to one of the electrodes of the capacitor element 320. The fifth line and the other electrode of the capacitance element 320 are electrically connected to each other. are electrically connected.

[0139] Here, the transistor 310 is formed using the oxide semiconductor of Embodiment 1 or 2. A transistor using an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 310 is turned off, Therefore, the potential of the gate electrode of the transistor 300 can be maintained for a very long time. By including the capacitance element 320, the gate electrode of the transistor 300 This makes it easier to hold the charge applied to the layer and to read out the held information.

[0140] The transistor 300 is not particularly limited. From the viewpoint of this, for example, transistors using single crystal silicon, etc. It is preferable to use high speed transistors.

[0141] As shown in FIG. 6B, a configuration without the capacitor 320 is also possible. .

[0142] In the semiconductor device shown in FIG. 6A, the potential of the gate electrode of the transistor 300 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0143] First, writing and holding of information will be described. The transistor 310 is turned on by applying a potential to the transistor 310. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 300 and the capacitor 320. That is, a predetermined charge is applied to the gate electrode of the transistor 300. Here, we apply two different electric potentials to the charges (hereafter, the low electric potential charge). Charge Q L , the charge that gives the high potential is charge Q H Either of the following shall be given: It is also possible to apply three or more different potentials to the charge to improve the memory capacity. After that, the potential of the fourth wiring is set to a potential at which the transistor 310 is turned off. By turning off the transistor 310, the gate electrode of the transistor 300 The charge applied to is retained (retention).

[0144] Since the off-state current of the transistor 310 is extremely small, the gate electrode of the transistor 300 The charge is retained for a long period of time.

[0145] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 300 The second wiring has a different potential depending on the amount of charge held in the transistor electrode. If the transistor 300 is an n-channel type, then the gate electrode of the transistor 300 is connected to Q H is given The apparent threshold V th_H is connected to the gate electrode of transistor 300. L but Given the apparent threshold Vth_L This is because the temperature is lower than that of the The threshold voltage of the transistor 300 is the fifth threshold voltage required to turn the transistor 300 “on”. Therefore, the potential of the fifth wire is V th_H and V th_L By setting the potential V0 at the midpoint between For example, in writing, Q H If given, the fifth wire The potential of V0 (>V th_H ), transistor 300 is in the "on state." Q L is given, the potential of the fifth wire is V0( <V th_L ) even if The transistor 300 remains in the "off state." Therefore, the potential of the second wiring is not observed. The stored information can be read out.

[0146] When memory cells are arranged in an array, only the information of a desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and To prevent the information in other memory cells from being read, transistor 3 is placed between each memory cell. When 00 is connected in parallel, the first 1 of the memory cell that is not the object of reading is For the wiring of 5, the transistor 300 is in the "off state" regardless of the state of the gate electrode. That is, V th_H A smaller potential can be applied to each memory cell. When the transistors 300 are connected in series between the transistors, For the fifth wiring of the memory cell that does not have a gate electrode, the transistor 3 The potential at which V00 is in the "on state," that is, V th_LThe larger potential is applied to the fifth wire. should be given to

[0147] Next, rewriting of information will be described. Rewriting of information is the same as writing and storing the above information. That is, the potential of the fourth wiring is changed to the potential of the transistor 310 when the transistor 310 is turned on. This causes the potential of the third wiring ( A potential related to new information is applied to the gate electrode of the transistor 300 and the capacitor element 320. After that, the potential of the fourth wiring is set to a potential at which the transistor 310 is turned off. By turning off the transistor 310, the gate electrode of the transistor 300 , a charge related to new information is given.

[0148] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using high voltages, and the erase operation In other words, it is possible to suppress the decrease in the operating speed caused by the above-mentioned problem. It will be revealed.

[0149] The source electrode or drain electrode of the transistor 310 is the gate of the transistor 300. The flow cell is electrically connected to a gate electrode, and is used as a non-volatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 310 and the gate of the transistor 300 The portion to which the gate electrode is electrically connected is sometimes called the floating gate portion FG. When the transistor 310 is off, the floating gate portion FG is embedded in an insulator. It can be seen that the floating gate portion FG holds electric charge. The off-state current of the transistor 310 using the Since the resistance is less than 1 / 100,000 of that of the transistor 310, the floating It is possible to ignore the loss of charge stored in the gate FG. The transistor 310 using the semiconductor material is a non-volatile memory that can retain data even without power supply. It is possible to realize a storage device having a high degree of reliability.

[0150] For example, the off-current of transistor 310 at room temperature is 10 zA (1 zeptoampere). is 1×10 -21 A) or less, and the capacitance value of the capacitive element 320 is about 10 fF. is at least 10 4 It is possible to hold data for more than 100 seconds. It goes without saying that this varies depending on the resistor characteristics and capacitance value.

[0151] In this case, the gate problem pointed out in the conventional floating gate type transistor is There is no problem of deterioration of the gate insulating film (tunnel insulating film). This solves the problem of gate insulating film deterioration when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times it can be written. In addition, in the conventional floating gate type transistor, writing and erasing The high voltage required for this is also unnecessary.

[0152] The semiconductor device shown in FIG. 6(A-1) includes elements such as transistors that constitute the semiconductor device. It is possible to consider the circuit as including resistance and capacitance as shown in FIG. In FIG. 6(A-2), the transistor 300 and the capacitor 320 are resistors and R1 and C1 are considered to be composed of a capacitance and a The resistance and capacitance of the element 320. The resistance R1 is the resistance of the insulating layer constituting the capacitive element 320. R2 and C2 correspond to the resistances of the transistor 300. The resistance R1 is the capacitance of the gate insulating layer when the transistor 300 is in the on state. The capacitance C2 corresponds to the so-called gate capacitance (the capacitance between the gate electrode and the source electrode or is the capacitance formed between the drain electrode and the gate electrode, and between the gate electrode and the channel forming region. This corresponds to the capacitance value of the capacitance formed by the

[0153] The resistance between the source and drain electrodes of the transistor 310 when it is in the off state (actual If the effective resistance (also called ROS) of the transistor 310 is sufficiently small, In the condition, R1 and R2 are R1 ≧ ROS (R1 is ROS or more), R2 ≧ ROS (R 2 is greater than or equal to ROS), the charge retention period (which can also be called the information retention period) is The off-state current of the transistor 310 determines the off-state current of the transistor 310.

[0154] On the other hand, if this condition is not satisfied, the off-state current of the transistor 310 is not sufficiently small. In addition, it becomes difficult to ensure a sufficient retention period. The leakage current (for example, the leakage current generated between the source electrode and the gate electrode) is large. For this reason, the semiconductor device disclosed in this embodiment has the above-mentioned characteristics. It is desirable that the above conditions be satisfied.

[0155] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2 (C1 is equal to or greater than C2). By increasing C1, the potential of the floating gate FG is controlled by the fifth wiring. When the fifth wiring is connected to the fifth wiring (for example, when reading), the fluctuation of the potential of the fifth wiring can be suppressed to a low level. This is why.

[0156] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are formed by the gate insulating layer of the transistor 300 and the insulating layer of the capacitance element 320. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer, etc. It is desirable to appropriately set the above-mentioned relationship.

[0157] In the semiconductor device shown in this embodiment, the floating gate portion FG is a flash Same function as the floating gate of a floating gate type transistor such as memory However, the floating gate portion FG of this embodiment is a floating gate of a flash memory or the like. In flash memory, the control gate has fundamentally different characteristics. The voltage applied to the floating gate of the adjacent cell is high, so the effect of the potential on the floating gate of the adjacent cell is large. In order to prevent this from reaching the cell, it is necessary to maintain a certain amount of space between the cells. This is one of the factors that hinder the high integration of semiconductor devices. This is due to the fundamental principle of flash memory, which is to generate a tunnel current by applying a magnetic field. It is something.

[0158] In addition, due to the above-mentioned principle of flash memory, the deterioration of the insulating film progresses, limiting the number of times it can be rewritten. Kai (10 4 ~10 5 Another problem arises:

[0159] The semiconductor device according to the disclosed invention is a transistor including an oxide semiconductor. This operates in this way and does not use the principle of charge injection by tunnel current as described above. Unlike flash memory, high electric fields are not required to inject charges. Since there is no need to consider the effect of the high electric field caused by the control gate on adjacent cells, Integration becomes easier.

[0160] In addition, since it does not use charge injection by tunnel current, there is no cause for degradation of memory cells. In other words, it has higher durability and reliability than flash memory.

[0161] In addition, flash memory does not require a high electric field or large peripheral circuits (such as a boost circuit). This is an advantage over memory.

[0162] The relative dielectric constant εr1 of the insulating layer constituting the capacitance element 320 and the In the case where the relative dielectric constant εr2 of the insulating layer constituting the gate capacitance is made different from that of the capacitance element 32, 0 and the area S1 of the insulating layer constituting the gate capacitance in the transistor 300. The area S2 of the edge layer is 2·S2≧S1 (2·S2 is equal to or greater than S1) (preferably S2≧S1) It is easy to achieve C1 ≥ C2 (C1 is ≥ C2) while satisfying S2 ≥ S1. That is, it is easy to make C1 equal to or larger than C2 while keeping S1 small. Specifically, for example, the insulating layer constituting the capacitance element 320 is made of hafnium oxide or the like. A film made of igh-k material or a film made of high-k material such as hafnium oxide and oxide A laminated structure with a film made of a semiconductor material is adopted to set εr1 to 10 or more, preferably 15 or more, The insulating layer that constitutes the gate capacitance of the transistor 300 is made of silicon oxide. Using this, it is possible to make εr2=3~4.

[0163] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be further improved. Integration is possible.

[0164] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of positive hole-causing transistors instead of n-type transistors. It goes without saying that a p-type transistor can be used as the carrier.

[0165] As described above, in the semiconductor device according to one embodiment of the disclosed invention, A write transistor having a small leakage current (off-current) between drain electrodes, A non-transistor including a read transistor and a capacitor element using a semiconductor material different from that of the transistor It has a volatile memory cell.

[0166] The off-current of the write transistor is 100zA ( 1×10 -19 A) or less, preferably 10zA (1×10 -20 A) The following is more preferable: For example, 1zA (1×10 -21 A) or less. In normal silicon semiconductors, Although it is difficult to obtain a very low off-state current, it is possible to obtain one by processing an oxide semiconductor under appropriate conditions. This can be achieved in a transistor that has been oxidized. It is preferable to use a transistor including a semiconductor material.

[0167] Furthermore, transistors using oxide semiconductors have a small subthreshold swing (S value). Therefore, even if the mobility is relatively low, the switching speed can be sufficiently high. Therefore, by using the transistor as a writing transistor, This makes it possible to make the rise of the write pulse applied to the write gate FG extremely steep. In addition, since the off-current is small, the amount of charge held in the floating gate FG is small. In other words, a transistor including an oxide semiconductor can be used as a writing transistor. By using it as a transistor, information can be rewritten at high speed.

[0168] There is no limit to the off-state current of the readout transistor, but the readout speed is To achieve high speed, it is desirable to use transistors that operate at high speed. It is preferable to use transistors with a switching speed of 1 nanosecond or less as the transistors for the semiconductor device. It is nice.

[0169] Data is written to the memory cell by turning on the write transistor. One of the source electrode or the drain electrode of the writing transistor and the electrode of the capacitor element A floating gate electrode electrically connected to the gate electrode of the read transistor A potential is supplied to the gate FG, and then the write transistor is turned off. This is done by holding a certain amount of charge in the floating gate portion FG. Since the off-current of the transistor for loading is extremely small, the floating gate FG is The charge stored in the transistor is retained for a long time. If the off-current is, for example, substantially zero, The refresh operation required for the DRAM of This makes it possible to reduce the frequency of such repairs extremely (for example, once a month or once a year). This can significantly reduce the power consumption of the device.

[0170] It is also possible to directly rewrite information by writing it again to the memory cell. This eliminates the need for the erase operation required in flash memories, etc. It is possible to suppress the decrease in the operation speed caused by the erase operation. In addition, writing and erasing can be performed with conventional floating gate transistors. Since the high voltage required for the semiconductor device is not required, the power consumption of the semiconductor device is further reduced. The voltage applied to the memory cell according to the present embodiment (each terminal of the memory cell) The maximum value of the difference between the maximum and minimum potentials applied simultaneously to the When writing information, the voltage in one memory cell should be 5V or less, preferably 3V or less. be.

[0171] A memory cell arranged in a semiconductor device according to the disclosed invention includes a write transistor and It is sufficient to include at least a read transistor and a capacitance element. Therefore, the area per memory cell can be reduced to, for example, Small enough compared to SRAM, which requires six transistors per memory cell This allows memory cells to be arranged at high density in a semiconductor device. .

[0172] In addition, in conventional floating gate transistors, the gate insulating film (TFT) The gate insulating film (tunnel insulating film) deteriorates because electric charges move through it. However, in the memory cell according to one embodiment of the present invention, Since information is written by the switching operation of the transistor, This is because there is no theoretical limit to the number of times data can be written, and the rewrite resistance is high. For example, a memory cell according to one embodiment of the present invention has a ×10 9 No degradation of current-voltage characteristics was observed even after more than 1 billion writes. stomach.

[0173] Furthermore, a transistor using an oxide semiconductor as a writing transistor in a memory cell In the case of using an oxide semiconductor, the energy gap is generally large (for example, In-Ga - Zn-O system: 3.0 to 3.5 eV) Thermally excited carriers are extremely few, e.g. For example, no degradation is observed in the current-voltage characteristics of the memory cell even in a high-temperature environment of 150°C.

[0174] As a result of intensive research, the present inventors have found that a transistor using an oxide semiconductor can be Even at 150℃, the characteristics do not deteriorate and the off-current is extremely low at 100zA or less. In the present embodiment, it has been found that the above-mentioned excellent characteristic is The transistor having the above characteristic is applied as a write transistor of a memory cell, and The present invention provides a semiconductor device having excellent characteristics.

[0175] According to one embodiment of the disclosed invention, defects in a transistor including an oxide semiconductor can be suppressed. It is possible to achieve miniaturization while maintaining good characteristics. By using such transistors, it is possible to highly integrate the above-mentioned excellent memory devices. It is possible.

[0176] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0177] (Embodiment 4) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. This will be explained using Figure 8.

[0178] 7(A) and 7(B) are diagrams illustrating the semiconductor device shown in FIG. 6(A-1) (hereinafter, memory cell 40 FIG. 7(A) is a circuit diagram of a semiconductor device formed using a plurality of metal oxide semiconductor layers (also referred to as metal oxide semiconductor layers). 1 is a circuit diagram of a so-called NAND type semiconductor device in which memory cells 400 are connected in series. FIG. 7B shows a so-called NOR type semiconductor device in which memory cells 400 are connected in parallel. FIG.

[0179] The semiconductor device shown in FIG. 7A includes a source line SL, a bit line BL, a first signal line S1, and m A second signal line S2, m word lines WL, and a plurality of memory cells 400(1, 1) to 400( m, 1) are arranged in a vertical matrix of m rows by 1 column. However, the present invention is not limited to this configuration. By having n source lines SL and n bit lines BL, a memory with m vertical (rows) x n horizontal (columns) can be obtained. A configuration having a recell array may also be used.

[0180] In each memory cell 400, the gate electrode of transistor 300 and the gate electrode of transistor 310 One of the source electrode and the drain electrode of the capacitor 320 is electrically connected to one of the electrodes of the capacitor 320. Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 310 are connected to each other. The other of the gate electrodes is electrically connected to the second signal line S2 and the gate of the transistor 310. The electrode of the capacitor 320 is electrically connected to the word line WL. The other is electrically connected.

[0181] The source electrode of the transistor 300 in the memory cell 400 is connected to the adjacent memory cell The drain electrode of the transistor 300 in the memory cell 400 is electrically connected to the drain electrode of the transistor 300 in the memory cell 400. The drain electrode of the transistor 300 is connected to the drain electrode of the transistor of the adjacent memory cell 400. 300 is electrically connected to the source electrode of the memory cell 300. The drain of the transistor 300 in the memory cell 400 provided at one end of the The electrode is electrically connected to a bit line. The source electrode of the transistor 300 in the memory cell 400 at the other end is , and is electrically connected to the source line.

[0182] In the semiconductor device shown in FIG. 7A, writing and reading operations are performed row by row. The write operation is performed as follows: Transistor 3 is connected to the second signal line S2 of the row to be written. 10 is applied with a potential to turn on the transistor 310 of the row to be written. As a result, the gate electrodes of the transistors 300 in the specified row are connected to the first signal line S1. A potential is applied, and a predetermined charge is applied to the gate electrode of the transistor 300. In this manner, data can be written to the memory cells of a specified row.

[0183] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are In other words, regardless of the charge applied to the gate electrode of transistor 300, transistor 300 A potential is applied to turn on the transistors 300 in the row other than the row to be read out. Then, the gate of the transistor 300 is connected to the word line WL of the row to be read. The charge carried by the electrode determines whether the transistor 300 is in an on or off state. Then, a constant potential is applied to the source line SL, and a constant potential is applied to the bit line The read circuit (not shown) connected to the source line BL is set to an operating state. The transistors 300 between the bit line SL and the bit line BL are turned on except for the row to be read. Since the read operation is in the read state, the conductance between the source line SL and the bit line BL is The state of the transistor 300 in the row is determined by the state (on or off). The charge on the gate electrode of the transistor 300 in the row that is being read out causes the transistor Since the conductance is different, the potential of the bit line BL will be different accordingly. The potential of the bit line is read by the read circuit, and the memory cell of the specified row is Information can be read from the

[0184] The semiconductor device shown in FIG. 7B includes n source lines SL, bit lines BL, and a first signal line S1. m second signal lines S2 and word lines WL, and a plurality of memory cells 400(1, 1) to 4 00(m,n) are memory cells arranged in a matrix of m vertical (rows) x n horizontal (columns). The array 410 includes a gate electrode of each transistor 300 and a source electrode of each transistor 310. One of the source electrode or the drain electrode and one of the electrodes of the capacitor element 320 are electrically connected. The source line SL and the source electrode of the transistor 300 are electrically connected. The bit line BL and the drain electrode of the transistor 300 are electrically connected. In addition, the first signal line S1 and the other of the source electrode or the drain electrode of the transistor 310 are electrically connected, and the second signal line S2 and the gate electrode of the transistor 310 are electrically The word line WL and the other electrode of the capacitor element 320 are electrically connected to each other. Connected.

[0185] In the semiconductor device shown in FIG. 7B, writing and reading operations are performed row by row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The read operation is performed as follows. First, transistors 3 and 4 are connected to word lines WL other than the row to be read. The transistor 300 is turned off regardless of the charge applied to the gate electrode of the A potential is applied to the transistors 300 in the row other than the row to be read out, and the transistors 300 are turned off. The charge held by the gate electrode of the transistor 300 is applied to the word line WL of the row to be read. Therefore, a potential (readout potential) that selects the on or off state of the transistor 300 is generated. A constant potential is applied to the source line SL, and a constant potential is applied to the bit line BL. A read circuit (not shown) that reads the source line SL and the bit line BL is in an operating state. The conductance between the two rows is determined by the state (on or In other words, the gate of the transistor 300 in the row to be read is determined by the off state. The potential of the bit line BL varies depending on the charge carried by the bit electrode. The potential of the line is read by the read circuit, allowing data to be read from the memory cells of a specified row. It can be seen.

[0186] In the above description, the amount of information stored in each memory cell 400 is 1 bit. The structure of the memory device described in the embodiment is not limited to this. Three or more potentials may be provided to increase the amount of information stored in each memory cell 400. For example, when four types of potentials are applied to the gate electrode of the transistor 300, Each memory cell can hold two bits of information.

[0187] Next, an example of a read circuit that can be used in the semiconductor device shown in FIG. This will be explained using:

[0188] FIG. 8A shows a schematic diagram of a readout circuit. The readout circuit is made up of a transistor and a sensor. It has a differential amplifier circuit.

[0189] When reading, terminal A is connected to the bit line to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and the potential at terminal A is The position is controlled.

[0190] The memory cell 400 exhibits different resistance values ​​depending on the data stored therein. When the transistor 300 of the selected memory cell 400 is in an on state, the resistance is low. When the transistor 300 of the selected memory cell 400 is in an off state, the memory cell 400 is in a high resistance state. .

[0191] When the memory cell is in the high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense amplifier outputs a potential corresponding to the potential of terminal A. On the other hand, when the memory cell is in the low-resistance state , the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential corresponding to the potential of terminal A .

[0192] In this way, by using the read circuit, data can be read from the memory cell . Note that the read circuit of this embodiment is an example. Other circuits may be used. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref, a reference bit line may be connected .

[0193] Fig. 8(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+ ) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output . When the differential sense amplifier is used in the read circuit, one of Vin(+) and Vin(-) is connected to input terminal A, and the reference potential Vref is applied to the other of Vin(+) and Vin(-) .

[0194] Fig. 8(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the signal Sp is set to High, the signal Sn is set to Low, and the power supply potential (Vdd) is cut off. Then, the potentials for comparison are applied to V1 and V2. After that, the signal Sp is set to Low, the signal Sn is ​When a power supply potential (Vdd) is supplied as High, potentials V1in and V2in for performing comparison If V1in > V2in, the output of V1 is High and the output of V2 is Low If V1in < V2in, the output of V1 is Low and the output of V2 is High By using such a relationship, the difference between V1in and V2in can be amplified. When using this latch-type sense amplifier in a readout circuit, one of V1 and V2 is connected to terminal A and the output terminal via a switch and a reference potential Vref is applied to the other of V1 and V2.

[0195] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0196] (Embodiment 5) In this embodiment, the case of applying the semiconductor device described in Embodiments 1 to 4 to an electronic device will be described with reference to FIG. 9. In this embodiment, the case of applying the semiconductor device described in Embodiments 1 to 4 to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio playback device, etc.), a digital camera, a digital video camera, an electronic paper, and a television device (also referred to as a television or a television receiver) will be described.

[0197]

[0197] FIG. 9(A) is a notebook personal computer, which is composed of a housing 601, a housing 602, a display unit 603, a keyboard 604, etc. Fine semiconductor devices shown in the previous embodiments are provided in the housing 601 and the housing 602. Therefore, it is small-sized ​​​A notebook-type personal computer with features such as high speed operation and low power consumption has been realized. It will be revealed.

[0198] FIG. 9B shows a personal digital assistant (PDA), and a main body 611 includes a display unit 613 and an external An interface 615 and an operation button 614 are provided. The main body 611 includes a stylus 612 for operating the touch panel. The semiconductor device is miniaturized to reduce size, operate at high speed, consume less power, and A portable information terminal having the above features is realized.

[0199] FIG. 9C shows an electronic book 620 that uses electronic paper. The electronic book 620 is made up of a housing 621 and a housing 623. The display unit 625 is disposed in each of the housing 621 and the housing 623. A display unit 627 is provided. The housing 621 and the housing 623 are connected by a hinge 637. The housing 621 can be opened and closed around the shaft 637. , a power supply 631, operation keys 633, a speaker 635, etc. At least one of the 623 is provided with the miniaturized semiconductor device shown in the previous embodiment. This has resulted in the realization of e-books that are compact, fast to operate, and consume low power. can be.

[0200] FIG. 9D shows a mobile phone that is composed of two housings, a housing 640 and a housing 641. Furthermore, the housing 640 and the housing 641 slide and are deployed as shown in FIG. The device can be folded from one side to the other, making it possible to reduce the size of the device to make it suitable for carrying. The housing 641 includes a display panel 642, a speaker 643, a microphone 644, and operation keys. 645, pointing device 646, camera lens 647, external connection terminal 648, etc. The housing 640 also includes a solar cell 649 for charging the mobile phone, an external The external memory slot 650 is also provided. The antenna is built into the housing 641. At least one of the housing 640 and the housing 641 is provided with the miniaturized semiconductor device shown in the previous embodiment. The semiconductor device is provided. Therefore, the device has features such as small size, high speed operation, and low power consumption. A mobile phone equipped with the above-mentioned features is realized.

[0201] FIG. 9E shows a digital camera, which includes a main body 661, a display unit 667, an eyepiece unit 663, and an operation unit. It is composed of a switch 664, a display unit 665, a battery 666, etc. The miniaturized semiconductor device shown in the previous embodiment is provided in 61. This will realize a digital camera that has features such as small size, high speed operation, and low power consumption.

[0202] FIG. 9F shows a television device 670, which includes a housing 671, a display unit 673, and a stand 6 The television device 670 is operated by a switch provided in the housing 671. The operation can be performed by a touch panel or a remote control 680. The miniaturized semiconductor device shown in the above embodiment is mounted on the 680. This realizes a television device with features such as high speed operation and low power consumption.

[0203] As described above, the electronic device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This has resulted in electronic devices that are small, operate at high speed, and consume low power. is realized. EXAMPLES

[0204] In this example, characteristics of a semiconductor device according to one embodiment of the present invention were verified using a computer. The results will be described with reference to Figs. 10 to 13. Specifically, The characteristics of the transistors were compared. The software Atlas (manufactured by Silvaco Data Systems) was used.

[0205] The structure of a transistor used in the calculation is shown in FIG. The structure in which a part of the source electrode or drain electrode is extended is shown in FIG. 10(B). indicates a comparative structure (wherein the source electrode or drain electrode is not partially extended). It is.

[0206] The details of the transistor used in the calculation are described below. The transistor shown in FIG. , the first conductive layer 742a (material: titanium, thickness: 100 nm) and the second conductive layer 745a (Material: titanium nitride, thickness: optional) are laminated in this order to form a source electrode and a first conductive layer 742 b (material: titanium, thickness: 100 nm) and the second conductive layer 745b (material: titanium nitride, A drain electrode having a thickness of 1000 nm and an insulating layer 743 formed on the source electrode. a (material: silicon oxide, thickness: 100 nm) and an insulating layer 7 provided on the drain electrode. 43b (material: silicon oxide, thickness: 100 nm), insulating layer 743a and insulating layer 743 An oxide semiconductor layer 744 (material: In-Ga-Zn-O-based oxide semiconductor) provided on b , thickness: 10 nm), and a gate insulating layer 746 (material: : hafnium oxide, thickness: 10 nm) and a gate electrode provided on the gate insulating layer 746 748 (material: tungsten).

[0207] In the transistor illustrated in FIG. 10A, the second conductive layer 745a is 2a (i.e., the second conductive layer 74 The end of the second conductive layer 5a is closer to the channel forming region than the end of the first conductive layer 742a. An end portion of the layer 745a is in contact with the channel formation region of the oxide semiconductor layer 744. The second conductive layer 745b has a region extending in the channel length direction from the end of the first conductive layer 742b. (i.e., the end of the second conductive layer 745b is adjacent to the end of the first conductive layer 742b. The end portion of the second conductive layer 745b is adjacent to the oxide semiconductor layer 744. The channel forming region is in contact with the channel forming region.

[0208] The transistor shown in FIG. 10B has a source electrode formed of a conductive layer 752a (material: titanium nitride). A drain electrode (material: titanium nitride, thickness: 100 nm) and a conductive layer 752b are formed. A semiconductor layer 744 is formed on the source electrode and the drain electrode. (Material: In-Ga-Zn-O oxide semiconductor, thickness: 10 nm) and oxide semiconductor layer A gate insulating layer 746 (material: hafnium oxide, thickness: 10 nm) provided on 744; A gate electrode 748 (material: tungsten) is provided on the gate insulating layer 746. .

[0209] The difference between FIG. 10(A) and FIG. 10(B) is that the first conductive layer 745a is A region extending in the channel length direction from the end of the first conductive layer 742a and a region extending in the channel length direction from the end of the second conductive layer 745b In the present embodiment, the presence or absence of a region extending in the channel length direction from the end of the first conductive layer 742b, The presence or absence of an insulating layer on the electrode and an insulating layer on the drain electrode.

[0210] In FIG. 10A, the second conductive layer 745a is closer to the end of the first conductive layer 742a than the end of the first conductive layer 742a. The region extending in the channel length direction (the region made of the second conductive layer) is connected to the other region (the region made of the first conductive layer). The thickness of the electrode is small compared to the area of ​​the first conductive layer (the area of ​​the first conductive layer and the second conductive layer). The area of ​​the cross section perpendicular to the second conductor is smaller. Since resistance is inversely proportional to the cross-sectional area, The region of the layer 745a extending in the channel length direction from the end of the first conductive layer 742a is The second conductive layer 745b has a higher resistance than the other regions. The same can be said. In the following, in this embodiment, the first A region extending in the channel length direction from the end of the conductive layer 742a and a second conductive layer 745b A region extending in the channel length direction from the end of the first conductive layer 742b is called a high resistance region. (HRR:High-Resistance Region).

[0211] In FIG. 10A, the top of the source electrode is covered with an insulating layer 743a, and the drain The top of the source electrode is covered with an insulating layer 743b, so that the source electrode and the drain electrode are not directly connected to the oxide. The contact area of ​​the GaN semiconductor layer 744 is very small (here, the edge of the second conductive layer In other words, the source and drain electrodes are in contact with the channel formation region. This means that the resistance in the vicinity of the region is higher than that in other regions.

[0212] In the above-mentioned configuration (FIGS. 10(A) and 10(B)), the channel length L is changed to We investigated how the threshold voltage Vth of the transistor behaves. The six conditions are 20nm, 30nm, 50nm, 100nm, 200nm, and 400nm. was adopted.

[0213] In addition, the behavior of the threshold voltage Vth was investigated by changing the thickness of the second conductive layer. Four layer thicknesses were used: 3 nm, 10 nm, 50 nm, and 100 nm.

[0214] The voltage Vds between the source electrode and the drain electrode was set to 1 V. In addition, the channel of the high resistance region The length in the longitudinal direction was set to 0.3 μm.

[0215] The parameters used in the calculation are as follows: 1. In-Ga-Zn-O oxide semiconductor (material for oxide semiconductor layer) Band gap Eg: 3.15 eV, electron affinity χ: 4.3 eV, relative dielectric constant: 15, electron Mobility: 10cm 2 / Vs, effective density of states in the conduction band: 5×10 18 cm -3 2. Titanium nitride (source and drain electrode material) Work function φ M :3.9eV, resistivity ρ:2.2×10 -4 Ω cm 3. Hafnium oxide (gate insulating layer material) Dielectric constant: 15 4. Tungsten (gate electrode material) Work function φ M : 4.9 eV

[0216] The calculation results are shown in Figs. 11 to 13. In Figs. 11 to 13, the horizontal axis represents the channel length L( The vertical axis indicates the shift amount of the threshold voltage ΔVth (V). , ΔVth is calculated based on the threshold voltage when the channel length L is 400 nm.

[0217] 11(A), 11(B), 12(A) and 12(B) show the structure shown in FIG. 10(A). The calculation results are shown in FIG. 11(A) when the thickness of the second conductive layer is 100 nm, and in FIG. 11(B) , the thickness of the second conductive layer is 50 nm, FIG. 12(A) shows the thickness of the second conductive layer is 10 nm, FIG. FIG. 12(B) shows the case where the thickness of the second conductive layer is 3 nm. 3 shows the calculation results for the structure shown in FIG. 10(B).

[0218] By comparing FIG. 11(A), FIG. 11(B), FIG. 12(A) and FIG. 12(B), the second conductive It can be seen that the thinner the layer, the more the negative shift in the threshold voltage is suppressed. By comparing FIG. 1(A) with FIG. 13, when an insulating layer is provided to cover the source electrode and the drain electrode, It can be seen that the negative shift of Vth is suppressed in the case of By reducing the contact area between the drain electrode and the oxide semiconductor layer and increasing the resistance, This suggests that the channel effect can be suppressed.

[0219] Furthermore, from the above results, it is possible to determine whether the source electrode or drain electrode is in contact with the semiconductor layer. If the resistance of the electrode is high, the short channel effect can be suppressed. It is also possible.

[0220] From the above, the vicinity of the region in contact with the channel formation region of the source electrode and the drain electrode is made highly resistive. (Specifically, for example, the cross-sectional area of ​​a part of the source electrode and the drain electrode is reduced, An insulating layer is formed to cover the top of the source electrode and the drain electrode, and the contact area with the oxide semiconductor layer is It can be seen that by reducing the dc voltage, the negative shift of the threshold voltage is suppressed. This is due to the relaxation of the electric field strength between the source electrode and the drain electrode. In this manner, one embodiment of the disclosed invention can reduce short channel effects such as a decrease in threshold voltage. It was shown that the effects of acetylcholinesterase inhibitors can be suppressed. [Explanation of symbols]

[0221] 100 Substrates 142a First conductive layer 142b First conductive layer 143 Insulating Film 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 145 Conductive Film 145a Second conductive layer 145b second conductive layer 146 Gate Insulation Layer 148 Gate electrode 160 Transistors 170 Transistors 180 Transistors 190 Transistors 200 Substrates 242 Conductive Film 242a First conductive layer 242b First conductive layer 243 Insulating Film 243a Insulating layer 243b Insulating layer 244 Oxide semiconductor layer 245 Conductive Film 245a Second conductive layer 245b second conductive layer 246 Gate Insulation Layer 248 Gate electrode 252 Insulating film 252a Sidewall insulating layer 252b Sidewall insulating layer 280 Transistors 300 Transistors 310 Transistor 320 Capacitive element 400 memory cells 410 Memory Cell Array 601 Case 602 Case 603 Display section 604 Keyboard 611 Main unit 612 Stylus 613 Display section 614 Operation button 615 External Interface 620 e-books 621 Case 623 Case 625 Display section 627 Display section 631 Power supply 633 Operation Key 635 Speaker 637 Shaft 640 Case 641 Case 642 Display Panel 643 Speakers 644 Microphone 645 Operation Key 646 Pointing Device 647 Camera Lenses 648 External connection terminal 649 Solar Cells 650 external memory slot 661 Main unit 663 Eyepiece 664 Operation switch 665 Display section 666 Battery 667 Display section 670 Television Equipment 671 Case 673 Display section 675 Stand 680 Remote Controlled Device 742a First conductive layer 742b First conductive layer 743a Insulating layer 743b Insulating layer 744 Oxide semiconductor layer 745a Second conductive layer 745b Second conductive layer 746 Gate Insulation Layer 748 Gate electrode 752a conductive layer 752b Conductive layer

Claims

[Claim 1] an oxide semiconductor layer; a source electrode and a drain electrode having a region in contact with the oxide semiconductor layer; a gate electrode having a region overlapping the oxide semiconductor layer; a gate insulating layer having a region between the oxide semiconductor layer and the gate electrode, the source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extending in a channel length direction from an end of the first conductive layer.

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