Optical Module and Image Display Device

Abstract

To provide an optical module capable of reducing power consumption.SOLUTION: An optical module of the present invention includes: a first panel including a first light-emitting element, first power supply wiring and second power supply wiring; a second panel including a second light-emitting element having light emission luminance per unit current lower than that of the first light-emitting element, third power supply wiring and fourth power supply wiring; and a prism configured to synthesize first image light emitted from the first panel and second image light emitted from the second panel. A first potential difference is smaller than a second potential difference, the first potential difference being a difference between a potential applied to the first power supply wiring and a potential applied to the second power supply wiring, the second potential difference being a difference between a potential applied to the third power supply wiring and a potential applied to the fourth power supply wiring.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an optical module and an image display device.

Background Art

[0002] Patent Document 1 below discloses an optical module including three panels that emit image light of different colors and a prism that synthesizes the image light emitted from the three panels. As a panel that emits image light, a self-luminous electro-optical device such as an organic EL (Electro Luminescence) panel is known. This type of optical module has been conventionally used in image display devices such as head-mounted displays and projectors.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The optical module of Patent Document 1 above includes a panel having a light-emitting element that emits red light, a panel having a light-emitting element that emits green light, and a panel having a light-emitting element that emits blue light. Each light-emitting element has a different light-emitting luminance per unit current. Therefore, when the power supply potential difference between the power supply wiring on the anode side of the light-emitting element and the power supply wiring on the cathode side of the light-emitting element is the same in the three panels, the light-emitting luminance at the time of maximum current application is different for each panel. As a result, among the three panels, there has been a case where the steady driving power of a specific panel becomes larger than necessary.

Means for Solving the Problems

[0005] To solve the above problems, an optical module according to one aspect of the present invention includes a first light-emitting element, a first power supply wiring provided on one electrode side of the first light-emitting element, and a second power supply wiring provided on the other electrode side of the first light-emitting element. A first panel having a second light-emitting element having a lower emission luminance per unit current than the first light-emitting element, a third power supply wiring provided on one electrode side of the second light-emitting element, and a fourth power supply wiring provided on the other electrode side of the second light-emitting element. A second panel having a prism that synthesizes the first image light emitted from the first panel and the second image light emitted from the second panel, and a first potential difference that is a difference between the potential applied to the first power supply wiring and the potential applied to the second power supply wiring is smaller than a second potential difference that is a difference between the potential applied to the third power supply wiring and the potential applied to the fourth power supply wiring.

[0006] An image display device according to one aspect of the present invention includes the optical module according to one aspect of the present invention.

Brief Description of the Drawings

[0007]

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MODE FOR CARRYING OUT THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each of the following drawings, for the sake of clarity of each component, the scale of dimensions may be shown differently depending on the component.

[0009] 〔Optical Module〕 FIG. 1 is a schematic configuration diagram of an optical module 1 according to an embodiment of the present invention. As shown in FIG. 1, the optical module 1 includes a first panel 10G, a second panel 10B, a third panel 10R, and a dichroic prism 20 (prism).

[0010] The first panel 10G is a self-luminous electro-optical device that emits a first image light LG to the dichroic prism 20. The second panel 10B is a self-luminous electro-optical device that emits a second image light LB to the dichroic prism 20. The third panel 10R is a self-luminous electro-optical device that emits a third image light LR to the dichroic prism 20. A self-luminous electro-optical device is a device that generates light by itself using electrical energy supplied from the outside without requiring a light source such as a backlight. In the present embodiment, the first panel 10G, the second panel 10B, and the third panel 10R are, for example, organic EL panels.

[0011] The first panel 10G emits colored light corresponding to the green wavelength range as the first image light LG. The green wavelength range includes wavelengths from, for example, 495 nm to 570 nm. In the following description, the colored light corresponding to the green wavelength range may be referred to as "green light". The first panel 10G has a plurality of first pixels 11G. The plurality of first pixels 11G are arranged in a matrix on the substrate of the first panel 10G. The first pixel 11G emits green light. The first image light LG emitted from the first panel 10G includes green light emitted from each of the plurality of first pixels 11G.

[0012] The first panel 10G has a first pixel region 12G including a plurality of first pixels 11G arranged in a matrix, and a first non-pixel region 13G surrounding the first pixel region 12G. The first panel 10G is bonded to the green light incident surface 22 of the dichroic prism 20 through a first adhesive layer 40G having translucency in a state of facing the green light incident surface 22. In other words, the first panel 10G is arranged such that the first image light LG is incident perpendicularly to the green light incident surface 22.

[0013] The second panel 10B emits color light corresponding to the blue wavelength range as the second image light LB. The blue wavelength range includes wavelengths from, for example, 450 nm to 490 nm. In the following description, the color light corresponding to the blue wavelength range may be referred to as "blue light". The second panel 10B has a plurality of second pixels 11B. The plurality of second pixels 11B are arranged in a matrix on the substrate of the second panel 10B. The second pixel 11B emits blue light. The second image light LB emitted from the second panel 10B includes blue light emitted from each of the plurality of second pixels 11B.

[0014] The second panel 10B has a second pixel region 12B including a plurality of second pixels 11B arranged in a matrix, and a second non-pixel region 13B surrounding the second pixel region 12B. The second panel 10B is bonded to the blue light incident surface 21 of the dichroic prism 20 through a second adhesive layer 40B having translucency in a state of facing the blue light incident surface 21. In other words, the second panel 10B is arranged such that the second image light LB is incident perpendicularly to the blue light incident surface 21.

[0015] The third panel 10R emits color light corresponding to the red wavelength range as the third image light LR. The red wavelength range includes wavelengths from, for example, 610 nm to 680 nm. In the following description, the color light corresponding to the red wavelength range may be referred to as "red light". The third panel 10R has a plurality of third pixels 11R. The plurality of third pixels 11R are arranged in a matrix on the substrate of the third panel 10R. The third pixel 11R emits red light. The third image light LR emitted from the third panel 10R includes red light emitted from each of the plurality of third pixels 11R.

[0016] The third panel 10R has a third pixel region 12R including a plurality of third pixels 11R arranged in a matrix, and a third non-pixel region 13R surrounding the third pixel region 12R. The third panel 10R is bonded to the red light incident surface 23 of the dichroic prism 20 via a third adhesive layer 40R having translucency in a state of facing the red light incident surface 23. In other words, the third panel 10R is arranged so that the third image light LR is incident perpendicularly to the red light incident surface 23.

[0017] Each of the first image light LG, the second image light LB, and the third image light LR does not have polarization characteristics. That is, each of the first image light LG, the second image light LB, and the third image light LR is non-polarized light having no specific vibration direction. Note that non-polarized light, that is, light having no polarization characteristics, is not in a completely non-polarized state and includes a certain degree of polarization component, but is, for example, light having a degree of polarization within a range that is considered not to positively affect the optical performance with respect to optical components such as dichroic mirrors, for example, light having a degree of polarization of 20% or less.

[0018] The dichroic prism 20 is composed of a light-transmissive member having a quadrangular prism shape. Further, the quadrangular prism-shaped light-transmissive member is composed of a combination of four triangular prism-shaped light-transmissive members. The dichroic prism 20 has a blue light incident surface 21, a red light incident surface 23 facing the blue light incident surface 21, a green light incident surface 22 perpendicularly contacting the blue light incident surface 21 and the red light incident surface 23, and a combined light emission surface 24 facing the green light incident surface 22.

[0019] The dichroic prism 20 has a first dichroic mirror 25 having no polarization separation characteristics and a second dichroic mirror 26 having no polarization separation characteristics. The first dichroic mirror 25 and the second dichroic mirror 26 intersect at an angle of 90° with each other. The first dichroic mirror 25 reflects the second image light LB incident through the blue light incident surface 21 toward the combined light emission surface 24 and transmits the first image light LG incident through the green light incident surface 22 toward the combined light emission surface 24. The second dichroic mirror 26 reflects the third image light LR incident through the red light incident surface 23 toward the combined light emission surface 24 and transmits the first image light LG incident through the green light incident surface 22 toward the combined light emission surface 24. Due to the characteristics of these first dichroic mirror 25 and second dichroic mirror 26, the combined image light LW obtained by combining the first image light LG, the second image light LB, and the third image light LR is emitted from the combined light emission surface 24.

[0020] FIG. 2 is a schematic configuration diagram showing the overall configuration of the first panel 10G. Since the basic configurations of the first panel 10G, the second panel 10B, and the third panel 10R are common, the overall configuration of the first panel 10G will be described below as a representative. In FIG. 2, the horizontal direction of the first panel 10G is defined as the X direction, and the vertical direction of the first panel 10G is defined as the Y direction.

[0021] As shown in FIG. 2, a first pixel region 12G and a first non-pixel region 13G are provided on a first surface 14a of a substrate 14 of the first panel 10G. The first non-pixel region 13G includes a peripheral region 15 and a mounting region 16. The first pixel region 12G is a rectangular region in which a plurality of first pixels 11G are arranged in a matrix. In the first pixel region 12G, a plurality of scanning lines 31 extending in the X direction and a plurality of data lines 33 extending in the Y direction intersecting the X direction are provided. The first pixel 11G is a region corresponding to each intersection of the plurality of scanning lines 31 and the plurality of data lines 33. Therefore, the plurality of first pixels 11G are arranged in a matrix over the X direction and the Y direction. The first pixel 11G has a pixel circuit as shown in FIG. 3. The configuration of the pixel circuit included in the first pixel 11G will be described later.

[0022] The peripheral region 15 is a rectangular frame-shaped region surrounding the first pixel region 12G. Three driving circuits 35 are provided within the peripheral region 15. The three driving circuits 35 are circuits for driving each first pixel 11G within the first pixel region 12G. The driving circuit 35 includes two scanning line driving circuits 36 and a data line driving circuit 37. The first panel 10G is a circuit-integrated electro-optical device in which the driving circuit 35 is composed of active elements such as transistors formed on the first surface 14a of the substrate 14.

[0023] The mounting region 16 is provided on the side opposite to the first pixel region 12G with the peripheral region 15 interposed therebetween, that is, outside the peripheral region 15. A plurality of mounting terminals 39 are provided in the mounting region 16. Although details will be described later, video signals, power supply voltages, etc. necessary for driving the first pixels 11G of the first panel 10G are input to the mounting terminals 39.

[0024] FIG. 3 is an equivalent circuit diagram showing the configuration of the pixel circuit included in the first pixel 11G. Since the configurations of the pixel circuits each of the plurality of first pixels 11G has are common, hereinafter, the pixel circuit of the first pixel 11G located at the i-th row and j-th column will be described as an example. Here, "i" is a symbol generally indicating the row number where the first pixel 11G is arranged, and is an integer of 1 or more and m or less. "j" is a symbol generally indicating the column number where the first pixel 11G is arranged, and is an integer of 1 or more and n or less.

[0025] As shown in FIG. 3, the pixel circuit of the first pixel 11G includes a first selection transistor 51G, a first driving transistor 52G, a first light-emitting element 54G, and a first holding capacitor 55G. In the present embodiment, the first selection transistor 51G and the first driving transistor 52G are each a P-channel type MOS-FET.

[0026] The gate electrode of the first selection transistor 51G is electrically connected to the scanning line 31 of the i-th row. The other of the source / drain regions of the first selection transistor 51G is electrically connected to the data line 33 of the j-th column. One of the source / drain regions of the first selection transistor 51G is electrically connected to the gate electrode of the first driving transistor 52G and one electrode of the first holding capacitor 55G. The back gate of the first selection transistor 51G is electrically connected to the first power supply wiring 61G to which a power supply potential is applied.

[0027] The gate electrode of the first driving transistor 52G is electrically connected to one of the source / drain regions of the first selection transistor 51G and one electrode of the first holding capacitor 55G. One of the source / drain regions of the first driving transistor 52G is electrically connected to the first power supply wiring 61G. The other of the source / drain regions of the first driving transistor 52G is electrically connected to one electrode (anode) of the first light-emitting element 54G. The back gate of the first driving transistor 52G is electrically connected to the first power supply wiring 61G.

[0028] The first light-emitting element 54G is a light-emitting element that emits green light. The first light-emitting element 54G has a configuration in which a light-emitting layer is sandwiched between an anode and a cathode, and is, for example, an organic EL diode. One electrode (anode) of the first light-emitting element 54G is electrically connected to the other of the source / drain regions of the first driving transistor 52G. The other electrode (cathode) of the first light-emitting element 54G is electrically connected to a second power supply wiring 62G to which a power supply potential is applied.

[0029] The first holding capacitor 55G is a capacitor for holding the voltage between the gate electrode of the first driving transistor 52G and one of the source / drain regions of the first driving transistor 52G that is electrically connected to the first power supply wiring 61G. One electrode of the first holding capacitor 55G is electrically connected to one of the source / drain regions of the first selection transistor 51G and the gate electrode of the first driving transistor 52G. The other electrode of the first holding capacitor 55G is electrically connected to the first power supply wiring 61G. Note that, as the first holding capacitor 55G, a capacitor parasitic on the gate electrode of the first driving transistor 52G may be used, or a capacitor formed by sandwiching an insulating layer with different conductive layers in a silicon substrate may be used.

[0030] In the pixel circuit of the first pixel 11G configured as described above, when the scan signal GWR(i) supplied to the scan line 31 in the i-th row is at a high level, the first selection transistor 51G is in an off state. On the other hand, when the scan signal GWR(i) is at a low level, the first selection transistor 51G is in an on state. When the first selection transistor 51G is in an on state, a charging current flows through the first holding capacitor 55G according to the potential difference Vd1 between the potential of the data line 33 and the potential of the first power supply wiring 61G, and the first holding capacitor 55G is charged until the voltage between the electrodes of the first holding capacitor 55G becomes the potential difference Vd1.

[0031] When the gate potential of the first driving transistor 52G exceeds the threshold voltage of the first driving transistor 52G, a driving current flows from the first power supply wiring 61G to the second power supply wiring 62G via the first driving transistor 52G and the first light-emitting element 54G. The value of the driving current is controlled by the gate potential of the first driving transistor 52G. The voltage between the gate electrode of the first driving transistor 52G and one of the source / drain regions of the first driving transistor 52G electrically connected to the first power supply wiring 61G is equal to the voltage held by the first holding capacitor 55G, that is, the voltage between the electrodes of the first holding capacitor 55G. Therefore, by flowing a driving current having a current value corresponding to the voltage held by the first holding capacitor 55G through the first light-emitting element 54G, the first light-emitting element 54G emits green light having an intensity corresponding to the driving current.

[0032] As described above, the first panel 10G includes a first light-emitting element 54G that emits green light, which is color light corresponding to the green wavelength range, a first power supply wiring 61G provided on one electrode side (anode side) of the first light-emitting element 54G, and a second power supply wiring 62G provided on the other electrode side (cathode side) of the first light-emitting element 54G. Hereinafter, the difference between the power supply potential applied to the first power supply wiring 61G and the power supply potential applied to the second power supply wiring 62G may be referred to as the "first power supply potential difference (first potential difference)".

[0033] Although illustration is omitted, similar to the first pixel 11G, the pixel circuit of the second pixel 11B disposed in the second panel 10B includes a second selection transistor 51B, a second driving transistor 52B, a second light-emitting element 54B, and a second holding capacitor 55B. The second selection transistor 51B and the second driving transistor 52B are each a P-channel type MOS-FET.

[0034] The gate electrode of the second selection transistor 51B is electrically connected to the scanning line 31 in the i-th row. The other of the source / drain regions of the second selection transistor 51B is electrically connected to the data line 33 in the j-th column. One of the source / drain regions of the second selection transistor 51B is electrically connected to the gate electrode of the second driving transistor 52B and one of the electrodes of the second holding capacitor 55B. The back gate of the second selection transistor 51B is electrically connected to the third power supply wiring 61B to which a power supply potential is applied.

[0035] The gate electrode of the second driving transistor 52B is electrically connected to one of the source / drain regions of the second selection transistor 51B and one of the electrodes of the second holding capacitor 55B. One of the source / drain regions of the second driving transistor 52B is electrically connected to the third power supply wiring 61B. The other of the source / drain regions of the second driving transistor 52B is electrically connected to one of the electrodes (anode) of the second light-emitting element 54B. The back gate of the second driving transistor 52B is electrically connected to the third power supply wiring 61B.

[0036] The second light-emitting element 54B is a light-emitting element having a lower light-emitting luminance per unit current than the first light-emitting element 54G. The second light-emitting element 54B emits blue light, which is color light corresponding to the blue wavelength range. The second light-emitting element 54B has a configuration in which a light-emitting layer is sandwiched between an anode and a cathode, and is, for example, an organic EL diode. One of the electrodes (anode) of the second light-emitting element 54B is electrically connected to the other of the source / drain regions of the second driving transistor 52B. The other electrode (cathode) of the second light-emitting element 54B is electrically connected to the fourth power supply wiring 62B to which a power supply potential is applied.

[0037] The second holding capacitor 55B is a capacitor for holding the voltage between the gate electrode of the second driving transistor 52B and one of the source / drain regions of the second driving transistor 52B electrically connected to the third power supply wiring 61B. One electrode of the second holding capacitor 55B is electrically connected to one of the source / drain regions of the second selection transistor 51B and the gate electrode of the second driving transistor 52B. The other electrode of the second holding capacitor 55B is electrically connected to the third power supply wiring 61B. Note that, as the second holding capacitor 55B, a capacitor parasitic on the gate electrode of the second driving transistor 52B may be used, or a capacitor formed by sandwiching an insulating layer with different conductive layers in the silicon substrate may be used.

[0038] In the pixel circuit of the second pixel 11B configured as described above, when the second selection transistor 51B is in the on state, a charging current flows through the second holding capacitor 55B according to the potential difference Vd2 between the potential of the data line 33 and the potential of the third power supply wiring 61B, and thus the second holding capacitor 55B is charged until the voltage between the electrodes of the second holding capacitor 55B becomes the potential difference Vd2.

[0039] When the gate potential of the second driving transistor 52B exceeds the threshold voltage of the second driving transistor 52B, a driving current flows from the third power supply wiring 61B toward the fourth power supply wiring 62B through the second driving transistor 52B and the second light-emitting element 54B. The value of the driving current is controlled by the gate potential of the second driving transistor 52B. The voltage between the gate electrode of the second driving transistor 52B and one of the source / drain regions of the second driving transistor 52B electrically connected to the third power supply wiring 61B is equal to the voltage held by the second holding capacitor 55B, that is, the voltage between the electrodes of the second holding capacitor 55B. Therefore, a driving current having a current value corresponding to the voltage held by the second holding capacitor 55B flows through the second light-emitting element 54B, and thus the second light-emitting element 54B emits blue light having an intensity corresponding to the driving current.

[0040] As described above, the second panel 10B includes a second light-emitting element 54B that emits blue light with a lower light-emitting luminance per unit current than the first light-emitting element 54G, a third power supply wiring 61B provided on one electrode side (anode side) of the second light-emitting element 54B, and a fourth power supply wiring 62B provided on the other electrode side (cathode side) of the second light-emitting element 54B. Hereinafter, the difference between the power supply potential applied to the third power supply wiring 61B and the power supply potential applied to the fourth power supply wiring 62B may be referred to as the "second power supply potential difference (second potential difference)".

[0041] Although not shown, similar to the first pixel 11G and the second pixel 11B, the pixel circuit of the third pixel 11R disposed in the third panel 10R includes a third selection transistor 51R, a third driving transistor 52R, a third light-emitting element 54R, and a third holding capacitor 55R. The third selection transistor 51R and the third driving transistor 52R are each a P-channel type MOS-FET.

[0042] The gate electrode of the third selection transistor 51R is electrically connected to the scanning line 31 of the i-th row. The other of the source / drain regions of the third selection transistor 51R is electrically connected to the data line 33 of the j-th column. One of the source / drain regions of the third selection transistor 51R is electrically connected to the gate electrode of the third driving transistor 52R and one electrode of the third holding capacitor 55R. The back gate of the third selection transistor 51R is electrically connected to the fifth power supply wiring 61R to which a power supply potential is applied.

[0043] The gate electrode of the third driving transistor 52R is electrically connected to one of the source / drain regions of the third selection transistor 51R and one of the electrodes of the third holding capacitor 55R. One of the source / drain regions of the third driving transistor 52R is electrically connected to the fifth power supply wiring 61R. The other of the source / drain regions of the third driving transistor 52R is electrically connected to one of the electrodes (anode) of the third light-emitting element 54R. The back gate of the third driving transistor 52R is electrically connected to the fifth power supply wiring 61R.

[0044] The third light-emitting element 54R is a light-emitting element having a lower light-emitting luminance per unit current than the first light-emitting element 54G. The third light-emitting element 54R emits red light, which is color light corresponding to the red wavelength range. The third light-emitting element 54R has a configuration in which a light-emitting layer is sandwiched between an anode and a cathode, and is, for example, an organic EL diode. One of the electrodes (anode) of the third light-emitting element 54R is electrically connected to the other of the source / drain regions of the third driving transistor 52R. The other electrode (cathode) of the third light-emitting element 54R is electrically connected to the sixth power supply wiring 62R to which a power supply potential is applied.

[0045] The third holding capacitor 55R is a capacitor for holding the voltage between the gate electrode of the third driving transistor 52R and one of the source / drain regions of the third driving transistor 52R that is electrically connected to the fifth power supply wiring 61R. One of the electrodes of the third holding capacitor 55R is electrically connected to one of the source / drain regions of the third selection transistor 51R and the gate electrode of the third driving transistor 52R. The other electrode of the third holding capacitor 55R is electrically connected to the fifth power supply wiring 61R. Note that, as the third holding capacitor 55R, a capacitance parasitic on the gate electrode of the third driving transistor 52R may be used, or a capacitance formed by sandwiching an insulating layer with different conductive layers in the silicon substrate may be used.

[0046] In the pixel circuit of the third pixel 11R configured as described above, when the third selection transistor 51R is in the on state, a charging current flows through the third holding capacitor 55R according to the potential difference Vd3 between the potential of the data line 33 and the potential of the fifth power supply line 61R, and the third holding capacitor 55R is charged until the voltage between the electrodes of the third holding capacitor 55R becomes the potential difference Vd3.

[0047] When the gate potential of the third driving transistor 52R exceeds the threshold voltage of the third driving transistor 52R, a driving current flows from the fifth power supply line 61R to the sixth power supply line 62R through the third driving transistor 52R and the third light-emitting element 54R. The value of the driving current is controlled by the gate potential of the third driving transistor 52R. The voltage between the gate electrode of the third driving transistor 52R and one of the source / drain regions of the third driving transistor 52R electrically connected to the fifth power supply line 61R is equal to the voltage held by the third holding capacitor 55R, that is, the voltage between the electrodes of the third holding capacitor 55R. Therefore, by flowing a driving current having a current value corresponding to the voltage held by the third holding capacitor 55R through the third light-emitting element 54R, the third light-emitting element 54R emits red light having an intensity corresponding to the driving current.

[0048] As described above, the third panel 10R includes a third light-emitting element 54R that emits red light with a lower emission luminance per unit current than the first light-emitting element 54G, a fifth power supply line 61R provided on one electrode side (anode side) of the third light-emitting element 54R, and a sixth power supply line 62R provided on the other electrode side (cathode side) of the third light-emitting element 54R. Hereinafter, the difference between the power supply potential applied to the fifth power supply line 61R and the power supply potential applied to the sixth power supply line 62R may be referred to as the "third power supply potential difference (third potential difference)".

[0049] In the optical module 1 of the present embodiment, the area of the first light-emitting element 54G included in the first pixel 11G, the area of the second light-emitting element 54B included in the second pixel 11B, and the area of the third light-emitting element 54R included in the third pixel 11R are the same. Note that the area of each light-emitting element 54 can also be said to be the area of a region where the anode, the light-emitting layer, and the cathode overlap in a plan view, or the area of a region where the anode and the light-emitting layer are in contact with each other. Note that the polarity of the potential applied to each power supply wiring in the present invention is not limited. For example, the potential applied to the first power supply wiring may be a positive polarity and the potential applied to the second power supply wiring may be a negative polarity, or the potentials applied to both the first power supply wiring and the second power supply wiring may be a positive polarity or a negative polarity. In other words, if the power supply potential difference, which is the potential difference between the potential applied to the first power supply wiring and the potential applied to the second power supply wiring, is a predetermined potential difference, the polarity of the potential applied to each power supply wiring is not limited.

[0050] As shown in FIG. 4, one connector portion of the flexible flat cable 70G is connected to the mounting terminal 39 of the first panel 10G. As shown in FIG. 5, the other connector portion of the flexible flat cable 70G is connected to the first daughter substrate 80G. The first daughter substrate 80G is connected to the parent substrate 100 via the flexible flat cable 90G.

[0051] As shown in FIG. 5, similar to the first panel 10G, the mounting terminal 39 of the second panel 10B is connected to the second daughter substrate 80B via the flexible flat cable 70B. The second daughter substrate 80B is connected to the parent substrate 100 via the flexible flat cable 90B. Similar to the first panel 10G, the mounting terminal 39 of the third panel 10R is connected to the third daughter substrate 80R via the flexible flat cable 70R. The third daughter substrate 80R is connected to the parent substrate 100 via the flexible flat cable 90R.

[0052] The video signal S and the external power supply voltage VIN are input to the parent substrate 100. The parent substrate 100 has a signal processing circuit that separates the video signal S input from the outside into a green video signal SG for the first panel 10G, a blue video signal SB for the second panel 10B, and a red video signal SR for the third panel 10R. Also, the parent substrate 100 has a power supply circuit such as a DC / DC converter that generates a reference voltage VREF from the external power supply voltage VIN input from the outside.

[0053] The parent substrate 100 outputs the green video signal SG and the reference voltage VREF to the first daughter substrate 80G via the flexible flat cable 90G. The parent substrate 100 outputs the blue video signal SB and the reference voltage VREF to the second daughter substrate 80B via the flexible flat cable 90B. The parent substrate 100 outputs the red video signal SR and the reference voltage VREF to the third daughter substrate 80R via the flexible flat cable 90R.

[0054] The first daughter substrate 80G has a power supply circuit such as a DC / DC converter that generates the potential of the first power supply wiring 61G and the potential of the second power supply wiring 62G from the reference voltage VREF input from the parent substrate 100, and generates them so that the potential difference therebetween becomes the first power supply voltage VDG. The first daughter substrate 80G outputs the potential supplied to the first power supply wiring 61G and the potential supplied to the second power supply wiring 62G to the mounting terminal 39 of the first panel 10G via the flexible flat cable 70G. Also, the first daughter substrate 80G outputs the green video signal SG input from the parent substrate 100 to the mounting terminal 39 of the first panel 10G via the flexible flat cable 70G.

[0055] The first power supply potential difference of the first panel 10G is equal to the first power supply voltage VDG. In other words, the first power supply potential difference of the first panel 10G can be individually set to an arbitrary value by a power supply circuit such as a DC / DC converter provided in the first daughter substrate 80G.

[0056] In the first panel 10G, the scanning line driving circuit 36 and the data line driving circuit 37 generate a scanning signal supplied to the scanning line 31 and a potential applied to the data line 33 based on the green video signal SG input from the first daughter substrate 80G to the first panel 10G.

[0057] The second daughter substrate 80B has a power supply circuit such as a DC / DC converter that generates the potential of the third power supply wiring 61B and the potential of the fourth power supply wiring 62B from the reference voltage VREF input from the parent substrate 100, and generates the potential difference between them to be the second power supply voltage VDB. The second daughter substrate 80B outputs, via the flexible flat cable 70B, the potential supplied to the third power supply wiring 61B and the potential supplied to the fourth power supply wiring 62B to the mounting terminal 39 of the second panel 10B. Also, the second daughter substrate 80B outputs the blue video signal SB input from the parent substrate 100 to the mounting terminal 39 of the second panel 10B via the flexible flat cable 70B.

[0058] The second power supply potential difference of the second panel 10B is equal to the second power supply voltage VDB. In other words, the second power supply potential difference of the second panel 10B can be individually set to an arbitrary value by a power supply circuit such as a DC / DC converter provided in the second daughter substrate 80B.

[0059] In the second panel 10B, the scanning line driving circuit 36 and the data line driving circuit 37 generate a scanning signal supplied to the scanning line 31 and a potential applied to the data line 33 based on the blue video signal SB input from the second daughter substrate 80B to the second panel 10B.

[0060] The third daughter substrate 80R has a power supply circuit such as a DC / DC converter that generates the potential of the fifth power supply wiring 61R and the potential of the sixth power supply wiring 62R from the reference voltage VREF input from the parent substrate 100, and generates them such that the potential difference therebetween becomes the third power supply voltage VDR. The third daughter substrate 80R outputs, via the flexible flat cable 70R, the potential supplied to the fifth power supply wiring 61R and the potential supplied to the sixth power supply wiring 62R to the mounting terminal 39 of the third panel 10R. Further, the third daughter substrate 80R outputs the red video signal SR input from the parent substrate 100 to the mounting terminal 39 of the third panel 10R via the flexible flat cable 70R.

[0061] The third power supply potential difference of the third panel 10R is equal to the third power supply voltage VDR. In other words, the third power supply potential difference of the third panel 10R can be individually set to an arbitrary value by a power supply circuit such as a DC / DC converter provided in the third daughter substrate 80R.

[0062] In the third panel 10R, the scanning line driving circuit 36 and the data line driving circuit 37 generate a scanning signal supplied to the scanning line 31 and a potential applied to the data line 33 based on the red video signal SR input from the third daughter substrate 80R to the third panel 10R.

[0063] In the optical module 1 configured as described above, the first power supply potential difference of the first panel 10G, the second power supply potential difference of the second panel 10B, and the third power supply potential difference of the third panel 10R are individually set as follows.

[0064] FIG. 6 shows an example of the maximum monochromatic luminance of each panel 10 when the power supply potential difference of each panel 10 is set to the basic set value of 6.0 (V). As shown in FIG. 6, when the first power supply potential difference of the first panel 10G is set to 6.0 (V), the maximum luminance of the green first image light LG emitted from the first panel 10G is, as an example, 34880 (cd / m 2) That is, when the second power potential difference of the second panel 10B is set to 6.0 (V), the maximum luminance of the blue second image light LB emitted from the second panel 10B is, as an example, 2640 (cd / m 2 ) That is, when the third power potential difference of the third panel 10R is set to 6.0 (V), the maximum luminance of the red third image light LR emitted from the third panel 10R is, as an example, 6000 (cd / m 2 ) That is.

[0065] FIG. 11 is a characteristic diagram showing the relationship between the current density and the emission luminance for each of the first light-emitting element 54G, the second light-emitting element 54B, and the third light-emitting element 54R. As shown in FIG. 11, the emission luminance per unit current of the second light-emitting element 54B is lower than that of the first light-emitting element 54G. The emission luminance per unit current of the third light-emitting element 54R is lower than that of the first light-emitting element 54G and higher than that of the second light-emitting element 54B. Therefore, as shown in FIG. 6, when the power potential differences of the respective panels 10 are set to the same value, the emission luminance at the time of maximum current application differs for each panel. Specifically, the maximum luminance of the second panel 10B becomes lower than the maximum luminance of the first panel 10G, and the maximum luminance of the third panel 10R becomes lower than the maximum luminance of the first panel 10G and higher than the maximum luminance of the second panel 10B. As a result, when the power potential differences of the respective panels 10 are set to the same value, there is a case where the steady driving power of a specific panel among the three panels 10 becomes larger than necessary.

[0066] In the optical module 1 of the present embodiment, in order to ensure a color reproducibility equivalent to that of a general display, the target luminance of each panel 10 is set so that the luminance ratio of RGB approaches "R:G:B = 3:6:1" with the maximum luminance shown in FIG. 6 as the upper limit. Here, "R" represents the luminance of the red third image light LR emitted from the third panel 10R. "G" represents the luminance of the green first image light LG emitted from the first panel 10G. "B" represents the luminance of the blue second image light LB emitted from the second panel 10B. Note that controlling the RGB luminance ratio to approach "R:G:B = 3:6:1" is just an example, and the RGB luminance ratio is not limited to this.

[0067] As shown in FIG. 7, three patterns can be considered as the setting patterns of the target luminance of each panel 10. The first setting pattern is a pattern in which the target luminance of each panel 10 is set so that the RGB luminance ratio approaches "R:G:B = 3:6:1" based on the maximum luminance of the third panel 10R. The second setting pattern is a pattern in which the target luminance of each panel 10 is set so that the RGB luminance ratio approaches "R:G:B = 3:6:1" based on the maximum luminance of the first panel 10G. The third setting pattern is a pattern in which the target luminance of each panel 10 is set so that the RGB luminance ratio approaches "R:G:B = 3:6:1" based on the maximum luminance of the second panel 10B.

[0068] Looking at the first setting pattern based on the maximum luminance of the third panel 10R in FIG. 7, the maximum luminance of the first panel 10G is higher than the target luminance. Therefore, if the first power potential difference of the first panel 10G is set to 6.0 (V), an excessive first power voltage VDG with respect to the target luminance of the first panel 10G will be supplied to the first panel 10G. Similarly, looking at the first setting pattern in FIG. 7, the maximum luminance of the second panel 10B is also higher than the target luminance. Therefore, if the second power potential difference of the second panel 10B is set to 6.0 (V), an excessive second power voltage VDB with respect to the target luminance of the second panel 10B will be supplied to the second panel 10B.

[0069] Therefore, in the optical module 1 of the present embodiment, when using the first setting pattern based on the maximum luminance of the third panel 10R, the first power potential difference is set to the minimum value that can ensure the target luminance of the first panel 10G, and the second power potential difference is set to the minimum value that can ensure the target luminance of the second panel 10B.

[0070] FIG. 8 shows the relationship between each power supply potential difference set to a value that can ensure the target luminance of each panel 10 and the maximum luminance of each panel 10 obtained by the set power supply potential difference when using the first setting pattern based on the maximum luminance of the third panel 10R. As shown in FIG. 8, in the optical module 1 of the present embodiment, when using the first setting pattern, the first power supply potential difference of the first panel 10G is set to 5.5 (V), the second power supply potential difference of the second panel 10B is set to 5.9 (V), and the third power supply potential difference of the third panel 10R is set to 6.0 (V).

[0071] In this case, the first power supply voltage VDG (the first power supply potential difference) is supplied from the first sub-board 80G to the first panel 10G through each power supply wiring so as to be 5.5 (V), and the second power supply voltage VDB (the second power supply potential difference) is supplied from the second sub-board 80B to the second panel 10B through each power supply wiring so as to be 5.9 (V), and the third power supply voltage VDR (the third power supply potential difference) is supplied from the third sub-board 80R to the third panel 10R through each power supply wiring so as to be 6.0 (V). As a result, as shown in FIG. 8, the maximum luminance above the target luminance is obtained for each of the panels 10, and the target luminance of each panel 10 set so that the luminance ratio of RGB approaches "R:G:B = 3:6:1" is ensured.

[0072] As described above, when using the first setting pattern based on the maximum luminance of the third panel 10R, while ensuring the target luminance of each panel 10 set so that the luminance ratio of RGB approaches "R:G:B = 3:6:1", by setting the first power supply potential difference of the first panel 10G and the second power supply potential difference of the second panel 10B to the minimum values, it is possible to reduce the power consumption of the first panel 10G and the second panel 10B compared to the third panel 10R while optimizing the white balance.

[0073] When using the first setting pattern, the first power potential difference of the first panel 10G is smaller than the second power potential difference of the second panel 10B and smaller than the third power potential difference of the third panel 10R. Therefore, the power consumption of the first panel 10G is smaller than that of the second panel 10B and the third panel 10R. Also, the second power potential difference of the second panel 10B is smaller than the third power potential difference of the third panel 10R and larger than the first power potential difference of the first panel 10G. Therefore, the power consumption of the second panel 10B is smaller than that of the third panel 10R and larger than that of the first panel 10G. When using the first setting pattern, the maximum luminance of the third panel 10R is higher than the maximum luminance of the second panel 10B and lower than the maximum luminance of the first panel 10G.

[0074] In FIG. 7, focusing on the second setting pattern with the maximum luminance of the first panel 10G as a reference, the maximum luminance with respect to the second panel 10B becomes lower than the target luminance. Therefore, if the second power potential difference of the second panel 10B is set to 6.0 (V), an insufficient second power supply voltage VDB for the target luminance of the second panel 10B will be supplied to the second panel 10B. Similarly, in FIG. 7, focusing on the second setting pattern, the maximum luminance with respect to the third panel 10R also becomes lower than the target luminance. Therefore, if the third power potential difference of the third panel 10R is set to 6.0 (V), an insufficient third power supply voltage VDR for the target luminance of the third panel 10R will be supplied to the third panel 10R.

[0075] Therefore, in the optical module 1 of the present embodiment, when using the second setting pattern with the maximum luminance of the first panel 10G as a reference, the second power potential difference is set to a value larger than the basic setting value to ensure the target luminance of the second panel 10B, and the third power potential difference is set to a value larger than the basic setting value to ensure the target luminance of the third panel 10R.

[0076] FIG. 9 shows the relationship between each power supply potential difference set to a value that can ensure the target luminance of each panel 10 and the maximum luminance of each panel 10 obtained by the set power supply potential difference when using the second setting pattern based on the maximum luminance of the first panel 10G. As shown in FIG. 9, in the optical module 1 of the present embodiment, when using the second setting pattern, the first power supply potential difference of the first panel 10G is set to 6.0 (V), the second power supply potential difference of the second panel 10B is set to 6.3 (V), and the third power supply potential difference of the third panel 10R is set to 6.4 (V).

[0077] In this case, the first power supply voltage VDG (the first power supply potential difference) is supplied from the first sub-board 80G to the first panel 10G through each power supply wiring so as to be 6.0 (V), and the second power supply voltage VDB (the second power supply potential difference) is supplied from the second sub-board 80B to the second panel 10B through each power supply wiring so as to be 6.3 (V), and the third power supply voltage VDR (the third power supply potential difference) is supplied from the third sub-board 80R to the third panel 10R through each power supply wiring so as to be 6.4 (V). As a result, as shown in FIG. 9, the maximum luminance equal to or higher than the target luminance is obtained for each of the panels 10, and the target luminance of each panel 10 set so that the luminance ratio of RGB approaches "R:G:B = 3:6:1" is ensured.

[0078] Thus, when using the second setting pattern based on the maximum luminance of the first panel 10G, while ensuring the target luminance of each panel 10 set so that the luminance ratio of RGB approaches "R:G:B = 3:6:1", by setting the second power supply potential difference of the second panel 10B and the third power supply potential difference of the third panel 10R to values larger than the basic set values, it is possible to reduce the power consumption of the first panel 10G and the second panel 10B compared to the third panel 10R while optimizing the white balance.

[0079] When using the second setting pattern, similar to the case of using the first setting pattern, the first power potential difference of the first panel 10G is smaller than the second power potential difference of the second panel 10B and smaller than the third power potential difference of the third panel 10R. Therefore, the power consumption of the first panel 10G is smaller than that of the second panel 10B and the third panel 10R. Also, the second power potential difference of the second panel 10B is smaller than the third power potential difference of the third panel 10R and larger than the first power potential difference of the first panel 10G. Therefore, the power consumption of the second panel 10B is smaller than that of the third panel 10R and larger than that of the first panel 10G. Even when using the second setting pattern, the maximum luminance of the third panel 10R is higher than the maximum luminance of the second panel 10B and lower than the maximum luminance of the first panel 10G.

[0080] Also, as shown in FIG. 8, while the maximum luminance of white when using the first setting pattern is about 20000 (cd / m 2 ), as shown in FIG. 9, the maximum luminance of white when using the second setting pattern increases to about 58000 (cd / m 2 ). Therefore, by using the second setting pattern as compared with the first setting pattern, high luminance of the optical module 1 can be realized.

[0081] Focusing on the third setting pattern with the maximum luminance of the second panel 10B as a reference in FIG. 7, the maximum luminance with respect to the first panel 10G becomes higher than the target luminance. Therefore, if the first power potential difference of the first panel 10G is set to 6.0 (V), an excessive first power voltage VDG with respect to the target luminance of the first panel 10G will be supplied to the first panel 10G. Also, focusing on the third setting pattern in FIG. 7, the maximum luminance with respect to the third panel 10R becomes lower than the target luminance. Therefore, if the third power potential difference of the third panel 10R is set to 6.0 (V), an insufficient third power voltage VDR with respect to the target luminance of the third panel 10R will be supplied to the third panel 10R.

[0082] Therefore, in the optical module 1 of the present embodiment, when using the third setting pattern based on the maximum luminance of the second panel 10B, the first power supply potential difference is set to the minimum value that can ensure the target luminance of the first panel 10G, and the third power supply potential difference is set to a value larger than the basic setting value to ensure the target luminance of the third panel 10R.

[0083] FIG. 10 shows the relationship between each power supply potential difference set to a value that can ensure the target luminance of each panel 10 and the maximum luminance of each panel 10 obtained by the set power supply potential differences when using the third setting pattern based on the maximum luminance of the second panel 10B. As shown in FIG. 10, in the optical module 1 of the present embodiment, when using the third setting pattern, the first power supply potential difference of the first panel 10G is set to 5.6 (V), the second power supply potential difference of the second panel 10B is set to 6.0 (V), and the third power supply potential difference of the third panel 10R is set to 6.1 (V).

[0084] In this case, the first power supply voltage VDG (the first power supply potential difference) is supplied from the first sub-board 80G to the first panel 10G through each power supply wiring so as to be 5.6 (V), the second power supply voltage VDB (the second power supply potential difference) is supplied from the second sub-board 80B to the second panel 10B through each power supply wiring so as to be 6.0 (V), and the third power supply voltage VDR (the third power supply potential difference) is supplied from the third sub-board 80R to the third panel 10R through each power supply wiring so as to be 6.1 (V). As a result, as shown in FIG. 10, the maximum luminance above the target luminance is obtained for each of the panels 10, and the target luminance of each panel 10 is set so that the luminance ratio of RGB approaches "R:G:B = 3:6:1" is ensured.

[0085] Thus, when using the third setting pattern based on the maximum luminance of the second panel 10B, while ensuring the target luminance of each panel 10 is set such that the luminance ratio of RGB approaches "R:G:B = 3:6:1", the first power potential difference of the first panel 10G is set to the minimum value, and the third power potential difference of the third panel 10R is set to a value larger than the basic setting value, thereby optimizing the white balance while reducing the power consumption of the first panel 10G and the second panel 10B compared to the third panel 10R.

[0086] Similar to the case of using the first setting pattern, when using the third setting pattern, the first power potential difference of the first panel 10G is smaller than the second power potential difference of the second panel 10B and smaller than the third power potential difference of the third panel 10R. Therefore, the power consumption of the first panel 10G is smaller than that of the second panel 10B and the third panel 10R. Also, the second power potential difference of the second panel 10B is smaller than the third power potential difference of the third panel 10R and larger than the first power potential difference of the first panel 10G. Therefore, the power consumption of the second panel 10B is smaller than that of the third panel 10R and larger than that of the first panel 10G. Even when using the third setting pattern, the maximum luminance of the third panel 10R is higher than the maximum luminance of the second panel 10B and lower than the maximum luminance of the first panel 10G.

[0087] Also, as shown in FIG. 8, the maximum luminance of white when using the first setting pattern is about 20000 (cd / m 2 ), whereas, as shown in FIG. 10, the maximum luminance of white when using the third setting pattern increases to about 26000 (cd / m 2 ). Therefore, by using the third setting pattern, the high luminance of the optical module 1 can be realized compared to the first setting pattern. As described above, among the three setting patterns, by using the second setting pattern, the effect of increasing the luminance of the optical module 1 can be obtained most significantly.

[0088] As described above, in the optical module 1 of the present embodiment, by individually setting the first power supply potential difference of the first panel 10G, the second power supply potential difference of the second panel 10B, and the third power supply potential difference of the third panel 10R to values that can ensure the target luminance of each panel 10, even when light-emitting elements 54 with different light-emitting luminances per unit current are provided in each panel 10, while optimizing the white balance, it is possible to reduce the power consumption of the first panel 10G and the second panel 10B compared to the third panel 10R.

[0089] 〔Image display device including an optical module〕 Hereinafter, an image display device including the optical module 1 of the above embodiment will be described. FIG. 12 is an explanatory diagram of a head-mounted display device (head-mounted display) 1000 which is an example of an image display device including the optical module 1. FIG. 13 is a perspective view schematically showing the configuration of the optical system of the virtual image display unit 1010 shown in FIG. 12. FIG. 14 is an explanatory diagram showing the optical path of the optical system shown in FIG. 13.

[0090] As shown in FIG. 12, the head-mounted display device 1000 is configured as a see-through type eyeglass display and has a frame 1110 provided with temples 1111 and 1112 on the left and right. In the head-mounted display device 1000, the virtual image display unit 1010 is supported by the frame 1110 and causes the user to recognize the image emitted from the virtual image display unit 1010 as a virtual image. In the present embodiment, the head-mounted display device 1000 includes a left-eye display unit 1101 and a right-eye display unit 1102 as the virtual image display unit 1010. The left-eye display unit 1101 and the right-eye display unit 1102 have the same configuration and are arranged symmetrically left and right.

[0091] In the following description, the left-eye display unit 1101 will be mainly described, and the description of the right-eye display unit 1102 will be omitted. As shown in FIGS. 13 and 14, in the head-mounted display device 1000, the left-eye display unit 1101 includes an optical module 1 and a light guide system 1030 that guides the combined image light LW emitted from the optical module 1 to the emission unit 1058. A projection lens system 1070 is disposed between the optical module 1 and the light guide system 1030. The combined image light LW emitted from the optical module 1 enters the light guide system 1030 through the projection lens system 1070. The projection lens system 1070 is composed of one collimating lens having a positive power.

[0092] The light guide system 1030 includes a light-transmissive incident portion 1040 into which the combined image light LW enters, and a light-transmissive light guide portion 1050 having one end 1051 side connected to the incident portion 1040. In the present embodiment, the incident portion 1040 and the light guide portion 1050 are formed of an integral light-transmissive member.

[0093] The incident portion 1040 includes an incident surface 1041 into which the combined image light LW emitted from the optical module 1 enters, and a reflecting surface 1042 that reflects the combined image light LW incident from the incident surface 1041 between the incident surface 1041. The incident surface 1041 is formed of a plane, an aspherical surface, a free-form surface, or the like, and faces the optical module 1 through the projection lens system 1070. The projection lens system 1070 is obliquely disposed such that the distance between the projection lens system 1070 and the end 1412 of the incident surface 1041 is wider than the distance between the projection lens system 1070 and the end 1411 of the incident surface 1041.

[0094] Although a reflective film is not formed on the incident surface 1041, light incident at an incident angle equal to or greater than the critical angle is totally reflected. Therefore, the incident surface 1041 has light transmissivity and light reflectivity. The reflecting surface 1042 is formed of a surface facing the incident surface 1041, and is obliquely disposed such that the end 1422 is spaced apart from the incident surface 1041 more than the end 1421 of the incident surface 1041. Therefore, the incident portion 1040 has a substantially triangular shape. The reflecting surface 1042 is formed of a plane, an aspherical surface, a free-form surface, or the like. The reflecting surface 1042 has a configuration in which a reflective metal layer mainly composed of aluminum, silver, magnesium, chromium, or the like is formed.

[0095] The light guide part 1050 includes a first surface 1056 (first reflection surface) extending from one end 1051 toward the other end 1052 side, a second surface 1057 (second reflection surface) facing the first surface 1056 in parallel and extending from the one end 1051 side toward the other end 1052 side, and an emission part 1058 provided at a portion spaced apart from the incident part 1040 of the second surface 1057. The first surface 1056 and the reflection surface 1042 of the incident part 1040 are continuous via an inclined surface 1043. The thicknesses of the first surface 1056 and the second surface 1057 are thinner than that of the incident part 1040. The first surface 1056 and the second surface 1057 totally reflect light incident at an incident angle equal to or greater than the critical angle based on the refractive index difference between the light guide part 1050 and the outside (air). For this reason, no reflection film is formed on the first surface 1056 and the second surface 1057.

[0096] The emission part 1058 is configured in a part on the second surface 1057 side in the thickness direction of the light guide part 1050. In the emission part 1058, a plurality of partial reflection surfaces 1055 inclined obliquely with respect to the normal direction to the second surface 1057 are arranged in parallel with each other. The emission part 1058 is a part of the second surface 1057 that overlaps with the plurality of partial reflection surfaces 1055 and is a region having a predetermined width in the extending direction of the light guide part 1050. The plurality of partial reflection surfaces 1055 are each composed of a dielectric multilayer film. Further, at least one of the plurality of partial reflection surfaces 1055 may be a composite layer of a dielectric multilayer film and a reflective metal layer (thin film) mainly composed of aluminum, silver, magnesium, chromium, or the like. When the partial reflection surface 1055 includes a metal layer, there is an effect of increasing the reflectance of the partial reflection surface 1055, or an effect of optimizing the incident angle dependence and polarization dependence of the transmittance and reflectance of the partial reflection surface 1055. Note that the emission part 1058 may be in a mode in which an optical element such as a diffraction grating or a hologram is provided.

[0097] In the head-mounted display device 1000 configured as described above, the composite image light LW composed of parallel light incident from the incident portion 1040 is refracted at the incident surface 1041 and travels toward the reflection surface 1042. Next, the composite image light LW is reflected by the reflection surface 1042 and travels back toward the incident surface 1041. At this time, since the composite image light LW enters the incident surface 1041 at an incident angle equal to or greater than the critical angle, it is reflected toward the light guide portion 1050 at the incident surface 1041 and travels toward the light guide portion 1050. Note that in the incident portion 1040, the composite image light LW, which is parallel light, is configured to enter the incident surface 1041. However, the incident surface 1041 and the reflection surface 1042 may be configured by a free-form surface or the like, and a configuration may be adopted in which the composite image light LW, which is non-parallel light, enters the incident surface 1041 and is converted into parallel light while being reflected between the reflection surface 1042 and the incident surface 1041.

[0098] In the light guide portion 1050, the composite image light LW travels while being reflected between the first surface 1056 and the second surface 1057. A part of the composite image light LW incident on the partial reflection surface 1055 is reflected by the partial reflection surface 1055 and emitted from the emission portion 1058 toward the observer's eye E. The remainder of the composite image light LW incident on the partial reflection surface 1055 passes through the partial reflection surface 1055 and enters the next adjacent partial reflection surface 1055. Therefore, the composite image light LW reflected by each of the plurality of partial reflection surfaces 1055 is emitted from the emission portion 1058 toward the observer's eye E. As a result, the observer can recognize a virtual image.

[0099] At this time, the light incident on the light guide portion 1050 from the outside reaches the observer's eye E after passing through the partial reflection surface 1055 after entering the light guide portion 1050. For this reason, the observer can visually recognize the color image emitted from the optical module 1 and can also visually recognize the scenery of the outside world in a see-through manner. According to the head-mounted display device 1000 including the optical module 1 of the present embodiment as described above, while optimizing the white balance of the color image visually recognized by the observer's eye E, the power consumption of the first panel 10G and the second panel 10B can be reduced as compared with the third panel 10R.

[0100] FIG. 15 is a schematic configuration diagram of a projection display device (projector) 2000, which is another example of an image display device including the optical module 1 of the present embodiment. As shown in FIG. 15, the projection display device 2000 includes the optical module 1 of the above embodiment and a projection optical system 2100 that enlarges and projects the combined image light LW emitted from the optical module 1 onto a projection member 2200 such as a screen. According to the projection display device 2000 including the optical module 1 of the present embodiment as described above, while optimizing the white balance of the combined image light LW projected onto the projection member 2200, it is possible to reduce the power consumption of the first panel 10G and the second panel 10B compared to the third panel 10R.

[0101] 〔Modification Example〕 Note that the technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

[0102] In the above embodiment, an example is illustrated in which the first sub-substrate 80G generates the potential of the first power supply wiring 61G and the potential of the second power supply wiring 62G from the reference voltage VREF input from the parent substrate 100, and their potential difference becomes the first power supply voltage VDG. The second sub-substrate 80B generates the potential of the third power supply wiring 61B and the potential of the fourth power supply wiring 62B from the reference voltage VREF input from the parent substrate 100, and their potential difference becomes the second power supply voltage VDB. The third sub-substrate 80R generates the potential of the fifth power supply wiring 61R and the potential of the sixth power supply wiring 62R from the reference voltage VREF input from the parent substrate 100, and their potential difference becomes the third power supply voltage VDR.

[0103] For example, as shown in FIG. 16, the first sub-substrate 81G may be provided instead of the first sub-substrate 80G, the second sub-substrate 81B may be provided instead of the second sub-substrate 80B, and the third sub-substrate 81R may be provided instead of the third sub-substrate 80R. The first sub-substrate 81G outputs the reference voltage VREF and the green video signal SG input from the parent substrate 100 to the first panel 10G via the flexible flat cable 70G. The second sub-substrate 81B outputs the reference voltage VREF and the blue video signal SB input from the parent substrate 100 to the second panel 10B via the flexible flat cable 70B. The third sub-substrate 81R outputs the reference voltage VREF and the red video signal SR input from the parent substrate 100 to the third panel 10R via the flexible flat cable 70R.

[0104] As shown in FIG. 16, the first panel 10G may have a power supply circuit 18G such as a DC / DC converter that generates the potential of the first power supply wiring 61G and the potential of the second power supply wiring 62G from the reference voltage VREF input from the first sub-substrate 81G, and generates the potential difference therebetween as the first power supply voltage VDG. The second panel 10B may have a power supply circuit 18B such as a DC / DC converter that generates the potential of the third power supply wiring 61B and the potential of the fourth power supply wiring 62B from the reference voltage VREF input from the second sub-substrate 81B, and generates the potential difference therebetween as the second power supply voltage VDB. The third panel 10R may have a power supply circuit 18R such as a DC / DC converter that generates the potential of the fifth power supply wiring 61R and the potential of the sixth power supply wiring 62R from the reference voltage VREF input from the third sub-substrate 81R, and generates the potential difference therebetween as the third power supply voltage VDR.

[0105] Also according to the modification shown in FIG. 16, the first power supply potential difference of the first panel 10G, the second power supply potential difference of the second panel 10B, and the third power supply potential difference of the third panel 10R can be individually set to values that can ensure the target luminance of each panel 10.

[0106] In the above-described embodiment, the form in which each light-emitting element is an organic EL diode has been exemplified, but the present invention is not limited thereto. As each light-emitting element, other self-luminous elements such as an inorganic EL element, an LED array, an organic LED, a laser array, and a quantum dot light-emitting element may be used.

[0107] In the above-described embodiment, the head-mounted display device 1000 and the projection display device 2000 have been exemplified as the image display device including the optical module 1, but the optical module of the present invention can be applied to various forms of image display devices.

[0108] An optical module according to an aspect of the present invention may have the following configuration. An optical module according to an aspect of the present invention includes a first panel having a first light-emitting element, a first power supply wiring provided on one electrode side of the first light-emitting element, and a second power supply wiring provided on the other electrode side of the first light-emitting element; a second light-emitting element having a lower light-emitting luminance per unit current than the first light-emitting element; a third power supply wiring provided on one electrode side of the second light-emitting element; and a fourth power supply wiring provided on the other electrode side of the second light-emitting element; a prism that synthesizes first image light emitted from the first panel and second image light emitted from the second panel, and a first potential difference, which is a difference between a potential applied to the first power supply wiring and a potential applied to the second power supply wiring, is smaller than a second potential difference, which is a difference between a potential applied to the third power supply wiring and a potential applied to the fourth power supply wiring.

[0109] In an optical module according to an aspect of the present invention, a third panel having a third light-emitting element having a lower light-emitting luminance per unit current than the first light-emitting element, a fifth power supply wiring provided on one electrode side of the third light-emitting element, and a sixth power supply wiring provided on the other electrode side of the third light-emitting element is provided, the prism synthesizes the first image light, the second image light, and third image light emitted from the third panel, and the first potential difference is smaller than a third potential difference, which is a difference between a potential applied to the fifth power supply wiring and a potential applied to the sixth power supply wiring.

[0110] In the optical module according to one aspect of the present invention, the first panel emits a color light corresponding to the green wavelength range as the first image light.

[0111] In the optical module according to one aspect of the present invention, the second panel emits a color light corresponding to the blue wavelength range as the second image light, the third panel emits a color light corresponding to the red wavelength range as the third image light, the second potential difference is smaller than the third potential difference, and the maximum luminance of the third panel is higher than the maximum luminance of the second panel and lower than the maximum luminance of the first panel.

[0112] The image display device according to one aspect of the present invention may have the following configuration. The image display device according to one aspect of the present invention includes the optical module according to one aspect of the present invention.

Description of Reference Numerals

[0113] 1... Optical module, 10G... First panel, 10B... Second panel, 10R... Third panel, 11G... First pixel, 11B... Second pixel, 11R... Third pixel, 20... Dichroic prism (prism), 54G... First light-emitting element, 54B... Second light-emitting element, 54R... Third light-emitting element, 61G... First power supply wiring, 62G... Second power supply wiring, 61B... Third power supply wiring, 62B... Fourth power supply wiring, 61R... Fifth power supply wiring, 62R... Sixth power supply wiring, 80G, 81G... First daughter substrate, 80B, 81B... Second daughter substrate, 80R, 81R... Third daughter substrate, 100... Mother substrate, 1000... Head-mounted display device (image display device), 2000... Projection display device (image display device)

Claims

1. A first panel having a first light-emitting element that emits light with a first emission luminance per unit current, a first power supply wiring electrically connected to one electrode of the first light-emitting element, and a second power supply wiring electrically connected to the other electrode of the first light-emitting element; A second panel having a second light-emitting element that emits light with a second emission luminance per unit current, a third power supply wiring electrically connected to one electrode of the second light-emitting element, and a fourth power supply wiring electrically connected to the other electrode of the second light-emitting element; A third panel having a third light-emitting element that emits light with a third emission luminance per unit current, a fifth power supply wiring electrically connected to one electrode of the third light-emitting element, and a sixth power supply wiring electrically connected to the other electrode of the third light-emitting element; A prism that synthesizes the first image light emitted from the first panel, the second image light emitted from the second panel, and the third image light emitted from the third panel; Comprising: The second emission luminance and the third emission luminance are lower than the first emission luminance; A first potential difference, which is the difference between the potential applied to the first power supply wiring and the potential applied to the second power supply wiring, is smaller than a second potential difference, which is the difference between the potential applied to the third power supply wiring and the potential applied to the fourth power supply wiring; The first potential difference is smaller than a third potential difference, which is the difference between the potential applied to the fifth power supply wiring and the potential applied to the sixth power supply wiring; The first potential difference, the second potential difference, and the third potential difference are set based on the maximum luminance of the first panel; An optical module.

2. The optical module according to claim 1, wherein the first panel emits a color light corresponding to a green wavelength range as the first image light.

3. The second panel emits a color light corresponding to a blue wavelength range as the second image light, The third panel emits a color light corresponding to a red wavelength range as the third image light, The second potential difference is smaller than the third potential difference, The optical module according to claim 1, wherein the maximum luminance of the third panel is higher than the maximum luminance of the second panel and lower than the maximum luminance of the first panel.

4. An image display device comprising the optical module according to any one of claims 1 to 3.

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