Semiconductor Package, Method for Manufacturing Semiconductor Package, and Electronic Device

Abstract

To provide a semiconductor package that has excellent bonding strength, a method for manufacturing the semiconductor package, and an electronic apparatus.SOLUTION: A semiconductor package has: a semiconductor device; terminals arranged on the periphery of the semiconductor device and electrically connected with the semiconductor device; and plating layers arranged on the terminals. The terminals have: a first terminal surface arranged on a first surface; a second terminal surface arranged on a second surface; and a third terminal surface arranged on a third surface. The plating layers have: a first plating layer arranged on the first terminal surface; a second plating layer arranged on the second terminal surface; and a third plating layer arranged on the third terminal surface. The third plating layer is separated from one of the first plating layer and the second plating layer, and the third terminal surface is exposed from the separated portion.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a semiconductor package, a method for manufacturing a semiconductor package, and an electronic device.

Background Art

[0002] The semiconductor device described in Patent Document 1 has an outer shape including an upper surface and a lower surface that are in a front-back relationship with each other, and a side surface that connects the upper surface and the lower surface. Further, the semiconductor device has a semiconductor element disposed between the upper surface and the lower surface, and terminals that are disposed around the semiconductor element in a plan view of the upper surface and are electrically connected to the semiconductor element. Further, the terminal has a first terminal surface exposed on the upper surface, a second terminal surface exposed on the lower surface, and a third terminal surface exposed on the side surface.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the semiconductor device of Patent Document 1, it is unclear whether a plating layer for improving the wettability of solder is formed on the surface of the terminal. For example, when mounting the semiconductor device on a mounting substrate, if the plating layer is not formed, the solder does not spread and the bonding strength with the mounting substrate cannot be sufficiently increased. On the contrary, if the plating layer is formed, the solder creeps up from the side surface and spreads also on the upper surface, the fillet becomes small, or the shape of the fillet is distorted, and the bonding strength may decrease.

Means for Solving the Problems

[0005] The semiconductor package of the present invention has an outer shape including a first surface and a second surface that are in a front-back relationship with each other, and a third surface that connects the first surface and the second surface. A semiconductor element disposed between the first surface and the second surface; In a plan view of the first surface, terminals disposed around the semiconductor element and electrically connected to the semiconductor element; A plating layer disposed on the terminals, and having: The terminal has a first terminal surface disposed on the first surface, a second terminal surface disposed on the second surface, and a third terminal surface disposed on the third surface; The plating layer has a first plating layer disposed on the first terminal surface, a second plating layer disposed on the second terminal surface, and a third plating layer disposed on the third terminal surface; The third plating layer is separated from one of the first plating layer and the second plating layer, and the third terminal surface is exposed from the separated portion.

[0006] A method for manufacturing a semiconductor package according to the present invention includes the steps of preparing and forming a substrate having a first substrate surface and a second substrate surface that are in a front-back relationship with each other, and having terminals including a first terminal surface disposed on the first substrate surface and a second terminal surface disposed on the second substrate surface, and in which a plurality of element regions are integrally formed; Disposing a semiconductor element in each of the element regions; Cutting a boundary portion between adjacent element regions from one surface side of the first substrate surface and the second substrate surface to form a bottomed recess that does not reach the other surface; Forming a plating layer on the first terminal surface, the second terminal surface, and the inner surface of the recess; Cutting the boundary portion between adjacent element regions from the other surface side to form a through hole that penetrates the other surface and the recess, and separating the plurality of element regions into individual pieces.

[0007] An electronic device according to the present invention includes the above-described semiconductor package.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, the semiconductor package, the method of manufacturing the semiconductor package, and the electronic device of the present invention will be described in detail based on the embodiments shown in the accompanying drawings.

[0010] For convenience of explanation, in each figure, three axes orthogonal to each other are illustrated as the X-axis, Y-axis, and Z-axis. The direction parallel to the X-axis is also referred to as the "X-axis direction", the direction parallel to the Y-axis is also referred to as the "Y-axis direction", and the direction parallel to the Z-axis is also referred to as the "Z-axis direction". Also, the tip side of the arrow indicating each axis is also referred to as the "plus side", and the opposite side is also referred to as the "minus side". Further, the plus side in the Z-axis direction is also referred to as "up", and the minus side in the Z-axis direction is also referred to as "down". Furthermore, the expressions of the upper surface and the lower surface are also expressions for convenience of referring to the figure, and do not mean that the upper surface and the lower surface of the present invention are limited to the vertical up and down.

[0011] <First Embodiment> FIG. 1 and FIG. 2 are perspective views showing a semiconductor package according to the first embodiment, respectively. FIG. 3 is a cross-sectional view taken along line A-A in FIG. 1. FIG. 4 is a cross-sectional view taken along line B-B in FIG. 1. FIG. 5 is a cross-sectional view taken along line C-C in FIG. 1. FIG. 6 is a cross-sectional view showing a state where a semiconductor package is mounted on a wiring board. FIG. 7 is a flowchart showing the manufacturing process of the semiconductor package. FIGS. 8 to 16 are cross-sectional views for explaining the method of manufacturing the semiconductor package, respectively.

[0012] As shown in FIGS. 1 and 2, the semiconductor package 1 is substantially rectangular parallelepiped. Therefore, the outer shape or contour shape of the semiconductor package 1 has an upper surface 11 as a first surface and a lower surface 12 as a second surface, which are in a front-back relationship with each other, and four side surfaces 13, 14, 15, 16 as a third surface located between the upper surface 11 and the lower surface 12 and connecting them. In particular, in this embodiment, the upper surface 11 and the lower surface 12 are each substantially square. Further, an annular step D around the Z-axis is formed in the middle of each of the side surfaces 13, 14, 15, 16 in the height direction, and the upper portion 1A of the semiconductor package 1 is smaller in size than the lower portion 1B by one size. That is, each side surface includes the step D and is formed by the upper portion and the lower portion of the step D.

[0013] As shown in FIGS. 3 to 5, the semiconductor package 1 mainly includes a frame 2, a semiconductor element 3 mounted on the frame 2, a molding portion 4 that molds the semiconductor element 3, and a plating layer 5 formed on the surface of the frame 2. The semiconductor element 3 is an IC chip (semiconductor chip), and an electronic circuit that performs a desired function is formed thereon.

[0014] The frame 2 has a base 21 on which the semiconductor element 3 is placed, a plurality of terminals 22 arranged around the base 21, four pillar portions 23 arranged at the four corners of the semiconductor package 1, and four beam portions 24 connecting each pillar portion 23 and the base 21. These are integrally formed by patterning a metal substrate 20 by etching as will be described later. The constituent material of these is not particularly limited as long as it has conductivity, but in this embodiment, a copper alloy is used. As a result, the frame 2 has a sufficiently low electrical resistance and is relatively inexpensive. The upper surface, lower surface, and side surface used in the description of the base 21, the plurality of terminals 22, the four pillar portions 23, and the four beam portions 24, which are components of the frame 2, are a member that serves as a base material of the frame 2 or a configuration including the member and the plating described later.

[0015] The base 21 is located at the center of the frame 2 in a plan view from the Z-axis direction. Also, the base 21 has a flat plate shape with the Z-axis direction as its thickness, and the shape in a plan view from the Z-axis direction is substantially square. Further, the base 21 is thinner than the semiconductor package 1. And a semiconductor element 3 is joined to its upper surface 211 via an adhesive (not shown). Also, the lower surface 212 of the base 21 is exposed on the lower surface 12. In this way, by exposing the lower surface 212 on the lower surface 12, the heat of the semiconductor element 3 is easily released to the outside through the base 21, and the heat dissipation performance of the semiconductor package 1 is enhanced. In particular, as described above, since the base 21 is made of a metal material and has a high thermal conductivity, the heat dissipation performance is further improved.

[0016] The four pillar portions 23 are arranged at the respective corner portions of the semiconductor package 1 in a plan view from the Z-axis direction. Also, each pillar portion 23 has a columnar shape extending in the Z-axis direction and has substantially the same height as the semiconductor package 1. Therefore, the upper surface of the pillar portion 23 is arranged as a part of the upper surface 11 of the semiconductor package 1, the lower surface is arranged as a part of the lower surface 12, and the side surfaces are arranged as parts of the side surfaces 13 to 16. These pillar portions 23 are connected to the base 21 via beam portions 24. Thereby, separation and detachment of the base 21 during the manufacture of the semiconductor package 1 can be prevented, and the manufacture of the semiconductor package 1 becomes easy. Also, the heat of the semiconductor element 3 is transmitted from the base 21 to the pillar portions 23 via the beam portions 24, and the heat of the semiconductor element 3 can be released to the outside not only from the base 21 but also from the pillar portions 23 and the beam portions 24. Therefore, the heat dissipation performance of the semiconductor package 1 is further enhanced.

[0017] Further, the plurality of terminals 22 are arranged so as to surround the base 21 in a plan view from the Z-axis direction. The plurality of terminals 22 include a plurality of terminals 22A arranged along the side surface 13, a plurality of terminals 22B arranged along the side surface 14, a plurality of terminals 22C arranged along the side surface 15, and a plurality of terminals 22D arranged along the side surface 16. Each terminal 22 has a first terminal surface 221 arranged on the upper surface 11 of the semiconductor package 1 and a second terminal surface 222 arranged on the lower surface 12. The terminal 22A has a third terminal surface 223 arranged on the side surface 13, the terminal 22B has a third terminal surface 223 arranged on the side surface 14, the terminal 22C has a third terminal surface 223 exposed on the side surface 15, and the terminal 22D has a third terminal surface 223 arranged on the side surface 16.

[0018] Also, each terminal 22 has the same shape as each other and is substantially L-shaped in the present embodiment. As shown in FIG. 3, the terminals 22A and 22C arranged along the side surfaces 13 and 15 are each substantially L-shaped in a plan view from the X-axis direction, and as shown in FIG. 4, the terminals 22B and 22D arranged along the side surfaces 14 and 16 are each substantially L-shaped in a plan view from the Y-axis direction. Therefore, when the Z-axis direction is defined as the height, each terminal 22 has a low back portion 224 having a height lower than that of the semiconductor package 1 and a high back portion 225 located outside the low back portion 224 and having the same height as the semiconductor package 1. The first terminal surface 221 is formed on the upper surface of the high back portion 225, the third terminal surface 223 is formed on the side surface of the high back portion 225, and the second terminal surface 222 is formed on each lower surface of the low back portion 224 and the high back portion 225.

[0019] Also, the upper surface of the low back portion 224 serves as a connection surface 224a, and this connection surface 224a is electrically connected to the semiconductor element 3 via the wire W. Thereby, an electrical connection between the semiconductor element 3 and an external device can be achieved via the terminal 22. By setting the upper surface of the low back portion 224 as the connection surface 224a as in the present embodiment, for example, it becomes easier to press the capillary against the terminal 22 during wire bonding, and the connection of the wire W to the terminal 22 becomes easier.

[0020] In this embodiment, a plating layer 226 for enhancing the connection strength with the wire W is disposed on the connection surface 224a. The plating layer 226 is a silver plating layer. However, the plating layer 226 is not particularly limited as long as it can exhibit its function. Further, the plating layer 226 may be omitted.

[0021] Also, in the terminal 22, the first terminal surface 221 and the second terminal surface 222 have different shapes from each other. In this embodiment, since the terminal 22 has a substantially L shape, the first terminal surface 221 is smaller than the second terminal surface 222. By making the shapes of the first terminal surface 221 and the second terminal surface 222 different from each other, the top and bottom of the semiconductor package 1 can be easily determined based on the shape of the terminal 22. Therefore, for example, mistakes such as mounting it upside down can be effectively suppressed.

[0022] The mold part 4 molds (resin-seals) the semiconductor element 3. Thereby, the semiconductor element 3 can be protected from moisture, dust, impact, etc. The mold material constituting the mold part 4 is not particularly limited, but for example, a thermosetting epoxy resin can be used, and it can be molded by a transfer molding method.

[0023] The plating layer 5 is disposed on the surface of the frame 2 (the portion exposed from the mold part 4). The plating layer 5 has a function of enhancing the wettability of the solder H described later and enhancing the bonding strength and the reliability of the electrical connection between the semiconductor package 1 and the wiring board 8. The plating layer 5 includes a first plating layer 51 disposed on the first terminal surface 221, a second plating layer 52 disposed on the second terminal surface 222, and a third plating layer 53 disposed on the third terminal surface 223. In addition, the plating layer 5 is also disposed on the lower surface of the base 21 and each beam part 24, and the upper surface, lower surface, and side surface of each column part 23.

[0024] The first plating layer 51 is disposed on substantially the entire surface of the first terminal surface 221, and the second plating layer 52 is disposed on substantially the entire surface of the second terminal surface 222. In contrast, the third plating layer 53 is disposed only on a part of the third terminal surface 223. Specifically, the third plating layer 53 is disposed on substantially the entire surface of the portion 223a below the step D of the third terminal surface 223, and is not disposed on the step D and the portion 223b above the step D. That is, the portion 223b of the third terminal surface 223 is not covered by the plating layer 5 and is exposed to the outside of the semiconductor package 1. Further, the first plating layer 51 and the third plating layer 53 are separated from each other by the portion 223b. In FIGS. 3 to 6, the portion 223b is formed as a surface recessed inward of the semiconductor package 1 compared to the portion 223a, but conversely, it may be formed as a surface protruding outward of the package 1 compared to the portion 223a.

[0025] The configuration of the semiconductor package 1 has been described above. According to the configuration of the semiconductor package 1 having such a configuration, since each terminal 22 is disposed not only on the lower surface 12 but also on the upper surface 11, for example, it can be mounted on the wiring board 8 in a posture as shown in FIG. 6. Thus, by having a plurality of mountable postures, the semiconductor package 1 with high convenience is obtained.

[0026] In FIG. 6, the semiconductor package 1 is joined to the wiring board 8 via solder H in a posture where the lower surface 12 faces the wiring board 8 side. At this time, the solder H spreads between the second plating layer 52 and the wiring board 8 and also spreads to the third plating layer 53 to form a fillet H1. Thus, by forming the fillet H1 around the semiconductor package 1, the bonding strength between the wiring board 8 and the semiconductor package 1 is improved, and the mechanical reliability and electrical reliability are enhanced. Here, as described above, in the semiconductor package 1, the plating layer 5 is not disposed on the portion 223b of the third terminal surface 223. Therefore, the spread of the solder H is suppressed only to the portion 223a by the portion 223b, and it is possible to effectively suppress the solder H from further spreading to the first plating layer 51 by climbing up the side surfaces 13 to 16 from there. Therefore, it is possible to suppress the fillet H1 from becoming smaller unintentionally or the shape of the fillet H1 from being distorted, and to prevent the bonding strength with the wiring board 8 and the reliability of the electrical connection from decreasing unintentionally. In particular, in the present embodiment, since a step D without a plating layer is formed between the portion 223a where the third plating layer 53 is disposed and the exposed portion 223b, it is possible to more effectively suppress the solder H from spreading to the first plating layer 51.

[0027] Here, the height T of the portion 223a where the plating layer 5 is disposed is not particularly limited. However, when the height of the semiconductor package 1 is T1, for example, it is preferably 50% ≦ T / T1 ≦ 95%, more preferably 60% ≦ T / T1 ≦ 90%, and even more preferably 65% ≦ T / T1 ≦ 85%. According to such a range, while ensuring that the portion 223b can exhibit its function, that is, the function of preventing the spread of the solder H to the first plating layer 51, the portion 223a can be made larger. Therefore, the fillet H1 can be formed larger, and the bonding strength with the wiring board 8 can be further increased.

[0028] The configuration of the semiconductor package 1 has been described above. As described above, such a semiconductor package 1 includes an outer shape having an upper surface 11 as a first surface and a lower surface 12 as a second surface that are in a front-back relationship with each other, and side surfaces 13, 14, 15, 16 as a third surface connecting the upper surface 11 and the lower surface 12. It has a semiconductor element 3 disposed between the upper surface 11 and the lower surface 12, terminals 22 disposed around the semiconductor element 3 in a plan view of the upper surface 11, that is, in a plan view in the Z-axis direction, and electrically connected to the semiconductor element 3, and a plating layer 5 disposed on the terminals 22. Further, the terminal 22 has a first terminal surface 221 disposed on the upper surface 11, a second terminal surface 222 disposed on the lower surface 12, and a third terminal surface 223 disposed on the side surfaces 13, 14, 15, 16. Also, the plating layer 5 has a first plating layer 51 disposed on the first terminal surface 221, a second plating layer 52 disposed on the second terminal surface 222, and a third plating layer 53 disposed on the third terminal surface 223. And the third plating layer 53 is separated from one of the first plating layer 51 and the second plating layer 52. In this embodiment, it is separated from the first plating layer 51, and the third terminal surface 223 is exposed from the separated portion. According to such a configuration, when joining an object such as a wiring board 8 via solder H as shown in FIG. 6 described above, it is possible to suppress the spread of wetting of the solder H on the upper surface 11 of the solder H. Therefore, it is possible to suppress the unintentional reduction in the size of the fillet H1 or the distortion of the shape of the fillet H1, and the unintentional decrease in the bonding strength with the wiring board 8 and the reliability of the electrical connection.

[0029] Also, as described above, in the semiconductor package 1, the third terminal surface 223 has a step D between a portion 223a where the third plating layer 53 is disposed and an exposed portion 223b. Thereby, it is possible to more effectively suppress the spread of wetting of the solder H to the first plating layer 51.

[0030] Also, as described above, in the semiconductor package 1, the first terminal surface 221 and the second terminal surface 222 have different shapes. Thereby, it is possible to easily determine the top and bottom of the semiconductor package 1 based on the shape of the terminal 22. Therefore, for example, mistakes such as mounting it upside down can be effectively suppressed.

[0031] Also, as described above, the semiconductor package 1 has a base 21 on which the semiconductor element 3 is mounted and is exposed on the lower surface 12. Thereby, the heat of the semiconductor element 3 is easily released to the outside through the base 21. Therefore, the heat dissipation performance of the semiconductor package 1 can be enhanced. Although not shown, a wiring layer is provided on the wiring board 8 facing the base 21, and by soldering the base 21 and the wiring board 8, the heat dissipation performance of the semiconductor package 1 can be further enhanced. The wiring layer in this case may be a dummy wiring layer.

[0032] Next, a manufacturing method of the semiconductor package 1 will be described. As shown in FIG. 7, the manufacturing process of the semiconductor package 1 includes a preparation step S1 of preparing a metal substrate 20 having a plurality of element regions Q, a frame forming step S2 of patterning the metal substrate 20 to form a frame 2 in each element region Q, an arrangement step S3 of arranging the semiconductor element 3 on the base 21, a connection step S4 of electrically connecting the semiconductor element 3 and the terminal 22 via a wire W, a molding step S5 of molding the semiconductor element 3, a recess forming step S6 of forming a bottomed recess 201 that opens on the upper surface of the metal substrate 20 at the boundary between the element regions Q, a plating step S7 of forming a plating layer 5 on the upper and lower surfaces of the frame 2 and the inner surface of the recess 201, and a singulation step S8 of forming a through hole 202 that penetrates the lower surface of the metal substrate 20 and the recess 201 at the boundary between the element regions Q and singulating each element region Q.

[0033] <Preparation Step S1> First, as shown in FIG. 8, a metal substrate 20 that serves as a base material of the frame 2 is prepared. The metal substrate 20 is plate-shaped and has an upper surface 20A as a first substrate surface and a lower surface 20B as a second substrate surface that are in a front-back relationship with each other. Further, a plurality of element regions Q are set in a matrix pattern on the metal substrate 20.

[0034] <Frame forming step S2> Next, as shown in FIG. 9, the metal substrate 20 is etched from the upper surface 20A to form the frame 2 in each element region Q. Also, a plating layer 226 is formed on each terminal 22.

[0035] <Arrangement step S3> Next, as shown in FIG. 10, in each element region Q, the semiconductor element 3 is arranged on the upper surface 211 of the base 21.

[0036] <Connection step S4> Next, as shown in FIG. 11, in each element region Q, the semiconductor element 3 and the terminal 22 are electrically connected using a wire W. The wire W is formed, for example, by wire bonding.

[0037] <Molding step S5> Next, as shown in FIG. 12, a leakage prevention sheet M1 for preventing leakage of the molding material is attached to the lower surface 20B of the metal substrate 20, and a mold M2 of the molding material is arranged on the upper surface 20A of the metal substrate 20. Next, the space between the leakage prevention sheet M1 and the mold M2 is filled with the molten molding material by transfer molding and hardened. Thereby, the molded portion 4 is formed. In this embodiment, the mold M2 is box-shaped, and the formed molded portion 4 protrudes upward from the upper surface 20A of the metal substrate 20. Next, as shown in FIG. 13, for example, the surface of the molded portion 4 is ground using a grinding device such as a grinder spindle so that the upper surface of the molded portion 4 coincides with the upper surface of the metal substrate 20. Thereby, the first terminal surface 221 of the terminal 22 appears from the molded portion 4.

[0038] <Recess forming step S6> Next, as shown in FIG. 14, using the dicing blade DB1, the boundary between the element regions Q is half-cut from the lower surface 20B side of the metal substrate 20, that is, cut halfway so as not to reach the upper surface 20A, and a bottomed recess 201 that opens to the lower surface 20B of the metal substrate 20 is formed.

[0039] <Electroplating step S7> Next, as shown in FIG. 15, an electroplated layer 5 is formed on the surface of the frame 2 (the surface exposed from the molding portion 4) by electroplating. Thereby, the electroplated layer 5 is formed on the upper and lower surfaces of the frame 2 and the inner surface of the recess 201. In the recess forming step S6 described above, since it is only half-cut, there is no portion separated from the outside in the metal substrate 20. Therefore, a current can be passed through the metal substrate 20 all at once, and electroplating can be easily performed.

[0040] <Singulation step S8> Next, as shown in FIG. 16, using the dicing blade DB2, the boundary between the element regions Q is cut from the upper surface 20A side of the metal substrate 20, and a through hole 202 that penetrates the upper surface 20A of the metal substrate 20 and the bottom surface of the recess 201 is formed. Thereby, each element region Q is separated, and a plurality of semiconductor packages 1 that are singulated are obtained. Here, the width W2 of the through hole 202 is larger than the width W1 of the recess 201. That is, the width of the dicing blade DB2 is larger than the width of the dicing blade DB1. Thereby, in this step, the through hole 202 that penetrates the upper surface 20A of the metal substrate 20 and the recess 201 can be formed more reliably. In addition, the steps D and the portions 223b where the electroplated layer 5 is not formed can be easily formed collectively on the side surfaces 13, 14, 15, and 16.

[0041] According to the method for manufacturing the semiconductor package 1 as described above, the semiconductor package 1 can be easily manufactured.

[0042] As described above, the method for manufacturing such a semiconductor package 1 includes a preparation step S1 and a frame formation step S2 of preparing and forming a metal substrate 20 as a substrate in which a plurality of element regions Q having a terminal 22 with a first terminal surface 221 disposed on the upper surface 20A as a first substrate surface and a second terminal surface 222 disposed on the lower surface 20B as a second substrate surface, which are in a front-back relationship with each other, are integrally formed; an arrangement step S3 of arranging semiconductor elements 3 in each element region Q; a recess formation step S6 of cutting the boundary portion between adjacent element regions Q from one surface side of the upper surface 20A and the lower surface 20B, which is the lower surface 20B in this embodiment, to form a bottomed recess 201 that does not reach the upper surface 20A; a plating step S7 of forming a plating layer 5 on the first terminal surface 221, the second terminal surface 222, and the inner surface of the recess 201; and a singulation step S8 of cutting the boundary portion between adjacent element regions Q from the upper surface 20A side to form a through hole 202 that penetrates the upper surface 20A and the recess 201, and singulating the plurality of element regions Q. According to such a manufacturing method, the semiconductor package 1 can be easily manufactured.

[0043] Also, as described above, the through hole 202 is wider than the recess 201. That is, the width W2 of the through hole 202 is larger than the width W1 of the recess 201. Thereby, in the singulation step S8, the through hole 202 that penetrates the upper surface 20A and the recess 201 can be formed more reliably. Also, the steps D and the portions 223b where the plating layer 5 is not formed can be easily formed in a batch on the side surfaces 13, 14, 15, 16 of the semiconductor package 1.

[0044] <Second Embodiment> FIG. 17 and FIG. 18 are cross-sectional views showing a semiconductor package according to the second embodiment, respectively. FIG. 19 and FIG. 20 are cross-sectional views showing a state in which the semiconductor package is mounted on a wiring board, respectively. FIGS. 21 to 23 are cross-sectional views for explaining a method for manufacturing the semiconductor package, respectively.

[0045] The semiconductor package 1 of this embodiment is mainly the same as the semiconductor package 1 of the first embodiment described above, except that the direction of the step D and the configuration of the third plating layer 53 are different. In the following description, regarding this embodiment, the differences from the above-described embodiments will be mainly described, and the description of the same matters will be omitted. Also, in FIGS. 17 to 23, the same components as those in the above-described embodiments are denoted by the same reference numerals.

[0046] In the semiconductor package 1 shown in FIGS. 17 and 18, an annular step D around the Z-axis is formed in the middle of the height direction on each of the side surfaces 13, 14, 15, and 16. This step D faces downward, contrary to the above-described first embodiment that faces upward. Therefore, in this embodiment, the lower portion 1B of the semiconductor package 1 is slightly smaller than the upper portion 1A.

[0047] The plating layer 5 includes a first plating layer 51 disposed on the first terminal surface 221, a second plating layer 52 disposed on the second terminal surface 222, and a third plating layer 53 disposed on the third terminal surface 223. In addition, the plating layer 5 is also disposed on the base 21, the lower surfaces of the respective beam portions 24, and the upper, lower, and side surfaces of the respective column portions 23. Among these, except for the third plating layer 53, it is the same as the first embodiment described above.

[0048] The third plating layer 53 is disposed only on a part of the third terminal surface 223. Specifically, the third plating layer 53 is disposed on substantially the entire surface of the upper portion 223b of the third terminal surface 223 above the step D, and is not disposed on the step D and the lower portion 223a below the step D. That is, the portion 223a of the third terminal surface 223 is not covered by the plating layer 5 and is exposed to the outside of the semiconductor package 1. Also, due to the portion 223a, the second plating layer 52 and the third plating layer 53 are separated.

[0049] The configuration of the semiconductor package 1 has been described above. According to the configuration of the semiconductor package 1 with such a configuration, since each terminal 22 is located not only on the lower surface 12 but also on the upper surface 11, for example, it can be mounted on the wiring board 8 in a posture as shown in FIG. 19. In this way, by having a plurality of mountable postures, the semiconductor package 1 with high convenience is obtained.

[0050] In particular, in FIG. 19, the semiconductor package 1 is joined to the wiring board 8 via the solder H in a posture where the upper surface 11 is located on the side of the wiring board 8. At this time, the solder H spreads wetly between the first plating layer 51 and the wiring board 8 and also spreads wetly to the third plating layer 53 to form the fillet H1. Here, as described above, in the semiconductor package 1, the plating layer 5 is not disposed in the portion 223a of the third terminal surface 223. Therefore, the wet spread of the solder H is suppressed only to the portion 223b by the portion 223a, and it is possible to effectively suppress the wet spread to the second plating layer 52 by climbing up the side surfaces 13 to 16 from there. Therefore, it is possible to suppress the fillet H1 from becoming smaller unintentionally or the shape of the fillet H1 from being distorted, and the bonding strength with the wiring board 8 and the reliability of the electrical connection from decreasing unintentionally. In particular, in the present embodiment, since the step D is formed between the portion 223b where the third plating layer 53 is disposed and the exposed portion 223a, it is possible to more effectively suppress the wet spread of the solder H to the second plating layer 52.

[0051] In this case, as shown in FIG. 20, the semiconductor package 1 may further have a heat sink 7 disposed on the lower surface 12 side and connected to the base 21. According to such a configuration, the heat of the semiconductor element 3 is transmitted to the heat sink 7 via the base 21 and efficiently released from the heat sink 7. Therefore, the heat dissipation characteristics of the semiconductor package 1 are further improved.

[0052] The configuration of the semiconductor package 1 has been described above. In such a semiconductor package 1, the third plating layer 53 is separated from one of the first plating layer 51 and the second plating layer 52. In this embodiment, it is separated from the second plating layer 52, and the third terminal surface 223 is exposed from the separated portion. According to such a configuration, when joining an object such as the wiring board 8 via the solder H as shown in FIGS. 19 and 20 described above, it is possible to suppress the spread of wetting of the solder H on the upper surface 11 of the solder H. Therefore, it is possible to suppress the unintentional reduction in the size of the fillet H1 or the distortion of the shape of the fillet H1, and the unintentional reduction in the bonding strength with the wiring board 8 and the reliability of the electrical connection.

[0053] Next, a method for manufacturing the semiconductor package 1 of this embodiment will be described. The manufacturing process of the semiconductor package 1 includes a preparation step S1 of preparing a metal substrate 20 having a plurality of element regions Q, a frame forming step S2 of patterning the metal substrate 20 to form a frame 2 in each element region Q, an arrangement step S3 of arranging the semiconductor element 3 on the base 21, a connection step S4 of electrically connecting the semiconductor element 3 and the terminal 22 via a wire W, a molding step S5 of molding the semiconductor element 3, a recess forming step S6 of forming a bottomed recess 201 that opens on the upper surface of the metal substrate 20 at the boundary between the element regions Q, a plating step S7 of forming a plating layer 5 on the upper and lower surfaces of the frame 2 and the inner surface of the recess 201, and a singulation step S8 of forming a through hole 202 that penetrates the lower surface of the metal substrate 20 and the recess 201 at the boundary between the element regions Q and singulating each element region Q. Among these, since up to the molding step S5 is the same as that of the first embodiment described above, the description will start from the recess forming step S6 below.

[0054] <Recess Forming Step S6> First, as shown in FIG. 21, using a dicing blade DB1, the boundary between the element regions Q is half-cut from the upper surface 20A side of the metal substrate 20, that is, cut halfway so as not to reach the lower surface 20B, and a bottomed recess 201 that opens on the upper surface 20A of the metal substrate 20 is formed.

[0055] <Electroplating Step S7> Next, as shown in FIG. 22, an electroplated layer 5 is formed on the surface of the frame 2 by electroplating. As a result, the electroplated layer 5 is formed on the upper and lower surfaces of the frame 2 and the inner surface of the recess 201.

[0056] <Chip Separation Step S8> Next, as shown in FIG. 23, using a dicing blade DB2, the boundary between the element regions Q is cut from the lower surface 20B side of the metal substrate 20 to form a through hole 202 that penetrates the lower surface 20B of the metal substrate 20 and the bottom surface of the recess 201. As a result, each element region Q is separated, and a plurality of semiconductor packages 1 that are individually separated are obtained.

[0057] Note that the processing method shown in FIG. 23 is a method of cutting from the lower surface 20B side of the metal substrate 20 to individually separate each element region Q, but it may also be cut and individually separated from the upper surface 20A side of the metal substrate 20. In that case, a through hole 202 that penetrates the lower surface 20B and the bottom surface of the recess 201 is formed with a blade having a width narrower than the width of the bottomed recess 201 including the electroplated layer 5. That is, the formation of the through hole 202 for individually separating each element region Q can be performed from either the upper surface 20A side or the lower surface 20B side.

[0058] According to the method for manufacturing the semiconductor package 1 as described above, the semiconductor package 1 can be easily manufactured.

[0059] As described above, the manufacturing method of such a semiconductor package 1 has an upper surface 20A as a first substrate surface and a lower surface 20B as a second substrate surface that are in a front-back relationship with each other, and includes a plurality of element regions Q having terminals 22 with a first terminal surface 221 disposed on the upper surface 20A and a second terminal surface 222 disposed on the lower surface 20B. The method includes a preparation step S1 and a frame formation step S2 of preparing and forming a metal substrate 20 as a substrate in which the element regions Q are integrally formed, an arrangement step S3 of arranging semiconductor elements 3 in each element region Q, a recess formation step S6 of cutting a boundary portion between adjacent element regions Q from one surface side of the upper surface 20A and the lower surface 20B, in this embodiment, from the upper surface 20A to form a bottomed recess 201 that does not reach the lower surface 20B, a plating step S7 of forming a plating layer 5 on the first terminal surface 221, the second terminal surface 222, and the inner surface of the recess 201, and a singulation step S8 of cutting the boundary portion between adjacent element regions Q to form a through hole 202 that penetrates the lower surface 20B and the recess 201 to singulate the plurality of element regions Q. According to such a manufacturing method, the semiconductor package 1 can be easily manufactured. Note that the boundary portion between adjacent element regions Q may be cut from the lower surface 20B side.

[0060] Also, as described above, in the singulation step S8, the boundary portion of the element region Q is cut from the lower surface 20B side. In this way, by cutting from the lower surface 20B side, singulation can be easily performed as compared with the case of cutting from the upper surface 20A side through the recess 201.

[0061] <Third Embodiment> FIG. 24 is a perspective view showing a smartphone according to the third embodiment.

[0062] A smartphone 1200 as an electronic device shown in FIG. 24 incorporates a semiconductor package 1. The semiconductor package 1 can, for example, change a display image displayed on the display unit 1208 based on a received signal, emit a warning sound or an effect sound, or drive a vibration motor to vibrate the main body.

[0063] Such a smartphone 1200 as an electronic device has a semiconductor package 1. Therefore, the smartphone 1200 can enjoy the effects of the semiconductor package 1 described above and can exhibit high reliability.

[0064] In addition to the smartphone 1200 described above, the electronic device includes, for example, a personal computer, a digital still camera, a tablet terminal, a watch including a smartwatch, an inkjet ejection device such as an inkjet printer, an HMD (head-mounted display), a wearable terminal such as smart glasses, a television, a video camera, a video tape recorder, a car navigation device, a pager, an electronic notebook, an electronic dictionary, an electronic translator, a calculator, an electronic game device, a training device, a word processor, a workstation, a videophone, a security television monitor, electronic binoculars, a POS terminal, an electronic thermometer, a blood pressure monitor, a blood glucose meter, an electrocardiogram measuring device, a medical device such as an ultrasonic diagnostic device, an electronic endoscope, a fish finder, various measuring devices, vehicles, instruments mounted on aircraft, ships, base stations for mobile terminals, flight simulators, etc. and can be applied thereto.

[0065] As described above, the semiconductor package, the manufacturing method of the semiconductor package, and the electronic device of the present invention have been described based on the illustrated embodiments. However, the present invention is not limited thereto, and the configuration of each part can be replaced with any configuration having the same function. Further, any other arbitrary component may be added to the present invention.

Explanation of reference numerals

[0066] 1... Semiconductor package, 1A... Upper part, 1B... Lower part, 11... Upper surface, 12... Lower surface, 13... Side surface, 14... Side surface, 15... Side surface, 16... Side surface, 2... Frame, 20... Metal substrate, 20A... Upper surface, 20B... Lower surface, 201... Recess, 202... Through hole, 21... Base, 211... Upper surface, 212... Lower surface, 22... Terminal, 22A... Terminal, 22B... Terminal, 22C... Terminal, 22D... Terminal, 221... First terminal surface, 222... Second terminal surface, 223... Third terminal surface, 223a... Portion, 223b... Portion, 224... Low back, 224a... Connection surface, 225... High back, 226... Plating layer, 23... Column part, 24... Beam part, 3... Semiconductor element, 4... Mold part, 5... Plating layer, 51... First plating layer, 52... Second plating layer, 53... Third plating layer, 7... Heat sink, 8... Wiring board, 1200... Smartphone, 1208... Display part, B... Metal bump, D... Step, DB1... Dicing blade, DB2... Dicing blade, H... Solder, H1... Fillet, M1... Leakage prevention sheet, M2... Mold, Q... Element area, S1... Preparation process, S2... Frame formation process, S3... Arrangement process, S4... Connection process, S5... Mold process, S6... Recess formation process, S7... Plating process, S8... Singulation process, T... Height, T1... Height, W... Wire, W1... Width, W2... Width

Claims

1. An outer shape including a first surface and a second surface that are in a front-back relationship with each other, and a third surface that connects the first surface and the second surface; A semiconductor element disposed between the first surface and the second surface; Terminals disposed around the semiconductor element in a plan view of the first surface and electrically connected to the semiconductor element; A plating layer disposed on the terminals; The terminals have a first terminal surface disposed on the first surface, a second terminal surface disposed on the second surface, and a third terminal surface disposed on the third surface; The plating layer has a first plating layer disposed on the first terminal surface, a second plating layer disposed on the second terminal surface, and a third plating layer disposed on the third terminal surface; The third plating layer is spaced apart from one of the first plating layer and the second plating layer, and the third terminal surface is exposed from the spaced-apart portion; The third terminal surface has a step in the middle in the direction perpendicular to the first surface; A portion of the third terminal surface on the second surface side of the step protrudes outward more than a portion of the third terminal surface on the first surface side of the step; The third plating layer is not disposed on a portion of the third terminal surface on the first surface side of the step and on the step; The semiconductor package, wherein the third plating layer is disposed on a portion of the third terminal surface on the second surface side of the step.

2. The semiconductor package according to claim 1, wherein the first terminal surface and the second terminal surface have different shapes.

3. The semiconductor package according to claim 1 or 2, further having a base on which the semiconductor element is mounted and exposed on the second surface.

4. A step of preparing and forming a substrate in which a plurality of element regions having a first substrate surface and a second substrate surface that are in a front-back relationship with each other and having terminals including a first terminal surface disposed on the first substrate surface and a second terminal surface disposed on the second substrate surface are integrally formed; A step of disposing a semiconductor element in each of the element regions; A step of cutting a boundary portion between adjacent element regions from one surface side of the first substrate surface and the second substrate surface to form a bottomed recess that does not reach the other surface; A step of forming a plating layer on the first terminal surface, the second terminal surface, and an inner surface of the recess; cutting the boundary between the adjacent element regions to form a through hole that penetrates the other surface and the recess, and singulating a plurality of the element regions; by singulating a plurality of the element regions in the singulating step; an outer shape including a first surface and a second surface that are in a front-back relationship with each other, and a third surface that connects the first surface and the second surface; the semiconductor element disposed between the first surface and the second surface; the terminals disposed around the semiconductor element in a plan view of the first surface and electrically connected to the semiconductor element; a plurality of semiconductor packages having the plating layer disposed on the terminals are formed; the terminals have a first terminal surface disposed on the first surface, a second terminal surface disposed on the second surface, and a third terminal surface disposed on the third surface; the plating layer has a first plating layer disposed on the first terminal surface, a second plating layer disposed on the second terminal surface, and a third plating layer disposed on the third terminal surface; the third plating layer is separated from one of the first plating layer and the second plating layer, and the third terminal surface is exposed from the separated portion; the third terminal surface has a step in the middle in the direction orthogonal to the first surface; the portion of the third terminal surface on the second surface side of the step protrudes outward more than the portion of the third terminal surface on the first surface side of the step; the third plating layer is not disposed on the portion of the third terminal surface on the first surface side of the step and on the step; A method of manufacturing a semiconductor package, wherein the third plating layer is disposed on a portion of the third terminal surface on the second surface side of the step.

5. The method of manufacturing a semiconductor package according to claim 4, wherein in the singulating step, the boundary of the element region is cut from the other surface side.

6. The method of manufacturing a semiconductor package according to claim 4 or 5, wherein the through hole is wider than the recess.

7. An electronic device comprising the semiconductor package according to any one of claims 1 to 3.

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