Package Land Pads in Closed-Loop Wiring for High-Speed Data Signaling

Abstract

To provide a semiconductor package having a base layer that includes land pads with closed-loop conductive lines.SOLUTION: An electronic package 100 comprises first and second surfaces. The second surface has a land pad 130 in a land pad opening 105. The land pad is separated from the land pad opening by an outer gap 109. The land pad is a closed loop. The electronic package is electrically coupled to a socket. The socket has an interconnect 123 with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. When the first connector is coupled to at least two or more portions of the closed loop, the portions are separated from each other by a portion of an inner gap 107 or the outer gap. The closed loop comprises a conductive line 131 continuously extending from a first end to a second end.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to semiconductor packages having a base layer including land pads with closed-loop conductive traces.

Background Art

[0002] The demand for integration for form factor miniaturization and high performance is driving advanced packaging approaches in the semiconductor industry. One such approach is to use microelectronic packages to enable form factor miniaturization and high performance. Such architectures generally rely on land grid array (LGA) sockets to couple the electronic package to the board. LGA sockets have various interconnects and land pads that are coupled together to form channels for communicating data between the package and the board.

[0003] LGA sockets are one of the main contributors to the data transfer rate associated with peripheral component interconnect express (PCIe) and double data rate (DDR) channels. The data rates of PCIe and DDR channels are constantly increasing and typically doubling for each successive generation. New generations of PCIe and DDR channels require a wider channel bandwidth. Thus, LGA sockets have their own integration challenges. One such challenge is that the land pads exhibit a concentrated capacitance (C) effect. Another challenge is that the interconnects are similarly subject to a concentrated inductance (L) effect. Thus, such challenges cause the LGA socket to have a series LC connection that increases reflection / loss, forms resonances, and limits the bandwidth of the PCIe and DDR channels.

[0004] Reducing the LGA land pad size has been proposed to reduce the concentrated C effect and mitigate the issues associated with series LC connection. However, reducing the land pad size decreases the effective contact area, increases the challenges for building a reliable mechanical connection, and requires more complex dimensional tolerances and alignment techniques. Also, aggressive voiding around or within the pad has been proposed to reduce the concentrated C effect. However, aggressive voidance reduces the routing space within the package layer above the pad, increases the package layer count / cost, and increases the risk of mechanical reliability of the substrate. Therefore, reducing the LGA land pad size and aggressive voidance around the pad nullify the advantages of the LGA socket and are not desirable solutions.

Brief Description of the Drawings

[0005]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 5

Figure 6

[0006] This specification describes electronic packages having a base layer that includes land grid array (LGA) land pads with closed-loop transmission lines, according to various embodiments. In the following description, various aspects of the illustrative implementations are described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For the purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the specific implementations. It will be apparent, however, to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0007] Although the various operations are described as multiple discrete operations in the most useful way to understand the present invention, the order of the description should not be construed to mean that these operations are necessarily order-dependent. In particular, these operations need not be performed in the order of presentation.

[0008] As described above, the architecture of an electronic package is at least partially limited by the sockets commonly used to couple the die, electronic package, and / or board together. For example, the new generation of Peripheral Component Interconnect Express (PCIe) and Double Data Rate (DDR) channels within the socket require a wider channel bandwidth to effectively communicate data between electronic package architectures. Such sockets have Land Grid Array (LGA) land pads that exhibit a concentrated inductance effect from the socket pins themselves in series with a concentrated C effect. Thus, these series LC connections formed within the socket can cause increased reflection / loss, resonance problems, and limited channel bandwidth.

[0009] Furthermore, as described above, the LGA land pads are subject to a concentrated C effect due to their large pad size. By reducing the size (or area) of the land pads, the concentrated C effect can be reduced. However, since the pad size cannot be made smaller than the existing envelope contact area of each pad, the reduction of the pad size is substantially limited in order to have a reliable and wider channel bandwidth connection within the socket. Therefore, reducing the pad size adversely affects the requirement for a wider channel bandwidth and negates the advantages of implementing an LGA socket.

[0010] Accordingly, embodiments disclosed herein include an electronic package comprising a base layer having a plurality of pads with closed-loop transmission lines. The electronic packages disclosed below replace existing solid LGA land pads with closed-loop transmission lines (or traces), thereby converting the concentrated C effect into transmission line behavior-type characteristics. Thus, the embodiments described herein provide pads in the form of closed-loop transmission lines as an alternative to conventional solid land pads without experiencing the problems of the LGA socket described above.

[0011] The use of such transmission lines in the base layer of the electronic package enables the advantages of the electronic package assembly to be realized by removing the LGA land pad concentrated capacitance effect without significantly reducing the socket pad size and / or the need for an aggressive package void. That is, the package land pads according to the embodiments disclosed herein provide closed-loop transmission lines for high-speed data signaling that suppress the concentrated C effect and allow for increased scaling of channel speed / bandwidth. In particular, the closed-loop transmission lines effectively reduce the parasitic capacitance from the package pads and improve component / channel reflection and loss, for example, to support the speed scaling of PCIe and DDR channels. Additionally, the transmission lines also allow for a reduction in the physical size of the pads and a relaxation of the requirements regarding package voids (gaps) above the pads. Such closed-loop transmission lines further free up the design space within the electronic package, avoiding the need for costly tolerances and alignment control, while existing package design rules can be used to form the closed-loop transmission lines.

[0012] Next, referring to FIG. 1, a cross-sectional view of an electronic package 100 according to one embodiment is shown. In one embodiment, the electronic package 100 has a base layer 108. The base layer 108 functions as a conductive layer having land pad openings 105 and land pads 130. In one embodiment, the base layer 108 can be one of the bottom surface or the lowest surface. For example, the base layer 108 can be disposed directly above the upper surface of the socket. In one embodiment, the base layer 108 can be a ground plane in which the land pad openings 105 completely surround the land pads 130. The land pad openings 105 enable the land pads 130 to be electrically insulated from the base layer 108. For example, the land pad openings 105 can be spaced apart from the land pads 130 by an outer gap 109.

[0013] The outer gap 109 can function as a non-uniform spacing between the land pad openings 105 and the outer periphery of the land pads 130. That is, the outer gap 109 can have one or more different widths measured between one or more different portions of the land pad openings 105 and the outer periphery of the land pads 130. In one embodiment, the outer gap 109 can be filled with a dielectric material. For example, the dielectric layer can be a build-up film, a photoimageable dielectric (PID), an epoxy molding material, a solder resist material, or any other dielectric material. The dielectric material can be disposed within the outer gap 109 to form a surface of the dielectric material that is substantially coplanar with the surface of the land pads 130 (e.g., the exposed surface of the land pads 130).

[0014] In some embodiments, the land pads 130 can be any electrical contact pads that provide an electrical connection between the base layer 108 and the interconnect 123 of the electronic package 100. In one embodiment, the interconnect 123 can be any type of socket interconnect such as a pin. For example, the interconnect 123 can be a socket pin.

[0015] As described above, in an embodiment, the landing pad 130 may have an exposed surface that defines the footprint of the landing pad 130. In one embodiment, the landing pad 130 may have one or more portions of the exposed surface that are directly coupled to the interconnect 123. For example, the landing pad 130 may have at least first and second portions that are directly attached to and electrically coupled to the footprint 122 of a connector (or the like) of the interconnect 123. Thus, in some embodiments, the interconnect 123 may be electrically coupled to at least the first portion of the landing pad 130 and a portion of the inner gap 107 and / or the outer gap 109. In particular, in some embodiments, the interconnect 123 may be electrically coupled to at least the first portion of the landing pad 130, the second portion of the landing pad 130, and a portion of the inner gap 107 and / or the outer gap 109, and the second portion may be spaced from the first portion of the landing pad 130 by a portion of the inner gap 107 and / or the outer gap 109. Accordingly, in the illustrated embodiment, the first and second portions of the landing pad 130, and a portion of the inner gap 107 (and a portion of the outer gap 109) are all disposed within the footprint 122 of the interconnect 123. For example, the first and second portions may be the illustrated portions on the left side of the landing pad 130 (i.e., the two corner edges on the left side of the landing pad 130) that are within the footprint 122 and separated by the inner gap 107.

[0016] In one embodiment, the land pad 130 is an LGA land pad. In other embodiments, the land pad 130 can be any type of land pad. For example, the land pad 130 can be a ball grid array (BGA) pad, a land grid array (LGA) pad, a pin grid array (PGA) pad, etc. In one embodiment, the land pad 130 is a closed loop with an inner gap 107. Thus, the inner gap 107 enables the land pad 130 to have an outer perimeter and an inner perimeter on the opposite side of the outer perimeter. That is, the land pad 130 is sandwiched directly between the outer gap 109 and the inner gap 107. In particular, the outer perimeter of the land pad 130 interfaces directly with the outer gap 109, while the inner perimeter of the land pad 130 interfaces directly with the inner gap 107.

[0017] Furthermore, in the illustrated embodiment, the land pad 130 can have a width S that separates a portion of the outer perimeter from the other portion of the outer perimeter. 1 Similarly, in the illustrated embodiment, the land pad 130 can have a width S that separates a portion of the inner perimeter from the other portion of the inner perimeter. 2 Also, as shown in the illustrated embodiment, the outer perimeter of the land pad 130 is generally positioned within a footprint 110 that defines the maximum (or outermost) possible contact area for the interconnect 123. In one embodiment, the footprint 110 is spaced from the land pad opening 105 by a width S that functions as a land pad void region. 3 In one embodiment, the widths S 1 , S 2 , and S 3 can be greater than about 20 μm. In some embodiments, the widths S 1 , S 2 , and S 3 can be about 20 μm to 60 μm. In other embodiments, the widths S 1 , S 2 , and S 3can be less than about 20 μm according to the substrate design rules. In one embodiment, the width S 1 , S 2 , and S 3 can all be substantially equal to each other. In other embodiments, one or more of the widths S 1 , S 2 , and S 3 can be different from the other widths.

[0018] In one embodiment, the inner gap 107 can have fingers directly surrounded by the inner circumference of the land pad 130. Further, in one embodiment, the inner gap 107 can be filled with a dielectric material similar to the outer gap 109 described above. In one embodiment, the inner gap 107 and the outer gap 109 can include the same dielectric material or different dielectric materials. The dielectric material of the inner gap 107 can have a surface that is substantially coplanar with the surfaces of the outer gap 109 and the land pad 130.

[0019] In one embodiment, the land pad 130 can have a conductive line 131 that is patterned (or formed to be) in a closed loop of the land pad 130. That is, since existing LGA land pads are patterned (or shaped) into rectangular pads, circular pads, elliptical pads, etc., the land pad 130 is patterned into a closed loop using the conductive line 131. For example, the closed loop uses line spacing(s) (e.g., spacing S 1 , S 2 , and W) that are smaller than the footprint 122 of the nominal contact area of the interconnect 123 to occupy as many contact areas as possible within the footprint 110, and is thereby routed with the conductive line 131 to ensure proper electrical connection between the land pad 130 and the interconnect 123.

[0020] In one embodiment, the conductive line 131 is a continuous line (or wiring without breaks) extending from a first end to a second end opposite the first end. In some embodiments, the conductive line 131 is a serpentine line or the like. That is, in one embodiment, the conductive line 131 is patterned into an interdigitated serpentine-shaped line that combines with the fingers of the inner gap 107. In other embodiments, the conductive line 131 can be any type of line having any type of shape. In one embodiment, the conductive line 131 includes a conductive material such as copper.

[0021] In particular, in some embodiments, the conductive line 131 functions as a kind of transmission line for the land pad 130. For example, the conductive line 131 can be patterned into the illustrated closed-loop transmission line that is disposed entirely within the footprint 110 and extends continuously between the via 112 and the footprint 122 of the interconnect 123. In one embodiment, the via 112 can be a microvia or the like that electrically couples the land pad 130 in the base layer 108 to an adjacent conductive layer.

[0022] The conductive line 131 extends continuously within a closed loop from one end to the other opposite end (e.g., the respective ends on the left and right sides of the via 112) in order to provide transmission-like properties of the land pad 130. Thus, there is substantially no lumped C effect due to the land pad 130 in series with the interconnect 123. For example, the land pad 130 may exhibit a minimal inductive effect. However, by adjusting the width, bend, and spacing of the conductive line 131 to mimic the behavior of a transmission line (i.e., the closed-loop transmission line described above), the minimal inductive effect can be substantially mitigated, thereby enabling the land pad 130 to have substantially no parasitic impact on a high-speed channel. Accordingly, the land pad 130 can eliminate the lumped C effect for scaling a PCIe channel, a DDR channel, or any other high-speed channel, and can improve both the return loss and insertion loss of such high-speed channels at high frequencies. Therefore, there is no need to reduce the size of the land pad, nor is there a need to use a positive void around the land pad that adversely affects the electrical connection between the electronic package 100, the socket interconnect 123, and / or any additional electronic components.

[0023] The conductive line 131 has a width W defined between an outer perimeter and an inner perimeter of the land pad 130. In one embodiment, the width W can be a uniform width that can be greater than about 20 μm. In some embodiments, the width W can be between about 20 μm and 60 μm. In other embodiments, the width W can be less than 20 μm depending on the substrate design rules. In another embodiment, the width W can have one or more different widths between about 20 μm and 60 μm, or less than about 60 μm. In one embodiment, the conductive line 131 can have a length. For example, the length can be greater than about 2 mm. In some embodiments, the length can be between about 2 mm and 5 mm. In other embodiments, the length can be less than about 2 mm depending on the substrate design rules.

[0024] Note that the electronic package 100 may include fewer or additional package components based on a desired package design.

[0025] Next, referring to FIG. 2, a plan view of an electronic package assembly 200 according to an additional embodiment is shown. In one embodiment, the electronic package assembly 200 has an electronic package 250 and a socket 202. In the illustrated embodiment, the electronic package 250 has a base layer 208 with a plurality of land pads 230 and 232 disposed directly on top of the socket 202. In an embodiment, the socket 202 can be any type of socket. In one embodiment, the socket 202 is an LGA socket. In particular, in one embodiment, the electronic package 250 is electrically coupled to the socket 202 by a plurality of interconnects 223. In an embodiment, the interconnects 223 can each have a connector 222 directly coupled to the respective land pads 230 and 232.

[0026] In one embodiment, the electronic package 250 can be substantially similar to the electronic package 100 of FIG. 1, except that the land pad 232 can be a ground pad and the land pad 230 is a differential pair of closed-loop pads having conductive lines 231 mounted with transmission line-like characteristics as described above. As such, in one embodiment, the land pad openings 205, inner and outer gaps 207 and 209, vias 212, and land pads 230 having conductive lines 231 can be substantially similar to the land pad openings 105, inner and outer gaps 107 and 109, vias 112, and land pads 130 having conductive lines 131 of FIG. 1. In some embodiments, the land pads 230 can be paired as differential signal nets and each coupled to an interconnect 223 that transmits a differential signal. However, it should be understood that any type of interconnect and signal can be coupled to the land pads 230 of the electronic package 250. Also, although only two land pads 230 are shown in FIG. 2, it should be understood that embodiments can include any number of land pads 230.

[0027] Note that the electronic package assembly 200 may include fewer or additional package components based on the desired package design.

[0028] Next, referring to FIG. 3, a cross-sectional view of an electronic package assembly 300 according to an additional embodiment is shown. In one embodiment, the electronic package assembly 300 includes an electronic package 350, a socket 302, and a board 351. In one embodiment, the electronic package assembly 300 may be substantially similar to the electronic package assembly 200 of FIG. 2, except that the socket 302 may be directly and electrically coupled to the board 351. In one embodiment, the board 351 is a printed circuit board (PCB), a motherboard, a substrate, or the like.

[0029] In some embodiments, the socket 302 may electrically couple the electronic package 350 to the board 351 by an interconnect 323. In the illustrated embodiment, the electronic package 350 has a base layer 308 having land pads 330 and 332 disposed directly on the interconnect 323 of the socket 302. In particular, the land pads 330 and 332 are directly coupled to the connector 322 of the interconnect 323.

[0030] In one embodiment, the electronic package 350 may be substantially similar to the electronic packages 100 and 250 of FIGS. 1-2. Thus, in some embodiments, the land pad 330 having the land pad opening 305 and the conductive line 331 may be substantially similar to the land pad 130 having the land pad opening 105 and the conductive line 131 of FIG. 1. In the illustrated embodiment, the land pad 330 may be a differential signal net directly coupled to each interconnect 323 for transmitting a differential signal between a first port 342 within the electronic package 350 and a second port 343 within the board 351.

[0031] Board 351 may have a conductive layer 301 with conductive pads 352. In one embodiment, board 351 may be directly coupled to socket 302 by solder balls 333 or the like. That is, in some embodiments, the conductive pads 352 of board 351 may be directly coupled to the conductive pads 321 (or the second connector) of interconnect 323 using solder balls 333. Also, although only two land pads 330 and ports 342 - 343 are shown in FIG. 3, it should be understood that embodiments may include any number of land pads 330 and ports 342 - 343.

[0032] Note that electronic package assembly 300 may include fewer or additional package components based on the desired package design.

[0033] Next, referring to FIGS. 4A - 4C, a series of plan views of an electronic package 400 according to some embodiments are shown. In one embodiment, the electronic package 400 of FIGS. 4A - 4C may be substantially similar to the electronic package 100 of FIG. 1, except that interconnect 423 may have three different footprints 422a - c respectively disposed at three different contact positions of land pads 430. Thus, in some embodiments, the base layer 408, interconnect 423, and land pads 430 having land pad openings 405, inner and outer gaps 407 and 409, vias 412, and conductive lines 431 of FIGS. 4A - 4C may be substantially similar to the base layer 108, interconnect 123, and land pads 130 having land pad openings 105, inner and outer gaps 107 and 109, vias 112, and conductive lines 131 of FIG. 1.

[0034] In the illustrated embodiment, since all regions enclosed by the footprint 410 (shown by the dashed line) are possible contact positions for the interconnect 423, the land pad 430 can be coupled to the interconnect 423 respectively with different footprints 422a - c as shown in FIGS. 4A - 4C. In one embodiment, the different contact positions may have very little impact on the reflection and loss of the interconnect 423, as well as on the land pad 430 itself. In some embodiments, the land pad 430 may have a smaller concentrated C effect when the footprint of the interconnect 423 is far from the via 412 (e.g., as shown by the footprint 422c in FIG. 4C compared to the other possible footprints 422a - b in FIGS. 4A - 4B). Also, although three different footprint positions are shown in FIGS. 4A - 4C, it should be understood that the embodiment includes any possible footprint position on the land pad 430 enclosed by the envelope 410.

[0035] Note that the electronic package 400 may include fewer or additional package components based on the desired package design.

[0036] Next, referring to FIG. 5, a cross - sectional view of an electronic package assembly 500 (or electronic package system) according to one embodiment is shown. In one embodiment, the electronic package assembly 500 may have an electronic package 550 similar to the electronic package 100 of FIG. 1. For example, the electronic package 550 may have a base layer 508 with land pad openings 505 and land pads 530. Also, in one embodiment, the land pad 530 may have conductive traces 531 that are directly patterned in a closed loop as shown for the land pad 130 in FIG. 1.

[0037] Regarding some embodiments, the electronic package assembly 500 may include a die 514, a substrate 513, an electronic package 550, a socket 502, and a board 551, according to one embodiment. As shown in FIG. 5, in one embodiment, the electronic package assembly 500 may include a die 514 disposed on a substrate 513 (or an interposer) and a stack of the die 514 and the substrate 513 respectively disposed on the electronic package 550. Additionally, regarding some embodiments, the semiconductor package assembly 500 may include a socket 502 for electrically coupling the electronic package 550 to the board 551. In one embodiment, the connector 522 of the interconnect 523 may be used to directly couple the socket 502 to the land pads 530 of the electronic package 550, while the connector 521 of the interconnect 523 may be used to directly couple the socket 502 to the board 551 by solder balls 533. As described above, in some embodiments, the land pads 530 may be patterned with conductive lines 531 in the form of closed-loop transmission lines to suppress the concentrated C effect of the land pads, scale PCIe and DDR speeds (e.g., PCIe generation 5 / 6 speeds, etc.), and significantly reduce the need for reduced socket pad size and / or positive package voids.

[0038] In these embodiments, the electronic package 550, the socket 502, and the board 551 may be substantially similar to the electronic package 350, the socket 302, and the board 351 of FIG. 3. Also, in an embodiment, the interconnect 523 and the land pads 530 having the land pad openings 505 and the conductive lines 531 may be substantially similar to the interconnect 123 and the land pads 130 having the land pad openings 105 and the conductive lines 131 of FIG. 1. It should be noted that the semiconductor package assembly 500 is not limited to the illustrated assembly / system, and thus may be designed / formed with fewer, alternative or additional package components, and / or different interconnect structures.

[0039] According to one embodiment, the electronic package assembly 500 is merely an example of an embodiment of an electronic package assembly (or system). In one embodiment, the electronic package assembly 500 may include a BGA package, an LGA package, and / or a PGA package. In one embodiment, the die 514 is coupled to a substrate 513 (e.g., an interposer) via one or more solder balls 518 (or bumps / joints) formed from respective microbumps, and the substrate 513 is coupled to an electronic package 550 via one or more solder balls 516 formed from respective microbumps. As described above, the solder balls formed by soldering microbumps according to one embodiment may be referred to as "bumps" and / or "microbumps" themselves. Further, one or more of the die 514, the substrate 513, the electronic package 550, and the board 551 may be coupled using an anisotropic conductive film (ACF) or the like. In one embodiment, the substrate 513 may be, but is not limited to, a silicon interposer and / or a die having through-silicon vias (TSVs). In another embodiment, the semiconductor package assembly 500 may omit the interposer / substrate 513.

[0040] The electronic package 550 can include various electronic structures formed thereon or therein. In certain embodiments, the electronic package assembly 500 can be an organic substrate composed of one or more layers of a polymer-based material or a ceramic-based material that includes conductive regions for transmitting signals. In some embodiments, the electronic package assembly 500 can include, but is not limited to, packages, substrates, PCBs, central processing unit (CPU) package substrates, and motherboards. In one embodiment, the electronic package 550 is a PCB and / or a CPU package substrate (or an electronic package substrate), while the board 551 is a motherboard. In one embodiment, the electronic package 550 is made of FR-4 glass epoxy-based with thin copper foils laminated on both sides. In certain embodiments, a multilayer electronic package 550 can be used, and additional layers can be fabricated using prepregs and copper foils. For example, the multilayer electronic package 550 can include one or more dielectric layers. In one embodiment, the electronic package 550 can include one or more conductive layers, which can further include copper (or metal) wiring, traces, pads, vias, holes, and / or planes.

[0041] In one embodiment, die 514 can include, but is not limited to, a semiconductor die, an electronic device (e.g., a wireless device), an IC, a CPU, a graphics processing unit (GPU), a microprocessor, a platform controller hub (PCH), a memory (e.g., high bandwidth memory (HBM)), and / or a field programmable gate array (FPGA). Further, in other embodiments, die 514, substrate 513, and / or electronic package 550 can be composed of one or more materials including glass, crystal, diamond, low thermal conductivity materials, high thermal conductivity materials (e.g., gallium nitride (GaN), etc.), silicon, glass-based materials, and / or silicon-based materials (e.g., silicon carbide (SIC), etc.). Also, in other embodiments, die 514 can be a plurality of chiplet dies. Die 514, substrate 513, and / or electronic package 550 can be formed from a material such as silicon and can have circuits thereon that are coupled to each other and / or to any other electronic device.

[0042] Some embodiments, but not limited to this point, board 551 may be coupled to another body. One or more connections (e.g., including some or all of bumps 516, 518, and 533) between one or more of die 514, substrate 513, electronic package 550, socket 502, and board 551 can include one or more interconnect structures and underfill layers 526 and 528. In some embodiments, these interconnect structures (or connections) can variously include alloys of nickel, palladium, and tin (and, in some embodiments, copper).

[0043] Connections between one or more of die 514, substrate 513, electronic package 550, socket, and board 551 can be made using any suitable structure such as exemplary bumps 516, 518, and 533 shown. Some embodiments, but not limited to this point, the electronic package assembly 500 may include, for example, a gap control structure 543 disposed between die 514, substrate 513, and electronic package 550. Such a gap control structure 543 can mitigate changes in the height of the gap between die 514, substrate 513, and electronic package 550. Note that the electronic package assembly 500 includes an underfill material 528 between die 514 and substrate 513, and an underflow material 526 between substrate 513 and electronic package 550. Also note that the underfill material may be disposed between any other components as needed. In one embodiment, the underfill materials (or layers) 526 and 528 can be one or more polymers injected between layers. In other embodiments, the underfill material can be a molded underfill (MUF).

[0044] Note that the electronic package assembly 500 may include fewer or additional package components based on the desired package design.

[0045] Figure 6 shows a computing device 600 according to one implementation of the present invention. Figure 6 shows an example of a computing device 600. The computing device 600 houses a motherboard 602. The motherboard 602 may include some components including, but not limited to, a processor 604, a device package 610 (or electronic package), and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some embodiments, at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In other embodiments, at least one communication chip 606 is part of the processor 604.

[0046] Depending on its use, computing device 600 may include other components that may or may not be physically and electrically coupled to motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0047] At least one communication chip 606 enables wireless communication for transferring data with computer device 600. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can communicate data via the use of electromagnetic radiation modulated through a non-solid medium. In some embodiments, this term does not mean that the associated devices may not include wires, although the associated devices may not include wires. At least one communication chip 606 can implement any of a wireless standard or protocol including, but not limited to, Wi-Fi (R) (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GPRS, CDMA, TDMA, DECT, Bluetooth (R), their derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and beyond. Computing device 600 may include a plurality of communication chips 606. For example, a first communication chip 606 may be dedicated to shorter range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 606 may be dedicated to longer range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0048] The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. The term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory in order to convert it into other electronic data that can be stored in registers and / or memory. The device package 610 can be an electronic package. In one embodiment, the device package 610 can be substantially similar to the electronic package 100 of FIG. 1. The device package 610 can include land pads having conductive traces patterned in a closed loop (or closed loop transmission line), as described herein (e.g., as illustrated and described using the land pads of FIGS. 1-3, 4A-4C, and 5), or any other component from the figures described herein.

[0049] Note that the device package 610 can be a single component / device, a subset of components, and / or the entire system, as materials, features, and components can be limited to the device package 610, which may require land pads with closed loop transmission lines as described herein, and / or any other component of the computing device 600 (e.g., the motherboard 602, the processor 604, the communication chip 606, and / or any other component of the computing device 600 that may require the embodiments described herein).

[0050] At least one communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In some embodiments, the integrated circuit die of the communication chip 606 can be packaged with one or more devices on an electronic package that includes one or more land pads with closed loop transmission lines, as described herein.

[0051] In the foregoing specification, embodiments have been described with reference to their specific exemplary embodiments. However, it should be noted that all of the above terms and similar terms correspond to appropriate physical quantities and are merely convenient labels applied to these physical quantities. It will be apparent that various modifications can be made without departing from the broader spirit and scope. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a limiting sense.

[0052] The following examples relate to further embodiments. Various features of different embodiments may be variously combined with some of the features included, and other features may be excluded to suit various different applications.

[0053] The following examples relate to further aspects:

[0054] Example 1: An assembly comprising: a socket having an interconnect portion, the interconnect portion having a first connector and a second connector on the opposite side of the first connector; an electronic package on the socket, the electronic package having a first surface and a second surface on the opposite side of the first surface, the second surface having land pads within land pad openings, the land pads being spaced from the land pad openings by an outer gap, the land pads being a closed loop having an inner gap, the closed loop being directly between the outer gap and the inner gap, the first connector of the interconnect portion being electrically coupled to at least a portion of the closed loop and a portion of the inner or outer gap.

[0055] Example 2: The assembly of Example 1, wherein the first connector of the interconnect portion is also electrically coupled to a second portion of the closed loop, the second portion being spaced from the portion of the closed loop by the portion of the inner or outer gap.

[0056] Example 3: The assembly of Examples 1 - 2, wherein the closed loop has an outer perimeter and an inner perimeter.

[0057] Example 4: The assembly of Examples 1-3, wherein the outer perimeter directly interfaces with the outer gap and the inner perimeter directly interfaces with the inner gap.

[0058] Example 5: The assembly of Examples 1-4, wherein the closed loop of the land pad is electrically coupled to the first connector of the interconnect.

[0059] Example 6: The assembly of Examples 1-5, wherein the closed loop has a conductive line having a first end and a second end opposite the first end, and the conductive line extends continuously from the first end to the second end.

[0060] Example 7: The assembly of Examples 1-6, further comprising: a conductive layer electrically coupled to the closed loop of the land pad by vias, the conductive layer being disposed on the second surface, and the first and second ends of the conductive line being directly coupled to the vias; a die electrically coupled to the electronic package, the die being on the first surface of the electronic package, and the second surface of the electronic package being on the board; and a board electrically coupled to the socket, the second connector of the interconnect being coupled to the board.

[0061] Example 8: The assembly of Examples 1-7, wherein the portion of the closed loop and the second portion are within the footprint of the first connector, and the portion of the inner or outer gap is also within the footprint of the first connector.

[0062] Example 9: The assembly of Examples 1-8, wherein the conductive line is a serpentine line.

[0063] Example 10: A package substrate comprising: a substrate having a first surface and a second surface opposite the first surface; a plurality of land pad openings in the second surface; a plurality of land pads in the second surface, each of the land pads being within one of the land pad openings, each of the land pads being spaced from the land pad opening by an outer gap, each of the land pads being a closed loop with an inner gap, the closed loop being directly between the outer gap and the inner gap, the closed loop having a conductive line having a first end and a second end opposite the first end, the conductive line continuously extending from the first end to the second end; and a plurality of land pads.

[0064] Example 11: The package substrate of Example 10, wherein the closed loop has an outer perimeter and an inner perimeter, the outer perimeter being directly connected to the outer gap and the inner perimeter being directly connected to the inner gap.

[0065] Example 12: A conductive layer electrically coupled to the closed loop of the land pad by a via, the conductive layer being disposed on the second surface, the first and second ends of the conductive line being directly coupled to the via; and an interconnect having a connector, the connector being directly beneath the closed loop. The package substrate of Examples 10 - 11 further comprises the above.

[0066] Example 13: The package substrate of Examples 10 - 12, wherein the connector of the interconnect is electrically coupled to at least a first portion of the closed loop and a portion of the inner or outer gap.

[0067] Example 14: The package substrate of Examples 10 - 13, wherein the connector of the interconnect is also electrically coupled to a second portion of the closed loop, the second portion being spaced from the first portion by the portion of the inner or outer gap.

[0068] Example 15: The first and second portions of the closed loop are within the footprint of the connector, and the portions of the inner or outer gap are also within the footprint of the connector, the package substrate of Examples 10 - 14.

[0069] Example 16: The conductive line is a serpentine line, the package substrate of Examples 10 - 15.

[0070] Example 17: An electronic package assembly comprising: a board; a socket electrically coupled to the board, the socket having a plurality of interconnects, each of the interconnects having a first connector and a second connector on the opposite side of the first connector; an electronic package electrically coupled to the socket, the electronic package having a first surface and a second surface on the opposite side of the first surface, the second surface having a plurality of land pad openings and a plurality of land pads, each land pad being within one of the land pad openings, each land pad being spaced from the respective land pad opening by an outer gap, each land pad being a closed loop, the closed loop being directly between the outer gap and an inner gap, the first connector of the interconnect being electrically coupled to at least a first portion of the closed loop, a second portion of the closed loop, and a portion of the inner or outer gap; a die electrically coupled to the electronic package.

[0071] Example 18: The second portion is spaced from the first portion by the portion of the inner or outer gap, the electronic package assembly of Example 17.

[0072] Example 19: The closed loop of the land pad is electrically coupled to the first connector of the interconnect, the die is on the first surface of the electronic package, the second surface of the electronic package is on the board, and the second connector of the interconnect is coupled to the board. The electronic package assembly of Examples 17 - 18.

[0073] Example 20: The closed loop has a conductive line having a first end and a second end opposite the first end, and the conductive line extends continuously from the first end to the second end. The electronic package assembly of Examples 17 - 19.

[0074] Example 21: The closed loop has an outer perimeter and an inner perimeter. The electronic package assembly of Examples 17 - 20.

[0075] Example 22: The outer perimeter is directly connected to the outer gap, and the inner perimeter is directly connected to the inner gap. The electronic package assembly of Examples 17 - 21.

[0076] Example 23: Further includes a conductive layer electrically coupled to the closed loop of the land pad by vias, the conductive layer is disposed above the second surface of the electronic package, and the first and second ends of the conductive line are directly coupled to the vias. The electronic package assembly of Examples 17 - 22.

[0077] Example 24: The first and second portions of the closed loop are within the footprint of the first connector, and the portion of the inner or outer gap is also within the footprint of the first connector. The electronic package assembly of Examples 17 - 23.

[0078] Example 25: The conductive line is a serpentine line. The electronic package assembly of Examples 17 - 24.

[0079] The foregoing description of illustrative implementations of the invention, including what is set forth in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Specific implementations and examples of the invention are described herein for illustrative purposes, but as will be understood by those of ordinary skill in the art, various equivalent modifications are possible within the scope of the invention.

[0080] These modifications can be added to the invention in light of the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific implementations disclosed in the specification and claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established principles of claim interpretation.

[0081] In the foregoing specification, methods and devices have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made without departing from the broader spirit and scope. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A socket having an interconnecting portion, wherein the interconnecting portion has a first connector and a second connector on the opposite side of the first connector, the socket; An electronic package on the socket, the electronic package having a first surface and a second surface on the opposite side of the first surface, the second surface having land pads within a land pad opening, the land pads being spaced from the land pad opening by an outer gap, the land pads being a closed loop having an inner gap, the closed loop being directly between the outer gap and the inner gap, the first connector of the interconnecting portion being electrically coupled to at least a portion of the closed loop and a portion of the inner or outer gap, the electronic package; having An assembly.

2. The first connector of the interconnecting portion is also electrically coupled to a second portion of the closed loop, the second portion being spaced from the portion of the closed loop by the portion of the inner or outer gap, The assembly according to claim 1.

3. The closed loop has an outer circumference and an inner circumference, The assembly according to claim 1 or 2.

4. The outer circumference is directly connected to the outer gap, and the inner circumference is directly connected to the inner gap, The assembly according to claim 3.

5. The closed loop of the land pad is electrically coupled to the first connector of the interconnecting portion, The assembly according to claim 1 or 2.

6. The closed loop has a conductive line having a first end and a second end on the opposite side of the first end, the conductive line extending continuously from the first end to the second end, The assembly according to claim 1 or 2.

7. A conductive layer electrically coupled to the closed loop of the land pad by vias, the conductive layer being disposed on the second surface, the first and second ends of the conductive line being directly coupled to the vias, the conductive layer; A die electrically coupled to the electronic package, the die being on the first surface of the electronic package, the die; A board electrically coupled to the socket, the second connector of the interconnecting portion being coupled to the board, the board; Further comprising The second surface of the electronic package is on the board, The assembly according to claim 6.

8. The portion of the closed loop and the second portion are within the footprint of the first connector, and the portion of the inner or outer gap is also within the footprint of the first connector. The assembly according to claim 2.

9. The conductive line is a circuitous line. The assembly according to claim 6.

10. A package substrate comprising: A substrate having a first surface and a second surface opposite the first surface; A plurality of land pad openings in the second surface; A plurality of land pads in the second surface, each of the land pads being within one of the land pad openings, each of the land pads being spaced from the land pad opening by an outer gap, each of the land pads being a closed loop with an inner gap, the closed loop being directly between the outer gap and the inner gap, the closed loop having a conductive line with a first end and a second end opposite the first end, the conductive line extending continuously from the first end to the second end; a plurality of land pads; Having Package substrate.

11. The closed loop has an outer circumference and an inner circumference, the outer circumference being directly connected to the outer gap, and the inner circumference being directly connected to the inner gap. The package substrate according to claim 10.

12. A conductive layer electrically coupled to the closed loop of the land pad by a via, the conductive layer being disposed on the second surface, the first and second ends of the conductive line being directly coupled to the via; a conductive layer; An interconnect having a connector, the connector being directly below the closed loop; an interconnect; Further having The package substrate according to claim 10 or 11.

13. The connector of the interconnect is electrically coupled to at least a first portion of the closed loop and a portion of the inner or outer gap. The package substrate according to claim 12.

14. The connector of the interconnect is also electrically coupled to a second portion of the closed loop, the second portion being spaced from the first portion by the portion of the inner or outer gap. The package substrate according to claim 13.

15. The first and second portions of the closed loop are within the footprint of the connector, and the portions of the inner or outer gap are also within the footprint of the connector. The package substrate according to claim 14. **Claim 16** The conductive line is a circuitous line. The package substrate according to claim 10 or 11. **Claim 17** An electronic package assembly comprising: A board; A socket electrically coupled to the board, the socket having a plurality of interconnects, each of the interconnects having a first connector and a second connector on the opposite side of the first connector; An electronic package electrically coupled to the socket, the electronic package having a first surface and a second surface on the opposite side of the first surface, the second surface having a plurality of land pad openings and a plurality of land pads, each land pad being within one of the land pad openings, each land pad being spaced from its respective land pad opening by an outer gap, each land pad being a closed loop, the closed loop being directly between the outer gap and an inner gap, the first connector of the interconnect being electrically coupled to at least a first portion of the closed loop, a second portion of the closed loop, and a portion of the inner or outer gap; A die electrically coupled to the electronic package; And having An electronic package assembly. **Claim 18** The second portion is spaced from the first portion by the portion of the inner or outer gap. The electronic package assembly according to claim 17. **Claim 19** The closed loop of the land pad is electrically coupled to the first connector of the interconnect, the die is on the first surface of the electronic package, the second surface of the electronic package is on the board, and the second connector of the interconnect is coupled to the board. The electronic package assembly according to claim 17 or 18. **Claim 20** The closed loop has a conductive line having a first end and a second end on the opposite side of the first end, and the conductive line extends continuously from the first end to the second end. The electronic package assembly according to claim 17 or 18.

21. The closed loop has an outer circumference and an inner circumference, The electronic package assembly according to claim 17 or 18.

22. The outer circumference is directly connected to the outer gap, and the inner circumference is directly connected to the inner gap, The electronic package assembly according to claim 21.

23. The land pad further has vias that electrically couple the closed loop to a conductive layer, the conductive layer is disposed above the base layer, and the first and second ends of the conductive line are directly coupled to the vias, The electronic package assembly according to claim 20.

24. The first and second portions of the closed loop are within the footprint of the first connector, and the portions of the inner or outer gap are also within the footprint of the first connector, The electronic package assembly according to claim 17 or 18.

25. The conductive line is a serpentine line, The electronic package assembly according to claim 20.

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