Organic interposer structure, method for manufacturing the same, and packaging structure

Abstract

To provide an organic interposer structure, a method for manufacturing the same, and a packaging structure.SOLUTION: An organic interposer structure has a rewiring layer 300 and a solder mask layer 504. The rewiring layer 300 includes a medium layer 301 and a circuit layer 304 on the medium layer 301. A via pillar 303 for conductively connecting the circuit layer 304 is provided in the medium layer 301. In the solder mask layer 504, a first pad 501 that is located in a circuit layer on a surface of the rewiring layer 300 and formed by a via pillar exposed on a surface of the rewiring layer 300 and a second pad 502 formed on the circuit layer 304 exposed on the solder mask layer 504 are provided. A height of the first pad 501 is lower than that of the medium layer 301 on which the first pad 501 is positioned.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductors, and more particularly, to an organic interposer structure, a method for manufacturing the same, and a packaging structure.

Background Art

[0002] As Moore's Law is approaching its end, advanced packaging technology has become one of the important factors for further improving chip performance and achieving higher density integration of semiconductor packaging structures. In recent years, various advanced packaging technologies such as 2D packaging and 2.5D packaging have been proposed and widely used.

Summary of the Invention

Problems to be Solved by the Invention

[0003] In view of this, an object of the present disclosure is to propose an organic interposer structure, a method for manufacturing the same, and a packaging structure.

Means for Solving the Problems

[0004] For the above object, as a first aspect, the present disclosure provides: (a) providing a mounting plate; (b) applying a temporary bonding layer to the mounting plate; (c) applying a photosensitive medium layer to the temporary bonding layer; (d) forming a window in the photosensitive medium layer and performing metallization to form a circuit layer, wherein the window forms via pillars; (e) repeating steps (c) and (d) until a target number of layers is reached in the circuit layer; (f) debonding the temporary bonding layer, removing the mounting plate, and exposing the via pillars. (g) Thinning the exposed via pillar to form a first pad, and forming a solder mask layer on the surface of the outermost exposed circuit layer, wherein the solder mask layer exposes some circuit layers to form a second pad; (h) providing a method for manufacturing an organic interposer structure, including performing a metal surface treatment on the first pad and the second pad.

[0005] In some embodiments, the material of the placement plate is glass or an acrylic-based material.

[0006] In some embodiments, the thickness of the placement plate is 200 - 1000 μm.

[0007] In some embodiments, the material of the temporary bonding layer is selected from an ultraviolet-decomposable adhesive tape, a heat-peelable adhesive tape, or a weak adhesive tape.

[0008] In some embodiments, step (c) specifically includes: applying a photosensitive medium material to the temporary bonding layer to form an organic photosensitive medium layer; forming the window in the organic photosensitive medium layer by an exposure and development method.

[0009] In some embodiments, step (d) specifically includes: applying a metal seed layer to the photosensitive medium layer; providing a photoresist layer on the surface of the metal seed layer, and forming a circuit layer pattern through exposure and development; electroplating the circuit layer pattern to form a via pillar and a circuit layer; removing the photoresist layer; etching the exposed metal seed layer.

[0010] In some embodiments, the surface treatment in step (h) includes OSP, ENEPIG, or ball attachment.

[0011] In some embodiments, the material of the solder mask layer is a photosensitive medium material.

[0012] In some embodiments, the first pad is used to connect a chip, and the second pad is used to connect a packaging substrate.

[0013] As a second aspect, the present disclosure provides a redistribution layer including at least two stacked wiring units, each wiring unit including a medium layer and a circuit layer on the medium layer, and via pillars connecting the circuit layers are provided in the medium layer; a solder mask layer covering the circuit layer on the surface of the redistribution layer; a first pad formed by a via pillar exposed on the surface of the redistribution layer and a second pad formed in a circuit layer exposed in the solder mask layer, the first pad having a height lower than the height of the medium layer, and an organic interposer structure including the first pad and the second pad.

[0014] In some embodiments, the first pad is used to connect a chip, and the second pad is used to connect a packaging substrate.

[0015] In some embodiments, the material of the solder mask layer is a photosensitive medium material.

[0016] As a third aspect, the present disclosure provides a packaging structure including the organic interposer structure according to any one of the second aspects.

[0017] In some embodiments, a chip and a packaging substrate are further included, provided that the chip is connected to the first pad and the packaging substrate is connected to the second pad.

Advantages of the Invention

[0018] As can be seen from the above description, the organic interposer structure, its manufacturing method, and the packaging structure provided by the present disclosure utilize a photosensitive medium material to form an organic interposer, realize the fabrication of ultra-fine circuits and micro solder mask windows, meet the flip-chip packaging of high-density I / O chips, and have the technical effects of low processing difficulty and low cost.

Brief Description of the Drawings

[0019] Hereinafter, to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced. Needless to say, the drawings described below are only embodiments of the present disclosure, and those skilled in the art can obtain other drawings from these drawings without performing any novel work. In the drawings, for better understanding and easier description, the thicknesses and shapes of some layers and regions may be exaggerated.

Fig. 1(a)

Fig. 1(b)

Fig. 1(c)

Fig. 1(d)

Fig. 1(e)

Fig. 1(f)

Fig. 1(g)

Fig. 1(h)

Fig. 1(i)

Fig. 1(j)

Fig. 1(k)

Fig. 1(l)

Fig. 2

Fig. 3

DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, the present disclosure will be described in more detail with reference to the drawings using specific embodiments so that the object, technical solution, and advantages of the present disclosure become clearer.

[0021] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure have the ordinary meanings understood by those skilled in the art. The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not represent any order, quantity or importance, but are used to distinguish different components. The term "including" or similar terms means that the elements or objects appearing before the term cover the elements or objects listed next to the term and their equivalents, but do not exclude other elements or objects. The term "connection" or similar terms is not limited to physical or mechanical connections, and may include electrical connections whether direct or indirect. When describing the positional relationship between two components using terms such as "above", "upper", "below", "horizontal", etc., one or more components may be located between the two components unless these terms are used together with the terms "adjacent" or "direct". When one element or layer is provided "above" another element or layer, another layer or element may be inserted directly above the other element or between them.

[0022] Currently, 2D packaging technology is to directly integrate multiple chips of different types on the surface of a substrate for packaging. The interconnection of chips is realized by the wiring of the substrate, which has good reliability. However, the interconnection density of multiple chips is limited by the process capabilities of the packaging substrate, so the integration density is low. To achieve high-density heterogeneous integration, a packaging substrate with a finer linewidth / line space (L / S for short), more layers, and a larger unit size is required, but it is difficult to meet the process capabilities of the substrate.

[0023] 2.5D packaging provides an interposer between the packaging substrate and the chip. The interposer realizes the interconnection between chips and the interconnection between the chip and the packaging carrier by means of through-silicon vias (TSVs). The interposer including through-silicon vias can realize fine wiring, but requires advanced processing equipment. Therefore, the production of large panels cannot be realized, and the cost of silicon wafers is high, and the processing cost is high.

[0024] In view of this, a first aspect of an embodiment of the present disclosure provides a method for manufacturing an organic interposer structure. FIGS. 1(a) to 1(l) show cross-sectional schematic views of intermediate structures of each step of a method for manufacturing an organic interposer structure according to an embodiment of the present disclosure.

[0025] The manufacturing method includes the following steps. As shown in FIG. 1(a), a mounting plate 100 is provided (step (a)).

[0026] In some embodiments, the material of the mounting plate 100 is a glass or acrylic-based material. The smooth surface of the glass or acrylic-based material helps to realize the fabrication of ultra-fine circuits.

[0027] Note that the thickness of the mounting plate 100 may be determined according to needs, and the present disclosure is not limited thereto. Exemplarily, the thickness of the mounting plate 100 is 200 to 1000 μm, for example, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 800 μm, 1000 μm.

[0028] Subsequently, as shown in FIG. 1(b), a temporary bonding layer 101 is formed on the mounting plate 100 (step (b)). Generally, the temporary bonding layer 101 has weak adhesiveness and can be used to adhere components. Since the adhesiveness weakens after debonding, it helps to remove the mounting plate 100. The temporary bonding layer 101 may be formed by spin coating and / or coating of a liquid resin, or may be formed by pressing a dry film.

[0029] Optionally, the material of the temporary bonding layer is selected from an ultraviolet-decomposable adhesive tape, a heat-peelable adhesive tape, or a weak adhesive tape.

[0030] Next, as shown in FIGS. 1(c) and 1(d), an organic photosensitive medium layer 201 having a window is formed on the temporary bonding layer 101 (step (c)).

[0031] In some embodiments, as shown in FIG. 1(c), step (c) specifically includes the step of applying a photosensitive medium material to the temporary bonding layer 101 to form an organic photosensitive medium layer 201. Here, the forming method of the organic photosensitive medium layer 201 may be pressing or coating, and the present disclosure is not limited thereto. Subsequently, as shown in FIG. 1(d), a window 202 is formed in the organic photosensitive medium layer 201 by an exposure and development method. Note that the resolution of the photosensitive medium material is very excellent. As an example, in order to realize the fabrication of a minute window, a photosensitive medium material with a thickness of 25 μm can be applied to form a window with a diameter of 25 μm.

[0032] Subsequently, as shown in FIG. 1(e), a via pillar 203 is formed at the position of the window 202, and a circuit layer 204 is formed on the organic photosensitive medium layer 201 (step (d)).

[0033] As a specific example, step (d) specifically includes the following. A metal seed layer is applied to the organic photosensitive medium layer 201, and then a photoresist layer is provided on the surface of the metal seed layer. After exposure and development, a circuit layer pattern is formed. Next, electroplating is performed to form the via pillar 203 and the circuit layer 204. Subsequently, the photoresist layer is removed, and finally, the metal seed layer is etched to expose the organic photosensitive medium layer 201.

[0034] Note that the above embodiments are merely exemplary, and those skilled in the art may select an appropriate process for forming the via pillar 203 and the circuit layer 204 based on actual production conditions.

[0035] Next, as shown in FIGS. 1(f) to 1(h), steps (c) and (d) are repeated until the target number of layers is reached in the circuit layer (step (e)).

[0036] Hereinafter, with reference to FIGS. 1(f) to 1(h), an embodiment in which steps (c) and (d) are repeated will be described in detail by taking the case where the target number of layers is three layers as an example. Note that the fabrication of the first organic photosensitive medium layer, the first via pillar, and the first circuit layer respectively corresponds to the organic photosensitive medium layer 201, the via pillar 203, and the circuit layer 204, and detailed descriptions thereof are omitted.

[0037] As shown in FIG. 1(f), a photosensitive medium material is applied to the first circuit layer to form a second organic photosensitive medium layer 301 including a second window 302. As shown in FIG. 1(g), a second via pillar 303 is formed at the position of the window 302, and a second circuit layer 304 is formed on the second organic photosensitive medium layer 301. As shown in FIG. 1(h), using the same method, a third photosensitive medium layer 401, a third via pillar 403, and a third circuit layer 404 are formed on the second circuit layer 304.

[0038] Here, the materials of the first photosensitive medium layer, the second photosensitive medium layer 301, and the third photosensitive medium layer 401 may be the same or different, and the present disclosure does not limit this.

[0039] Optionally, the materials of the first circuit layer, the second circuit layer 304, and the third circuit layer 404 may be copper. Optionally, the materials of the first via pillar 203, the second via pillar 303, and the third via pillar 403 may be copper.

[0040] Subsequently, as shown in FIG. 1(i), the temporary bonding layer 101 is debonded and the placement plate 100 is removed (step (f)). Note that the debonding method is determined by the material of the temporary bonding layer 101. For example, when the temporary bonding layer 101 is an ultraviolet-decomposable adhesive tape, it is debonded by irradiation with ultraviolet rays, and when the temporary bonding layer 101 is a heat-peelable adhesive tape, it is debonded by heating.

[0041] Next, as shown in FIGS. 1(j) and 1(k), the exposed via pillars are thinned to form the first pad 501, and a solder mask layer 503 having a window is formed on the surface of the exposed circuit layer to expose a part of the circuit layer to form the second pad 502 (step (g)). Here, the method of thinning the via pillars may be etching.

[0042] Optionally, the material of the solder mask layer 503 is a photosensitive medium material, and by utilizing the high resolution of the photosensitive medium material, the fabrication of a minute solder mask window is realized. Exemplarily, the window is formed by an exposure and development method.

[0043] Finally, as shown in FIG. 1(l), the surfaces of the first pad 501 and the second pad 502 are treated, which is for packaging the chip and the packaging substrate, respectively (step (h)).

[0044] In some embodiments, the surface treatment in step (h) includes one or more of an organic solderability preservative (OSP), electroless nickel electroless palladium immersion gold (ENEPIG), and ball attach.

[0045] Optionally, the first pad 501 is used for packaging the chip, and the second pad 502 is used for packaging the packaging substrate. Here, the first pad 501 can achieve a small size and a narrow pitch, and can be used for flip chip packaging of a plurality of high-density I / O chips.

[0046] As can be seen from the above, the method for manufacturing the organic interposer structure of the present disclosure can achieve panel-level processing, has high processing efficiency, low processing cost, and the organic interposer structure can achieve 2.5D packaging. Compared with the silicon interposer, the processing difficulty is low and the cost is low, so that low-cost and high-density integrated packaging can be realized.

[0047] As a second aspect, the embodiments of the present disclosure also provide an organic interposer structure. As shown in FIG. 2, the organic interposer structure includes at least two wiring units (in this example, three wiring units are provided), and each wiring unit includes a dielectric layer 301 and a circuit layer 304 on the dielectric layer 301. A redistribution layer 300 including via pillars 303 that conductively connect the circuit layer 304 is provided in the dielectric layer 301. It should be noted that the redistribution layer 300 shown in FIG. 2 has a three-layer structure, and the remaining dielectric layer, circuit layer, and via pillars are not shown in the figure. The solder mask layer 504 is located on the circuit layer on the surface of the redistribution layer 300, and there are a first pad 501 formed by the via pillars exposed on the surface of the redistribution layer 300 and a second pad 502 formed in the circuit layer exposed in the solder mask layer 504. Among them, since the first pad 501 is formed by etching the exposed via pillars, the height of the first pad 501 is lower than the height of the dielectric layer where it is located. Such a first pad 501 recessed in the dielectric layer may be provided with a hole for accommodating solder. Since the fine circuit structure can accommodate the solder of the chip terminals, the first pad 501 can better fix and connect the chip terminals, thereby simplifying the connection process between the chip terminals and the pads.

[0048] In such a technical solution, the redistribution layer 300 may be manufactured by using an organic photosensitive dielectric material, so it has high resolution, can realize the manufacture of fine circuits, can realize 2.5D packaging, and has low processing difficulty and low cost.

[0049] In some embodiments, the first pad 501 is used to connect the chip, and the second pad 502 is used to connect the packaging substrate.

[0050] In some embodiments, the material of the solder mask layer 504 is a photosensitive medium material, which can realize the fabrication of minute solder mask windows.

[0051] As shown in FIG. 3, as a third aspect, embodiments of the present disclosure also provide a packaging structure including any of the organic interposer structures described above. Optionally, the packaging structure further includes a chip and a packaging substrate, provided that the chip is connected to the first pad 501 and the packaging substrate is connected to the second pad 502. The number of chips may be plural and is not limited herein.

[0052] Those skilled in the art will understand that the description of any of the above embodiments is merely exemplary and does not imply that the scope of the present disclosure (including the claims) is limited to these examples. Under the spirit of the present disclosure, the technical features of the above embodiments or different embodiments can be combined with each other, the steps can be implemented in any order, and many other variations of different aspects of the above embodiments of the present disclosure may exist, and they are not provided in the detailed description for simplicity.

[0053] Embodiments of the present disclosure intend to cover all such substitutions, corrections, and modifications that fall within the broad scope of the claims. Therefore, any omissions, corrections, equivalent substitutions, improvements, etc. made in accordance with the spirit and principles of the embodiments of the present disclosure shall be included in the claims of the present disclosure.

Description of Reference Numerals

[0054] 100 mounting plate, 101 temporary bonding layer, 201 organic photosensitive medium layer, 202 window, 203 via pillar, first via pillar, 204 circuit layer, 300 rewiring layer, 301 medium layer, second organic photosensitive medium layer, second photosensitive medium layer, 302 window, second window, 303 via pillar, second via pillar, 304 second circuit layer, circuit layer, 401 third photosensitive medium layer, 403 third via pillar, 404 third circuit layer, 501 first pad, 502 second pad, 503 solder mask layer, 504 solder mask layer

Claims

1. (a) providing a mounting plate; (b) applying a temporary bonding layer to the mounting plate; (c) applying a photosensitive medium layer to the temporary bonding layer; (d) creating windows in the photosensitive medium layer and metallizing to form a circuit layer, the windows forming via pillars; (e) repeating steps (c) and (d) for the circuit layers until a target number of layers is reached; (f) debonding the temporary bonding layer and removing the mounting plate to expose the via pillar; (g) thinning the exposed via pillars to form first pads and forming a solder mask layer on a surface of the outermost exposed circuit layer, the solder mask layer exposing a portion of the circuit layer to form a second pad; (h) performing a metal surface treatment on the first pads and the second pads.

2. 2. The method according to claim 1, wherein the material of the support plate is glass or an acrylic material.

3. 2. The method according to claim 1, wherein the thickness of the support plate is 200 to 1000 μm.

4. 2. The method according to claim 1, wherein the temporary bonding layer is selected from an ultraviolet decomposable adhesive tape, a heat peelable adhesive tape, or a weak adhesive tape.

5. Specifically, step (c) comprises: applying a photosensitive medium material to the temporary bonding layer to form a photosensitive medium layer; 2. The method according to claim 1, further comprising the step of forming a window in said photosensitive medium layer by exposure and development.

6. Specifically, step (d) includes the steps of: applying a metal seed layer to the photosensitive medium layer; providing a photoresist layer on the surface of the metal seed layer, and forming a circuit layer pattern through exposure and development; electroplating the circuit layer pattern to form via pillars and a circuit layer; removing the photoresist layer; 2. The method of claim 1, further comprising the step of: etching the exposed metal seed layer.

7. 2. The method of claim 1, wherein the surface treatment in step (h) includes OSP, ENEPIG, or ball attach.

8. 2. The method of claim 1, wherein the solder mask layer is a photosensitive medium layer.

9. 2. The method according to claim 1, wherein the first pads are used to connect a chip, and the second pads are used to connect a packaging substrate.

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