Semiconductor device

Abstract

To provide a semiconductor device that alleviates an influence by variations of threshold voltages of transistors, and accurately and easily distinguishes a plurality of (for example, three or more) states.SOLUTION: The semiconductor device includes: a source line: a bit line BL: a word line WL; a plurality of memory cells 200 connected to the bit line and the word line; a driving circuit 213 for second signal lines and word lines, which drives a plurality of second signal lines S2 and a plurality of word lines so that a memory cell specified by an input address signal is selected; a write circuit 211 that outputs a write potential to a first signal line S1; a readout circuit 212 that compares a potential of the bit line, which is input from the bit line connected to the specified memory cell, with a plurality of readout potentials; a control circuit 216 that selects one of a plurality of correction voltages, based on a result of the comparison of the potentials; and a potential generation circuit 217 that generates a write potential and a plurality of readout potentials, and supplies the potentials to the write circuit and the readout circuit.SELECTED DRAWING: Figure 21

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element, a method for manufacturing the same, and a method for driving the same.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into a volatile memory device in which stored contents are lost when power supply is cut off, and a non-volatile memory device in which stored contents are retained even when power supply is cut off.

[0003] As a typical example of a volatile memory device, there is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting a transistor constituting a memory element and accumulating electric charges in a capacitor.

[0004] According to the above principle, in DRAM, since the electric charge of the capacitor is lost when information is read out, a rewrite operation is required again every time data is read out. In addition, there is a leakage current in the transistor constituting the memory element, and electric charges flow out or flow in even when the transistor is not selected, so the data retention period is short. For this reason, a rewrite operation (refresh operation) is required at a predetermined cycle, and it is difficult to sufficiently reduce power consumption. Further, since the stored contents are lost when the power supply is cut off, another memory device using a magnetic material or an optical material is required for long-term storage.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM stores stored contents using a circuit such as a flip-flop.​​​​​​​​​​​​ For retention, a refresh operation is not required, which is advantageous over DRAM in this regard. However, since circuits such as flip-flops are used, there is a problem that the unit price per storage capacity becomes high. Also, in terms of the fact that the stored content is lost when the power supply is cut off, there is no difference from DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A flash memory has a floating gate between the gate electrode and the channel formation region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi-permanent), and there is an advantage that a refresh operation required for a volatile memory device is not necessary (see, for example, Patent Document 1). However, since the gate insulating layer constituting the memory element deteriorates due to the tunnel current generated during writing, there is a problem that the memory element stops functioning after a predetermined number of writes. To mitigate the influence of this problem, for example, a technique for equalizing the number of writes of each memory element is adopted. However, to realize this, complex peripheral circuits are required.

[0007] And even if such a technique is adopted, the fundamental problem of lifespan is not solved. That is, flash memory is not suitable for applications where the information rewrite frequency is high.

[0008] Also, in order to hold charges in the floating gate or to remove the charges, a high voltage is required. Furthermore, it takes a relatively long time to hold or remove charges, and there is also a problem that it is not easy to speed up writing and erasing.

[0009] Furthermore, in a so-called multi-value memory that causes a single memory element to hold a plurality of states, a complicated circuit is required to ensure the accuracy of writing, and there is also a problem that the operation speed decreases due to this. Furthermore, in a so-called multi-value memory that causes a single memory element to hold a plurality of states, a complicated circuit is required to ensure the accuracy of writing, and there is also a problem that the operation speed decreases due to this. There is also a problem of the like.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0011] In view of the above problems, in one aspect of the disclosed invention, a semiconductor device having a new structure is provided that can hold memory contents even in a situation where no power is supplied and has no limitation on the number of write operations. In view of the above problems, in one aspect of the disclosed invention, a semiconductor device having a new structure is provided that can hold memory contents even in a situation where no power is supplied and has no limitation on the number of write operations. This is one of the objectives.

[0012] Or, one of the objectives is to provide a semiconductor device that reduces the influence of variations in the threshold voltage of transistors and accurately and easily distinguishes between a plurality of states (for example, three or more states). Or, one of the objectives is to provide a semiconductor device that reduces the influence of variations in the threshold voltage of transistors and accurately and easily distinguishes between a plurality of states (for example, three or more states). This is one of the objectives.

Means for Solving the Problems

[0013] One aspect of the present invention relates to a semiconductor device having a stacked structure of a transistor formed using an oxide semiconductor and a transistor formed using other materials. One aspect of the present invention relates to a semiconductor device having a stacked structure of a transistor formed using an oxide semiconductor and a transistor formed using other materials.

[0014] Or, one aspect of the present invention is a semiconductor device that accurately and easily distinguishes between a plurality of states (for example, three or more states) by having a circuit that selects a correction voltage based on the comparison result between the potential of the bit line and the read potential. Or, one aspect of the present invention is a semiconductor device that accurately and easily distinguishes between a plurality of states (for example, three or more states) by having a circuit that selects a correction voltage based on the comparison result between the potential of the bit line and the read potential. This is a semiconductor device that accurately and easily distinguishes between a plurality of states (for example, three or more states).

[0015] For example, the following configuration can be adopted.

[0016] One aspect of the present invention is a semiconductor device having a source line, a bit line, a word line, a memory cell connected to the bit line and the word line, a drive circuit for driving a plurality of second signal lines and a plurality of word lines so as to select a memory cell specified by an input address signal, a write circuit for outputting a write potential to a first signal line, a read circuit for comparing the potential of the bit line input from the bit line connected to the specified memory cell with a plurality of read potentials, a control circuit for selecting any one of a plurality of correction voltages based on the comparison result between the potential of the bit line and the plurality of read potentials, and a potential generation circuit for generating the write potential and the plurality of read potentials and supplying them to the write circuit and the read circuit.

[0017] Another aspect of the present invention is a semiconductor device having a source line, a bit line, a word line, a memory cell connected to the bit line and the word line, a drive circuit for driving a plurality of second signal lines and a plurality of word lines so as to select a memory cell specified by an input address signal, a write circuit for outputting a first write potential to the first signal line in a first write operation and outputting any one of a plurality of second write potentials to the first signal line in a second write operation, a read circuit for comparing the potential of a first bit line input from the bit line connected to the specified memory cell with a plurality of first read potentials in a first read operation and comparing the potential of the bit line input from the bit line connected to the specified memory cell with a plurality of second read potentials in a second read operation. ​​​​​​​​​​​​​​​Compare the potential of the second bit line to be forced with a plurality of second readout potentials to read the data of the memory cell A readout circuit that reads out the data of the memory cell, the potential of the first bit line, and a plurality of first readout Based on the comparison result of the potentials, select one of a plurality of correction voltages and select one of a plurality of second write voltages A control circuit, a first write potential, a plurality of second write potentials, A potential generation circuit that generates a plurality of first readout potentials and a plurality of second readout potentials and supplies them to the write circuit and the readout circuit, and a semiconductor device having the same is.

[0018] Another aspect of the present invention is a source line, a bit line, a first signal line, a plurality of second signal lines, A plurality of memory cells connected in parallel between the source line and the bit line, a plurality of second signal lines, and a plurality of word lines, A drive circuit for the second signal line and the word line that drives the plurality of second signal lines and the plurality of word lines so as to select the memory cell specified by the input address signal, a write circuit that outputs a write potential to the first signal line, A readout circuit that compares the potential of the bit line input from the bit line connected to the specified memory cell with a plurality of readout potentials, a control circuit that selects one of a plurality of correction voltages based on the comparison result of the potential of the bit line and the plurality of readout potentials, A potential generation circuit that generates a write potential and a plurality of readout potentials and supplies them to the write circuit and the readout circuit, and one of the plurality of memory cells A first transistor having a first gate electrode, a first source electrode, and a first drain electrode, a second transistor having a second gate electrode, a second source electrode, and a second drain electrode, A third transistor having a third gate electrode, a third source electrode, and a third drain electrode, has and is. and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode, A third transistor having a third gate electrode, a third source electrode, and a third drain electrode a third transistor having a pole, and the first transistor is a base including a semiconductor material is provided on a plate, the second transistor is configured to include an oxide semiconductor layer, and the first gate electrode is electrically connected to one of the second source electrode or the second drain electrode, and the source line is electrically connected to the first source electrode, the first drain electrode is electrically connected to the third source electrode, the bit line is electrically connected to the third drain electrode, the first signal line is electrically connected to the other of the second source electrode or the second drain electrode is continued, one of the plurality of second signal lines is electrically connected to the second gate electrode, and one of the plurality of word lines is electrically connected to the third gate electrode, which is a semiconductor device Another aspect of the present invention is a source line, a bit line, a first signal line, a plurality of second signal lines, a plurality of word lines, a plurality of memory cells connected in parallel between the source line and the bit line,

[0019] a driving circuit for the second signal line and the word line to drive the plurality of second signal lines and the plurality of word lines so as to select a memory cell specified by an input address signal, and in the first writing operation, output a first writing potential to the first signal line, and in the second writing operation, output any one of a plurality of second writing potentials to the first signal line a writing circuit, in the first reading operation, compare the potential of the first bit line input from the bit line connected to the specified memory cell with a plurality of first reading potentials, and in the second reading operation, compare the potential of the second bit line input from the bit line connected to the specified memory cell with a plurality of second reading potentials to read the data of the memory cell and a plurality of second signal lines and a driving circuit for the word line, and in the first writing operation, output a first writing potential to the first signal line, and in the second writing operation, output any one of a plurality of second writing potentials to the first signal line In the writing operation, output a first writing potential to the first signal line, and in the second writing operation, output any one of a plurality of second writing potentials to the first signal line a writing circuit, and in the first reading operation, compare the potential of the first bit line input from the bit line connected to the specified memory cell with a plurality of first reading potentials, and in the second reading operation, compare the potential of the second bit line input from the bit line connected to the specified memory cell with a plurality of second reading potentials to read the data of the memory cell In the first reading operation, compare the potential of the first bit line input from the bit line connected to the specified memory cell with a plurality of first reading potentials, and in the second reading operation, compare the potential of the second bit line input from the bit line connected to the specified memory cell with a plurality of second reading potentials to read the data of the memory cell is compared with a plurality of first reading potentials, and in the second reading operation, the potential of the second bit line input from the bit line connected to the specified memory cell is compared with a plurality of second reading potentials to read the data of the memory cell In the second reading operation, the potential of the second bit line input from the bit line connected to the specified memory cell is compared with a plurality of second reading potentials to read the data of the memory cell is compared with a plurality of second reading potentials to read the data of the memory cell A read circuit, based on the potential of a first bit line and the comparison results of a plurality of first read potentials, selects one of a plurality of correction voltages and selects one of a plurality of second write potentials. A control circuit, a first write potential, a plurality of second write potentials, a plurality of first read potentials, and a potential generation circuit that generates a plurality of second read potentials and supplies them to a write circuit and a read circuit. One of a plurality of memory cells includes a first transistor having a first gate electrode, a first source electrode, and a first drain electrode, a second transistor having a second gate electrode, a second source electrode, and a second drain electrode, and a third transistor having a third gate electrode, a third source electrode, and a third drain electrode. The first transistor is provided on a substrate containing a semiconductor material, the second transistor is configured to include an oxide semiconductor layer, and the first gate electrode is electrically connected to one of the second source electrode or the second drain electrode. The source line is electrically connected to the first source electrode, the first drain electrode is electrically connected to the third source electrode, the bit line is electrically connected to the third drain electrode, the first signal line is electrically connected to the other of the second source electrode or the second drain electrode, one of the plurality of second signal lines is electrically connected to the second gate electrode, and one of the plurality of word lines is electrically connected to the third gate electrode. The semiconductor device is as described above. In the above, the first transistor includes a channel formation region provided on a substrate containing a semiconductor material, an impurity region provided so as to sandwich the channel formation region, a first gate insulating layer on the channel formation region, a first gate electrode on the first gate insulating layer, and an electrical connection between the impurity region and the gate electrode. The first gate electrode is electrically connected to one of the second source electrode or the second drain electrode, the source line is electrically connected to the first source electrode, the first drain electrode is electrically connected to the third source electrode, the bit line is electrically connected to the third drain electrode, the first signal line is electrically connected to the other of the second source electrode or the second drain electrode, one of the plurality of second signal lines is electrically connected to the second gate electrode, and one of the plurality of word lines is electrically connected to the third gate electrode. The semiconductor device is as described above. In the above, the first transistor includes a channel formation region provided on a substrate containing a semiconductor material, an impurity region provided so as to sandwich the channel formation region, a first gate insulating layer on the channel formation region, a first gate electrode on the first gate insulating layer, and an electrical connection between the impurity region and the gate electrode. One of the plurality of second signal lines is electrically connected to the second gate electrode, and one of the plurality of word lines is electrically connected to the third gate electrode. The semiconductor device is as described above.

[0020] In the above, the first transistor includes a channel formation region provided on a substrate containing a semiconductor material, an impurity region provided so as to sandwich the channel formation region, a first gate insulating layer on the channel formation region, a first gate electrode on the first gate insulating layer, and an electrical connection between the impurity region and the gate electrode. The first gate electrode is electrically connected to one of the second source electrode or the second drain electrode, the source line is electrically connected to the first source electrode, the first drain electrode is electrically connected to the third source electrode, the bit line is electrically connected to the third drain electrode, the first signal line is electrically connected to the other of the second source electrode or the second drain electrode, one of the plurality of second signal lines is electrically connected to the second gate electrode, and one of the plurality of word lines is electrically connected to the third gate electrode. a first source electrode and a first drain electrode that are connected thereto.

[0021] Also, in the above, the second transistor includes a second gate electrode on a substrate containing a semiconductor material, a second gate insulating layer on the second gate electrode, an oxide semiconductor layer on the second gate insulating layer, a second source electrode and a second drain electrode that are electrically connected to the oxide semiconductor layer. and.

[0022] Also, in the above, as the substrate containing a semiconductor material, it is preferable to employ a single crystal semiconductor substrate or an SOI substrate. In particular, it is preferable that the semiconductor material is silicon.

[0023] Also, in the above, the oxide semiconductor layer preferably contains an In-Ga-Zn-O-based oxide semiconductor material. Also, the oxide semiconductor layer may contain crystals of In 2 Ga 2 ZnO 7 . Further, the hydrogen concentration of the oxide semiconductor layer is preferably 5×10 atoms / cm 19 3 or less. Also, the off-current of the second transistor is preferably 1×10 -13 A or less.

[0024] Also, another aspect of the present invention includes a source line, a bit line, a word line, a first signal line, a second signal line, a drive circuit for the second signal line and the word line that drives the second signal line and the word line so as to select a memory cell specified by an input address signal, a write circuit, a read circuit, a control circuit, a potential generation circuit, a source line, a bit line, a word line, a drive circuit for the second signal line and the word line that drives the second signal line and the word line so as to select a memory cell specified by an input address signal, a write circuit, a read circuit, a control circuit, a potential generation circuit, a source line, a bit line, a word line, a write circuit, a read circuit, a control circuit, a potential generation circuit, a source line, a bit line, a word line, In a semiconductor device having a memory cell connected to a first signal line and a second signal line, In a first write operation, a write potential is output from a write circuit to a first signal line connected to a specified memory cell, and in a first read operation, a first bit line potential input from a bit line connected to the specified memory cell is compared with a plurality of first read potentials by a read circuit, and any one of a plurality of correction voltages is selected by a control circuit based on the comparison result, and in a second write operation, a write potential corrected based on the correction voltage is output to the first signal line connected to the specified memory cell. This is a driving method of a semiconductor device.

[0025] Another aspect of the present invention is a semiconductor device having a source line, a bit line, a word line, a first signal line, a second signal line, a driving circuit for driving the second signal line and the word line to select a memory cell specified by an input address signal, a write circuit, a read circuit, a control circuit, a potential generation circuit, and a memory cell connected to the source line, the bit line, the word line, the first signal line, and the second signal line. In a first write operation, a write potential is output from the write circuit to a first signal line connected to the specified memory cell, and in a first read operation, a first bit line potential input from a bit line connected to the specified memory cell is compared with a plurality of first read potentials by the read circuit, and any one of a plurality of correction voltages is selected by the control circuit based on the comparison result, and in a second write operation, a write potential corrected based on the correction voltage is output to the first signal line connected to the specified memory cell, and in a second read operation, ​​​​​A second bit input from a bit line connected to a specified memory cell by an extraction circuit compares the potential of the line with a plurality of second readout potentials to read the data of the memory cell, which is a method for driving a semiconductor device.

[0026] In addition, in this specification and the like, terms such as "upper" and "lower" do not limit the positional relationship of components to be "directly above" or "directly below". For example, in the expression "the first gate electrode on the gate insulating layer", other components may be included between the gate insulating layer and the gate electrode. Moreover, the terms "upper" and "lower" are merely expressions used for convenience of explanation, and unless otherwise specified, they also include those with their upper and lower positions swapped.

[0027] Also, in this specification and the like, terms such as "electrode" and "wiring" do not limit these components functionally. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" or "wirings" are integrally formed.

[0028] Also, the functions of "source" and "drain" may be swapped when transistors with different polarities are adopted or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0029] In addition, in this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" ​​​​​​​" is not particularly limited as long as it enables the exchange of electrical signals between connection targets.

[0030] For example, "something having some electrical action" includes, of course, electrodes and wiring, as well as switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0031] In general, a "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification and the like, it is used as a concept including a substrate having a configuration in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. That is, the semiconductor layer included in the "SOI substrate" is not limited to a silicon semiconductor layer. Also, the substrate in the "SOI substrate" is not limited to a semiconductor substrate such as a silicon wafer, but also includes non-semiconductor substrates such as glass substrates, quartz substrates, sapphire substrates, and metal substrates. That is, a conductor substrate having an insulating surface or a substrate having a layer made of a semiconductor material on an insulator plate is also widely included in the "SOI substrate". Furthermore, in this specification and the like, the "semiconductor substrate" does not merely refer to a substrate made of only a semiconductor material, but indicates all substrates including a semiconductor material. That is, in this specification and the like, the "SOI substrate" is also widely included in the "semiconductor substrate".

Advantages of the Invention

[0032] In one aspect of the present invention, a semiconductor device is provided that has a transistor using a material other than an oxide semiconductor at the lower part and a transistor using an oxide semiconductor at the upper part.

[0033] Since a transistor using an oxide semiconductor has an extremely small off-current, using this It is possible to retain the memory content for an extremely long period. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low so that the power consumption can be sufficiently reduced. Also, even when there is no power supply , it is possible to retain the memory content for a long period.

[0034] In addition, a high voltage is not required for writing information, and there is no problem of element degradation. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information is unnecessary .

[0035] In addition, a transistor using a material other than an oxide semiconductor can perform further high-speed operation compared to a transistor using an oxide semiconductor. Therefore, by using this, it is possible to read out the memory content at high speed.

[0036] Alternatively, in one aspect of the present invention, by selecting a correction voltage based on the comparison result between the potential of the bit line and the read potential, the distinction between a plurality of states (for example, three or more states) is made accurate and easy. Thereby, it is possible to provide a multi-value type semiconductor device having excellent characteristics .

[0037] In this way, by providing a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor integrally, and also by having a circuit that selects a correction voltage based on the comparison result between the potential of the bit line and the read potential, it is possible to realize a semiconductor device having unprecedented features .

Brief Description of the Drawings

[0038]

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Embodiments for Carrying Out the Invention

[0039] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0040] Note that the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. for ease of understanding. Therefore, it is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. Thus, it is not limited to the position, size, range, etc. disclosed in the drawings and the like. Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0041] Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting. It is noted that they are not numerically limiting.

[0042] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 13. with reference to FIGS. 1 to 13.

[0043] <Circuit Configuration of Semiconductor Device> FIG. 1 shows an example of the circuit configuration of a semiconductor device. The semiconductor device is composed of a transistor 160 using a material other than an oxide semiconductor and a transistor 162 using an oxide semiconductor. and a transistor 162 using an oxide semiconductor. is formed. In FIG. 1, since an oxide semiconductor is used for the transistor 162, the symbol of OS is also attached accordingly.

[0044] Here, one of the gate electrode of the transistor 160 and the source electrode or the drain electrode of the transistor 162 is electrically connected. Also, the first wiring (1st Line : also called source line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line: also called bit line) and the drain electrode of the transistor 160 are electrically connected. And, the third wiring (3rd Line: also called first signal line ) and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected , and the fourth wiring (4th Line: also called second signal line) and the gate electrode of the transistor 162 are electrically connected.

[0045] The transistor 160 using a material other than the oxide semiconductor can operate at a higher speed compared to the transistor using the oxide semiconductor. Therefore, by using this, it is possible to read the stored content at high speed. Also, the transistor 162 using the oxide semiconductor has a feature that the off-current is extremely small. For this reason, by turning off the transistor 162, the potential of the gate electrode of the transistor 160 can be held for an extremely long time.

[0046] By taking advantage of the feature that the potential of the gate electrode can be held, information can be written, held, and read as follows.

[0047] First, writing and holding of information will be described. First, the potential of the fourth wiring is set as the potential at which the transistor 162 turns on, and the transistor 162 is turned on. Thereby, the potential of the third wiring is applied to the gate electrode of the transistor 160 (writing). After that, the potential of the fourth wiring is set as the potential at which the transistor 162 turns off, and by turning off the transistor 162, the potential of the gate electrode of the transistor 160 is held (held).

[0048] Since the off-current of the transistor 162 is extremely small, the potential of the gate electrode of the transistor 160 is held for a long time. For example, if the potential of the gate electrode of the transistor 160 is the potential at which the transistor 160 turns on, the on-state of the transistor 160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 160 is the potential at which the transistor 160 turns off, the off-state of the transistor 160 will be held for a long time.

[0049] Next, reading of information will be described. As described above, in the state where the on-state or off-state of the transistor 160 is held, when a predetermined potential (low potential) is applied to the first wiring the potential of the second wiring takes different values according to the on-state or off-state of the transistor 160. For example, when the transistor 160 is in the on-state, the potential of the second wiring decreases according to the potential of the first wiring. Conversely, when the transistor 160 is in the off-state the potential of the second wiring does not change. In this way, in the state where information is held, the potential of the second wiring is compared with a predetermined potential.

[0050] ​ In this way, information can be read out.

[0051] Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring (the potential related to the new information) is applied to the gate electrode of the transistor 160. Then, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned off, and the transistor 1 62 is turned off, so that the new information is held.

[0052] Thus, the semiconductor device according to the disclosed invention can directly rewrite information by writing information again. Therefore, the erasing operation required in a flash memory or the like is unnecessary, and a decrease in the operating speed due to the erasing operation can be suppressed. That is, high-speed operation of the semiconductor device is realized.

[0053] Note that the above description is for the case of using an n-type transistor (n-channel transistor) in which electrons are majority carriers, but it goes without saying that a p-type transistor in which holes are majority carriers can be used instead of the n-type transistor.

[0054] Also, it goes without saying that additional elements may be further added to the above configuration. For example, a capacitor element may be connected to one of the gate electrode of the transistor 160, the source electrode, or the drain electrode of the transistor 162 to adopt a configuration with increased tolerance for potential fluctuations.

[0055] ​​​ <Planar and Cross-Sectional Configurations of Semiconductor Device> FIG. 2 shows an example of the configuration of the semiconductor device. In FIG. 2(A), a cross-section of the semiconductor device is shown, and in FIG. 2(B), a plan view of the semiconductor device is shown. Here, FIG. 2(A) corresponds to the cross-section along lines A1 - A2 and B1 - B2 in FIG. 2(B). The semiconductor device shown in FIGS. 2(A) and 2(B has a transistor 160 using a material other than an oxide semiconductor at the lower part and a transistor 162 using an oxide semiconductor at the upper part. Note that both the transistor 160 and the transistor 162 are described as n-type transistors, but a p-type transistor may be employed. In particular, it is easy to make the transistor 160 p-type.

[0056] The transistor 160 includes a channel formation region 11 6 provided in a substrate 100 containing a semiconductor material, impurity regions 114 and high-concentration impurity regions 120 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108 provided on the channel formation region 11 6, a gate electrode 110 provided on the gate insulating layer 108, and a source electrode or drain electrode 130a electrically connected to the impurity region 114 and a source electrode or drain electrode 130b.

[0057] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. Also, in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, there is a high-concentration impurity region 120, and a metal compound region 124 exists on the high-concentration impurity region 120. Further, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. ​​​​​​​​​is provided, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 160. The source electrode or drain electrode 130a, the source electrode or drain electrode 130b are electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or drain electrode 130a, the source electrode or drain electrode 130b are electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 124. Also, an electrode 130c provided in the same manner as the source electrode or drain electrode 130a and the source electrode or drain electrode 130b is electrically connected to the gate electrode 110. The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, an oxide semiconductor layer 140 provided on the gate insulating layer 138, and a source electrode or drain electrode 142a provided on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, and a source electrode or drain electrode 142b.

[0058] Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Also, in the same manner as the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c. The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, an oxide semiconductor layer 140 provided on the gate insulating layer 138, and a source electrode or drain electrode 142a provided on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, and a source electrode or drain electrode 142b.

[0059] Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Also, in the same manner as the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c. Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Also, in the same manner as the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c. are respectively formed.

[0060] Also, on the transistor 162, a protective insulating layer 144 is provided so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with openings reaching the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b, and through the openings, the electrodes 150d and 150e are formed in contact with the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b. Also, in the same manner as the electrodes 150d and 150e, through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146, the electrodes 150a, 150b, and 150c that are in contact with the electrodes 136a, 136b, and 136c are formed. Here, it is desirable that the oxide semiconductor layer 140 has sufficiently removed impurities such as hydrogen and is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 atoms / cm or less, desirably 5×10

[0061] atoms / cm or less, more desirably 5×10 19 atoms / cm 3 or less. Also, in the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified, the carrier concentration is 1×10 18 / cm 3 or less, desirably 1×10 / cm 17 or less. Thus, by using an oxide semiconductor in which the hydrogen concentration is sufficiently reduced and highly purified and is i - type or substantially i - type, extremely 3 12 / cm 3 less 11 / cm 3 Therefore, the transistor 162 can have excellent off-state current characteristics. For example, When Vd is +1V or +10V, the gate voltage Vg is in the range of -5V to -20V. In this range, the off-state current is 1×10 -13 In this way, the hydrogen concentration is sufficiently reduced. The oxide semiconductor layer 140 is highly purified by using the oxide semiconductor layer 140, and the off-state current of the transistor 162 is reduced. By reducing the amount of oxidation, a semiconductor device with a new structure can be realized. The hydrogen concentration in the compound semiconductor layer 140 was measured by secondary ion mass spectrometry (SIMS). The results were measured using a y Ion Mass Spectroscopy (Y-Ion Mass Spectroscopy).

[0062] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes 154a, 154b, 154c, and 154d are inserted into the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0063] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110 of the transistor 160 and The source electrode or drain electrode 142a of the transistor 162 is connected to the electrode 130c and the electrode 1 36c, the electrodes 150c, 154c and 150d are electrically connected to each other. do.

[0064] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for fabricating the transistor 160 will be described with reference to FIG. The manufacturing method of the will be described with reference to FIGS. 4 and 5.

[0065] <Manufacturing Method of Lower Transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). As the substrate 100 containing a semiconductor material, a single-crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, as an example of the case where a single-crystal silicon substrate is used as the substrate 100 containing a semiconductor material, it will be shown. In general, an "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification and the like, it is used as a concept including a substrate having a configuration in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. That is, the semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. Also, the SOI substrate includes those having a configuration in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate. On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see FIG. 3(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, etc. can be used as the material. Note that before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon, as the impurity imparting n-type conductivity, for example, phosphorus, arsenic, etc. can be used. Also, as the impurity imparting p-type conductivity, for example, boron, aluminum, etc. can be used. On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see FIG. 3(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, etc. can be used as the material. Note that before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon,

[0066] On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see FIG. 3(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, etc. can be used as the material. Note that before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon, as the impurity imparting n-type conductivity, for example, phosphorus, arsenic, etc. can be used. Also, as the impurity imparting p-type conductivity, for example, boron, aluminum, etc. can be used. When the semiconductor is silicon, as the impurity imparting n-type conductivity, for example, phosphorus, arsenic, etc. can be used. Also, as the impurity imparting p-type conductivity, for example, boron, aluminum, etc. can be used. Yttrium, gallium, etc. can be used.

[0067] Next, using the above protective layer 102 as a mask, etching is performed to remove a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region). As a result, the separated semiconductor region 104 is formed (see Fig. 3(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and etching solution can be appropriately selected according to the material to be etched. Next, an insulating layer is formed so as to cover the semiconductor region 104, and by selectively removing the insulating layer in the region overlapping the semiconductor region 104, the element isolation insulating layer 106 is formed (see Fig. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. As a method for removing the insulating layer, there are polishing processes such as CMP and etching processes, and any of them may be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the above protective layer 102 is removed. Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. The insulating layer will be the subsequent gate insulating layer, and it is preferably a single-layer structure or a laminated structure of a film containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. obtained by the CVD method, sputtering method, etc. Alternatively, by high-density plasma treatment or thermal oxidation treatment, the surface of the semiconductor region 104 is oxidized and nitrided.

[0068]

[0069]

[0070] Further, the insulating layer may be formed. The high-density plasma treatment can be performed, for example, using a mixed gas of a noble gas such as He, Ar, Kr, Xe, etc. and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but can be, for example, 1 nm or more and 10 0 nm or less.

[0071] The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, tungsten, etc. Also, a semiconductor material such as polycrystalline silicon containing a conductive material can be used to form the layer containing the conductive material. The forming method is not particularly limited, and various film-forming methods such as vapor deposition method, C VD method, sputtering method, spin coating method, etc. can be used. In this embodiment, an example of forming the layer containing the conductive material using a metal material is shown.

[0072] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 and the gate electrode 110 (see Fig. 3(C)).

[0073] Next, an insulating layer 112 covering the gate electrode 110 is formed (see Fig. 3(C)). Then, phosphorus (P), arsenic (As), etc. are added to the semiconductor region 104 to form an impurity region 114 with a shallow junction depth with the substrate 100 (see Fig. 3(C)). Here, phosphorus and arsenic are added to form an n-type transistor, but when forming a p-type transistor, impurity elements such as boron (B) and aluminum (Al) may be added. Note that due to the formation of the impurity region 114, a channel formation is formed under the gate insulating layer 108 of the semiconductor region 104. A region 116 is formed (see FIG. 3C). The concentration of the added impurity is appropriately set. However, when semiconductor elements are highly miniaturized, the concentration can be increased. In this embodiment, after the insulating layer 112 is formed, the impurity is introduced. The process of forming the region 114 is adopted, but after forming the impurity region 114, the insulating layer 1 This may be a process for forming 12.

[0074] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, the film can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is a good idea to expose the top surface of 14.

[0075] Next, a semiconductor device is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed in the region where the insulating layer contacts the impurity region 114. By doping the silicon substrate with ions such as phosphorus (P) or arsenic (As), a high-concentration impurity region 120 is formed (see FIG. 3(E)). After that, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, A metal layer 122 is formed so as to cover the high concentration impurity region 120 and the like (see FIG. 3(E)). The metal layer 122 can be formed by a variety of film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed using the semiconductor material that constitutes the semiconductor region 104. It is preferable to form the insulating layer using a metal material that reacts with the metal to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, nickel, and cobalt. There are tungsten, platinum, etc.

[0076] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the high concentration impurity region 120 is formed (see Fig. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110, a metal compound region is also formed in the portion of the gate electrode 110 that contacts the metal layer 122.

[0077] As the heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is desirable to use a method that can achieve a very short-time heat treatment. Note that the above metal compound region is formed by the reaction between the metal material and the semiconductor material and is a region with sufficiently enhanced conductivity. By forming the metal compound region , the electrical resistance can be sufficiently reduced and the device characteristics can be improved. Note that after forming the metal compound region 124, the metal layer 122 is removed.

[0078] Next, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover each component formed by the above-described process (see Fig. 3(G)). The interlayer insulating layer 126 and the interlayer insulating layer 128 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form them using an organic insulating material such as polyimide or acrylic. Here, a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is adopted, but the configuration of the interlayer insulating layer is not limited to this. this. It is not. After the formation of the interlayer insulating layer 128, it is desirable to flatten its surface by CMP, etching, or the like. It is desirable to flatten it.

[0079] Thereafter, an opening reaching the metal compound region 124 is formed in the interlayer insulating layer, and a source electrode or drain electrode 130a and a source electrode or drain electrode 130b are formed in the opening (see Fig. 3(H)). The source electrode or drain electrode 130a and the source electrode or drain electrode 130b can be formed, for example, by forming a conductive layer in the region including the opening using a PVD method, a CVD method, or the like, and then removing a part of the conductive layer using methods such as etching and CMP. When forming the source electrode or drain electrode 130a and the source electrode or drain electrode 130b by removing a part of the conductive layer, it is desirable to process the surface so that it becomes flat. For example, when forming a tungsten film so as to fill the opening after thinly forming a titanium film or a titanium nitride film in the region including the opening, unnecessary tungsten films, titanium films, titanium nitride films, etc. are removed by subsequent CMP, and the flatness

[0080] of the surface can be improved. By flattening the surface including the source electrode or drain electrode 130a and the source electrode or drain electrode 130b in this way, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. Here, only the source electrode or drain electrode 130a and the source electrode or drain electrode 130b in contact with the metal compound region 124 are shown, but in this process, the gate is also formed. is also formed. By flattening the surface including the source electrode or drain electrode 130a and the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. Here, only the source electrode or drain electrode 130a and the source electrode or drain electrode 130b in contact with the metal compound region 124 are shown, but in this process, the gate

[0081] is also formed. a and the source electrode or drain electrode 130b, although only these are shown here, in this step, the gate The electrode in contact with the base electrode 110 (for example, the electrode 130c in FIG. 2) is also formed. A source electrode or drain electrode 130a, a source electrode or drain There is no particular limitation on the material that can be used for the electrode 130b, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0082] In this manner, a transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0083] <How to make the upper transistor> Next, referring to FIG. 4 and FIG. 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0084] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0085] Next, the source or drain electrode 130a, the source or Openings are formed so as to reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed so as to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by a method such as exposure to light. As for etching, wet etching is used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnSe, and scandium, as well as their alloys and compounds (e.g., nitrides) are examples of such materials. can be done.

[0086] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is A bottom electrode (here, a source electrode or a drain electrode 130a, The oxide film at the interface with the lower electrode (electrode 130b, electrode 130c, etc.) is reduced to reduce the contact resistance with the lower electrode. The titanium nitride film formed afterwards also serves to reduce the diffusion of conductive materials. It has a barrier function to be suppressed. Also, after forming a barrier film made of titanium, titanium nitride, etc., a copper film may be formed by a plating method.

[0087] After forming the conductive layer 134, a part of the conductive layer 13 4 is removed using methods such as etching treatment or CMP to expose the insulating layer 132, and electrodes 136a, 136b, 13 6c, and gate electrode 136d are formed (see Fig. 4(C)). Note that when forming electrodes 136a, 136b, 136c, and gate electrode 136d by removing a part of the conductive layer 134, it is desirable to process so that the surface becomes flat. In this way, by planarizing the surfaces of the insulating layer 132, electrodes 136a, 136b, 136c, and gate electrode 136d, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes.

[0088] Next, a gate insulating layer 138 is formed so as to cover the insulating layer 132, electrodes 136a, 136b, 136c, and gate electrode 136d (see Fig. 4(D)). The gate insulating layer 138 can be formed using a CVD method, a sputtering method, etc. Also, the gate insulating layer 138 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the gate insulating layer 138 may have a single-layer structure or a laminated structure. For example, using silane (SiH 4 )), oxygen, and nitrogen as raw material gases, a gate insulating layer 138 made of silicon oxynitride can be formed by a plasma CVD method. The thickness of the gate insulating layer 138 is not particularly limited. Although it cannot be, for example, it can be set to 10 nm or more and 500 nm or less. In the case of a stacked structure , for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and the first gate insulating layer and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the layer are preferably stacked.

[0089] Note that an oxide semiconductor that has been i - type or substantially i - type by removing impurities (a highly purified oxide semiconductor) is extremely sensitive to interface levels and interface charges. Therefore, when such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important . That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is required to be of high quality .

[0090] For example, the high - density plasma CVD method using microwaves (2.45 GHz) is suitable in that it can form a high - quality gate insulating layer 138 that is dense and has high breakdown voltage. By closely contacting the highly purified oxide semiconductor layer with the high - quality gate insulating layer, the interface level can be reduced and the interface characteristics can be improved . This is because the interface characteristics can be made favorable.

[0091] Of course, as long as a high - quality insulating layer can be formed as the gate insulating layer, other methods such as sputtering or plasma CVD can be applied even when using a highly purified oxide semiconductor layer. Also, an insulating layer whose film quality and interface characteristics with the oxide semiconductor layer are modified by heat treatment after formation may be applied. In any case, a gate insulating layer 138 with good film quality, which can reduce the interface level density with the oxide semiconductor layer and form a good interface, should be formed.

[0092] Furthermore, 85 °C, 2×106 V / cm, 12-hour gate bias-thermal stress test (B T test), when impurities are added to the oxide semiconductor, the bond between the impurities and the main component of the oxide semiconductor is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated unbonded hands will induce a drift of the threshold voltage (Vth).

[0093] On the other hand, by minimizing the impurities in the oxide semiconductor, especially hydrogen and water, and improving the interface characteristics with the gate insulating layer as described above, a stable transistor can be obtained even for the BT test.

[0094] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and the oxide semiconductor layer is processed by methods such as etching using a mask to form an island-shaped oxide semiconductor layer 140 (see Fig. 4(E)).

[0095] As the oxide semiconductor layer, quaternary metal oxide In-Sn-Ga-Zn-O, ternary system metal oxides such as In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, binary system metal oxides such as In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, S n-Mg-O, In-Mg-O, and oxide semiconductor layers using In-O, Sn-O, Zn-O, etc. can be applied. Also, SiO can be included in the above oxide semiconductor layer 2 if desired .

[0096] In addition, as the oxide semiconductor layer, a thin film represented by InMO 3 (ZnO) m (m>0) can be used ​​It can be done. Here, M is one or more selected from Ga, Al, Mn, and Co indicating a metal element. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO 3 (ZnO) m (m>0), an oxide semiconductor film with the structure represented by Among them, an oxide semiconductor with a structure containing Ga as M is called an In-Ga-Zn-O oxide semiconductor and its thin film is called an In-Ga-Zn-O oxide semiconductor film (In-Ga-Zn-O amorphous film), etc.

[0097] In this embodiment, an amorphous oxide semiconductor layer is formed by sputtering using a target for forming an In-Ga-Zn-O-based oxide semiconductor as the oxide semiconductor layer It is to be formed. Note that by adding silicon to the amorphous oxide semiconductor layer, its crystallization can be suppressed so, for example, a target containing 2 wt% or more and 10 wt% or less of SiO 2 can be used to form the oxide semiconductor layer It may also be formed.

[0098] As a target for producing the oxide semiconductor layer by sputtering, for example, a target of a metal oxide mainly composed of zinc oxide can be used. Also, a target for forming an oxide semiconductor containing In, Ga, and Zn (as a composition ratio, In O 2 :Ga 3 :ZnO = 1:1:1 [mole ratio], In:Ga:Zn = 1:1:0.5 [atom 2 %]) etc. can also be used. Also, as a target for forming an oxide semiconductor film containing In, Ga, and Zn, In 3 :Ga %]) etc. can also be used. Also, as a target for forming an oxide semiconductor film containing In, Ga, and Zn, In film, In 2 O 3 :Ga 2 O3 :ZnO=1:1:2 [mol ratio], Or In 2 O 3 :Ga 2 O 3 ZnO=1:1:4 [molar ratio] The filling rate of the oxide semiconductor film forming target is 90% or more. 0% or less, preferably 95% or more (for example, 99.9%). By using a bulk deposition target, a dense oxide semiconductor layer is formed.

[0099] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a fluorine-containing gas atmosphere. Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. In general, the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is about several ppm. It is preferable to use a high-purity gas in which the concentration has been reduced to about several ppb.

[0100] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while performing the above-mentioned step, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage caused by sputtering can be reduced. The residual moisture in the metal oxide film is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. In order to remove residual moisture in the treatment chamber, It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump. A titanium sublimation pump can be used. A cold trap may be added to the Bobo pump. Exhaust using a cryopump The film-forming chamber evacuated using, for example, a cryopump contains compounds containing hydrogen atoms such as hydrogen atoms and water (H 2 O), etc. (more preferably compounds containing carbon atoms as well), etc. are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced.

[0101] As the formation conditions, for example, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC (direct current) power is 0.5 kW, the atmosphere is an oxygen (oxygen flow ratio 100%) atmosphere, and the like conditions can be applied. Note that when using a pulsed DC (direct current) power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution also becomes uniform Therefore, it is preferable. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied Therefore, the thickness may be appropriately selected according to the material used.

[0102] Note that before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas and remove the dust adhering to the surface of the gate insulating layer 138 Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, whereas in normal sputtering, ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate And so on. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used. ​

[0103] For the etching of the above oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both can also be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that etching can be performed into a desired shape.

[0104] Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases, for example, chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride ( CCl 4 ), etc.). Also, gases containing fluorine (fluorine-based gases, for example, carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (C HF 3 ), etc.), hydrogen bromide (HBr), oxygen (O 2 ), and gases obtained by adding noble gases such as helium (He) or argon (Ar) to these gases may also be used.

[0105] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately set so that etching can be performed into a desired shape.

[0106] ​​As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% aqueous ammonia: water = 5:2:2), etc. can be used. Further, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may also be used. ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% aqueous ammonia: water = 5:2:2) etc. can be used. Further, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may also be used.

[0107] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be performed. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere so that re-mixing of water or hydrogen does not occur. Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be performed. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere so that re-mixing of water or hydrogen does not occur. 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere so that re-mixing of water or hydrogen does not occur.

[0108] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats an object to be processed by heat conduction from a medium such as heated gas, or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be processed by heat treatment can be used. Rapid Thermal Anneal) apparatus, LRTA (Lamp Rapid Thermal Anneal) apparatus, etc. of RTA (Rapid Thermal Ann eal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, etc. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be processed by heat treatment can be used. noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be processed by heat treatment​​ A gas is used.

[0109] For example, as the first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C and heated for several minutes, and then a GRTA treatment of taking out the substrate from the inert gas may be performed. When the GRTA treatment is used, high-temperature heat treatment in a short time becomes possible. Also, since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0110] Note that the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc.) and containing no water, hydrogen, etc. For example, the purity of nitrogen or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0111] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become microcrystalline or polycrystalline. For example, it may become an oxide semiconductor layer of microcrystals with a crystallization rate of 90% or more, or 80 % or more. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer containing no crystal components.

[0112] In addition, an oxide semiconductor layer in which microcrystals (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in an amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer) may be formed.

[0113] Also, by arranging microcrystals in the amorphous material, the electrical properties of the oxide semiconductor layer can be changed. This is also possible. For example, when forming an oxide semiconductor layer using a target for forming an In-Ga-Zn-O-based oxide semiconductor film, the electrical properties of the oxide semiconductor layer can be changed by forming a microcrystalline portion in which the crystal grains of In 2 Ga 2 ZnO 7 are oriented. Specifically, for example, by orienting the c-axis of In

[0114] Ga 2 Ga 2 ZnO 7 to be perpendicular to the surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved, and the insulation in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Also, such a microcrystalline portion has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer.

[0115] Note that the oxide semiconductor layer having the above-described microcrystalline portion can be formed by surface heating of the oxide semiconductor layer by GRTA treatment. Also, by using a sputtering target in which the Zn content is smaller than the In or Ga content, it can be more suitably formed.

[0116] The first heat treatment for the oxide semiconductor layer 140 can also be performed on the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the substrate is taken out from the heating device, and a photolithography process is performed.

[0117] Note that the above-described first heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. ​​​​​Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. Such dehydration treatment, de- hydrogenation treatment can be performed at the timing such as after forming the oxide semiconductor layer and laminating a source electrode or a drain electrode on the oxide semiconductor layer 140, and then forming a protective insulating layer on the source electrode or the drain electrode. Moreover, such dehydration treatment and dehydrogenation treatment may be performed not only once but also multiple times. Next, source electrodes or drain electrodes 142a and source electrodes or drain electrodes 142b are formed so as to be in contact with the oxide semiconductor layer 140 (see FIG. 4(F)). The source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer.

[0118] The conductive layer can be formed by using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. As the material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described elements as components, etc. can be used. Any one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. Also, a material in which an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium is combined singly or in plurality with aluminum may be used. Furthermore, the conductive layer may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In Moreover, the conductive layer can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer. The conductive layer can be formed by using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. As the material of the conductive layer, an element selected from aluminum, chromium, copper,

[0119] tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described elements as components, etc. can be used. Any one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. Also, a material in which an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium is combined singly or in plurality with aluminum may be used. Furthermore, the conductive layer may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described elements as components, etc. can be used. Any one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. Also, a material in which an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium is combined singly or in plurality with aluminum may be used. Moreover, the conductive layer can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer. The conductive layer can be formed by using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. As the material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described elements as components, etc. can be used. Any one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. Also, a material in which an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium is combined singly or in plurality with aluminum may be used. Furthermore, the conductive layer may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In

[0120] Moreover, the conductive layer can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer. oxide (In2 O 3 ) Tin oxide (SnO 2 ), zinc oxide (ZnO), indium tin oxide alloy (In 2 O 3 ―SnO 2 , sometimes abbreviated as ITO), indium zinc oxide alloy (In 2 O 3 ―ZnO), or those obtained by adding silicon or silicon oxide to these metal oxide materials can be used.

[0121] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned.

[0122] Here, for the exposure during mask formation used for etching, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light.

[0123] The channel length (L) of the transistor is determined by the distance between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142b. Note that when performing exposure when the channel length (L) is less than 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for mask formation exposure. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to make the channel length (L) of the transistor formed later 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit. Furthermore, since the off-current value is extremely small, the power consumption does not increase.

[0124] Note that when etching the conductive layer, appropriate adjustment is made to each material and etching condition so that the oxide semiconductor layer 140 is not removed. Depending on the material and etching condition, a part of the oxide semiconductor layer 140 may be etched in this step, resulting in an oxide semiconductor layer having a groove (recess). Note that when etching the conductive layer, appropriate adjustment is made to each material and etching condition so that the oxide semiconductor layer 140 is not removed. Depending on the material and etching condition, a part of the oxide semiconductor layer 140 may be etched in this step, resulting in an oxide semiconductor layer having a groove (recess). Note that when etching the conductive layer, appropriate adjustment is made to each material and etching condition so that the oxide semiconductor layer 140 is not removed. Depending on the material and etching condition, a part of the oxide semiconductor layer 140 may be etched in this step, resulting in an oxide semiconductor layer having a groove (recess). )

[0125] In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced, and thus high-speed operation of the transistor can be realized. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced, and thus high-speed operation of the transistor can be realized. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced, and thus high-speed operation of the transistor can be realized. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced, and thus high-speed operation of the transistor can be realized. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced, and thus high-speed operation of the transistor can be realized. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced, and thus high-speed operation of the transistor can be realized. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or drain region can be reduced, and thus high-speed operation of the transistor can be realized.

[0126] In addition, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so that it can be used in a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo mask can be reduced. In addition, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so that it can be used in a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo mask can be reduced. In addition, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so that it can be used in a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo mask can be reduced. In addition, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so that it can be used in a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo mask can be reduced. In addition, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so that it can be used in a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo mask can be reduced. In addition, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so that it can be used in a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo mask can be reduced. In addition, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so that it can be used in a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo mask can be reduced. Since the photolithography process can also be reduced, the process can be simplified.

[0127] Note that after the above process, 2 NO, N 2 or plasma treatment using a gas such as Ar is preferably performed. By this plasma treatment, water or the like adhering to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon. Next, without exposing to the atmosphere, a protective insulating layer 144 in contact with a part of the oxide semiconductor layer 140 is formed (see FIG. 4(G)). The protective insulating layer 144 can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the protective insulating layer 144. Also, its thickness should be at least 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, its structure may be a single-layer structure or a laminated structure. The substrate temperature when forming the protective insulating layer 144 is preferably room temperature or higher and 300°C or lower, and the atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen.

[0128] Next, without exposing to the atmosphere, a protective insulating layer 144 in contact with a part of the oxide semiconductor layer 140 is formed (see FIG. 4(G)). 4 is formed (see FIG. 4(G)).

[0129] The protective insulating layer 144 can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the protective insulating layer 144. Also, its thickness should be at least 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, its structure may be a single-layer structure or a laminated structure. The substrate temperature when forming the protective insulating layer 144 is preferably room temperature or higher and 300°C or lower, and the atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen.

[0130] If the protective insulating layer 144 contains hydrogen, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, resulting in a lower resistance on the back channel side of the oxide semiconductor layer and the possibility of forming a parasitic channel. Therefore, it is important that the protective insulating layer 1 44 contains as little hydrogen as possible and that hydrogen is not used in the formation method. 44 is formed without using hydrogen as much as possible in the formation method.​​ It is.

[0131] Also, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. Acid This is to ensure that the oxide semiconductor layer 140 and the protective insulating layer 144 do not contain hydrogen, hydroxyl groups, or water. This is for that purpose.

[0132] To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump has, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H 2 O), etc. removed, so the concentration of impurities contained in the protective insulating layer 144 formed in the film formation chamber can be reduced. The protective insulating layer 144 formed in the film formation chamber can be reduced. layer 144 can be reduced.

[0133] As the sputtering gas used when forming the protective insulating layer 144, a high-purity gas with the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides removed to about several ppm (preferably about several ppb) is preferably used. As the sputtering gas used when forming the protective insulating layer 144, a high-purity gas with the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides removed to about several ppm (preferably about several ppb) is preferably used. removed to about several ppm (preferably about several ppb) is preferably used.

[0134] Next, it is desirable to perform a second heat treatment (preferably at 20 0 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) in an inert gas atmosphere or an oxygen gas atmosphere. For example , a second heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistor. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistor.

[0135] Also, a heat treatment may be performed in the atmosphere at 100 °C or higher and 200 °C or lower for 1 hour or more and 30 hours or less. Okay. This heat treatment may be performed by heating while maintaining a constant heating temperature, or by repeatedly raising the temperature from room temperature to a heating temperature of 100°C or higher and 200°C or lower, and then lowering the temperature from the heating temperature to room temperature. Further, this heat treatment may be performed under reduced pressure before forming the protective insulating layer. Performing the heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment may be performed instead of the second heat treatment, or before or after the second heat treatment. Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 5(A)). The interlayer insulating layer 146 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. After forming the interlayer insulating layer 146, it is desirable to planarize its surface by a method such as CMP or etching. Next, openings reaching the electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, and source electrode or drain electrode 142b are formed in the interlayer insulating layer 146, protective insulating layer 144, and gate insulating layer 138, and a conductive layer 148 is formed so as to fill the openings (see Fig. 5(B)). The above openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching, either wet etching or dry etching may be used, but from the viewpoint of microfabrication, dry etching is used.

[0136]

[0137] ​​​​​​​​​​​​​​is preferable. The conductive layer 148 is formed using a film formation method such as PVD or CVD. This can be done. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and any other conductive materials, as well as alloys and compounds (such as nitrides) of these.

[0138] Specifically, for example, a thin titanium film is formed by PVD in a region including an opening, and a thin titanium nitride film is formed by CVD, and then a tungsten film is formed so as to fill the opening. Here, the titanium film formed by PVD reduces the oxide film at the interface with the lower electrode (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source electrode or drain electrode 142b), and has the function of reducing the contact resistance with the lower electrode. Also, the subsequently formed titanium nitride has a barrier function of suppressing the diffusion of the conductive material. Also, after forming a barrier film made of titanium or titanium nitride, etc., a copper film may be formed by electroplating.

[0139] After forming the conductive layer 148, a part of the conductive layer 148 is removed using methods such as etching or CMP to expose the interlayer insulating layer 146, and electrodes 150a, 150b, 150c, 150d, 150e are formed (see Fig. 5(C)). Note that when removing a part of the conductive layer 148 to form electrodes 150a, 150b, 150c, 150d, 150e, it is desirable to process so that the surface becomes flat. In this way, the interlayer insulating layer 146, electrodes 150a, 150b, 150c, 150d, 150e are formed. By planarizing the surface of the electrode 150e, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes.

[0140] Furthermore, an insulating layer 152 is formed, and openings reaching the electrodes 150a, 150b, electrode 1 50c, electrode 150d, and electrode 150e are formed in the insulating layer 152, and a conductive layer is formed by embedding it into the openings. Then, a part of the conductive layer is removed using methods such as etching or CMP to expose the insulating layer 152 and form electrodes 154a, 154b, 154c, and electrode 154 d (see Fig. 5(D)). This process is the same as when forming the electrodes 150a, etc., so the details are omitted. When the transistor 162 is fabricated by the method as described above, the hydrogen concentration in the oxide semiconductor layer 140 becomes 5×10

[0141] atoms / cm or less, and the off-current 19 of the transistor 162 3 becomes 1×10 A or less. By applying such an oxide semiconductor layer 140 with a sufficiently reduced and highly purified hydrogen concentration, a transistor 162 with excellent characteristics can be obtained. Also, a semiconductor device with excellent characteristics having a transistor 160 using a material other than an oxide semiconductor at the bottom and a transistor 162 using an oxide semiconductor at the top can be fabricated. -13 Moreover, as a semiconductor material that can be a comparison target with the oxide semiconductor, there is silicon carbide (e.g., 4H -SiC). The oxide semiconductor and 4H-SiC have several common points. Carrier density is one example. The intrinsic carrier density of the oxide semiconductor at room temperature is 10 / cm

[0142] Note that as a semiconductor material that can be a comparison target with the oxide semiconductor, there is silicon carbide (e.g., 4H -SiC). The oxide semiconductor and 4H-SiC have several common points. Carrier density is one example. The intrinsic carrier density of the oxide semiconductor at room temperature is 10 / cm -7 ​​​3 is estimated to be on the order of, which is 6.7×10 in 4H-SiC -11 / cm 3 and similarly, is an extremely low value. Comparing with the intrinsic carrier density of silicon (1.4×10 10 / cm 3 order of magnitude), it can be well understood that the degree is quite different.

[0143] Also, the energy band gap of the oxide semiconductor is 3.0~3.5eV, and that of 4H-S iC is 3.26eV. Therefore, in terms of being a wide bandgap semiconductor, the oxide semiconductor and silicon carbide have something in common.

[0144] On the other hand, there are extremely large differences between the oxide semiconductor and silicon carbide. That is the process temperature. The semiconductor process using silicon carbide requires, for example, heat treatment at 1 500°C~2000°C for the activation of dopants. Therefore, it is difficult to form a stacked structure with semiconductor elements using other semiconductor materials. This is because at such high temperatures, semiconductor substrates, semiconductor elements, etc. will be destroyed. On the other hand, the oxide semiconductor can be fabricated by heat treatment at 300°C~500°C (below the glass transition temperature, up to about 700°C at most). It is possible to form semiconductor elements using the oxide semiconductor after forming integrated circuits using other semiconductor materials.

[0145] Also, different from the case of silicon carbide, it has the advantage that substrates with low heat resistance, such as glass substrates, can be used. Furthermore, in terms of not requiring heat treatment at high temperatures, it has the advantage that the energy cost can be sufficiently reduced compared with silicon carbide.

[0146] ​​​​In the case of oxide semiconductors, many physical property studies have been conducted, but these studies do not include the idea of sufficiently reducing the localized levels themselves in the energy gap. In one aspect of the disclosed invention, by removing water and hydrogen that can cause localized levels from the oxide semiconductor, a highly purified oxide semiconductor is produced. This is based on the idea of sufficiently reducing the localized levels themselves in the energy gap. And this enables the production of extremely excellent industrial products.

[0147] When removing hydrogen, water, etc., oxygen may be removed at the same time. Therefore, by supplying oxygen to the unbonded hands of the metal generated by oxygen deficiency and reducing the localized levels due to oxygen defects, it is possible to obtain a more highly purified (type-i) oxide semiconductor. For example, by forming an oxygen-excess oxide film in close contact with the channel formation region and performing heat treatment under temperature conditions of 200°C to 400°C, typically about 250°C, it is possible to supply oxygen from the oxide film and reduce the localized levels due to oxygen defects.

[0148] Following the second heat treatment, it is also possible to supply oxygen to the oxide semiconductor by passing through a temperature drop process in an oxygen atmosphere or an atmosphere in which hydrogen and water have been sufficiently removed.

[0149] Donors in the oxide semiconductor are considered to be caused by shallow levels of 0.1 eV to 0.2 eV below the conduction band due to excess hydrogen, deep levels due to oxygen deficiency, etc. In order to eliminate these defects, the technical idea of thoroughly removing hydrogen and sufficiently supplying oxygen would be correct.

[0150] In addition, although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, impurities, in particular, achieve i-type conversion by removing water and hydrogen. In this regard, since it is not i-type conversion by adding impurities like silicon, etc., it can be said to include a novel technical idea. .

[0151] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of transistors using oxide semiconductors will be described with reference to FIGS. 6 to 9. In the following description, an ideal situation is assumed for ease of understanding, and not all of it necessarily reflects the actual situation. Also, it should be noted that the following description is merely a consideration and does not affect the validity of the invention.

[0152] FIG. 6 is a cross-sectional view of a transistor (thin-film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI) on a gate electrode (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon, and an insulating layer is provided so as to cover the source electrode (S) and the drain electrode (D).

[0153] FIG. 7 shows an energy band diagram (schematic diagram) in the A-A' cross-section of FIG. 6. Also, the black circles (●) in FIG. 7 indicate electrons, and the white circles (○) indicate holes, each having a charge (-q, +q ). After applying a positive voltage (V ) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V D = 0), and the solid line indicates the case where a positive voltage (V ) is applied to the gate electrode (V G = 0), and the solid line indicates the case where a positive voltage (V G ) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, It shows an off state where carriers (electrons) are not injected from the electrode to the oxide semiconductor side and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. State.

[0154] Figure 8 shows an energy band diagram (schematic diagram) of the cross-section of B-B' in Figure 6. Figure 8(A) shows a state where a positive voltage (V G > 0) is applied to the gate electrode (GE1), showing an on state where carriers (electrons) flow between the source electrode and the drain electrode. Also, Figure 8(B) shows a state where a negative voltage (V G < 0) is applied to the gate electrode (GE1), showing a case of an off state (a state where minority carriers do not flow).

[0155] Figure 9 shows the relationship between the vacuum level, the work function of the metal (φ M ), and the electron affinity (χ) of the oxide semiconductor. Show.

[0156] At room temperature, electrons in the metal are degenerate, and the Fermi level is located within the conduction band. On the other hand, Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located away from the intrinsic Fermi level (E i ) at the center of the bandgap and closer to the conduction band. Note that in the oxide semiconductor, it is known that a part of hydrogen becomes a donor and is one of the factors for n-type conversion. Yes.

[0157] On the other hand, the oxide semiconductor according to one aspect of the disclosed invention removes hydrogen, which is a factor for n-type conversion, from the oxide semiconductor and purifies it to high purity so that it contains as few elements (impurity elements) other than the main components of the oxide semiconductor as possible, making it intrinsic (i-type) or attempting to make it intrinsic. It is not included, Yes, or it is something that attempts to be intrinsic. That is, instead of adding impurity elements for i - type conversion, impurities such as hydrogen and water are removed as much as possible. By doing so, it is characterized by achieving or approaching a highly purified i - type (intrinsic semiconductor). As a result, the Fermi level (E F ) can be made approximately the same as the intrinsic Fermi level (E i ). This can be achieved.

[0158] The bandgap (E g ) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is said to be 4.3 V. The work function of titanium (Ti) constituting the source electrode and the drain electrode is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal - oxide semiconductor interface, a Schottky - type barrier for electrons is not formed.

[0159] At this time, as shown in Fig. 8(A), electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the energetically stable lowest part of the oxide semiconductor).

[0160] Also, as shown in Fig. 8(B), when a negative potential is applied to the gate electrode (GE1), since the number of minority carriers, holes, is substantially zero, the current becomes a value extremely close to zero.

[0161] By highly purifying the oxide semiconductor so that elements (impurity elements) other than the main component are contained as little as possible, it becomes intrinsic (i - type) or substantially intrinsic. As a result, the interface characteristics with the gate insulating layer become apparent. Therefore, the gate insulating layer is required to be able to form a good interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high - density plasma generated at a power frequency in the VHF band to microwave band or a sputtering is required. It is preferable to use an insulating layer or the like formed by a method.

[0162] While purifying the oxide semiconductor to high purity, the interface between the oxide semiconductor and the gate insulating layer is made good so that, for example, when the channel width (W) of the transistor is 1×10 4 μm and the channel length (L) is 3 μm, an off-current of 10 -13 A or less and a subthreshold swing value (S value) of 0.1 V / dec. (gate insulating layer thickness: 100 nm) can be realized.

[0163] Thus, by purifying to high purity so that elements (impurity elements) other than the main component of the oxide semiconductor are not contained as much as possible, the operation of the transistor can be made good.

[0164] <Modification example> Figs. 10 to 13 show modification examples of the configuration of the semiconductor device. Hereinafter, as a modification example, the configuration of the transistor 162 different from the above will be described. That is, the configuration of the transistor 160 is the same as the above.

[0165] Fig. 10 shows a semiconductor device having a gate electrode 136d under the oxide semiconductor layer 140, and source electrodes or drain electrodes 142a and source electrodes or drain electrodes 142b in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 1 40. Note that since the planar structure may be appropriately changed corresponding to the cross section, here, only the cross section will be shown.

[0166] As a major difference between the configuration shown in Fig. 10 and the configuration shown in Fig. 2, the contact between the source electrode or drain electrode 142a and the source electrode or drain electrode 142b and the oxide semiconductor layer 140 ​ There is a subsequent position. That is, in the configuration shown in FIG. 2, on the upper surface of the oxide semiconductor layer 140, the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are in contact, while in the configuration shown in FIG. 10, on the lower surface of the oxide semiconductor layer 140, the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are in contact. And due to this difference in contact, the arrangements of other electrodes, insulating layers, etc. are different. The details of each component are the same as those in FIG. 2. Specifically, the semiconductor device includes a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, and an oxide semiconductor layer 140 provided on the gate insulating layer 138 and in contact with the upper side surfaces of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c.

[0167] On the transistor 162, a protective insulating layer 144 is provided so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144.

[0168]

[0169] ​​​​​​​​​​​exist. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with openings that reach the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b, and through the openings, the electrodes 150d and 150e are formed in contact with the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b. Also, similar to the electrodes 150d and 150e, the electrodes 150a, 150b, and 150c that are in contact with the electrodes 136a, 136b, and 136c are formed through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. Also, an insulating layer 152 is provided on the interlayer insulating layer 146, and the electrodes 154a, 154b, 154c, and 154d are provided so as to be embedded in the insulating layer 152. Here, the electrode 154a is in contact with the electrode 150a, the electrode 154b is in contact with the electrode 150 b, the electrode 154c is in contact with the electrodes 150c and 150d, and the electrode 1 54d is in contact with the electrode 150e.

[0170] FIG. 11 shows an example of a configuration having a gate electrode 136d on the oxide semiconductor layer 140. Here, FIG. 11(A) shows an example of a configuration in which the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140, and FIG. 11(B) shows an example of a configuration in which the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140.

[0171] FIG. 11 is an example of a configuration having a gate electrode 136d on the oxide semiconductor layer 140. Here, FIG. 11(A) is an example of a configuration in which the source electrode or the drain electrode 142a or the source electrode or the drain electrode 142b is in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140, and FIG. 11(B) is an example of a configuration in which the source electrode or the drain electrode 142a or the source electrode or the drain electrode 142b is in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140.

[0172] A major difference between the configuration shown in FIG. 2 or FIG. 10 and the configuration shown in FIG. 11 is that it has a gate electrode 136d on the oxide semiconductor layer 140. Another major difference between the configuration shown in FIG. 11(A) and the configuration shown in FIG. 11(B ) is whether the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b contact either the lower surface or the upper surface of the oxide semiconductor layer 140. Due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. The details of each component are the same as those in FIG. 2 and the like . Specifically, the semiconductor device shown in FIG. 11(A) includes a source electrode or drain electrode 142a provided on the interlayer insulating layer 128, a source electrode or drain electrode 142b, and a source electrode

[0173] or drain electrode 142a, a source electrode or drain electrode 142b, an oxide semiconductor layer 140 that contacts the upper surface of the source electrode or drain electrode 142a, a source electrode or drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140 , and a gate electrode 136d in a region that overlaps the oxide semiconductor layer 140 on the gate insulating layer 138 .

[0174] Also, the semiconductor device shown in FIG. 11(B) includes an oxide semiconductor layer 140 provided on the interlayer insulating layer 128, a source electrode or drain electrode 142a provided so as to contact the upper surface of the oxide semiconductor layer 140, a source electrode or drain electrode 142b, an oxide semiconductor layer 140, a source electrode or drain electrode 142a, and a source electrode or drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, a source electrode or drain electrode 142b, and a gate electrode 136d in a region that overlaps the oxide semiconductor layer 140 on the gate insulating layer 138 .

[0175] ​​In the configuration shown in FIG. 11, there are cases where components can be omitted compared to the configuration shown in FIG. 2 (for example, electrode 150a, electrode 154a, etc.). In this case, a secondary effect of simplifying the manufacturing process can also be obtained. Of course, it goes without saying that non-essential components can also be omitted in the configuration shown in FIG. 2 and the like. For example, in the case of the electrodes 150a and 154a, etc., a secondary effect of simplifying the manufacturing process can also be obtained. Of course, it goes without saying that non-essential components can also be omitted in the configuration shown in FIG. 2 and the like. In the configuration shown in FIG. 11, there are cases where components can be omitted compared to the configuration shown in FIG. 2 (for example, electrode 150a, electrode 154a, etc.). In this case, a secondary effect of simplifying the manufacturing process can also be obtained. Of course, it goes without saying that non-essential components can also be omitted in the configuration shown in FIG. 2 and the like. In the configuration shown in FIG. 11, there are cases where components can be omitted compared to the configuration shown in FIG. 2 (for example, electrode 150a, electrode 154a, etc.). In this case, a secondary effect of simplifying the manufacturing process can also be obtained. Of course, it goes without saying that non-essential components can also be omitted in the configuration shown in FIG. 2 and the like.

[0176] FIG. 12 is an example of a configuration having a gate electrode 136d under the oxide semiconductor layer 140 when the size of the element is relatively large. In this case, since the requirements for surface flatness and coverage are relatively loose, there is no need to form wiring, electrodes, etc. embedded in the insulating layer. For example, by patterning after forming the conductive layer, it is possible to form the gate electrode 136d and the like. Although not shown here, the transistor 160 can also be manufactured in the same manner. FIG. 12 is an example of a configuration having a gate electrode 136d under the oxide semiconductor layer 140 when the size of the element is relatively large. In this case, since the requirements for surface flatness and coverage are relatively loose, there is no need to form wiring, electrodes, etc. embedded in the insulating layer. For example, by patterning after forming the conductive layer, it is possible to form the gate electrode 136d and the like. Although not shown here, the transistor 160 can also be manufactured in the same manner. FIG. 12 is an example of a configuration having a gate electrode 136d under the oxide semiconductor layer 140 when the size of the element is relatively large. In this case, since the requirements for surface flatness and coverage are relatively loose, there is no need to form wiring, electrodes, etc. embedded in the insulating layer. For example, by patterning after forming the conductive layer, it is possible to form the gate electrode 136d and the like. Although not shown here, the transistor 160 can also be manufactured in the same manner. FIG. 12 is an example of a configuration having a gate electrode 136d under the oxide semiconductor layer 140 when the size of the element is relatively large. In this case, since the requirements for surface flatness and coverage are relatively loose, there is no need to form wiring, electrodes, etc. embedded in the insulating layer. For example, by patterning after forming the conductive layer, it is possible to form the gate electrode 136d and the like. Although not shown here, the transistor 160 can also be manufactured in the same manner. FIG. 12 is an example of a configuration having a gate electrode 136d under the oxide semiconductor layer 140 when the size of the element is relatively large. In this case, since the requirements for surface flatness and coverage are relatively loose, there is no need to form wiring, electrodes, etc. embedded in the insulating layer. For example, by patterning after forming the conductive layer, it is possible to form the gate electrode 136d and the like. Although not shown here, the transistor 160 can also be manufactured in the same manner. FIG. 12 is an example of a configuration having a gate electrode 136d under the oxide semiconductor layer 140 when the size of the element is relatively large. In this case, since the requirements for surface flatness and coverage are relatively loose, there is no need to form wiring, electrodes, etc. embedded in the insulating layer. For example, by patterning after forming the conductive layer, it is possible to form the gate electrode 136d and the like. Although not shown here, the transistor 160 can also be manufactured in the same manner.

[0177] A major difference between the configuration shown in FIG. 12(A) and the configuration shown in FIG. 12(B) is whether the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b, contacts either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. A major difference between the configuration shown in FIG. 12(A) and the configuration shown in FIG. 12(B) is whether the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b, contacts either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. A major difference between the configuration shown in FIG. 12(A) and the configuration shown in FIG. 12(B) is whether the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b, contacts either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. A major difference between the configuration shown in FIG. 12(A) and the configuration shown in FIG. 12(B) is whether the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b, contacts either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. The details of each component are the same as those in FIG. 2 and the like.

[0178] Specifically, the semiconductor device shown in FIG. 12(A) includes a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, and a source electrode or drain electrode 142a provided on the gate insulating layer 138, a source electrode or drain electrode 142b Specifically, the semiconductor device shown in FIG. 12(A) includes a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, and a source electrode or drain electrode 142a provided on the gate insulating layer 138, a source electrode or drain electrode 142b Specifically, the semiconductor device shown in FIG. 12(A) includes a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, and a source electrode or drain electrode 142a provided on the gate insulating layer 138, a source electrode or drain electrode 142b A drain electrode 142b, a source electrode or drain electrode 142a, and an oxide semiconductor layer 140 in contact with the upper surface of the inner electrode 142b.

[0179] In addition, the semiconductor device shown in FIG. 12B has a gate electrode 1 provided on an interlayer insulating layer 128. 36d, a gate insulating layer 138 provided on the gate electrode 136d, and a gate insulating layer 13 An oxide semiconductor layer 140 is provided in a region overlapping with the gate electrode 136d on the oxide semiconductor layer 136. A source or drain electrode 14 provided in contact with the upper surface of the semiconductor layer 140 2a, and a source or drain electrode 142b.

[0180] In addition, in the configuration shown in FIG. 12, compared to the configuration shown in FIG. 2, some components can be omitted. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0181] FIG. 13 shows a case where the size of the element is relatively large, in which a gate electrode is formed on the oxide semiconductor layer 140. In this case, the flatness of the surface and the coverage are not important. Since the requirements for this are relatively mild, wiring, electrodes, etc. can be embedded in the insulating layer. For example, the gate electrode can be formed by patterning after the conductive layer is formed. Although not shown here, it is possible to form transistors 136d, etc. It is possible to prepare 160 in the same manner.

[0182] The major difference between the configuration shown in FIG. 13(A) and the configuration shown in FIG. 13(B) is that the source electrode The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. It is a matter of whether it contacts on the lower surface or the upper surface of 40. And Due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. The details of each component are the same as those in FIG. 2 and the like.

[0183] Specifically, the semiconductor device shown in FIG. 13(A) includes a source electrode or drain electrode 142a, a source electrode or drain electrode 142b, and a source electrode or drain electrode 142a, a source electrode or drain electrode 142b, and an oxide semiconductor layer 140 that contacts the upper surface of the source electrode or drain electrode 142a, a source electrode or drain electrode 142b, and an oxide semiconductor layer 140, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate electrode 1 36d provided in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. It has.

[0184] Also, the semiconductor device shown in FIG. 13(B) includes an oxide semiconductor layer 140 provided on the interlayer insulating layer 128, a source electrode or drain electrode 142a provided so as to contact the upper surface of the oxide semiconductor layer 140, a source electrode or drain electrode 142a, a source electrode or drain electrode 142b, and an oxide semiconductor layer 140, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate electrode 136d provided in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. It has.

[0185] Note that also in the configuration shown in FIG. 13, compared with the configuration shown in FIG. 2 and the like, components may be omitted. Even in this case, the effect of simplifying the manufacturing process can be obtained.

[0186] As described above, a semiconductor device having a novel structure can be realized according to one embodiment of the disclosed invention. In this embodiment, the transistor 160 and the transistor 162 are stacked. Although the above example has been described, the configuration of the semiconductor device is not limited to this example. In this embodiment, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as that in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0187] For ease of understanding, the present embodiment will be described with reference to a semiconductor device having a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the above semiconductor devices, more advanced semiconductor devices can be constructed. By using multiple devices, it is possible to configure a NAND type or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0188] The semiconductor device according to this embodiment has a very low off-state current characteristic of the transistor 162. It is possible to retain information for a long period of time. In other words, it is the type of memory required for DRAM. No refresh operation is required, and power consumption can be reduced. It can be used as a storage device.

[0189] In addition, in order to write information by switching the transistor 162, It does not require high voltage and does not have the problem of element degradation. Furthermore, it is possible to turn the transistor on and off with a Therefore, since information writing and erasing are performed, high-speed operation can be easily achieved. Also, there is an advantage that an operation for erasing information required in a flash memory or the like is unnecessary.

[0190] In addition, transistors using materials other than oxide semiconductors can operate at a higher speed compared to transistors using oxide semiconductors. Therefore, by using these transistors, it is possible to read the stored content at high speed.

[0191] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0192] (Embodiment 2) In this embodiment, the circuit configuration and operation of a semiconductor device according to an aspect of the present invention will be described.

[0193] FIG. 14 shows an example of a circuit diagram of a semiconductor device (hereinafter also referred to as a memory cell). The memory cell 200 shown in FIG. 14 includes a source line SL, a bit line BL, a first signal line S1, a second signal line S2, a word line WL, a transistor 201, a transistor 202, and a transistor 203. Transistors 201 and 203 are formed using materials other than oxide semiconductors, and transistor 202 is formed using an oxide semiconductor.

[0194] Here, one of the gate electrode of transistor 201 and the source electrode or drain electrode of transistor 202 is electrically connected. Also, the source line SL and the source electrode of transistor 201 are electrically connected, and the drain electrode of transistor 201 and the t​​​​​​ is electrically connected to the source electrode of the transistor 203. And the bit line BL and is electrically connected to the drain electrode of the transistor 203, and is also electrically connected to the first signal line S1 and the other of the source electrode or the drain electrode of the transistor 202, is electrically connected to the second signal line S2, and the gate electrode of the transistor 202 is electrically connected to the word line WL and is electrically connected to the gate electrode of the transistor 203. is electrically connected to the gate electrode of the transistor 203.

[0195] FIG. 15 shows an example of the writing circuit 211. The first signal line S1 is electrically connected to the writing potential Vwrite or Vs1_0 via a switch. The switch is controlled by the signal Φw1 and the signal Φw2. is electrically connected to the writing potential Vwrite or Vs1_0 via a switch. The switch is controlled by the signal Φw1 and the signal Φw2.

[0196] FIG. 16 shows an example of the reading circuit 212. The reading circuit 212 has a sense amplifier circuit. The reading circuit 212 is electrically connected to the bit line BL. The bit line BL is connected to one terminal of the resistor R via a switch. The other terminal of the resistor R is connected to Vdd. And the potential Vin determined by the resistance ratio between the resistor R and the load connected to the bit line BL is input to one of the input terminals of the sense amplifier circuit. One of the input terminals of this sense amplifier circuit is connected to the bit line BL via a switch or the like, and the potential Vin is also called the potential of the bit line. The resistor R is not limited to a resistive element, and as long as it effectively functions as a resistor, it can be a diode connection of a transistor, a transistor whose gate electrode is controlled by another signal, or another circuit. The other of the input terminals of the sense amplifier circuit is connected to the reading potential Vread. Also, the bit line BL is a switch has a sense amplifier circuit. The reading circuit 212 is electrically connected to the bit line BL. The bit line BL is connected to one terminal of the resistor R via a switch. The other terminal of the resistor R is connected to Vdd is connected. And the potential Vin determined by the resistance ratio between the resistor R and the load connected to the bit line BL is input to one of the input terminals of the sense amplifier circuit. One of the input terminals of this sense amplifier circuit is connected to the bit line BL via a switch or the like, and the potential Vin is also called the potential of the bit line. The resistor R is not limited to a resistive element, and as long as it effectively functions as a resistor, it can be a diode connection of a transistor, a transistor whose gate electrode is controlled by another signal, or another circuit. The other of the input terminals of the sense amplifier circuit is connected to the reading potential Vread. Also, the bit line BL is a switch is fine, and it can be a diode connection of a transistor, a transistor whose gate electrode is controlled by another signal, or another circuit. The other of the input terminals of the sense amplifier circuit is connected to the reading potential Vread. Also, the bit line BL is a switch by other signals, or another circuit. The other of the input terminals of the sense amplifier circuit is connected to the reading potential Vread. Also, the bit line BL is a switch is connected to the reading potential Vread. Also, the bit line BL is a switch is connected to the potential VBL_0 through. The switch is controlled by the signal Φr1 and the signal Φr2 as follows.

[0197] Next, the write and read operations of the memory cell 200 shown in FIG. 14 will be described. The memory cell 200 can take various states because the effective resistance of the transistor 201 changes according to the charge or potential accumulated at the node A. And since the off-current of the transistor 202 is extremely small or substantially zero, the charge or potential at the node A is held for a long time. In the following description, writing means moving the memory cell to a predetermined state by charging and discharging the node A of the memory cell. Reading means comparing the potential determined according to the state of the memory cell with a predetermined potential. Writing and reading are also used in the following meaning according to the context. Writing, or data writing, refers to a series of operations for writing predetermined data into the memory cell. Reading, or data reading, refers to a series of operations for reading the data stored in the memory cell. When writing to the memory cell 200, the source line SL is set to 0V, the word line WL is set to 0V to turn off the transistor 203, and the second signal line S2 is set to Vdd to turn on the transistor 202. The read circuit 212 connected to the bit line BL asserts (activates) the signal Φr2 and de-asserts (deactivates) the signal Φr1. As a result, the potential VBL_0 is applied to the bit line BL. The write circuit 211 connected to the first signal line S1 de-asserts the signal Φw2 and asserts the signal Φw1 to enter the write state. As a result,

[0198] ​​​​​​​​​​​​​​As a result, a write potential Vwrite corresponding to the data to be written is applied to the first signal line. And oh, at the end of writing, before the potential of the first signal line S1 changes, the second signal line S 2 is set to 0V to turn off the transistor 202.

[0199] As a result, charges corresponding to the potential of the first signal line Vwrite are accumulated at node A, and a state corresponding to the data is written. Since the off-current of the transistor 202 is extremely small or substantially 0, the potential of the gate electrode of the transistor 201 is maintained over a long period of time. maintained.

[0200] When reading from the memory cell 200, the source line SL is set to 0V, the word line WL is set to Vd d to turn on the transistor 203, and the second signal line S2 is set to 0V to turn off the transistor 202. The write circuit 211 connected to the first signal line S1 asserts the signal Φw 2 and de-asserts the signal Φw1. As a result, VS1_0 is applied to the first signal line. The read circuit 212 connected to the bit line BL de-asserts the signal Φr2, asserts the signal Φr1, and enters the read operation state.

[0201] As a result, according to the state of node A of the memory cell 200, the effective resistance value of the transistor 201 of the memory cell 200 is determined. The read circuit 212 reads by comparing the potential Vin (the potential of the bit line Vin) determined according to the effective resistance value of the transistor 201 of the memory cell 200 with the read potential Vread.

[0202] Note that the "potential Vin (potential Vin) of the bit line" compared in reading includes the switch including the potential of the node at the input terminal of the sense amplifier circuit connected to the bit line via a switch or the like be assumed. That is, the potential to be compared in the read circuit does not necessarily have to be exactly the same as the potential of the bit line .

[0203] Next, the write operation which is one aspect of the present invention will be described. The write operation of one aspect of the present invention has, as shown in FIG. 17, three steps of a first write (write for obtaining variation information), a first read (read for obtaining variation information), and a second write (write of data to be stored). Each step will be described below .

[0204] The first write is for the purpose of initializing the memory cell and writes the memory cell into a predetermined state . Specifically, using Vwi (potential for initialization) as the write potential Vwrite, the above-described write operation is performed .

[0205] The first read is for the purpose of obtaining variation information of the memory cell. The threshold voltage of the transistor 201 varies depending on the memory cell. For example, as shown in FIG. 18(A) , it has a distribution .

[0206] As a result, after performing the first write and then performing the above-described read operation, the potential Vin (or the potential of the bit line BL) of the node at the input terminal of the sense amplifier circuit, which is determined according to the effective resistance value of the memory cell, also varies depending on the memory cell. For example, as shown in FIG. 18(B) , it has a distribution .

[0207] Therefore, in the first read, in order to obtain variation information of the memory cell, for the read Perform a detailed readout of the potential Vin of the relevant bit line BL. Specifically, the readout circuit 21 in 2, as the readout potential Vread applied to the sense amplifier circuit, a plurality of potentials Vri_ 0 to Vri_m (m is an integer greater than 0), the potential Vri_j (j is an integer greater than or equal to 0 and less than or equal to m is used to compare Vin with Vri_j. This comparison is performed multiple times by changing j at Vri_j. As a result, the potential Vin of the bit line related to the readout is determined to belong to which interval delimited by Vri_j (the interval delimited by Vri_j and Vri_(j + 1)).

[0208] Each of the plurality of potentials Vri_j (j is an integer greater than or equal to 0 and less than or equal to m) is, for example, such that the threshold voltage Vth of the transistor 201 satisfies V0 + j×ΔVth < Vth < V0 + (j + 1)×ΔV th in the memory cell, and Vri_j < Vin < Vri_(j + 1) is determined. Among the intervals delimited by V0 + j×ΔVth (j is an integer greater than or equal to 0 and less than or equal to m), the interval delimited by V0 + i×ΔVth and V0 + (i + 1)×ΔVth is called interval i (i is an integer greater than or equal to 0 and less than or equal to m - 1). The Vri_j that satisfies this can be determined, for example, from simulations or experiments.

[0209] V0, m, and ΔVth are determined such that the threshold voltage of the transistor 201 of a normal memory cell is included in the interval from V0 to V0 + (m + 1)×ΔVth. ΔVth is a quantity that determines the distribution width of the state of the memory cell after writing. When ΔVth is small, the distribution of the state of the memory cell after writing becomes narrow. Consider the degree of multi - valuedness "n" of the data written into the memory cell, the power supply potential, etc. and determine. ​​​​​​

[0210] Note that the variation in Vri is mainly due to the variation in the Vth of transistor 201, but variations due to other factors are also conceivable. That is, even if the Vth of transistor 201 is fixed, the potential Vin is still considered to have a narrow distribution. In consideration of this, more accurately Vri_j may be set to, for example, a representative value of the distribution of Vri_j.

[0211] In the first read, a method of multiple comparisons using a plurality of potentials Vri_0 to Vri_m (m is an integer greater than 0) will be described with an example. For example, by performing m - 1 comparisons in order for a plurality of potentials Vri_1 to Vri_(m - 1), it is possible to determine in which interval the threshold voltage Vth of the transistor 20 of the memory cell belongs.

[0212] Also, as shown in FIG. 19, it is also possible to take a method of feeding back the comparison result and repeating the comparison. Using FIG. 19, for the case of m = 8, a method of determining in which interval the threshold voltage Vth of the transistor 201 of the memory cell belongs by performing three comparisons will be described. First, as the read potential Vread, a potential Vri_4, which is near the center of a plurality of potentials Vri_0 to Vri_8,

[0213] is used to perform the first comparison with the potential Vin. As a result of the first comparison, if the output of the sense amplifier circuit is "0" (SA_OUT = "0"), that is, when the potential Vin < the potential Vri_4, a potential Vri_2, which is near the center of a plurality of potentials Vri_1 to Vri_4, is used as the read potential Vread to perform the second comparison with the potential Vin. Also, if the output of the sense amplifier circuit is "1" (SA_OUT = "1"), that is, when the potential Vin is... > In the case of the potential Vri_4, it is the potential near the center of the plurality of potentials Vri_4 to Vri_7. Using the potential Vri_6 as the read potential Vread, a second comparison with the potential Vin is performed.

[0214] As a result of the comparison with the potential Vri_2 as the read potential Vread, SA_OUT = "0", that is, when the potential Vin < the potential Vri_2, the potential Vri_1 is used as the read potential Vread and a third comparison with the potential Vin is performed. Similarly, when SA_OUT = "1", that is, the potential Vin > the potential Vri_2, the potential Vri_3 is used as the read potential Vread, and the potential Vin is compared for the third time. Similarly, as a result of the comparison with the potential Vri_6 as the read potential Vread and SA_OUT = "0", that is, when the potential Vin < the potential Vri_6, the potential Vri_5 is used as the read potential Vread and a third comparison with the potential Vin is performed. Similarly when SA_OUT = "1", that is, when the potential Vin > the potential Vri_6, the potential Vri_7 is used as the read potential Vread and a third comparison with the potential Vin is performed.

[0215] As a result of the third comparison, when the potential Vin < the potential Vri_1, the threshold voltage Vth of the transistor 2 01 of the memory cell can be determined to belong to interval 0. Similarly hereinafter, if the potential Vin > the potential Vri_1, it belongs to interval 1, if the potential Vin < the potential Vri_3, it belongs to interval 2, if the potential Vin > the potential Vri_3, it belongs to interval 3, if the potential Vin < the potential Vri_5, it belongs to interval 4, if the potential Vin > the potential Vri_5, it belongs to interval 5, if the potential Vin < the potential Vri_7, it belongs to interval 6, if the potential Vin > the potential Vri_7, it belongs to interval 7, and the threshold voltage Vth of the transistor 201 of the memory cell can be determined to belong. As described above, the comparison result is fed back. By repeatedly comparing, even when the number of intervals is m = 2 M cases, the number of comparisons can be reduced to M times and the reading can be performed.

[0216] In addition, when performing multiple comparisons in the first reading, except for the first comparison, since there is no charge and discharge of the bit line, high-speed reading is possible.

[0217] In addition, in the first reading, as a method of comparison using a plurality of potentials VVri_0 to Vri_m (m is an integer greater than 0), an example of performing multiple comparisons has been described, but it is also possible to perform only one comparison. Specifically, m - 1 sense amplifier circuits may be provided in the reading circuit.

[0218] Next, in the second writing (writing of data to be stored), desired data is written to the memory cell. As data, n values of "0", "1", ··· "n - 1" are to be written. Also, let the writing potential when writing data "i" (i is an integer from 0 to n) to a memory cell whose threshold voltage of transistor 201 is the representative value Vth_typ be Vw_i.

[0219] In the second writing, when writing data "i" to the memory cell, writing is performed using a corrected writing potential based on which interval the memory cell belongs to. For example, let the interval including the representative value Vth_typ of the threshold voltage of transistor 201 be interval i0. At this time, the correction voltage in interval i0 + k (k is an integer from -i0 to m - 1 - i0) is k × ΔVth. Table 1 shows the threshold voltage and the correction voltage corresponding to the range of each interval of the threshold voltage of transistor 201.

[0220] ​​​​​​​​​​​​​

Table 1

[0221] For example, in interval i0, the correction voltage is 0. In the adjacent interval that is ΔVth greater than interval i0, the correction voltage is ΔVth. In the adjacent interval that is ΔVth smaller than interval i0, the correction voltage is -ΔV th. When the memory cell belongs to interval (i0 + k), writing is performed using the corrected write bit Vw_i + k×ΔVth.

[0222] By performing such writing, the distribution of the state after writing can be narrowed. As a result, it is possible to improve the degree of multi-valuedness. Also, in the writing operation which is one aspect of the present invention, since it only writes and reads once at the first time, compared with the conventional verify write operation which repeats writing and reading many times, high-speed writing can be realized.

[0223] Note that Fig. 20 shows an example of data after writing without correction (that is, when all correction voltages are set to 0 V) (Fig. 20(A)) and an example of data after writing with correction ( Fig. 20(B)). In Fig. 20(A), the write potential is constant regardless of the memory cell, and the state after writing has a distribution similar to the distribution of the threshold voltage of transistor 201. As a result, for example, the memory cell can store only states of 4 values or less. On the other hand, in Fig. 20(B), since the write potential is corrected for each memory cell, the state after writing has a narrow distribution of about ΔVth. As a result, for example, the memory cell can store 16-value states.

[0224] Next, the read operation (the read operation of the stored data) according to one aspect of the present invention will be described.

[0225] To read n values of "0", "1", ··· "n - 1" as data, multiple comparisons are performed using a potential Vread selected from a plurality of potentials Vr_j to Vr_n - 2 (n - 2 is an integer greater than 0) as the potential Vr_j (j is an integer from 0 to n - 2). The read potential Vr_j is set to be a potential between the value of the potential Vin when reading the memory cell of data "j" and the value of the potential Vin when reading the memory cell of data "j + 1". That is how it is determined.

[0226] A method of performing multiple comparisons using a plurality of potentials Vr_j to Vr_n - 2 (n - 2 is an integer greater than 0) will be described with an example. For example, by performing n - 1 comparisons in order for a plurality of potentials Vr_j (j is an integer from 0 to n - 2) , it is possible to determine in which state of data "0", "1", ··· "n" the state of the memory cell is. Also, it is possible to use a method similar to the method described with reference to FIG. 1 9 in the first read operation. As a result, it is also possible to read with a small number of comparisons. Furthermore, it is possible to provide n - 1 sense amplifier circuits and perform a read in one comparison.

[0227] An example of specific operating voltages (potentials) is shown in Table 2. For example, the degree of multi - valuedness is n = 16, the power supply potential is Vdd = 2V, the representative value of the threshold voltage of transistor 201 is Vth_typ = 0. 3V, the interval width of the threshold voltage of transistor 201 is ΔVth = 0.04V, the number of intervals of the threshold voltage of transistor 201, and the interval of Vin of the read potential in the first read operation of transistor 201, and the interval of Vin of the read potential in the first read operation It is sufficient to set the number of rooms to m = 8 and the writing potential of the first writing operation to Vwi = 0.98V. .

[0228] [Table 2]

[0229] In addition, the correction voltages corresponding to the ranges of each section of the threshold voltage of the transistor 201 are shown in Table 3. The values to be used for the reading potentials Vri_0 to Vri_8 (i is an integer from 0 to 8) related to the first reading ) are the values shown in Table 4, and the pre-correction writing potentials Vw_0 to Vw_15 (i = an integer from 0 to 15) are the values shown in Table 5, and the reading potentials V r_0 to Vr_14 related to the reading of the stored data are the values shown in Table 6, and they can each be used. By using such voltage values , writing and reading operations can be performed at potentials within Vdd = 2V. .

[0230] [Table 3]

[0231] [Table 4]

[0232] [Table 5]

[0233] [Table 6]

[0234] As described above, the writing in one aspect of the present invention is the first writing (for obtaining variation information) (writing), first reading (reading for obtaining variation information), and second writing (writing of data to be stored), and has three steps. By performing the first writing and the first reading, variation information of memory cells is obtained, and in the second writing, predetermined data is written to the memory cells using a writing voltage corrected based on the obtained variation information of the memory cells. As a result, it is possible to narrow the distribution of the state after writing.

[0235] FIG. 21 shows an example of a block circuit diagram of a semiconductor device according to one aspect of the present invention having a memory cell array of kr×(kc×kw). For example, if the degree of multiplicity is n = 4, the storage capacity is 2×kr×(kc×kw) bits, and if n = 16, the storage capacity is 4×kr×(kc ×kw) bits. Generally, if n = 2 (k is an integer of 1 or more), compared with the case of binary, the memory capacity becomes k times. k

[0236] The semiconductor device shown in FIG. 21 includes kr word lines WL and second signal lines S2, kc×kw bit lines BL(1_1) to BL(kw_kc) and first signal lines S1(1_1) to S1( kw_kc), and a plurality of memory cells 200(1, 1) to 200(kr, kw_kc) arranged in a matrix of kr (rows) × horizontal (kc×kw) (kr, kc, kw are natural numbers), a memory cell array 210, a reading circuit 212, a writing circuit 211, a plurality of multiplexers 219, a driving circuit 213 for the second signal line and the word line, a column decoder 21 4, an address buffer 215, a data buffer 218, a potential generation circuit 217, and a control circuit 2 It is composed of peripheral circuits such as 16. As other peripheral circuits, a refresh circuit or the like may be provided. Here, kc is the number of columns that can be independently selected by the column decoder 214, and kw is the number of columns selected simultaneously.

[0237] The memory cell 200 can use the circuit shown in FIG. 14. Each memory cell (taking the memory cell 200(i, j) as a representative. Here, i is an integer from 1 to kr, and j is an integer from 1 to kc×kw) is connected to the bit line BL(j), the first signal line S1(j), the word line WL(i), the second signal line S2(i), and the source wiring respectively. Also, the bit lines BL(1_1) to BL(kw_kc) and the first signal lines S1(1_1) to S1(k w_kc) are connected to the multiplexer 219. The word lines WL(1) to WL(k r) and the second signal lines S2(1) to S2(kr) are connected to the driving circuits 21 3 of the word lines and the second signal lines respectively.

[0238] Next, each circuit will be described. The write circuit 211 and the read circuit 212 can use the circuits shown in FIGS. 15 and 16 respectively.

[0239] The multiplexer 219 inputs the output signal of the column decoder 214 as a control signal, and connects the bit line selected from kc bit lines to the read circuit 212. Specifically, one of the kc control signals is asserted, and the bit line controlled by the asserted control signal is connected to the BL_S line. Also, the multiplexer 219 connects the first signal line selected from kc first signal lines S1 to the write circuit 211. Specifically, among the kc control signals, one signal is asserted, and the first signal line controlled by the asserted control signal is connected to the write circuit 211. ​One of the signals is asserted, and the first signal line controlled by the asserted control signal is connected to the S1_S line.

[0240] The column decoder 214 uses the column address output from the address buffer 215, the control signal output from the control circuit 2 16, etc. as input signals, and asserts one output signal specified by the address and deasserts the other output signals.

[0241] When the semiconductor device has a configuration of kc = 1, it is not necessary to provide the column decoder 214 and the multiplexer 219. In this case, the writing circuit 211 and the first signal line S1 may be directly connected and the reading circuit 212 and the bit line BL may be directly connected.

[0242] The driving circuit 213 for the second signal line and the word line uses the row address output from the address buffer 215, the control signal output from the control circuit 216, etc. as input signals, and applies a predetermined potential to the word line and the second signal line specified by the address and the other word lines and the second signal line, respectively.

[0243] The potential generation circuit 217 outputs a write potential Vwrite, a read potential Vread, VBL_0, VS1_0, etc. according to the control signal output from the control circuit 216. The write potential Vwrite outputs Vwi in the first write operation and the write potential (Vw_j (j = 0 ~n - 1 integer)) corrected according to the write data and the result of the first read in the second write operation. The read potential Vread outputs one of the potentials of Vr_j (j = 0~n - 2 integer) in the data read operation and Vri_ in the first read operation. Outputs any potential of j (where j is an integer from 0 to m + 1). These potentials are specified by the output signal of the control circuit. For example, it may have a digital-to-analog converter (DAC) that uses the digital signal representing the voltage level output from the control circuit as the input signal.

[0244] Note that the potential generation circuit 217 may output a plurality of write potentials Vwrite and a plurality of read potentials Vread. For example, when there are multiple write circuits 211 and it is necessary to write different potentials to each of them, the appropriate potential can be supplied to each write circuit 211 by the plurality of write potentials Vwrite. Also, for example, when there are multiple read circuits 212 and, as shown in FIG. 19, a method of feeding back the comparison result and repeatedly comparing is taken, the appropriate potential can be supplied to each read circuit 212 by the plurality of read potentials Vread.

[0245] The address buffer 215 uses the address signal input to the semiconductor device and the control signal output from the control signal circuit as input signals, and outputs a predetermined column address and row address at a predetermined timing according to the control signal. It may have an address register.

[0246] The data buffer 218 uses the Din signal input to the semiconductor device, the output signal from the read circuit 212, and the control signal output from the control circuit 216 as input signals, and outputs signals input to the write circuit 21 1, the Dout signal output from the semiconductor device, and signals input to the control circuit 216 as output signals. The data buffer 218 has a data register and, according to the control signal, ​​​​​At a predetermined timing, various input signals are stored in the data register. In the control circuit 216 The output signal input thereto is a signal necessary for selecting a write potential Vwrite, a read potential Vread, etc., and is data to be written to the memory cell, data read from the memory cell, etc. There is.

[0247] The control circuit 216 uses signals such as WE, RE, CLK input to the semiconductor device and output signals from the data buffer 218 as input signals, and includes a potential generation circuit 217, an address buffer 215 , data buffer 218, column decoder 214, second signal line, and word line drive circuit 213 Output various control signals to etc. The control signal is a control signal having information such as a timing control signal for executing a data write operation or a data read operation and a potential to be used. In particular In the second write operation, corrected write potential information is generated from the write potential information and the correction voltage information and output. The control circuit 216 may have a ROM for generating corrected write potential information from the write potential information and the correction Voltage information. For example, when the write potential information is represented by 4 bits, the correction voltage information is represented by 3 bits, and the corrected write Potential is represented by 6 bits, it may have an 8 kbit ROM. Alternatively, it may have an arithmetic circuit for generating corrected write potential information from the write potential information and the correction voltage information.

[0248] Note that in this embodiment, the read potential Vread is generated by the potential generation circuit 217, but it is also possible to generate the read potential Vread by other configurations. For example A reference circuit having the same configuration as the circuit for generating Vin and the memory cell is provided, and the reference circuit has It is possible to generate Vread by controlling the potential of node A of the memory cell. Note that although the configuration in which the read circuit 212 has one sense amplifier circuit has been shown, it may have a plurality of sense amplifier circuits. By having the read circuit 212 have a plurality of sense amplifier circuits, it is possible to reduce the number of read operations.

[0249] The semiconductor device according to the present embodiment can hold information for an extremely long time due to the low off-current characteristics of the transistor 202. That is, the refresh operation required in a DRAM or the like is unnecessary, and power consumption can be suppressed. Further, it can be used as a substantially non-volatile memory device.

[0250] Also, since information writing and the like are performed by the switching operation of the transistor 202, a high voltage is not required, and there is no problem of element degradation. Furthermore, since information writing and erasing are performed by turning the transistor on and off, a high-speed operation can be easily realized. Also, it is possible to directly rewrite information by controlling the potential input to the transistor. As a result, the erase operation required in a flash memory or the like is unnecessary, and a decrease in the operation speed due to the erase operation can be suppressed.

[0251] Also, a transistor using a material other than an oxide semiconductor can operate at a higher speed compared to a transistor using an oxide semiconductor. Therefore, by using this, it is possible to read the stored content at high speed.

[0252] Also, since the semiconductor device according to the present embodiment is a multi-value type, the storage capacity per area can be increased. Therefore, the semiconductor device can be made smaller and more highly integrated.

[0253] As described above, the variation information of the memory cell is acquired, and the write voltage is set according to the variation information. By writing a value to the memory cell, the distribution of the memory cell states after writing is narrowed. As a result, it is possible to improve the degree of multi-value. In the write operation, the potential of the floating node can be directly controlled. Therefore, the write operation is a three-step process: first write, first read, and second write. This operation allows for highly accurate threshold voltage control. Faster than repeated write and read operations in a phi write operation Writing can be achieved.

[0254] (Embodiment 3) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment operates without the supply of power. In addition, the data can be retained even if the data is written or erased. Furthermore, the operation is also fast. Therefore, the semiconductor device can be used to realize a new configuration of a power supply. It is possible to provide a child device. The semiconductor device is then mounted on a circuit board or the like and installed inside each electronic device.

[0255] FIG. 22A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. is made. By applying the semiconductor device according to one aspect of the present invention to a notebook personal computer it is possible to retain information even when there is no power supply. Also, there is no deterioration due to writing and erasing. Furthermore, its operation is also fast. Therefore, applying the semiconductor device according to one aspect of the present invention to a notebook personal computer is suitable

[0256] FIG. 22(B) shows a personal digital assistant (PDA) including the semiconductor device according to the previous embodiment. In the main body 311, there are a display unit 313, an external interface 315, operation buttons 314, etc. There is also a stylus 312 as an accessory for operation. By applying the semiconductor device according to one aspect of the present invention to a PDA, it is possible to retain information even when there is no power supply. Also, there is no deterioration due to writing and erasing. Furthermore, its operation is also fast. Therefore, applying the semiconductor device according to one aspect of the present invention to a PDA is suitable

[0257] FIG. 22(C) shows an electronic book 320 as an example of an electronic paper including the semiconductor device according to the previous embodiment. The electronic book 320 is composed of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337, and can perform an opening and closing operation around the shaft portion 337. With such a configuration, the electronic book 320 can be used like a paper book. By applying the semiconductor device according to one aspect of the present invention to an electronic paper, it is possible to retain information even when there is no power supply. Also, there is no deterioration due to writing and erasing. Furthermore, its operation is also fast ​​​​​​​​​​​​​Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to an electronic paper. Yes.

[0258] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration for displaying different screens, for example, a text can be displayed on the right display unit (display unit 325 in FIG. 22(C)), and an image can be displayed on the left display unit (display unit 327 in FIG. 22(C)). (C)). (C)).

[0259] In addition, FIG. 22(C) shows an example in which the housing 321 is provided with an operation unit or the like. For example, the housing 321 includes a power supply 331, operation keys 333, a speaker 335, and the like. The page can be advanced by operating the operation keys 333. Note that the housing may be provided with a keyboard, a pointing device, or the like on the same surface as the display unit. Further, the back surface or side surface of the housing may be provided with external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, or the like. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. The housing 321 includes a power supply 331, operation keys 333, a speaker 335, and the like. The page can be advanced by operating the operation keys 333. Note that the housing may be provided with a keyboard, a pointing device, or the like on the same surface as the display unit. Further, the back surface or side surface of the housing may be provided with external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, or the like. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. The page can be advanced by operating the operation keys 333. Note that the housing may be provided with a keyboard, a pointing device, or the like on the same surface as the display unit. Further, the back surface or side surface of the housing may be provided with external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, or the like. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. The page can be advanced by operating the operation keys 333. Note that the housing may be provided with a keyboard, a pointing device, or the like on the same surface as the display unit. Further, the back surface or side surface of the housing may be provided with external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, or the like. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. The page can be advanced by operating the operation keys 333. Note that the housing may be provided with a keyboard, a pointing device, or the like on the same surface as the display unit. Further, the back surface or side surface of the housing may be provided with external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, or the like. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. The page can be advanced by operating the operation keys 333. Note that the housing may be provided with a keyboard, a pointing device, or the like on the same surface as the display unit. Further, the back surface or side surface of the housing may be provided with external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, or the like. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary.

[0260] In addition, the electronic book 320 may be configured to be able to wirelessly transmit and receive information. With wireless communication, it is possible to purchase and download desired book data or the like from an electronic book server. In addition, the electronic book 320 may be configured to be able to wirelessly transmit and receive information. With wireless communication, it is possible to purchase and download desired book data or the like from an electronic book server. In addition, the electronic book 320 may be configured to be able to wirelessly transmit and receive information. With wireless communication, it is possible to purchase and download desired book data or the like from an electronic book server.

[0261] Note that the electronic paper can be applied to any field as long as it can display information. is. For example, in addition to e-books, it can be applied to displays on various cards such as posters, in-vehicle advertisements on vehicles such as trains, and credit cards. It can be applied to displays on various cards such as credit cards.

[0262] FIG. 22(D) shows a mobile phone including a semiconductor device according to the previous embodiment. The mobile phone is composed of two housings, a housing 340 and a housing 341. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, and the like. Further, the housing 340 includes a solar cell 349 for charging the mobile phone, an external memory slot 350, and the like. The antenna is built into the housing 341. By applying the semiconductor device according to one aspect of the present invention to a mobile phone, it is possible to retain information even when there is no power supply. Further, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to a mobile phone. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, and the like. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, and the like. The housing 340 includes a solar cell 349 for charging the mobile phone, an external memory slot 350, and the like. The housing 340 includes a solar cell 349 for charging the mobile phone, an external memory slot 350, and the like. The antenna is built into the housing 341. By applying the semiconductor device according to one aspect of the present invention to a mobile phone, it is possible to retain information even when there is no power supply. By applying the semiconductor device according to one aspect of the present invention to a mobile phone, it is possible to retain information even when there is no power supply. Further, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to a mobile phone.

[0263] The display panel 342 has a touch panel function, and FIG. 22(D) shows a plurality of operation keys 345 where video is displayed by a dotted line. The mobile phone has a boost circuit for boosting the voltage output by the solar cell 349 to the voltage required for each circuit. In addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, and the like. The display panel 342 has a touch panel function, and FIG. 22(D) shows a plurality of operation keys 345 where video is displayed by a dotted line. The mobile phone has a boost circuit for boosting the voltage output by the solar cell 349 to the voltage required for each circuit. The mobile phone has a boost circuit for boosting the voltage output by the solar cell 349 to the voltage required for each circuit. In addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, and the like. In addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, and the like.

[0264] The display direction of the display panel 342 changes appropriately according to the usage form. Further, since the camera lens 347 is provided on the same surface as the display panel 342, a video phone is possible. Since the camera lens 347 is provided on the same surface as the display panel 342, a video phone is possible. The peaker 343 and the microphone 344 can be used not only for voice calls but also for video calls, recording, playback, etc. Furthermore, the housing 340 and the housing 341 can slide and be changed from the unfolded state shown in Fig. 22(D) to an overlapping state, enabling miniaturization suitable for portability.

[0265] The external connection terminal 348 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication. Also, by inserting a recording medium into the external memory slot 350, it is possible to support the storage and transfer of a larger amount of data. In addition to the above functions, it may be equipped with an infrared communication function, a television reception function, etc.

[0266] Fig. 22(E) shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera is composed of a main body 361, a display unit (A) 367, an eyepiece 363, an operation switch 364, a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to one aspect of the present invention to a digital camera, it is possible to retain information even when there is no power supply. Also, deterioration due to writing and erasing does not occur. Furthermore, its operation is fast. Therefore, it is preferable to apply the semiconductor device according to one aspect of the present invention to a digital camera.

[0267] Fig. 22(F) shows a television device including the semiconductor device according to the previous embodiment. In the television device 370, a display unit 373 is incorporated in the housing 371. The display unit 373 can display video. Here, a configuration is shown in which the housing 371 is supported by a stand 375.

[0268] The operation of the television device 370 can be performed by operation switches provided in the housing 371 or a separate remote control operation unit 380. By operating keys 379 provided on the remote control operation unit 380 , operations such as channel and volume can be performed, and the video displayed on the display unit 373 can be operated . Further, the remote control operation unit 380 may be configured to include a display unit 377 that displays information output from the remote control operation unit 380 . By applying the semiconductor device according to one aspect of the present invention to a television device, information can be retained even when there is no power supply . Further, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is preferable to apply the semiconductor device according to one aspect of the present invention to a television device .

[0269] Note that the television device 370 is preferably configured to include a receiver, a modem, and the like . The receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via a modem , one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication can be performed .

[0270] The configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments .

Description of Reference Numerals

[0271] 100 Substrate 102 Protective layer 104 Semiconductor region 106 Element isolation insulating layer 108 Gate insulating layer ​​110 Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High-concentration impurity region 122 Metal layer 124 Metal compound region 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c Electrode 132 Insulating layer 134 Conductive layer 136a Electrode 136b Electrode 136c Electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protection insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a Electrode 150b Electrode 150c Electrode 150d Electrode 150e Electrode 152 Insulating layer 154a Electrode 154b Electrode 154c Electrode 154d Electrode 160 Transistor 162 Transistor 200 Memory cell 201 Transistor 202 Transistor 203 Transistor 210 Memory cell array 211 Writing circuit 212 Readout Circuit 213 Drive Circuit 214 Column Decoder 215 Address Buffer 216 Control Circuit 217 Potential Generation Circuit 218 Data Buffer 219 Multiplexer 301 Main Body 302 Housing 303 Display Unit 304 Keyboard 311 Main Body 312 Stylus 313 Display Unit 314 Operation Button 315 External Interface 320 E - book 321 Housing 323 Housing 325 Display Unit 327 Display Unit 331 Power Supply 333 Operation Key 335 Speaker 337 Shaft Portion 340 Housing 341 Housing 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lens 348 External Connection Terminal 349 Solar Cell 350 External Memory Slot 361 Main Body 363 Eyepiece 364 Operation Switch 365 Display Unit (B) 366 Battery 367 Display Unit (A) 370 Television Set 371 Housing 373 Display Unit 375 Stand 377 Display unit 379 Operation key 380 Remote control operation unit

Claims

1. A semiconductor device having a first transistor and a second transistor, wherein one of the source or drain of the second transistor is electrically connected to the gate of the first transistor, a silicon semiconductor layer, a first insulating layer having a region on the silicon semiconductor layer, a first conductive layer having a region on the first insulating layer, a second conductive layer located in the same layer as the first conductive layer and made of the same material as the first conductive layer, an oxide semiconductor layer having a region on the second conductive layer, a second insulating layer having a region on the oxide semiconductor layer, a third conductive layer having a region on the second insulating layer, wherein the silicon semiconductor layer has a channel formation region of the first transistor, the oxide semiconductor layer has a channel formation region of the second transistor, the first conductive layer has a region overlapping with the silicon semiconductor layer, the first conductive layer does not have a region overlapping with the channel formation region of the second transistor, the second conductive layer has a region overlapping with the oxide semiconductor layer, and the first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer.

2. A semiconductor device having a first transistor and a second transistor, wherein one of the source or drain of the second transistor is electrically connected to the gate of the first transistor, a silicon semiconductor layer, a first insulating layer having a region on the silicon semiconductor layer, a first conductive layer having a region on the first insulating layer, a second conductive layer located in the same layer as the first conductive layer and made of the same material as the first conductive layer, an oxide semiconductor layer having a region on the second conductive layer, a second insulating layer having a region on the oxide semiconductor layer, a third conductive layer having a region on the second insulating layer, wherein the silicon semiconductor layer has a channel formation region of the first transistor, the oxide semiconductor layer has a channel formation region of the second transistor, the first conductive layer has a region overlapping with the silicon semiconductor layer, the first conductive layer does not have a region overlapping with the channel formation region of the second transistor, the second conductive layer has a region overlapping with the oxide semiconductor layer, and the first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer. A semiconductor device in which a channel formation region of the first transistor does not overlap with a channel formation region of the second transistor. **Claim 3** In Claim 1 or Claim 2, A semiconductor device in which the second insulating layer contains nitrogen and silicon. **Claim 4** In any one of Claims 1 to 3, A semiconductor device in which the oxide semiconductor layer contains In, M (where M is Ga, Al, Mn, or Co), and Zn.

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