Nitride Semiconductor Device

Abstract

A nitride semiconductor device having a first active region (8) surrounded by an element separation region (9), a source electrode (11) on the first active region (8), a first gate electrode (21) and a second gate electrode (23) located on both sides of the source electrode (11) and separated therefrom in a first direction in a plan view, and at least one drain electrode (31 / 33) located with respect to the first gate electrode (21) or the second gate electrode (23) in a direction opposite that toward the source electrode (11), wherein the source electrode (11), the first gate electrode (21), the second gate electrode (23), and the drain electrode (31 / 33) have finger-shaped portions extending in a second direction perpendicular to the first direction in a plan view, a first dielectric film (43) is formed on the source electrode (11), and the first gate electrode (21) and the second gate electrode (23) are electrically connected by a gate electrode connecting portion (25) formed on the first dielectric film (43).

Description

[Technical field]

[0001] The present disclosure relates to a nitride semiconductor device that uses a nitride semiconductor such as gallium nitride (GaN) as a semiconductor material. [Background technology]

[0002] In recent years, the commercialization of field effect transistors (GaN-FETs) using the nitride semiconductor GaN as a power transistor for switching has progressed. GaN-FETs generally have a structure in which a GaN layer is formed as a channel layer on a semiconductor substrate, and an AlGaN layer is formed as a barrier layer, and two-dimensional electron gas generated by spontaneous polarization and piezoelectric polarization at the heterojunction interface formed by these two layers is used as a channel.

[0003] In a GaN-FET with this structure, the channel current flows in a direction parallel to the substrate. As a result, the source pad, drain pad, and gate pad, which supply voltage and current to the FET from the outside via wire bonding, etc., are all formed on the front side of the substrate. Therefore, in order to reduce the cost of GaN-FET by reducing the chip area, it is important to reduce the pad area that occupies the entire chip area.

[0004] To reduce the pad area, a technology called POE (Pad on Element) or POA (Pad over Active) has been developed, in which pads are formed on the area (active area) where the FET actually operates as a transistor (Patent Document 1, Patent Document 2). By using this technology, there is no increase in chip area due to pads, so it is extremely effective in reducing chip area. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2008-177527 A [Patent Document 2] International Publication No. 2012 / 176399 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the wiring technology for realizing POE in conventional nitride semiconductor devices, the wiring of the gate electrode is formed in the element isolation region outside the active region. As described in paragraph 0038 of Patent Document 2, "The gate electrodes 8 are bundled outside the active region, and are connected to the gate electrode pad layer 23 by bypassing the periphery of the active region." As a result, there is a problem that the wiring length of the gate electrode to reach the gate pad becomes longer as the number of unit transistors included in the power transistor increases to increase the output. In that case, the gate wiring resistance increases, making it impossible to perform high-speed switching. In other words, there is room for improvement in the wiring technology of the gate electrode.

[0007] In view of the above problems, a main object of the present disclosure is to provide a nitride semiconductor device suitable for high-speed switching operation by wiring a gate electrode above an active region, thereby shortening the wiring length to a gate electrode pad and reducing the gate wiring resistance.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] In order to solve the above-mentioned problems, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a semiconductor stacked structure formed on the substrate and including a plurality of nitride semiconductor layers, a first active region on an upper surface side of the semiconductor stacked structure and surrounded by an isolation region, a source electrode on the first active region, a first gate electrode and a second gate electrode positioned on both sides of the source electrode and spaced apart in a first direction in a planar view, and at least one drain electrode positioned in an opposite direction to the source electrode with respect to the first gate electrode or the second gate electrode, the source electrode, the first gate electrode, the second gate electrode, and the drain electrode each have a finger-shaped portion extending in a second direction perpendicular to the first direction in a planar view, a first dielectric film is formed on the source electrode, and the first gate electrode and the second gate electrode are electrically connected to each other by a gate electrode coupling portion formed on the first dielectric film.

[0010] In order to solve the above-described problems, a nitride semiconductor device according to another embodiment of the present disclosure includes a substrate, a semiconductor laminate structure formed on the substrate and including a plurality of nitride semiconductor layers, a first active region on an upper surface side of the semiconductor laminate structure and surrounded by an element isolation region, a first source electrode on the first active region, a first gate electrode and a second gate electrode positioned on both sides of the first source electrode and spaced apart in a first direction in a plan view, a second source electrode, and a third gate electrode and a fourth gate electrode positioned on both sides of the second source electrode and spaced apart in the first direction in a plan view, The electrode, the first gate electrode, the second gate electrode, the second source electrode, the third gate electrode, and the fourth gate electrode have finger-shaped portions extending in a second direction perpendicular to the first direction in a planar view, a first dielectric film is formed on the first source electrode and the second source electrode, the first gate electrode and the second gate electrode are electrically connected by a first gate electrode connecting portion formed on the first dielectric film, and the third gate electrode and the fourth gate electrode are electrically connected by a second gate electrode connecting portion formed on the first dielectric film. Effect of the Invention

[0011] The present disclosure provides a nitride semiconductor device capable of reducing gate wiring resistance. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view of the nitride semiconductor device according to the first embodiment. [Figure 2A] FIG. 2A is a cross-sectional view taken along line IIa-IIa of the nitride semiconductor device of FIG. 1 according to the first embodiment. [Figure 2B] 2B is a cross-sectional view taken along line IIb-IIb of the nitride semiconductor device of FIG. 1 according to the first embodiment. [Figure 2C] 2C is a cross-sectional view taken along line IIc-IIc of the nitride semiconductor device of FIG. 1 according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a first modification of the first embodiment. [Figure 4] FIG. 4 is a plan view of a nitride semiconductor device according to Modification 2 of Embodiment 1. FIG. [Figure 5A] 5A is a cross-sectional view taken along line Va-Va of the nitride semiconductor device of FIG. 4 according to Modification 2 of Embodiment 1. FIG. [Figure 5B] 5B is a cross-sectional view taken along line Vb-Vb of the nitride semiconductor device of FIG. 4 according to Modification 2 of Embodiment 1. FIG. [Figure 5C] 5C is a cross-sectional view taken along line Vc-Vc of the nitride semiconductor device of FIG. 4 according to Modification 2 of Embodiment 1. FIG. [Figure 6] FIG. 6 is a plan view of the nitride semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a plan view of a nitride semiconductor device according to a modification of the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a PN diode used in a nitride semiconductor device in a modification of the second embodiment. [Figure 9] FIG. 9 is a plan view of the nitride semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is an enlarged plan view of the dotted line portion M in FIG. [Figure 11] FIG. 11 is an enlarged plan view of a dotted line portion N in FIG. [Figure 12] FIG. 12 is a plan view of the nitride semiconductor device according to the fourth embodiment. [Figure 13A] 13A is a cross-sectional view of the nitride semiconductor device of Embodiment 4 taken along line XIIIa-XIIIa of FIG. [Figure 13B] 13B is a cross-sectional view of the nitride semiconductor device of FIG. 12 taken along line XIIIb-XIIIb according to the fourth embodiment. [Figure 13C] 13C is a cross-sectional view of the nitride semiconductor device of FIG. 12 taken along line XIIIc-XIIIc according to the fourth embodiment. [Figure 13D] FIG. 13D is a cross-sectional view of the nitride semiconductor device of FIG. 12 according to the fourth embodiment taken along line XIIId-XIIId. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, the realization of the present disclosure is not limited to the current independent claims, and may be expressed by other independent claims.

[0014] (Embodiment 1) FIG. 1 is a plan view of a nitride semiconductor device 10 of the first embodiment, and FIGS. 2A, 2B, and 2C are cross-sectional views taken along lines IIa-IIa, IIb-IIb, and IIc-IIc in FIG. 1, respectively.

[0015] As shown in FIG. 2A, FIG. 2B, and FIG. 2C, a buffer layer 2 made of an AlN layer or an AlGaN layer, a GaN channel layer 3, and an AlGaN barrier layer 4 are formed on a Si substrate 1 by epitaxial growth as a semiconductor laminate structure. On the AlGaN barrier layer 4, a p-type GaN layer 5 and a p-type GaN layer 6 are formed by epitaxial growth on the AlGaN barrier layer 4 and then etching. At the interface between the GaN channel layer 3 and the AlGaN barrier layer 4, a high concentration of two-dimensional electron gas is formed due to the effects of piezoelectric polarization and spontaneous polarization. The region where this two-dimensional electron gas is formed is the first active region 8 shown in FIG. 1, and the region where the two-dimensional electron gas is made highly resistive by ion implantation is the element isolation region 9. The boundary between the first active region 8 and the element isolation region 9 is the boundary 8A of the ion implantation region. The element isolation region 9 may be formed by removing the region containing the two-dimensional electron gas by mesa etching.

[0016] 2A, 2B, and 2C, a SiN film 41 is formed as a surface protective film on the surfaces of the AlGaN barrier layer 4, the p-type GaN layer 5, and the p-type GaN layer 6, and openings are made in the SiN film 41 to form the source electrode 11, the drain electrode 31, and the drain electrode 33. Furthermore, a SiO film is formed as a first dielectric film 43 on the SiN film 41. Openings are made in the SiN film 41 and the first dielectric film 43 on the p-type GaN layer 5 and the p-type GaN layer 6, and a first gate electrode 21 and a second gate electrode 23 are formed, respectively.

[0017] As shown in FIG. 1, the first gate electrode 21 and the second gate electrode 23 are formed at positions on both sides of the finger-shaped source electrode 11, spaced apart in a first direction in a plan view. Here, the first direction is the X direction in FIG. 1. Furthermore, the finger-shaped drain electrode 31 is located in the opposite direction to the source electrode 11 with respect to the first gate electrode 21, and the finger-shaped drain electrode 33 is located in the opposite direction to the source electrode 11 with respect to the second gate electrode 23. Furthermore, the first gate electrode 21 and the second gate electrode 23, together with the p-type GaN layer 5 and the p-type GaN layer 6 located below each, extend in a finger shape in a second direction that is perpendicular to the first direction in a plan view, and are connected at both ends in an arc shape. Here, the second direction is the Y direction in FIG. 1. With this configuration, the leakage current flowing between the source electrode 11, the drain electrode 31, and the drain electrode 33 in the off state is reduced. If the first gate electrode 21 and the second gate electrode 23 are not connected at their ends, the finger-shaped gate electrode needs to reach the element isolation region 9 beyond the boundary 8A of the ion implantation region.

[0018] As shown in FIG. 2B, the first gate electrode 21 and the second gate electrode 23 are connected at their centers by the gate electrode connecting portion 25. The gate electrode connecting portion 25 is formed at the same time as the first gate electrode 21 and the second gate electrode 23 by using the same metal layer. Therefore, the number of manufacturing steps does not increase. However, while the first gate electrode 21 and the second gate electrode 23 are in contact with the p-type GaN layer 5 and the p-type GaN layer 6, respectively, the gate electrode connecting portion 25 is formed on the SiO film, which is the first dielectric film 43, and is electrically insulated from the source electrode 11. In addition, the width (depth direction of the paper surface) of the gate electrode connecting portion 25 is about 3 μm, which is designed to be larger than the first gate electrode 21 and the second gate electrode 23, both of which have a length of about 1 μm. This design makes it possible to perform a wiring process using vias and plugs, which will be described later, which is difficult to perform on the gate electrodes.

[0019] As shown in FIG. 2A, FIG. 2B, and FIG. 2C, a SiO film is formed on the first gate electrode 21, the second gate electrode 23, the gate electrode connecting portion 25, the source electrode 11, the drain electrode 31, and the drain electrode 33 as the second dielectric film 47. In a high voltage transistor, the second dielectric film 47 is designed to have a thickness that prevents dielectric breakdown between the source and drain. For example, in a 600V voltage transistor, when the second dielectric film 47 is an SiO film, its thickness is set to 2 μm to 3 μm. In this case, if the widths of the source electrode 11, the gate electrode connecting portion 25, and the drain electrode 31 are all set to about 3 μm, a via 51 on the source electrode 11, a via 61 on the gate electrode connecting portion 25, and a via 71 on the drain electrode 31 and the drain electrode 33 are formed by a normal photolithography technique and a technique of dry etching the second dielectric film 47 and the first dielectric film 43. Then, plugs 53, 63, and 73 are formed to fill the respective vias. W (tungsten) is used for the plugs 53, 63, and 73, with a TiN film as a barrier layer in the portion in contact with the second dielectric film 47. The plug 53 is connected to the first source lead wiring 55, the plug 63 is connected to the first gate lead wiring 65, and the plug 73 is connected to the first drain lead wiring 75.

[0020] In this embodiment, the first gate electrode 21 and the second gate electrode 23 are connected at their central portions by a gate electrode connecting portion 25. A via 61 is formed in the gate electrode connecting portion 25 for gate wiring. Therefore, the gate wiring resistance is significantly reduced compared to the case where the gate wiring is performed from the end portion of the gate electrode. The reduced gate wiring resistance makes the nitride semiconductor device 10 suitable for high-speed switching operation.

[0021] Moreover, the gate wiring is formed on the first active region 8, not on the element isolation region 9. As a result, no increase in chip area occurs. Furthermore, a capacitance is generated between the source electrode 11 and the gate electrode connector 25 due to the first dielectric film 43. This capacitance is the gate-source capacitance, and in order to prevent erroneous firing in a switching power transistor, it is desirable to increase the gate-source capacitance relative to the gate-drain capacitance. Therefore, by using this embodiment, a switching power transistor can be realized that has a large gate-source capacitance and is capable of preventing erroneous firing.

[0022] In the nitride semiconductor device 10 of the present embodiment, W is used as the plug filling the via, but Al (aluminum) or Cu (copper) may also be used. When Cu is used, the plug and the wiring connected thereto may be formed simultaneously using a dual damascene method.

[0023] 1, one via 61 is provided on the gate electrode connector 25, but multiple vias may be provided if possible from the standpoint of manufacturing technology. The number of vias 71 on the source electrode 11 and the drain electrodes 31 and 33 is preferably large in order to reduce wiring resistance, but is appropriately designed from the standpoint of manufacturing technology for forming vias and plugs.

[0024] As described above, the nitride semiconductor device according to the first embodiment includes a substrate, a semiconductor stacked structure on the substrate, the semiconductor stacked structure including a plurality of nitride semiconductor layers, a first active region on an upper surface side of the semiconductor stacked structure, the first active region being surrounded by an isolation region, a source electrode on the first active region, a first gate electrode and a second gate electrode positioned on both sides of the source electrode spaced apart in a first direction in a planar view, and at least one drain electrode positioned in an opposite direction to the source electrode with respect to the first gate electrode or the second gate electrode, the source electrode, the first gate electrode, the second gate electrode, and the drain electrode each have a finger-shaped portion extending in a second direction perpendicular to the first direction in a planar view, a first dielectric film is formed on the source electrode, and the first gate electrode and the second gate electrode are electrically connected to each other by a gate electrode coupling portion formed on the first dielectric film.

[0025] According to this, by forming the wiring of the gate electrode (including the finger-shaped portion) inside the first active region instead of outside it in a plan view, the wiring length can be shortened and the wiring resistance of the gate can be reduced. As a result, there is an effect that it is suitable for high-speed switching operation. In addition, by forming the wiring of the gate electrode inside the active region in a plan view, there is an effect that the chip area as a nitride semiconductor device can be reduced.

[0026] For example, the first gate electrode, the second gate electrode, and the gate electrode connector may be formed of the same metal layer.

[0027] According to this, the wiring resistance of the gate electrode can be reduced by the gate electrode connecting portion, and there is an effect that the number of manufacturing steps is not increased in the formation of the first gate electrode, the second gate electrode, and the gate electrode connecting portion.

[0028] For example, the width of the gate electrode connecting portion may be greater than the first gate electrode length and the second gate electrode length.

[0029] This enables wiring using vias and plugs for the gate electrode connecting portion, and reduces the chip area.

[0030] (Modification 1 of the first embodiment) FIG. 3 is a partial cross-sectional view of a nitride semiconductor device 110 showing a modification of the first embodiment, and is an enlarged view of a portion corresponding to the vicinity of the source electrode 11 in FIG. 2B of the first embodiment. The drain electrode, via, plug, wiring, etc. are omitted. As shown in FIG. 3, a SiN film 141 is formed as a surface protection film on the surfaces of the AlGaN barrier layer 4 and the p-type GaN layers 105 and 106, and the source electrode 111 is formed by opening the SiN film 141. Furthermore, a SiO film is formed as a first dielectric film 143 on the SiN film 141. The first gate electrode 121 and the second gate electrode 123 are formed on the p-type GaN layers 105 and 106, respectively, by opening the SiN film 141 and the first dielectric film 143. The first gate electrode 121 and the second gate electrode 123 are connected by a gate electrode connecting portion 125.

[0031] In this modification, the side surface of the source electrode 111 that contacts the first dielectric film 143 has a forward tapered cross-sectional shape. The angle of the forward tapered shape is preferably 45° or more and 75° or less, and more preferably 50° or more and 70° or less. This shape improves the coverage of the side surface of the source electrode 111 by the first dielectric film 143, and prevents the occurrence of voids or seams. As a result, even when a reverse bias voltage of several tens of volts is applied between the source electrode 111 and the gate electrode connector 125, the first dielectric film 143 is less likely to undergo dielectric breakdown.

[0032] The forward tapered cross-sectional shape in this modification can be realized by, for example, forming a forward tapered cross-sectional shape by heat treatment of a resist that serves as an etching mask for dry etching.

[0033] As described above, in the nitride semiconductor device according to the first modification of the first embodiment, the portion of the side surface of the source electrode that is in contact with the first dielectric film has a forward tapered shape.

[0034] This improves the coverage of the first dielectric film on the side surface of the source electrode, suppressing the occurrence of voids and seams, and as a result, even when a reverse bias voltage (e.g., several tens of volts) is applied between the source electrode and the gate electrode connection portion, the first dielectric film is less likely to break down.

[0035] (Modification 2 of the first embodiment) FIG. 4 is a plan view of a nitride semiconductor device 210 according to Modification 2 of the first embodiment, and FIGS. 5A, 5B, and 5C are cross-sectional views taken along lines Va-Va, Vb-Vb, and Vc-Vc in FIG. 4, respectively.

[0036] As shown in FIG. 5A, FIG. 5B, and FIG. 5C, a buffer layer 2 made of an AlN layer or an AlGaN layer, a GaN channel layer 3, and an AlGaN barrier layer 4 are formed on a Si substrate 1 by epitaxial growth as a semiconductor laminate structure. On the AlGaN barrier layer 4, a p-type GaN layer 5 and a p-type GaN layer 6 are formed by etching after epitaxial growth. At the interface between the GaN channel layer 3 and the AlGaN barrier layer 4, a high concentration of two-dimensional electron gas (not shown) is formed due to the effects of piezoelectric polarization and spontaneous polarization. The region where this two-dimensional electron gas is formed is the first active region 208 in FIG. 4, and the region where the two-dimensional electron gas is made highly resistive by ion implantation is the element isolation region 209. The boundary between the first active region 208 and the element isolation region 209 is the boundary 208A of the ion implantation region. The element isolation region 209 may be formed by removing the region containing the two-dimensional electron gas by mesa etching.

[0037] 5A, 5B, and 5C, a SiN film 241 is formed as a surface protective film on the surfaces of the AlGaN barrier layer 4, the p-type GaN layer 5, and the p-type GaN layer 6, and the source electrode 211 and the drain electrodes 231 and 233 are formed by opening the SiN film 241. Furthermore, a SiO film is formed as a first dielectric film 243 on the SiN film 241. The SiN film 241 and the first dielectric film 243 are opened, and a first gate electrode 221 and a second gate electrode 223 are formed on the p-type GaN layer 5 and the p-type GaN layer 6, respectively.

[0038] 4, the first gate electrode 221 and the second gate electrode 223 are formed on both sides of the finger-shaped source electrode 211, spaced apart in the X direction. Furthermore, the finger-shaped drain electrode 231 is located on the opposite side to the source electrode 211 with respect to the first gate electrode 221, and the finger-shaped drain electrode 233 is located on the opposite side to the source electrode 211 with respect to the second gate electrode 223.

[0039] In addition, the first gate electrode 221 and the second gate electrode 223, together with the p-type GaN layer 5 and the p-type GaN layer 6 located below them, extend in a finger-like shape in the Y direction, which is a direction perpendicular to the X direction, and are connected at both ends in an arc shape. This configuration reduces the leakage current flowing between the source electrode 211 and the drain electrodes 231 and 233 in the off state. If the first gate electrode 221 and the second gate electrode 223 are not connected at their ends, the finger-like gate electrode needs to reach the element isolation region 209 beyond the boundary 208A of the ion implantation region.

[0040] As shown in FIG. 5B, the first gate electrode 221 and the second gate electrode 223 are connected at their respective centers by the gate electrode connecting portion 225. The gate electrode connecting portion 225 is formed at the same time as the first gate electrode 221 and the second gate electrode 223, using the same metal layer. Therefore, the number of manufacturing steps does not increase. However, the first gate electrode 221 and the second gate electrode 223 are in contact with the p-type GaN layer 5 and the p-type GaN layer 6, respectively, whereas the gate electrode connecting portion 225 is formed on the first dielectric film 243 and is electrically insulated from the source electrode 211. In addition, the width (depth direction of the paper surface) of the gate electrode connecting portion 225 is about 3 μm, which is designed to be larger than the first gate electrode 221 and the second gate electrode 223, both of which have a length of about 1 μm. This design enables a wiring process using vias and plugs, which is difficult to perform on the gate electrodes, as described later.

[0041] As shown in FIG. 5A, FIG. 5B, and FIG. 5C, a SiO film 245 is formed as a field plate film covering the first gate electrode 221, the second gate electrode 223, the source electrode 211, and the drain electrodes 231 and 233. As shown in FIG. 5A and FIG. 5C, an opening is made in the SiO film 245 and the first dielectric film 243 on the source electrode 211, and a low-resistance metal layer 285 serving as a source field plate electrode is formed. The low-resistance metal layer 285 has the effect of mitigating electric field concentration at the drain-side ends of the p-type GaN layer 5 and the p-type GaN layer 6. As a result, the breakdown voltage is improved, and the phenomenon of current collapse, which is a problem in nitride semiconductor devices, is also mitigated. Furthermore, since the low-resistance metal layer 285 is formed on the source electrode 211 except in the vicinity of the gate electrode connection portion 225, it also has the effect of reducing the wiring resistance of the source electrode 211.

[0042] 5A, 5B, and 5C, openings are made in the SiO film 245 and the first dielectric film 243 on the drain electrodes 231 and 233, and low-resistance metal layers 281 and 283 are formed thereon. The low-resistance metal layers 281 and 283 are formed entirely on the drain electrodes 231 and 233 as shown in FIG. 4, and therefore have the effect of reducing the wiring resistance of the drain electrodes 231 and 233.

[0043] Furthermore, as shown in FIG. 5B, by forming an opening in the SiO film 245 on the gate electrode coupling portion 225 and forming a low resistance metal layer 287 thereon, there is an effect of reducing the wiring resistance of the gate.

[0044] A SiO film, which is the second dielectric film 247, is formed on the low-resistance metal layers 281, 283, 285, and 287. In a high-voltage transistor, the second dielectric film 247 is designed to have a thickness that prevents dielectric breakdown between the source and drain. For example, in a 600V transistor, if the second dielectric film 247 is a SiO film, its thickness is set to 2 μm to 3 μm. In this case, if the shortest dimension of the low-resistance metal layers 281, 283, 285, and 287 is about 3 μm or more, a via 251 on the low-resistance metal layer 285, a via 261 on the low-resistance metal layer 287, and a via 271 on the low-resistance metal layers 281 and 283 are formed by a normal photolithography technique and a technique of dry etching the second dielectric film 247. Then, plugs 253, 263, and 273 are formed to fill the respective vias. The plugs 253, 263, and 273 are made of W (tungsten) with a TiN film as a barrier layer in the portion in contact with the second dielectric film 247. The plug 253 is connected to a first source lead wiring 255, the plug 263 is connected to a first gate lead wiring 265, and the plug 273 is connected to a first drain lead wiring 275.

[0045] In this embodiment, the first gate electrode 221 and the second gate electrode 223 are connected at the center by the gate electrode connecting portion 225. Then, a via 261 is formed in the gate electrode connecting portion 225 to perform gate wiring. Therefore, the gate wiring resistance is significantly reduced compared to the case where the gate wiring is performed from the end of the gate electrode. In addition, the gate wiring is formed on the first active region 208, not on the element isolation region 209. As a result, no increase in chip area occurs. Furthermore, a capacitance is generated between the source electrode 211 and the gate electrode connecting portion 225 due to the first dielectric film 243. This capacitance is the gate-source capacitance, but in order to prevent erroneous firing in a switching power transistor, it is desirable to increase the gate-source capacitance relative to the gate-drain capacitance. Therefore, by using this embodiment, a switching power transistor that has a large gate-source capacitance and can prevent erroneous firing can be realized.

[0046] In the nitride semiconductor device 210 of this embodiment, W is used as the plug filling the via, but Al (aluminum) or Cu (copper) may also be used. When Cu is used, the plug and the wiring connected thereto may be formed simultaneously using a dual damascene method.

[0047] 4, one via 261 is provided on the low-resistance metal layer 287 on the gate electrode connector 225, but multiple vias may be provided if possible from the standpoint of manufacturing technology. The number of vias 271 on the source electrode 211 and the drain electrodes 231 and 233 is preferably large in order to reduce wiring resistance, but is appropriately designed from the standpoint of manufacturing technology for forming vias and plugs.

[0048] As described above, in the nitride semiconductor device according to the second modification of the first embodiment, a low-resistance metal layer is formed on the source electrode except for the portion below the gate electrode coupling portion, and on the drain electrode.

[0049] According to this, since the low-resistance metal layer is formed on the source electrode, it has the effect of lowering the wiring resistance of the source electrode, and since the low-resistance metal layer is formed on the drain electrode, it has the effect of lowering the wiring resistance of the drain electrode.

[0050] For example, the low-resistance metal layer formed on the source electrode may be a source field plate electrode extending toward the drain electrode beyond above the first gate electrode and the second gate electrode.

[0051] According to this, the low-resistance metal layer has the effect of mitigating electric field concentration at the drain side end of the gate, which results in an improvement in breakdown voltage and an effect of mitigating the phenomenon of current collapse.

[0052] (Embodiment 2) A plan view of a nitride semiconductor device 310 according to the second embodiment is shown in FIG.

[0053] In this embodiment, the nitride semiconductor devices according to the first embodiment or its modified example 1 or 2 are repeatedly arranged in the X direction shown in Fig. 6 to configure a power transistor. For simplification, components that are not particularly necessary for explaining this embodiment are omitted in Fig. 6.

[0054] As shown in FIG. 6, a plurality of source electrodes 311 and drain electrodes 331, each of which extends in the Y direction in a finger shape, are alternately arranged in the X direction. The ends in the X direction are not drain electrodes 331 to which a high voltage is applied, but source electrodes 311, which are often grounded, and therefore have the effect of preventing moisture from entering from the outside, and are excellent in terms of reliability. A gate electrode connection portion 325 formed on a plurality of source electrodes 311 has a via 361 opened in a dielectric film (not shown) formed thereon, and a plug 363 is formed to fill the via 361. A first gate lead wiring 365 is formed to connect the plugs 363. The first gate lead wiring 365 has a gate pad 393 having a large area at its end. The gate pad 393 has a gate pad opening 393A formed in the surface protection film (not shown) of the nitride semiconductor device 310.

[0055] The multiple source electrodes 311 have vias 351 opened in a dielectric film (not shown) formed thereon, and plugs 353 are provided to fill the vias 351. A first source lead wiring 355 is formed to connect the plugs 353. The first source lead wiring 355 forms a source pad 391 at its center. The source pad 391 has a source pad opening 391A formed in a surface protection film (not shown).

[0056] The multiple drain electrodes 331 have vias 371 opened in a dielectric film (not shown) formed thereon, and plugs 373 are provided to fill the vias 371. A first drain lead wiring 375 is formed to connect the plugs 373. The first drain lead wiring 375 serves as a drain pad 395 at its center. The drain pad 395 has a drain pad opening 395A formed in a surface protection film (not shown).

[0057] In this embodiment, the first source lead-out wiring 355 and the first drain lead-out wiring 375 are formed on either side of the first gate lead-out wiring 365. Since the first gate lead-out wiring 365 is connected to each gate electrode (not shown) via the gate electrode connector 325, the gate wiring resistance is low, and since it is formed above the first active region 308, there is no increase in the chip area.

[0058] In this embodiment, the first gate lead wiring 365, the first source lead wiring 355, and the first drain lead wiring 375 are formed of the same metal layer. This simplifies the manufacturing process. Examples of the same metal layer include Al (aluminum), Cu (copper), and Au (gold). In particular, when Cu is used, it is possible to form the plugs 363, 353, and 373 simultaneously by using a dual damascene method, further simplifying the manufacturing process.

[0059] In this embodiment, there is a first active region 308, an element isolation region 309, and an ion-implanted region boundary 308A which is the boundary between the first active region 308 and the element isolation region 309. Since the ratio of the first active region 308 to the chip area is high in the nitride semiconductor device 310, the on-resistance is low and the chip area is small.

[0060] As described above, in the nitride semiconductor device of embodiment 2, the source electrode, the first gate electrode, the second gate electrode, the gate electrode coupling portion, and the drain electrode are repeatedly formed in the first direction, a second dielectric film is formed on the plurality of the gate electrode coupling portions, and a first gate extraction wiring is provided that electrically connects the plurality of the gate electrode coupling portions through vias formed in the second dielectric film and extends in the first direction.

[0061] This has the advantage of being able to control a large current for power supply during high-speed switching operations. In addition, since the first source lead wire and the first drain lead wire are formed with the first gate lead wire 365 in between, it has the advantage of being able to reduce the chip area.

[0062] For example, the second dielectric film may also be formed on the source electrode, the first gate electrode, the second gate electrode, and the drain electrode, and may include a first source lead-out wiring that extends in the first direction, electrically connecting the multiple source electrodes through vias formed in the second dielectric film, and a first drain lead-out wiring that extends in the first direction, electrically connecting the multiple drain electrodes through vias formed in the second dielectric film, sandwiching the first gate lead-out wiring.

[0063] According to this, the ratio of the first active region to the chip area of ​​the nitride semiconductor device can be increased, which has the effect of reducing the on-resistance and the chip area.

[0064] For example, the first gate lead-out wiring, the first source lead-out wiring, and the first drain lead-out wiring may be formed from the same metal wiring layer.

[0065] This has the effect of simplifying the manufacturing process for forming the first gate lead-out wiring, the first source lead-out wiring, and the first drain lead-out wiring.

[0066] For example, the semiconductor device may have a gate pad formed on a part of the first gate lead-out wiring, a source pad formed on a part of the first source lead-out wiring, and a drain pad formed on a part of the first drain lead-out wiring.

[0067] This realizes POE (Pad on Element) or POA (Pad over Active) in which a gate pad, a source pad, and a drain pad are formed on the first active region, thereby suppressing the increase in chip area due to the pads or reducing the chip area.

[0068] (Modification of the second embodiment) 7 shows a plan view of a nitride semiconductor device 410 according to a modification of the second embodiment, and FIG 8 shows a cross-sectional view of a PN diode 490, which is a component thereof. This modification has a configuration in which a protection diode 492 formed by a series connection of PN diodes 490 is inserted between the gate and source of the nitride semiconductor device 310 according to the second embodiment. This protection diode 492 is manufactured and integrated on the same chip as the FET, by the same manufacturing process as the FET.

[0069] As shown in Fig. 8, a buffer layer 2 made of an AlN layer or an AlGaN layer, a GaN channel layer 3, and an AlGaN barrier layer 4 are formed on a Si substrate 1 by epitaxial growth as a semiconductor laminate structure. A p-type GaN layer 405 is formed on the AlGaN barrier layer 4 by etching after epitaxial growth. At the interface between the GaN channel layer 3 and the AlGaN barrier layer 4, a high concentration of two-dimensional electron gas (not shown) is formed due to the effects of piezoelectric polarization and spontaneous polarization. The region where the two-dimensional electron gas is made highly resistive by ion implantation is the element isolation region 409.

[0070] A SiN film 441 is formed as a surface protection film on the surfaces of the AlGaN barrier layer 4 and the p-type GaN layer 405, and openings are made in the SiN film 441 to form a dummy electrode 411 and a cathode electrode 413. Furthermore, a SiO film is formed as a first dielectric film 443 on the SiN film 441. Openings are made in the SiN film 441 and the first dielectric film 443 to form an anode electrode 425 on the p-type GaN layer 405. The anode electrode 425 extends onto the dummy electrode 411.

[0071] A SiO film, which is a second dielectric film 447, is formed on the anode electrode 425 and the cathode electrode 413. A via 451 on the cathode electrode 413 and a via 461 on the anode electrode 425 are formed by normal photolithography and a technique for dry etching the second dielectric film 447 and the first dielectric film 443. Then, plugs 453 and 463 are formed to fill the respective vias. W (tungsten) is used for the plugs 453 and 463, with a TiN film as a barrier layer in the portion in contact with the second dielectric film 447. The plug 453 is connected to a cathode electrode lead wiring 455, and the plug 463 is connected to an anode lead wiring 465.

[0072] FIG. 7 shows a nitride semiconductor device 410 in which a protection diode 492 is electrically placed between the source and the gate. The protection diode 492 is formed by connecting five PN diodes 490 shown in FIG. 8 in series. Each PN diode 490 is formed in a second active region 498 surrounded by an element isolation region 409 whose periphery is made highly resistive by ion implantation. The five PN diodes 490 are electrically connected in series by an anode-cathode wiring 483. The protection diode 492 is connected to the first source lead-out wiring 355 by an anode-source wiring 481, and is connected to the first gate lead-out wiring 365 or the gate pad 393 by a cathode-gate wiring 485.

[0073] The dielectric breakdown voltage of the SiO film is about 3 MV / cm, and when the thickness of the SiO film (not shown) between the source electrode 311 and the gate electrode connector 325 in FIG. 7 is 0.1 μm, the dielectric breakdown voltage is 30 V. On the other hand, the turn-on voltage of a GaN PN diode is about 3.5 V. In the protection diode 492 of the nitride semiconductor device 310 in this embodiment, five PN diodes 490 are connected in series, so that a current flows when a reverse bias of about 17.5 V is applied between the source and gate. That is, there is a sufficient voltage margin, and the dielectric film between the gate electrode connector 325 and the source electrode 311 does not break down, and the source and gate of the nitride semiconductor device 410 is protected.

[0074] 7, in the nitride semiconductor device 410, the area of ​​the element isolation region 409 is increased by the protective diode 492 compared to the nitride semiconductor device 310, resulting in a slight increase in chip area. However, since the protective diode 492 can be designed to have a smaller area compared to the FET, which is a power transistor, the increase in chip area is only slight.

[0075] In the nitride semiconductor device 410 of this embodiment, the number of PN diodes connected in series is five, but the number can be appropriately designed to be, for example, three to ten, depending on the required protection voltage.

[0076] In the nitride semiconductor device 410 of this embodiment, the ratio of the first active region 408 to the chip area is smaller than that of the nitride semiconductor device 310 of the second embodiment, but is still sufficiently larger than that when the POE technology is not used. As a result, the on-resistance is small and the chip area is small.

[0077] As described above, the nitride semiconductor device according to the first modification of the second embodiment has a second active region on the substrate, the periphery of which is surrounded by an element isolation region, a protection diode is formed in which a plurality of diodes formed in the second active region are connected in series, the anode of the protection diode is electrically connected to the source electrode, the cathode of the protection diode is electrically connected to the gate electrode coupling portion, and a rise voltage of a current flowing from the anode to the cathode of the protection diode is lower than a dielectric breakdown voltage of the first dielectric film.

[0078] This has the effect of suppressing dielectric breakdown of the dielectric film between the gate electrode connector and the source electrode, thereby improving the reliability of the nitride semiconductor device.

[0079] (Embodiment 3) 9, 10, and 11 are plan views showing a nitride semiconductor device 510 according to a third embodiment of the present disclosure. Fig. 10 is an enlarged view of a dotted line portion M in Fig. 9, and Fig. 11 is an enlarged view of a dotted line portion N in Fig. 10. In Fig. 11, the wiring layer is omitted in order to explain the FET portion located below the wiring layer.

[0080] FIG. 11 shows a configuration similar to that of the first embodiment. The first gate electrode 521 and the second gate electrode 523 are connected at their centers by a gate electrode connecting portion 525. The gate electrode connecting portion 525 is formed simultaneously with the first gate electrode 521 and the second gate electrode 523 from the same metal layer. Therefore, the number of manufacturing steps does not increase. However, the first gate electrode 521 and the second gate electrode 523 are in contact with a p-type GaN layer (not shown), whereas the gate electrode connecting portion 525 is formed on a SiO film (not shown) that is a first dielectric film, and is electrically insulated from the source electrode 511. The width of the gate electrode connecting portion 525 is about 3 μm, which is designed to be larger than the first gate electrode 521 and the second gate electrode 523, which are about 1 μm in length. This design enables a wiring process using vias and plugs, which is difficult to perform on the gate electrodes, as described below.

[0081] A SiO film (not shown) is formed as a second dielectric film on the first gate electrode 521, the second gate electrode 523, the gate electrode connecting portion 525, the source electrode 511, and the drain electrodes 531 and 533. In a high voltage transistor, the SiO film is designed to have a thickness that prevents dielectric breakdown between the source and drain. For example, in a 600V voltage transistor, the thickness of the SiO film is set to 2 μm to 3 μm. In this case, if the widths of the source electrode 511, the gate electrode connecting portion 525, and the drain electrodes 531 and 533 are set to about 3 μm, a via 551 on the source electrode 511, a via 561 on the gate electrode connecting portion 525, and a via 571 on the drain electrodes 531 and 533 are formed by a normal photolithography technique and a technique of dry etching the SiO film. Then, plugs 553, 563, and 573 are formed to fill the respective vias. The plugs 553, 563, and 573 are made of W (tungsten) and have a TiN film as a barrier layer in the portions in contact with the SiO film.

[0082] As shown in FIG. 10, the plug 553 is connected to the first source lead wiring 555, the plug 563 is connected to the first gate lead wiring 565, and the plug 573 is connected to the first drain lead wiring 575. On the first source lead wiring 555, the first gate lead wiring 565, and the first drain lead wiring 575, a SiO film (not shown) is formed as a third dielectric film. As in the above, a via 581 on the first source lead wiring, a via 583 on the first gate lead wiring, and a via 585 on the first drain lead wiring are formed by photolithography and dry etching of the third dielectric film. Then, plugs 582, 584, and 586 are formed to fill the respective vias. The plugs 582, 584, and 586 are made of W (tungsten) with a TiN film as a barrier layer in the portions in contact with the SiO film. The plug 582 is connected to a second source lead-out wiring 587 , the plug 584 is connected to a second gate lead-out wiring 588 , and the plug 586 is connected to a second drain lead-out wiring 589 .

[0083] 10, the first source lead wire 555 is sandwiched between the first gate lead wires 565, and the drain lead wire 575 is sandwiched between the first gate lead wires 565. As a result, the gate wire resistance is reduced, and at the same time, the drain lead wire 575, to which a high voltage is applied, is not disposed at the chip end, improving reliability in terms of moisture resistance.

[0084] 10, the distance W2 between the first drain lead wire 575 and the first gate lead wire 565 is larger than the distance W1 between the first source lead wire 555 and the first gate lead wire 565. As a result, the electric field in the vicinity of the first drain lead wire 575 to which a high voltage is applied is weakened, improving reliability in terms of moisture resistance.

[0085] As shown in FIG. 9, the second gate lead wiring 588 extends in the Y direction, and its end portion becomes a gate pad 593 having a large area. The gate pad 593 has a gate pad opening 593A formed in the surface protective film (not shown) of the nitride semiconductor device 510. The second source lead wiring 587 extends in the Y direction, and its central portion becomes a source pad 591. The source pad 591 has a source pad opening 591A formed in the surface protective film (not shown) of the nitride semiconductor device 510. Similarly, the second drain lead wiring 589 extends in the Y direction, and its central portion becomes a drain pad 595. The drain pad 595 has a drain pad opening 595A formed in the surface protective film (not shown) of the nitride semiconductor device 510.

[0086] In this embodiment, there is a first active region 508, an element isolation region 509, and an ion implantation region boundary 508A which is the boundary between the first active region 508 and the element isolation region 509. Since the ratio of the first active region 508 to the chip area is high in the nitride semiconductor device 510, the on-resistance is low and the chip area is small.

[0087] In this embodiment, the second gate lead wiring 588, the second source lead wiring 587, and the second drain lead wiring 589 are formed of the same metal layer. This simplifies the manufacturing process. Examples of the same metal layer include Al (aluminum), Cu (copper), and Au (gold). In particular, when Cu is used, it is possible to form the plugs 582, 584, and 586 simultaneously by using a dual damascene method, further simplifying the manufacturing process.

[0088] In the second embodiment and the modified example of the second embodiment, each pad is formed with only one wiring layer, but in the present embodiment, two wiring layers are used. As a result, even if the finger length of the source / drain is long or the number of source / drain fingers is increased, the wiring resistance of each source / drain / gate can be lowered compared to the case where only one wiring layer is used. In particular, since two wiring layers are used for the gate wiring resistance, it can be significantly reduced compared to the examples of the cited document 2 and the like. Furthermore, since it is not necessary to form the gate wiring in the element isolation region 509, the chip area is also reduced.

[0089] In this embodiment as well, it is possible to insert a protective diode between the source and gate, as in the modified example of the second embodiment.

[0090] As described above, in the nitride semiconductor device of embodiment 3, there are multiple first gate pull-out wiring, first source pull-out wiring, and first drain pull-out wiring, a third dielectric film is formed on the first gate pull-out wiring, the first source pull-out wiring, and the first drain pull-out wiring, and vias formed in the third dielectric film are provided to form a second gate pull-out wiring that electrically connects the multiple first gate pull-out wirings and extends in the second direction, a second source pull-out wiring that electrically connects the multiple first source pull-out wirings and extends in the second direction, and a second drain pull-out wiring that electrically connects the multiple first drain pull-out wirings and extends in the second direction.

[0091] According to this, since two wiring layers connected through vias are used, the resistance of each of the source / drain / gate lead wirings can be lowered compared to the case where a single wiring layer is used. In particular, since two wiring layers consisting of the first gate lead wiring and the second gate lead wiring are used, there is an effect that the wiring resistance of the gate can be reduced. Furthermore, since there is no need to form the gate lead wiring in the element isolation region, there is an effect that the chip area can be reduced.

[0092] For example, both sides of the first source lead-out wiring may be sandwiched between the first gate lead-out wirings, and the first drain lead-out wiring may be sandwiched between the first gate lead-out wirings.

[0093] This reduces the gate wiring resistance and improves reliability in terms of moisture resistance since the drain lead wiring to which a high voltage is applied is not disposed at the chip end.

[0094] For example, the distance between the first drain lead-out wiring and the first gate lead-out wiring may be larger than the distance between the first source lead-out wiring and the first gate lead-out wiring.

[0095] This makes it possible to weaken the electric field in the vicinity of the first drain withdrawal wiring to which a high voltage is applied, thereby improving reliability in terms of moisture resistance.

[0096] For example, the second gate lead-out wiring, the second source lead-out wiring, and the second drain lead-out wiring may be formed from the same metal wiring layer.

[0097] This can simplify the manufacturing process for forming the second gate lead-out wiring, the second source lead-out wiring, and the second drain lead-out wiring.

[0098] For example, the semiconductor device may have a gate pad formed on a part of the second gate lead-out wiring, a source pad formed on a part of the second source lead-out wiring, and a drain pad formed on a part of the second drain lead-out wiring.

[0099] This has the effect of realizing two-layer POE, thereby significantly reducing the chip area.

[0100] (Embodiment 4) Fig. 12 is a plan view of a nitride semiconductor device 620 of embodiment 4, and Fig. 13A, Fig. 13B, Fig. 13C, and Fig. 13D are cross-sectional views taken along lines XIIIa-XIIIa, XIIIb-XIIIb, XIIIc-XIIIc, and XIIId-XIIId in Fig. 12. This embodiment is a double-gate transistor having two gates.

[0101] As shown in FIG. 13A, FIG. 13B, FIG. 13C, and FIG. 13D, a buffer layer 2 made of an AlN layer or an AlGaN layer, a GaN channel layer 3, and an AlGaN barrier layer 4 are formed on a Si substrate 1 by epitaxial growth as a semiconductor laminate structure. On the AlGaN barrier layer 4, p-type GaN layers 605, 606, 607, and 608 are formed by epitaxial growth and then etching. At the interface between the GaN channel layer 3 and the AlGaN barrier layer 4, a high concentration of two-dimensional electron gas (not shown) is formed due to the effects of piezoelectric polarization and spontaneous polarization. The region where this two-dimensional electron gas is formed is the active region 609 in FIG. 12, and the region where the two-dimensional electron gas is made highly resistive by ion implantation is the element isolation region 610. The boundary between the two is the boundary 609A of the ion implantation region. The element isolation region 610 may be formed by removing the region containing the two-dimensional electron gas by mesa etching.

[0102] As shown in Figures 13A, 13B, 13C, and 13D, a SiN film 641 is formed as a surface protection film on the surfaces of the AlGaN barrier layer 4 and the p-type GaN layers 605, 606, 607, and 608, and a first source electrode 631 and a second source electrode 633 are formed by opening the SiN film 641. Furthermore, a SiO film is formed as a first dielectric film 643 on the SiN film 641. A first gate electrode 621, a second gate electrode 622, a third gate electrode 625, and a fourth gate electrode 626 are formed on the p-type GaN layers 605, 606, 607, and 608, respectively, by opening the SiN film 641 and the first dielectric film 643.

[0103] 12, the first gate electrode 621 and the second gate electrode 622 are formed on both sides of the finger-shaped first source electrode 631, spaced apart in the X direction. The third gate electrode 625 and the fourth gate electrode 626 are formed on both sides of the finger-shaped second source electrode 633, spaced apart in the X direction.

[0104] In addition, the first gate electrode 621 and the second gate electrode 622, together with the p-type GaN layer 605 and the p-type GaN layer 606 located below them, extend in a finger-like shape in the Y direction, which is a direction perpendicular to the X direction, and are connected at both ends in an arc shape. This configuration reduces the leakage current flowing between the first source electrode 631 and the second source electrode 633 in the off state. If the first gate electrode 621 and the second gate electrode 622 are not connected at their ends, the finger-like gate electrode needs to reach the element isolation region 610 beyond the boundary 609A of the ion implantation region. The same applies to the third gate electrode 625 and the fourth gate electrode 626.

[0105] As shown in FIG. 13C, the first gate electrode 621 and the second gate electrode 622 are connected to each other near the center by the first gate electrode connecting portion 623. The first gate electrode connecting portion 623 is formed at the same time as the first gate electrode 621 and the second gate electrode 622 by using the same metal layer. Therefore, the number of manufacturing steps does not increase. However, the first gate electrode 621 and the second gate electrode 622 are in contact with the p-type GaN layer 605 and the p-type GaN layer 606, respectively, whereas the first gate electrode connecting portion 623 is formed on the SiO film, which is the first dielectric film 643, and is electrically insulated from the first source electrode 631. The width (depth direction of the paper surface) of the first gate electrode connecting portion 623 is about 3 μm, which is designed to be larger than the first gate electrode 621 and the second gate electrode 622, which are about 1 μm in length. This design makes it possible to perform a wiring process using vias and plugs, which is difficult to perform on the gate electrodes, as described below. Similarly, as shown in FIG. 13B, the third gate electrode 625 and the fourth gate electrode 626 are each coupled near the center by a second gate electrode connecting portion 627.

[0106] A SiO film, which is a second dielectric film 647, is formed on the first gate electrode 621, the second gate electrode 622, the first gate electrode connecting portion 623, the third gate electrode 625, the fourth gate electrode 626, the second gate electrode connecting portion 627, the first source electrode 631, and the second source electrode 633. In a high-voltage double-gate transistor, the second dielectric film 647 is designed to have a thickness that prevents dielectric breakdown between the first source and the second source. For example, in a 600V double-gate transistor, when the second dielectric film 647 is made of SiO, its thickness is set to 2 μm to 3 μm. In this case, if the widths of the first source electrode 631, the first gate electrode connecting portion 623, the second gate electrode connecting portion 627, and the second source electrode 633 are about 3 μm, a via 681 on the first source electrode 631, a via 671 on the first gate electrode connecting portion 623, a via 651 on the second source electrode 633, and a via 661 on the second gate electrode connecting portion 627 are formed by a normal photolithography technique and a technique for dry etching the second dielectric film 647 and the first dielectric film 643. Then, plugs 683, 673, 653, and 663 are formed to fill the respective vias. W (tungsten) is used for the plugs 683, 673, 653, and 663 in the portions in contact with the second dielectric film 647, with a TiN film as a barrier layer. The plug 683 is connected to an interconnection 685 for the first source electrode, the plug 673 is connected to an interconnection 675 for the first gate electrode, the plug 653 is connected to an interconnection 655 for the second source electrode, and the plug 663 is connected to an interconnection 665 for the second gate electrode.

[0107] In this embodiment, the first gate electrode 621 and the second gate electrode 622 are connected at their central portions by a first gate electrode connecting portion 623. Then, a via 671 is formed in the first gate electrode connecting portion 623 to perform gate wiring. Also, the third gate electrode 625 and the fourth gate electrode 626 are connected at their central portions by a second gate electrode connecting portion 627. Then, a via 671 is formed in the first gate electrode connecting portion 623, and a via 661 is formed in the second gate electrode connecting portion 627 to perform gate wiring. Therefore, the gate wiring resistance is significantly reduced compared to the case where the gate wiring is performed from the end of the gate electrode. Also, the gate wiring is formed on the active region 609, not on the element isolation region 610. As a result, the chip area does not increase.

[0108] In the nitride semiconductor device 620 of this embodiment, as in the first modification of the first embodiment, the side surfaces of the first source electrode 631 and the second source electrode 633 in contact with the first dielectric film 643 may have a forward tapered cross-sectional shape. The forward tapered shape improves the coverage of the first dielectric film 643 to the side surfaces of the first source electrode 631 and the second source electrode 633, and prevents the occurrence of voids (gaps) and seams (joints). As a result, even when a reverse bias voltage of several tens of volts is applied between the first source electrode 631 and the first gate electrode connector 623 or between the second source electrode 633 and the second gate electrode connector 627, the first dielectric film 643 is unlikely to break down.

[0109] In the nitride semiconductor device 620 of this embodiment, as in the second modification of the first embodiment, a low-resistance metal layer serving as a field plate electrode may be provided on the first source electrode 631 and the second source electrode 633.

[0110] In the nitride semiconductor device 620 of this embodiment, as in the second embodiment, the configuration of FIG. 12 may be repeatedly formed in the X direction, and a first source pad may be formed in the lead-out wiring 685 of the first source electrode, a second source pad may be formed in the lead-out wiring 655 of the second source electrode, a first gate pad may be formed in the lead-out wiring 675 of the first gate electrode, and a second gate pad may be formed in the lead-out wiring 665 of the second gate electrode.

[0111] In the nitride semiconductor device 620 of this embodiment, as in the modified example of embodiment 2, a protection diode may be inserted between the first source and the first gate, or between the second source and the second gate.

[0112] In the nitride semiconductor device 620 of this embodiment, the first source pad, the second source pad, the first gate pad, and the second gate pad may be formed by using a second layer wiring technique as in the third embodiment.

[0113] As described above, the nitride semiconductor device according to the fourth embodiment includes a substrate, a semiconductor laminate structure formed on the substrate and including a plurality of nitride semiconductor layers, a first active region on an upper surface side of the semiconductor laminate structure and surrounded by an element isolation region, and a first source electrode on the first active region, a first gate electrode and a second gate electrode positioned on both sides of the first source electrode and spaced apart in a first direction in a plan view, a second source electrode, and a third gate electrode and a fourth gate electrode positioned on both sides of the second source electrode and spaced apart in the first direction in a plan view. The first source electrode, the second gate electrode, the second source electrode, the third gate electrode, and the fourth gate electrode have finger-shaped portions extending in a second direction perpendicular to the first direction in a plan view, a first dielectric film is formed on the first source electrode and the second source electrode, the first gate electrode and the second gate electrode are electrically connected by a first gate electrode connecting portion formed on the first dielectric film, and the third gate electrode and the fourth gate electrode are electrically connected by a second gate electrode connecting portion formed on the first dielectric film.

[0114] According to this, by forming the wiring of the gate electrode inside the first active region in a plan view, the wiring length can be shortened and the wiring resistance of the gate can be reduced. As a result, there is an effect that it is suitable for high-speed switching operations. In addition, by forming the wiring of the gate electrode inside the active region in a plan view, there is an effect that the chip area of ​​the nitride semiconductor device can be reduced.

[0115] For example, the first gate electrode, the second gate electrode, the first gate electrode connector, the third gate electrode, the fourth gate electrode, and the second gate electrode connector may be formed of the same metal layer.

[0116] This has the advantage of not increasing the number of manufacturing steps in forming the first gate electrode, the second gate electrode, the first gate electrode connecting portion, the third gate electrode, the fourth gate electrode, and the second gate electrode connecting portion.

[0117] For example, the width of the first gate electrode connecting portion may be greater than the first gate electrode length and the second gate electrode length, and the width of the second gate electrode connecting portion may be greater than the third gate electrode length and the fourth gate electrode length.

[0118] This enables wiring using vias and plugs for the gate electrode connecting portion, and reduces the chip area.

[0119] For example, a portion of a side surface of the first source electrode that contacts the first dielectric film may have a forward tapered shape, and a portion of a side surface of the second source electrode that contacts the first dielectric film may also have a forward tapered shape.

[0120] This improves the coverage of the first dielectric film on the side surfaces of the first and second source electrodes, suppressing the occurrence of voids and seams, resulting in the effect that the first dielectric film is less likely to break down even when a reverse bias voltage (e.g., several tens of volts) is applied between the source electrode and the gate electrode connection portion.

[0121] Although the nitride semiconductor device according to one or more aspects has been described based on the embodiment, the present disclosure is not limited to this embodiment. As long as it does not deviate from the spirit of the present disclosure, various modifications conceived by a person skilled in the art to this embodiment and forms constructed by combining components in different embodiments may also be included within the scope of one or more aspects. [Industrial Applicability]

[0122] The nitride semiconductor device according to the present disclosure can be used as a switching transistor having a low gate wiring resistance. [Explanation of symbols]

[0123] 1. Si substrate 2. Buffer layer 3 GaN channel layer 4. AlGaN barrier layer 5, 6, 105, 106, 405 p-type GaN layer 8, 208, 308, 408, 508 First active area 8A, 208A, 308A, 408A, 508A, 609A Ion implantation area boundaries 9, 209, 309, 409, 509 Element isolation area 10, 110, 210, 310, 410, 510, 620 Semiconductor device 11, 111, 211, 311, 511 Source electrode 21, 121, 221, 521 First gate electrode 23, 123, 223, 523 Second gate electrode 25, 125, 225, 325, 525 Gate electrode connection part 31, 33, 231, 233, 331, 531, 533 Drain electrode 41, 141, 241, 441 SiN film 43, 143, 243 443 First dielectric film (SiO film) 47, 247, 447 Second dielectric film (SiO film) 51, 251, 351, 551 Vias on source electrodes 53, 253 plug 55, 255, 355, 555 First source lead wire 61, 261, 361, 561 Vias on gate electrode connection 63, 263 Plug 65, 265, 365, 565 First gate lead wire 71, 271, 371, 571 Via on drain electrode 73, 273 Plug 75, 275, 375, 575 First drain lead 245 SiO film (field plate film) 281, 283, 287 Low resistance metal layer 285 Low-resistance metal layer (source field plate electrode) 391 Sauce Pad 391A Source Pad Opening 393 Gate Pad 393A Gate Pad Opening 395 Drain Pad 395A Drain Pad Opening 405 p-type layer 411 Dummy Electrode 413 Cathode Electrode 425 Anode Electrode 451 Beer 453 Plug 455 Cathode electrode lead wire 461 Beer 463 Plug 465 Anode electrode lead wire 481 Anode-source wiring 483 Anode-cathode wiring 485 Cathode-gate wiring 490 PN Diode 492 Protection Diode 498 Second active region 581 Via on the first source lead 582 584, 586 Plug 583 Via on the first gate lead 585 Via on the first drain lead 587 Second source lead wire 588 Second gate lead wire 589 Second drain lead 591 Sauce Pad 591A Source Pad Opening 593 Gate Pad 593A Gate Pad Opening 595 Drain Pad 595A Drain Pad Opening 605, 606, 607, 608 p-type GaN layer 609 Active region 610 Element isolation region 621 First gate electrode 622 Second gate electrode 623 First gate electrode connection portion 625 Third gate electrode 626 4th gate electrode 627 Second gate electrode connection part 631 First source electrode 633 Second Source Electrode 641 SiN film 643 First dielectric film (SiO film) 647 Second dielectric film (SiO film) 651 Via on the second source electrode 653 Plug 655 Lead wire for second source electrode 661 Via on second gate electrode connection portion 663 Plug 665 Lead wire for second gate electrode 671 Via on the first gate electrode connection part 673 Plug 675 Lead wire for the first gate electrode 681 Via on the first source electrode 683 Plug 685 Lead wire for the first source electrode

Claims

1. A substrate; a semiconductor laminate structure formed on the substrate and including a plurality of nitride semiconductor layers; a first active region on an upper surface side of the semiconductor laminated structure, the first active region being surrounded by an element isolation region; a source electrode on the first active region, a first gate electrode and a second gate electrode positioned on both sides of the source electrode and spaced apart in a first direction in a plan view, and at least one drain electrode positioned in an opposite direction to the source electrode with respect to the first gate electrode or the second gate electrode; the source electrode, the first gate electrode, the second gate electrode, and the drain electrode each have a finger-shaped portion extending in a second direction perpendicular to the first direction in a plan view; a first dielectric film is formed on the source electrode; The first gate electrode and the second gate electrode are electrically connected by a gate electrode connecting portion formed on the first dielectric film. Nitride semiconductor devices.

2. the first gate electrode, the second gate electrode, and the gate electrode coupling portion are formed of a same metal layer; The nitride semiconductor device according to claim 1 .

3. a width of the gate electrode connection portion is greater than a length of the first gate electrode and a length of the second gate electrode; 3. The nitride semiconductor device according to claim 1 or 2.

4. a portion of the side surface of the source electrode that is in contact with the first dielectric film has a forward tapered shape; The nitride semiconductor device according to claim 1 .

5. a second active region on the substrate, the second active region being surrounded by an element isolation region; A protection diode is formed by connecting a plurality of diodes in series in the second active region, the anode of the protection diode is electrically connected to the source electrode; the cathode of the protection diode is electrically connected to the gate electrode connection part; a rise voltage of a current flowing from the anode to the cathode of the protection diode is lower than a dielectric breakdown voltage of the first dielectric film; The nitride semiconductor device according to claim 1 .

6. a low-resistance metal layer is formed on the source electrode except for a portion below the gate electrode connection portion and on the drain electrode; The nitride semiconductor device according to claim 1 .

7. the low-resistance metal layer formed on the source electrode is a source field plate electrode extending toward the drain electrode beyond above the first gate electrode and the second gate electrode; The nitride semiconductor device according to claim 6 .

8. the source electrode, the first gate electrode, the second gate electrode, the gate electrode connector, and the drain electrode are repeatedly formed in the first direction; a second dielectric film is formed on the gate electrode connecting portions; a first gate lead wiring electrically connecting the gate electrode coupling parts through vias formed in the second dielectric film and extending in the first direction; The nitride semiconductor device according to claim 1 .

9. the second dielectric film is also formed on the source electrode, the first gate electrode, the second gate electrode, and the drain electrode; With the first gate lead wiring in between, a first source lead wiring that electrically connects the plurality of source electrodes through vias formed in the second dielectric film and extends in the first direction; a first drain lead wiring electrically connecting the plurality of drain electrodes through vias formed in the second dielectric film and extending in the first direction; The nitride semiconductor device according to claim 8 .

10. the first gate lead wiring, the first source lead wiring, and the first drain lead wiring are formed of the same metal wiring layer; The nitride semiconductor device according to claim 9 .

11. a gate pad formed on a part of the first gate lead wiring; a source pad formed in a part of the first source lead wiring; a drain pad formed on a part of the first drain lead wiring; The nitride semiconductor device according to claim 9 or 10.

12. the first gate lead-out wiring, the first source lead-out wiring, and the first drain lead-out wiring are each provided in a plurality of wirings, a third dielectric film is formed on the first gate lead wiring, the first source lead wiring, and the first drain lead wiring; through a via formed in the third dielectric film, a second gate lead wiring electrically connecting a plurality of the first gate lead wirings and extending in the second direction; a second source lead wiring electrically connecting a plurality of the first source lead wirings and extending in the second direction; a second drain lead wiring electrically connecting the first drain lead wirings and extending in the second direction; The nitride semiconductor device according to claim 10.

13. the first source lead wiring is sandwiched between the first gate lead wirings on both sides; the first drain lead wiring is sandwiched between the first gate lead wirings; The nitride semiconductor device according to claim 12.

14. The distance between the first drain lead wiring and the first gate lead wiring is a distance between the first source lead-out wiring and the first gate lead-out wiring; The nitride semiconductor device according to claim 12 or 13.

15. the second gate lead wiring, the second source lead wiring, and the second drain lead wiring are formed of the same metal wiring layer; The nitride semiconductor device according to claim 12 .

16. a gate pad formed on a part of the second gate lead wiring; a source pad formed in a part of the second source lead wiring; a drain pad formed on a part of the second drain lead wiring; The nitride semiconductor device according to claim 12 .

17. A substrate; a semiconductor laminate structure formed on the substrate and including a plurality of nitride semiconductor layers; a first active region on an upper surface side of the semiconductor laminated structure, the first active region being surrounded by an element isolation region; on the first active region, a first source electrode; and a first gate electrode and a second gate electrode located on both sides of the first source electrode and spaced apart from each other in a first direction in a plan view; a second source electrode, and a third gate electrode and a fourth gate electrode located on both sides of the second source electrode and spaced apart from each other in a first direction in a plan view; the first source electrode, the first gate electrode, the second gate electrode, the second source electrode, the third gate electrode, and the fourth gate electrode each have a finger-shaped portion extending in a second direction perpendicular to the first direction in a plan view; a first dielectric film is formed on the first source electrode and the second source electrode; the first gate electrode and the second gate electrode are electrically connected by a first gate electrode connecting portion formed on the first dielectric film; The third gate electrode and the fourth gate electrode are electrically connected by a second gate electrode connecting portion formed on the first dielectric film. Nitride semiconductor devices.

18. the first gate electrode, the second gate electrode, the first gate electrode connecting portion, the third gate electrode, the fourth gate electrode, and the second gate electrode connecting portion are formed of a same metal layer; The nitride semiconductor device according to claim 17.

19. a width of the first gate electrode connection portion is greater than a length of the first gate electrode and a length of the second gate electrode; a width of the second gate electrode connection portion is greater than a length of the third gate electrode and a length of the fourth gate electrode; 19. The nitride semiconductor device according to claim 17 or 18.

20. a side surface of the first source electrode, the portion of which contacts the first dielectric film, has a forward tapered shape; a portion of a side surface of the second source electrode that is in contact with the first dielectric film has a forward tapered shape; 20. The nitride semiconductor device according to claim 17,

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