Epitaxial growth template using carbon buffer on sublimated SiC substrate.

Abstract

Apparatuses, systems, and methods for forming semiconductor materials (e.g., using nano-fabrication) are generally described. In one example, the method includes forming a carbon buffer layer on a first substrate by silicon sublimation and a graphene layer on the carbon buffer layer, and then removing the graphene layer to reveal the carbon buffer layer and form a processing platform. In one embodiment, the first substrate comprises silicon carbide and the graphene layer comprises a single-crystalline graphene layer.

Description

[Technical field]

[0001] (Related Applications) This application claims priority under §119(e) to U.S. Provisional Patent Application No. 62 / 746,072, filed October 16, 2018, and entitled “Epitaxial Growth Template Using Carbon Buffer on Sublimated SiC Substrate,” which is incorporated herein by reference in its entirety for all purposes.

[0002] (Technical field) Generally, apparatus, systems, and methods for forming semiconductor materials (eg, using nano-fabrication) are described. [Background technology]

[0003] In advanced electronic and photonic technologies, devices are mostly fabricated from functional semiconductors such as III-N, III-V, II-VI, and Ge. The lattice constants of these functional semiconductors typically do not match the lattice constant of silicon substrates. As understood in the industry, the mismatch of the lattice constant between the substrate and the epitaxial layer on the substrate introduces strain in the epitaxial layer, thereby preventing epitaxial growth of defect-free thicker layers. Therefore, non-silicon substrates are mostly employed as seeds for epitaxial growth of most functional semiconductors. However, non-Si substrates with lattice constants matching the lattice constants of the functional materials can be costly and thus limit the development of non-Si electronic / photonic devices. Summary of the Invention [Means for solving the problem]

[0004] (overview) Embodiments of the invention include apparatus, systems and methods for nano-fabrication. In one example, a method for fabricating a semiconductor device includes forming a carbon buffer layer on a first substrate by silicon sublimation and a graphene layer on the carbon buffer layer. The method also includes removing the graphene layer to reveal the carbon buffer layer and form a processing platform.

[0005] It should be recognized that all combinations of the above concepts and additional concepts discussed in more detail below (provided such concepts are not mutually inconsistent) are contemplated as part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as part of the inventive subject matter disclosed herein. It should also be recognized that terms explicitly deployed herein that may also appear in any of the disclosures incorporated by reference are intended to mean most consistent with the specific concepts disclosed herein. The present invention provides, for example, the following: (Item 1) forming a carbon buffer layer on a first substrate and forming a graphene layer on the carbon buffer layer; removing the graphene layer to reveal the carbon buffer layer and form a processing platform; A method comprising: (Item 2) Item 13. The method of item 1, wherein the first substrate comprises silicon carbide and the graphene layer comprises a single crystal graphene layer. (Item 3) forming a first epitaxial layer on the carbon buffer layer; transferring the first epitaxial layer from the carbon buffer layer to a second substrate; The method according to any one of items 1 to 2, further comprising: (Item 4) 4. The method of claim 3, wherein forming the first epitaxial layer comprises epitaxially growing the first epitaxial layer using the first substrate as a seed crystal. (Item 5) 5. The method according to any one of items 3 to 4, further comprising forming a second epitaxial layer on the carbon buffer layer after transferring the first epitaxial layer to the second substrate. (Item 6) 6. The method according to any one of items 3 to 5, wherein transferring the first epitaxial layer includes detaching the first epitaxial layer. (Item 7) Transferring the first epitaxial layer includes: forming a metal stressor on the first epitaxial layer; placing a flexible tape over the metal stressor; stripping the first epitaxial layer and the metal stressor from the carbon buffer layer using the flexible tape; The method according to any one of items 3 to 6, comprising: (Item 8) 8. The method of any one of claims 3 to 7, wherein the first epitaxial layer comprises a semiconductor. (Item 9) 9. The method of any one of claims 3 to 8, wherein the first epitaxial layer comprises a III-V semiconductor, Si, Ge, a III-N semiconductor, SiC, SiGe, and / or a II-VI semiconductor. (Item 10) 10. The method according to any one of items 3 to 9, wherein the first epitaxial layer is processed into a semiconductor device. (Item 11) 10. A semiconductor device comprising the first epitaxial layer formed by the method according to any one of items 3 to 9. [Brief description of the drawings]

[0006] BRIEF DESCRIPTION OF THE DRAWINGS Those skilled in the art will appreciate that the drawings are primarily for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale, and in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate understanding of different features. In the drawings, like reference numbers generally refer to like features (e.g., functionally similar elements and / or structurally similar elements).

[0007] [Figure 1] 1A-1D illustrate methods of fabricating semiconductor devices using layer transfer techniques according to some embodiments.

[0008] [Diagram 2] 2A-2C illustrate a method of processing semiconductor devices using a processing platform processed by the method illustrated in FIGS. 1A-1D, according to some embodiments.

[0009] [Figure 3-1] 3A-3F illustrate a method of pseudo-graphene-based layer transfer according to some embodiments. [Figure 3-2]3A-3F illustrate a method of pseudo-graphene-based layer transfer according to some embodiments.

[0010] [Figure 4] FIG. 4 is a photograph of a semiconductor material processed by a particular inventive method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Detailed Description) One way to address the high cost of non-silicon substrates is the "layer transfer" technique, where a functional device layer is grown on a lattice-matched substrate, then removed and transferred to another substrate. The remaining lattice-matched substrate can then be reused to fabricate another device layer, thereby reducing costs. To significantly reduce manufacturing costs, it may be desirable for a layer transfer method to have the following characteristics: 1) substrate reusability; 2) minimal substrate recovery steps after layer peeling; 3) fast peel speed; and 4) precise control of peel thickness.

[0012] Conventional methods for removing and transferring device layers from lattice-matched substrates include chemical lift-off (also called epitaxial lift-off or ELO), optical lift-off (also called laser lift-off or LLO), and mechanical lift-off (also called controlled spalling). Unfortunately, none of these methods have all four of the desired properties noted above.

[0013] Chemical lift-off techniques can be used to lift off device layers made of III-V semiconductors from GaAs wafers. Usually, a sacrificial layer of AlAs is epitaxially inserted between the device layer and the substrate. Chemical lift-off techniques selectively etch the sacrificial layer in a wet chemical solution, releasing the device layer.

[0014] Despite its continued development over the past 30 years, chemical lift-off still has several drawbacks. For example, the stripping rate is slow (e.g., typically several days to strip a single 8-inch wafer) due to the slow penetration of the chemical etchant through the sacrificial layer. Second, the etch residues tend to become surface contaminants after stripping. Third, chemical lift-off has limited reuse capabilities due to the chemical mechanical planarization (CMP) performed after stripping to restore the roughened substrate surface to an epitaxial-ready surface. Fourth, it can be difficult to handle the stripped epilayer in the chemical solution.

[0015] Optical lift-off techniques usually use a high-power laser to irradiate the backside of a lattice-matched substrate (e.g., a transparent sapphire or SiC substrate) and selectively heat the device-substrate interface, causing decomposition of the interface and delamination of the device layers (e.g., III-N films). This technique can reduce the cost of manufacturing III-N-based light-emitting diodes (LEDs) and address the problem of heat accumulation from the devices by transferring the delaminate III-N to a substrate with high thermal conductivity.

[0016] However, optical lift-off has its own limitations. First, the molten III-N / substrate interface roughens the substrate, so a reconditioning step is usually performed before reuse, thereby reducing the reuse capability to less than five times. Second, the localized compression at the interface caused by high-power thermal irradiation may induce cracks or dislocations. Third, the laser scanning speed may be too slow to enable high throughput.

[0017] Controlled spalling can have a higher throughput than optical lift-off. In this technique, a highly stressful film (also called a "stressor") is deposited on the epitaxial film, inducing fracture beneath the epilayer, resulting in separation of the active material from the substrate. When sufficient tensile stress is applied at the interface, K II The shear mode can initiate a crack, K IThe opening mode may allow the propagation of a crack parallel to the interface between the epilayer and the substrate. By controlling the internal stress and the thickness of the stressor, the critical K I If sufficient strain energy is provided to reach a value, it can lead to the fracture of the film / substrate interface. The spalling process can cause rapid delamination of the thin film as the crack propagation leads to separation.

[0018] However, controlled spalling is not mature enough to be used for commercial manufacturing for at least the following reasons. First, crack propagation generally occurs through cleavage planes that are not necessarily aligned perpendicular to the surface, so the surface may need to be polished for reuse. Second, thick stressors are often used to provide sufficient energy to break strong covalent bonds, especially when working with high Young's modulus materials such as III-N semiconductors. Third, the internal stress of the stressor can only be controlled within a narrow range, which constrains the achievable thickness of the resulting spalled film. For example, since the maximum internal stress in a typical Ni stressor is about 1 GPa, the critical Ni thickness under a tensile stress of 1 GPa to initiate spalling of GaAs thin films is about 1.5 μm, which may induce spalling of the GaAs film itself if the GaAs is about 10 μm thick. Thus, when using Ni stressors it can be difficult to make GaAs films less than 10 μm thick, although typically most devices use much thinner films.

[0019] The systems and methods described herein according to certain embodiments employ a pseudo-graphene-based layer transfer approach to fabricate devices. This approach may address one or more of the shortcomings of the layer transfer methods described above. In certain embodiments, functional devices may be fabricated on a carbon buffer layer (also referred to as a pseudo-graphene layer) and subsequently formed on a SiC substrate. The fabricated functional devices may then be removed from the lattice-matched substrate, for example, by a stressor attached to the functional device.

[0020] In certain embodiments, the carbon buffer layer serves as a reusable universal platform for growing device layers and also provides a release layer that allows for fast, precise and repeatable release at the graphene surface. Compared to conventional methods, the approach described herein may provide one or more advantages. First, the weak interaction between the carbon buffer layer and the device layer may substantially relax the mismatch rule for epitaxial growth, potentially enabling growth of most semiconductor films with low defect density. Second, epilayers (e.g., functional devices) grown on the carbon buffer layer may be easily and precisely peeled off from the substrate due to the weak van der Waals interaction between the carbon buffer layer and the epilayer, which allows for fast mechanical release of the epilayer without post-release readjustment of the peeled surface. Third, the carbon buffer layer is often mechanically robust and therefore may be highly reusable for multiple growth / release cycles.

[0021] 1A-1D illustrate a method 100 of fabricating a semiconductor device by pseudo-graphene layer transfer according to some embodiments. FIG 1A shows a first substrate 110 (e.g., a SiC substrate) having a first surface 115, which may be unpolished. In some embodiments, the first surface 115 may be characterized by a surface roughness approximately equal to or greater than about 100 nm (e.g., about 100 nm, about 200 nm, about 500 nm, or greater, including any values ​​and subranges therebetween).

[0022] FIG. 1B shows that the first surface 115 of the first substrate 110 is planarized. For example, a chemical mechanical planarization (CMP) process and / or high temperature hydrogen etching may be employed to reduce the surface roughness of the first substrate. In FIG. 1C, the top silicon layer is sublimated, and a carbon buffer layer 120 is formed on the first substrate 110, forming a graphene layer 130 on the carbon buffer layer 120 (also referred to as a layer formation step). In certain embodiments, the graphene layer 130 may interact with the carbon buffer layer 120 by van der Waals forces. In some embodiments, the carbon buffer layer 120 may be formed during the initial stages of the growth of the graphene layer 130. The carbon buffer layer 120 may include, for example, carbon clusters and / or carbon networks. In certain embodiments, the carbon buffer layer 120 comprises a crystalline structure. In certain embodiments, the crystalline structure may be the same as or similar to graphene. In some embodiments, the carbon buffer layer is covalently bonded to the underlying substrate. For example, in some embodiments, the carbon buffer layer 120 may be covalently bonded to the first layer 115 of the substrate 110 .

[0023] In Fig. 1D, the graphene layer 130 is removed from the carbon buffer layer 120, thus forming a platform 140 including the first substrate 110 and the carbon buffer layer 120. The platform 140 can be used and reused to fabricate various types of semiconductor devices (as shown in more detail in Figs. 2A-2C and the associated description below). Compared to the graphene layer 130, the carbon buffer layer 120 has a stronger bond with the underlying substrate 110, thereby enabling more stable device fabrication in subsequent processing.

[0024] The layer formation steps illustrated in FIG. 1C can be performed by a variety of methods. In some embodiments, the graphene layer 130 can include epitaxial graphene with a single crystal orientation and the substrate 110 can include a (0001) 4H-SiC wafer with a silicon surface. The processing of the graphene layer 130 can include a multi-step annealing step. A first annealing step uses H for surface etching. 2 The first annealing step may be performed in Ar gas for graphenization at high temperatures (e.g., at least about 1000° C., such as about 1575° C. or higher).

[0025] In some embodiments, the carbon buffer layer 120 and the graphene layer 130 may be grown on the first substrate 110 by a chemical vapor deposition (CVD) process. The substrate 110 may include a nickel substrate or a copper substrate. Alternatively, the substrate 110 may be a SiO 2 , HfO 2 , Al 2 O 3 , Si 3 N 4 , and any other flat insulating material that is particularly compatible with high temperature CVD. In some embodiments, the carbon buffer layer 120 and the graphene layer 130 can be grown on the first substrate 110 by molecular beam epitaxy (MBE) techniques.

[0026] Various methods may also be used to remove the graphene layer 130 from the carbon buffer layer 120 and the first substrate 110. For example, a carrier film may be attached to the graphene layer 130. The carrier film may include a thin film of poly(methyl methacrylate) (PMMA) or a thermal release tape, and attachment may be achieved by a spin coating process.

[0027] 2A-2C illustrate a method 200 of processing an epilayer (e.g., that may be used to form a portion of a semiconductor device) using a processing platform processed by the method illustrated in FIGS. 1A-1D according to some embodiments. FIG. 2A shows a schematic diagram of a processing platform 240 including a first substrate 210 and a carbon buffer layer 220 deposited on the first substrate 210. The processing platform may be the same as or substantially similar to the processing platform 140 shown in FIG. 1D and described above. In FIG. 2B, an epilayer 250 is formed on the carbon buffer layer 220 (e.g., by epitaxial growth or any other suitable method). As described below, in some embodiments, the epilayer 250 may be epitaxially matched to the carbon buffer layer 220. In some embodiments, the epilayer 250 may also be epitaxially matched to the substrate 210.

[0028] 2C, epi layer 250 is removed from carbon buffer layer 220. For example, epi layer 250 may be transferred to another substrate for further processing. After removing epi layer 250, processing platform 240 may be employed for another round of processing (e.g., forming a second epi layer on carbon buffer layer 220).

[0029] The epi layer 250 may include III-V semiconductors, Si, Ge, III-N semiconductors, SiC, SiGe, or II-VI semiconductors, among others. In one example, the lattice of the first substrate 210 is matched to the lattice of the epi layer 250, in which case, if the carbon buffer layer 220 is porous or thin enough, the first substrate 210 acts as a seed for the growth of the epi layer 250. For example, in some cases, the carbon buffer layer 220 includes holes, and the material from which the epi layer 250 is formed can contact the first substrate 210 below through the holes, allowing the first substrate to seed the growth of the epi layer 250. In another example, the first substrate 210 seeding the epi layer 250 may occur even when there is no direct contact between the epi layer 250 and the first substrate 210. For example, according to certain embodiments, first substrate 210 may have a potential field (e.g., created by van der Waals forces and / or other atomic or molecular forces) and because carbon buffer layer 220 is thin, the potential field of first substrate 210 may reach beyond carbon buffer layer 220 into and interact with the region where epi layer 250 is formed. As a result, in some embodiments, the potential field from first substrate 210 affects the growth of epi layer 250.

[0030] Sandwiching the carbon buffer layer 220 between the first substrate 210 and the epi layer 250 can facilitate rapid and damage-free release and transfer of the epi layer 250.

[0031] In another example, the carbon buffer layer 220 may be thick enough (e.g., several layers thick) to act as a seed for growing the epilayer 250, in which case the epilayer 250 may be lattice matched to the carbon buffer layer 220. This example also allows for repeated use of the first substrate 210. In yet another example, the first substrate 210 together with the carbon buffer layer 220 may act as a seed for growing the epilayer 250.

[0032] In one example, epilayer 250 includes a 2D material system. In another example, epilayer 250 includes a 3D material system. The flexibility to process 2D and 3D material systems enables the fabrication of a wide range of optical, optoelectronic, and photonic devices known in the industry.

[0033] Processing of the epi layer 250 may be performed using any of a variety of semiconductor processing techniques known in the art. For example, low pressure metalorganic chemical vapor deposition (MOCVD) may be used to grow the epi layer 250 (e.g., a GaN film) on the carbon buffer layer 220, which is subsequently deposited on the first substrate 210 (e.g., a SiC substrate). In this example, the carbon buffer layer 220 and the first substrate 210 are pretreated (e.g., with H 2 O 4 at a temperature greater than 1100° C. for a time greater than 15 minutes) to clean the surface. 2 The GaN-containing epilayer 250 may then be baked at, for example, 200 mbar. Trimethylgallium, ammonia, and hydrogen may be used as Ga source, nitrogen source, and carrier gas, respectively. To obtain a smooth GaN epitaxial film on the carbon buffer layer 220, a modified two-step growth may be developed. The first step may be performed at a growth temperature of 1100° C. for a few minutes to promote guided nucleation at the terrace edges. The second growth step may be performed at an elevated temperature of 1250° C. to promote lateral growth. The vertical GaN growth rate in this case may be about 20 nm per minute.

[0034] 3A-3F illustrate a method 300 of layer transfer according to some embodiments. FIG. 3A shows that a carbon buffer layer 320 is formed on a donor wafer 310, which may be a single crystal wafer. For example, the carbon buffer layer 320 may be grown directly on the donor wafer 310 using, for example, any of the methods described above with respect to FIGS. 1A-1D. FIG. 3B shows that an epilayer 330 is epitaxially grown on the carbon buffer layer 320. The epilayer 330 may include an electronic layer, a photonic layer, or any other functional device layer. Methods for fabricating the epilayer 330 may include any of the methods and techniques described above with respect to FIGS. 2A-2C.

[0035] 3C shows that stressor 340 is disposed on epilayer 330. For example, stressor 340 may include a high pressure metal film, such as a Ni film. In this example, the Ni stressor is 1×10 -5 It can be deposited in an evaporator at a vacuum level of Torr.

[0036] 3D shows that a tape layer 350 is placed on the stressor 340 to handle the stressor 340. Using the tape layer 350 and stressor 340 can mechanically detach the epi layer 330 from the carbon buffer layer 320 at high peel rates by imparting high strain energy at the interface between the epi layer 330 and the carbon buffer layer 320. The peel rate can be high due at least to the weak van der Waals bonds between the carbon buffer layer 320 and other materials such as the epi layer 330.

[0037] In Figure 3E, the peeled epi layer 330 is placed on a host wafer 360 along with stressor 340 and tape layer 350. In Figure 3F, tape 350 and stressor 340 are removed, leaving epi layer 330 for further processing, such as forming more sophisticated devices or depositing additional materials on epi layer 330. In one example, tape layer 350 and stressor 340 are formed of FeCl 3 It can be etched away by the base solution.

[0038] In method 300, after the stripping of epi layer 330 shown in FIG. 3D, the remaining donor wafer 310 and carbon buffer layer 320 may be reused for the next cycle of epi layer processing. Alternatively, the carbon buffer layer 320 may also be stripped. In this case, a new carbon buffer layer may be deposited and / or formed on the donor wafer 310 prior to the next cycle of epi layer processing. In either case, the carbon buffer layer 320 protects the donor wafer 310 from damage, thereby allowing multiple uses and reducing costs. More details may be found in U.S. Patent Application No. 15 / 914,295, filed March 7, 2018, published July 12, 2018 as U.S. Patent Application Publication No. 2018 / 0197736, and entitled "SYSTEMS AND METHODS FOR GRAPHENE BASED LAYER TRANSFER," which is incorporated herein by reference in its entirety.

[0039] Figure 4 shows a photograph of a GaN thin film epitaxially grown on a carbon buffer layer and then removed from the surface of the carbon buffer layer by delamination using a flexible mechanical handler. Briefly, 4-inch diameter (0001) 4H-SiC wafers were used as substrates for growth on the silicon side. First, H 2The top surface of the SiC wafer was sublimated and a carbon buffer layer and a graphene layer were grown by annealing in Ar gas followed by a graphenization step in Ar at 1575°C. The graphene layer (located on the carbon buffer layer and substrate) was then removed using a mechanical peeling layer, leaving the carbon buffer layer on the SiC substrate. A GaN thin film was then grown on the carbon buffer layer using MOCVD. Trimethylgallium, ammonia, and hydrogen were used in a two-step growth process (the first step performed at 1100°C for several minutes and the second step performed at 1250°C). The GaN thin film was then detached from the carbon buffer layer using a flexible mechanical handler. In FIG. 4, the GaN thin film is shown as a free-standing GaN thin film attached to the flexible mechanical handler used to detach the GaN from the carbon buffer layer and substrate.

[0040] U.S. Provisional Patent Application No. 62 / 746,072, filed October 16, 2018, and entitled "Epitaxial Growth Template Using Carbon Buffer on Sublimated SiC Substrate," is hereby incorporated by reference in its entirety for all purposes.

[0041] While various inventive embodiments have been described and illustrated herein, those skilled in the art will readily envision a variety of other means and / or structures for performing the functions and / or obtaining the results and / or one or more advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. In general, those skilled in the art will readily recognize that all parameters, dimensions, materials, and configurations described herein are meant to be examples, and that the actual parameters, dimensions, materials, and / or configurations will depend on the particular application(s) for which the teachings of the present invention are used. Those skilled in the art will recognize, or be able to ascertain, using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. Thus, it should be understood that the foregoing embodiments are presented by way of example only, and that inventive embodiments may be practiced apart from what is specifically described and claimed within the scope of the appended claims and equivalents thereof. The inventive embodiments of the present disclosure relate to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and methods is within the inventive scope of the present disclosure, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent.

[0042] The embodiments described above can be implemented in any of numerous ways. For example, the embodiments of designing and creating the technology disclosed herein can be implemented using hardware, software, or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

[0043] Further, it should be appreciated that a computer may be embodied in any of numerous forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer, etc. In addition, a computer may be embodied in devices not generally considered computers but having suitable processing capabilities, including a personal digital assistant (PDA), a smart phone, or any suitable portable or fixed electronic device.

[0044] Similarly, a computer may have one or more input and output devices. These devices may be used, among other things, to present a user interface. Examples of output devices that may be used to provide a user interface include a printer or display screen for visual presentation of output, and a speaker or sound generating device for audible presentation of output. Examples of input devices that may be used for a user interface include keyboards and pointing devices such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through voice recognition or in another acoustic format.

[0045] Such computers may be interconnected by one or more networks in any suitable form, including local area networks or wide area networks, such as an enterprise network, an intelligent network (IN), or the Internet. Such networks may be based on any suitable technology and operate according to any suitable protocol, and may include wireless networks, wired networks, or fiber optic networks.

[0046] The various methods or processes outlined herein may be coded as software executable on one or more processors deploying any one of a variety of operating systems or platforms. In addition, such software may be written using any of a number of suitable programming languages ​​and / or programming or scripting tools, as well as compiled into executable machine language code or intermediate code that runs in a framework or virtual machine.

[0047] In this regard, the various inventive concepts may be embodied as a computer-readable storage medium (or multiple computer-readable storage media) (e.g., a computer memory, one or more floppy disks, compact disks, optical disks, magnetic tapes, flash memory, circuitry in a field programmable gate array or other semiconductor device, or other non-transitory or tangible computer storage medium) that is encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement various embodiments of the invention as discussed above. The computer-readable medium(s) may be portable, such that the program(s) stored thereon may be loaded onto one or more different computers or other processors to implement various aspects of the invention as discussed above.

[0048] The terms "program" or "software" are used herein in their original sense to refer to any type of computer code or set of computer-executable instructions that can be deployed to program a computer or other processor to implement various aspects of the embodiments as discussed above. In addition, according to one aspect, it should be recognized that one or more computer programs that, when executed, perform the methods of the present invention need not reside on a single computer or processor, but can be distributed in a modular manner among a number of different computers or processors to implement various aspects of the present invention.

[0049] Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments.

[0050] Similarly, data structures may be stored in a computer-readable medium in any suitable format. For simplicity of illustration, the data structures may be shown as having fields that are related through locations within the data structure. Such relationships may similarly be achieved by allocating storage for the fields with locations in the computer-readable medium that convey the relationship between the fields. However, any suitable mechanism may be used to establish relationships between information in fields of the data structure, for example through the use of pointers, tags, or other mechanisms that establish relationships between data elements.

[0051] Similarly, various inventive concepts may be embodied as one or more methods for which examples have been provided. The acts performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed to perform acts in an order different from that illustrated, which may include performing some acts simultaneously even if shown as sequential acts in the illustrative embodiments.

[0052] All definitions defined and used herein should be understood to take precedence over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined words.

[0053] The indefinite articles "a" and "an," as used herein and in the claims, unless clearly indicated otherwise, should be understood to mean "at least one."

[0054] The clause "and / or" as used herein and in the claims should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are conjunctive in some cases and disjunctive in other cases. Multiple elements listed with "and / or" should be interpreted in the same manner, i.e., "one or more" of the elements so conjoined. Multiple elements listed with "and / or" should be interpreted in the same manner, i.e., "one or more" of the elements so conjoined. There may optionally be other elements present other than the elements specifically indicated by the clause "and / or", whether related or unrelated to those elements specifically indicated. Thus, as a non-limiting example, when used in conjunction with non-limiting language such as "comprising", a reference to "A and / or B" may, for example, refer in one embodiment to only A (optionally including elements other than B), in another embodiment to only B (optionally including elements other than A), and in yet another embodiment to both A and B (optionally including other elements).

[0055] When used in the specification and claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" should be interpreted as being inclusive, i.e., the inclusion of at least one, but also one or more of several elements or lists of elements, and optionally additionally including unlisted items. Only words clearly indicating otherwise, such as "only one of" or "exactly one of," or "consisting of," when used in the claims, refer to the inclusion of exactly one element of numerous elements or lists of elements. In general, the word "or" used in this specification, when preceded by an exclusive word such as "either," "one of," "only one of," or "exactly one of," should be interpreted to indicate exclusive alternatives (i.e., "one or the other, but not both"). When used in the claims, "subject to" has its ordinary meaning as used in the field of patent law.

[0056] As used herein and in the claims, the clause "at least one" in reference to a list of one or more elements should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed in the list of elements, and not excluding any combinations of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically listed in the list of elements to which the clause "at least one" refers, whether related or unrelated to the specifically listed element. Thus, as a non-limiting example, "at least one of A and B" (or, similarly, "at least one of A or B" or, similarly, "at least one of A and / or B") can refer, for example, in one embodiment to at least one A, optionally including more than one A, and no B (and optionally including elements other than B), in another embodiment to at least one B, optionally including more than one B, and no A (and optionally including elements other than A), and in yet another embodiment to at least one A, optionally including more than one A, and at least one B, optionally including more than one B (and optionally including other elements).

[0057] In the above specification, as well as in the claims, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," "composed of," and the like, are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" are closed or semi-closed transitional phrases, respectively, as set forth in the U.S. Patent and Trademark Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

1. 1. A method comprising: forming a carbon buffer layer on a first substrate and forming a graphene layer on the carbon buffer layer, the carbon buffer layer being covalently bonded to the first substrate; removing the graphene layer to reveal the carbon buffer layer and form a processing platform; forming a first epitaxial layer on the carbon buffer layer covalently bonded to the first substrate, the first epitaxial layer comprising a semiconductor; The method includes:

2. The method of claim 1 , wherein the first substrate comprises silicon carbide and the graphene layer comprises a single crystal graphene layer.

3. The method of any one of claims 1 to 2, wherein the method further comprises transferring the first epitaxial layer from the carbon buffer layer to a second substrate.

4. The method of any one of claims 1 to 3, wherein forming the first epitaxial layer comprises epitaxially growing the first epitaxial layer using the first substrate as a seed crystal.

5. The method of claim 3 , further comprising forming a second epitaxial layer on the carbon buffer layer after transferring the first epitaxial layer to the second substrate.

6. The method of any one of claims 3 to 5, wherein transferring the first epitaxial layer comprises detaching the first epitaxial layer.

7. Transferring the first epitaxial layer includes: forming a metal stressor on the first epitaxial layer; placing a flexible tape over the metal stressor; stripping the first epitaxial layer and the metal stressor from the carbon buffer layer using the flexible tape; The method according to any one of claims 3 to 6, comprising:

8. The method of any one of claims 1 to 7, wherein the first epitaxial layer comprises a III-V semiconductor, Si, Ge, a III-N semiconductor, SiC, SiGe, and / or a II-VI semiconductor.

9. The method of any one of claims 1 to 8, wherein the carbon buffer layer comprises carbon clusters.

10. The method of any one of claims 1 to 9, wherein the carbon buffer layer comprises a carbon network.

11. The method of any one of claims 1 to 10, wherein the carbon buffer layer comprises a crystalline structure.

12. The method of any one of claims 1 to 11, wherein the graphene layer interacts with the carbon buffer layer via van der Waals forces.

13. The method of any one of claims 1 to 12, wherein there is no direct contact between the first epitaxial layer and the first substrate.

14. 14. The method of claim 1, wherein the first substrate has a potential field that crosses the carbon buffer layer to reach the first epitaxial layer and interacts with the first epitaxial layer.

15. 15. The method of any one of claims 1 to 14, wherein forming a carbon buffer layer on the first substrate and forming the graphene layer on the carbon buffer layer comprises a multi-step annealing process.

16. The method of any one of claims 1 to 15, wherein forming the first epitaxial layer comprises metalorganic chemical vapor deposition.

17. The method of any one of claims 1 to 16, wherein the first epitaxial layer is processed into a semiconductor device.

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