Semiconductor device

Abstract

To provide a circuit that can be applied to at least part of a shift register capable of switching a shift direction, and a method of driving the same.SOLUTION: A circuit SR having a function of controlling a potential of a terminal O has a function of shifting a signal of a terminal S1 and a function of shifting a signal of a terminal S2. In addition, the circuit SR has a function of outputting a signal delayed for the signal of the terminal S1 from the terminal O and a function of outputting a signal delayed for the signal of the terminal S2 from the terminal O. The circuit SR has a function as a stage of a sequential circuit, a flip-flop, or a shift register.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, one aspect of the present invention disclosed in this specification The technical field can include, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, their driving methods, or their manufacturing methods.

Background Art

[0003] A shift register is adopted as a driving circuit for a storage device, an image sensor, a display device, etc. In particular, the development of a shift register composed of transistors of the same polarity has been advanced. Regarding the technology related to such a shift register, it is disclosed in Patent Document 1 and Patent Document 2.

[0004] The shift direction of the shift register disclosed in Patent Documents 1 and 2 is only in one direction.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present invention aims to provide a novel circuit or a driving method thereof. In particular it aims to provide a novel circuit or a driving method thereof applicable to at least a part of a shift register capable of switching the shift direction.

[0007] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0008] An invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has first to third flip - flops. The first flip - flop has a function of outputting a first signal to a first wiring. The second flip - flop has a function of outputting a second signal to a second wiring. The third flip - flop has a function of outputting a third signal to a third wiring. The first signal has a value synchronized with a first clock signal. The second signal has a value synchronized with a second clock signal. The third signal has a value synchronized with a third clock signal. The second flip - flop has first to third transistors. One of the source or drain of the first transistor is electrically connected to a fourth wiring. One of the source or drain of the first transistor is electrically connected to a fourth wiring. The source or drain of the first transistor of the first transistor is electrically connected to the fourth wiring. One of the source or drain of the first transistor ​​​​​​​The other is electrically connected to the second wiring. The source or drain of the second transistor One of them is electrically connected to the first wiring. The source or drain of the second transistor The other is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the fifth wiring. The source or drain of the third transistor One of them is electrically connected to the third wiring. The source or drain of the third transistor The other is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the sixth wiring. The fourth wiring has a function of transmitting the second clock signal The fifth wiring has a function of transmitting the first clock signal The sixth wiring has a function of transmitting the third clock signal .

[0009] An invention according to an aspect of the present invention is a semiconductor device having a shift register. The shift register has first to third flip-flops. The first flip-flop has a function of outputting a first signal to the first wiring The second flip-flop has a function of outputting a second signal to the second wiring The third flip-flop has a function of outputting a third signal to the third wiring The first signal has a value synchronized with the first clock signal The second signal has a value synchronized with the second clock signal The third signal has a value synchronized with the third clock signal. The second flip-flop has first to third transistors. One of the source or drain of the first transistor is electrically connected to the fourth wiring. The source or drain of the first transistor The other is electrically connected to the second wiring. The source or drain of the second transistor One of them is electrically connected to the fifth wiring. The source or drain of the second transistor The other is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first wiring. The source or drain of the third transistor One of them is electrically connected to the sixth wiring. The source or drain of the third transistor The other is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the third wiring. The fourth wiring has a function of transmitting the second clock signal The fifth wiring has a function of transmitting the first clock signal The sixth wiring has a function of transmitting the third clock signal .

[0010] An invention according to an aspect of the present invention is a semiconductor device having a shift register. The shift register has first to fifth flip-flops. The first flip-flop has a function of outputting a first signal to the first wiring The second flip-flop has a function of outputting a second signal to the second wiring The third flip-flop has a function of outputting a third signal to the third wiring The fourth flip-flop has a function of outputting a fourth signal to the fourth wiring The fifth flip-flop has a function of outputting a fifth signal to the fifth wiring The first signal has a value synchronized with the first clock signal The second signal has a value synchronized with the second clock signal The third signal has a value synchronized with the third clock signal. The fourth signal , and has a value synchronized with the fourth clock signal. The fifth signal has a value synchronized with the first clock signal. The third flip-flop has the first to fifth transistors. One of the source or drain of the first transistor is electrically connected to the sixth wiring. The other of the source or drain of the first transistor is electrically connected to the third wiring. One of the source or drain of the second transistor is electrically connected to the second wiring. The other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the third transistor is electrically connected to the fourth wiring. The other of the source or drain of the third transistor is electrically connected to the gate of the first transistor. At least one of one of the source or drain of the fourth transistor and the gate of the fourth transistor is electrically connected to the first wiring. The other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor. At least one of one of the source or drain of the fifth transistor and the gate of the fifth transistor is electrically connected to the fifth wiring. The other of the source or drain of the fifth transistor is electrically connected to the gate of the third transistor. The sixth wiring has a function of being able to transmit the third clock signal. The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal.

[0011] The invention according to one aspect of the present invention is a semiconductor device having a shift register. The shift register has the first to third flip-flops. The first flip-flop has a function of being able to output a first signal to the first wiring. The second flip-flop has a second signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. signal output to the second wiring. The third flip-flop has a function of outputting a third signal to the third wiring. The first transistor has a source or drain electrically connected to the first wiring and a gate electrically connected to the second wiring. The second transistor has a source or drain electrically connected to the second wiring and a gate electrically connected to the third wiring. The third transistor has a source or drain electrically connected to the third wiring and a gate electrically connected to the first wiring. The fourth transistor has a source or drain electrically connected to the fourth wiring and a gate electrically connected to the first wiring. The fifth transistor has a source or drain electrically connected to the fifth wiring and a gate electrically connected to the third wiring. The sixth wiring has a function of being able to transmit the third clock signal. It has a function of being able to output a second signal to the wiring. The third flip-flop has a function of being able to output a third signal to the third wiring. The first signal has a value synchronized with the first clock signal. The second signal has a value synchronized with the second clock signal . The third signal has a value synchronized with the third clock signal. The second flip-flop has the first to fifth transistors. One of the source or drain of the first transistor is electrically connected to the fourth wiring. The other of the source or drain of the first transistor is electrically connected to the second wiring. One of the source or drain of the second transistor is electrically connected to the first wiring. The other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source or drain of the third transistor is electrically connected to the third wiring. The other of the source or drain of the third transistor is electrically connected to the gate of the first transistor. At least one of one of the source or drain of the fourth transistor and the gate of the fourth transistor is electrically connected to the first wiring. The other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor. At least one of one of the source or drain of the fifth transistor and the gate of the fifth transistor is electrically connected to the third wiring . The other of the source or drain of the fifth transistor is electrically connected to the gate of the third transistor. The fourth wiring has a function of being able to transmit the second clock signal .

[0012] Note that the W (W is the channel width) / L (L is the channel length) of the fourth transistor is the fifth transistor​​ It is preferably 0.8 times or more and 1.2 times or less of the W / L of the transistor.

[0013] In addition, the W (W is the channel width) / L (L is the channel length) of the second transistor is the third It is preferably 0.8 times or more and 1.2 times or less of the W / L of the transistor.

[0014] In addition, the first transistor preferably has an oxide semiconductor in the channel formation region .

[0015] An invention according to an aspect of the present invention is a display module having the above semiconductor device and an FPC .

[0016] An invention according to an aspect of the present invention is an electronic device having the above semiconductor device or the above display module, a speaker, an operation button, and / or an antenna.

Advantages of the Invention

[0017] An aspect of the present invention can provide a novel circuit or a driving method thereof. In particular, a novel circuit applicable to at least a part of a shift register capable of switching the shift direction or a driving method thereof can be provided.

[0018] Note that the description of these effects does not prevent the existence of other effects. Note that an aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be naturally apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0019]

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Embodiments for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is as follows The present invention is not limited to the description in the embodiments, and various modifications can be made to the form and details thereof without departing from the spirit and scope of the present invention, which can be easily understood by those skilled in the art. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. Accordingly, it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0021] In addition, one aspect of the present invention includes all devices including integrated circuits, display devices, and RF tags within its scope. The display devices include liquid crystal display devices, light-emitting devices having light-emitting elements typified by organic light-emitting elements in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), etc., and display devices having integrated circuits in the circuit are included within its scope. When explaining the configuration of the invention using drawings, the same reference numerals are commonly used among different drawings to indicate the same components. In addition, in this specification, etc., in the figures or sentences described in a certain embodiment, it is possible to extract a part thereof to constitute one aspect of the invention. Therefore, when a figure or sentence describing a part is described, the content obtained by extracting a part of the figure or sentence is also disclosed as one aspect of the invention and can be considered to constitute one aspect of the invention. And it can be said that one aspect of the invention is clear.

[0022] When explaining the configuration of the invention using drawings, the same reference numerals are commonly used among different drawings to indicate the same components. That is, when explaining the configuration of the invention using drawings, the same reference numerals are commonly used among different drawings to indicate the same components.

[0023] In addition, in this specification, etc., in the figures or sentences described in a certain embodiment, it is possible to extract a part thereof to constitute one aspect of the invention. Therefore, when a figure or sentence describing a part is described, the content obtained by extracting a part of the figure or sentence is also disclosed as one aspect of the invention and can be considered to constitute one aspect of the invention. That is, when a figure or sentence describing a part is described, the content obtained by extracting a part of the figure or sentence is also disclosed as one aspect of the invention and can be considered to constitute one aspect of the invention. Therefore, for example, when one or more active elements (such as transistors), wirings, passive elements (such as capacitive elements), conductive layers, insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described, the content obtained by extracting a part of the figure or sentence is also disclosed as one aspect of the invention and can be considered to constitute one aspect of the invention. And it can be said that one aspect of the invention is clear. Therefore, for example, when one or more active elements (such as transistors), wirings, passive elements (such as capacitive elements), conductive layers, insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described, In the drawings or the text, it is assumed that a part can be extracted to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (transistors, capacitor elements, etc.) to constitute an aspect of the invention. As another example, from the text stating that "A has B, C, D, E, or F", by arbitrarily extracting some elements, aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E" can be constituted. For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (transistors, capacitor elements, etc.) to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (transistors, capacitor elements, etc.) to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (transistors, capacitor elements, etc.) to constitute an aspect of the invention. As another example, from the text stating that "A has B, C, D, E, or F", by arbitrarily extracting some elements, aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E" can be constituted. As another example, from the text stating that "A has B, C, D, E, or F", by arbitrarily extracting some elements, aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E" can be constituted. As another example, from the text stating that "A has B, C, D, E, or F", by arbitrarily extracting some elements, aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E" can be constituted. As another example, from the text stating that "A has B, C, D, E, or F", by arbitrarily extracting some elements, aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E" can be constituted.

[0024] Also, in this specification, etc., in the drawings or text described in a certain embodiment, when at least one specific example is described, it is easily understood by those skilled in the art to derive the upper concept of that specific example. Therefore, in the drawings or text described in a certain embodiment, when at least one specific example is described, the upper concept of that specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention. And it can be said that that aspect of the invention is clear. Also, in this specification, etc., in the drawings or text described in a certain embodiment, when at least one specific example is described, it is easily understood by those skilled in the art to derive the upper concept of that specific example. Therefore, in the drawings or text described in a certain embodiment, when at least one specific example is described, the upper concept of that specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, in the drawings or text described in a certain embodiment, when at least one specific example is described, the upper concept of that specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, in the drawings or text described in a certain embodiment, when at least one specific example is described, the upper concept of that specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention. And it can be said that that aspect of the invention is clear.

[0025] Also, in this specification, etc., at least the content described in the drawings (even a part of the drawings) is disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for a certain content, if it is described in the drawings, even if it is not described in the text, that content is disclosed as an aspect of the invention and can constitute an aspect of the invention. Also, in this specification, etc., at least the content described in the drawings (even a part of the drawings) is disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for a certain content, if it is described in the drawings, even if it is not described in the text, that content is disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for a certain content, if it is described in the drawings, even if it is not described in the text, that content is disclosed as an aspect of the invention and can constitute an aspect of the invention. It is possible to achieve. Similarly, for a figure obtained by extracting a part of a figure, it is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And it can be said that one aspect of the invention is clear. And it is disclosed as such, and it is possible to constitute one aspect of the invention. And it can be said that one aspect of the invention is clear.

[0026] (Embodiment 1) In this embodiment, an apparatus according to one aspect of the present invention will be described.

[0027] The apparatus according to one aspect of the present invention illustrated in FIG. 1 has a circuit 100. The circuit 100 is connected to wiring CK1, wiring CK2, wiring CK3, wiring CK4, wiring SP1, wiring SP2, and N (N is a natural number of 3 or more) pieces of wiring OUT (also referred to as wiring OUT[1] to [N]). CK1, wiring CK2, wiring CK3, wiring CK4, wiring SP1, wiring SP2, and N (N is a natural number of 3 or more) pieces of wiring OUT (also referred to as wiring OUT[1] to [N]).

[0028] Each of wiring CK1, wiring CK2, wiring CK3, wiring CK4, wiring SP1, wiring SP2, and wiring OUT[1] to [N] has a function of transmitting a signal, potential, current, etc. That is, each of wiring CK1, wiring CK2, wiring CK3, wiring CK4, wiring SP1, wiring SP2, and wiring OUT[1] to [N] has a function as a signal line, power supply line, or current supply line. For example, signals are input to each of wiring CK1, wiring CK2, wiring CK3, and wiring CK4. The signal input to wiring CK1 (also referred to as signal V ), the signal input to wiring CK2 (also referred to as signal V ), the signal input to wiring CK3 (also referred to as signal V ), and the signal input to wiring CK4 (also referred to as signal V ) include clock signals. However, signals V to signal V CK1 ), the signal input to wiring CK2 ), the signal input to wiring CK3 (also referred to as signal V CK2 ), and the signal input to wiring CK4 (also referred to as signal V CK 3 ), and the signal input to wiring CK4 (also referred to as signal V CK4 ) include clock signals. However, signals V to signal V CK1 to signal V CK4 have different phases from each other ​is preferred. For example, signals are input to each of wiring SP1 and wiring SP2. The wiring The signal input to SP1 (also referred to as signal V SP1 ) and the signal input to wiring SP2 (also referred to as signal V ) include a start pulse. As will be described later, the shift direction of data can be controlled by signal V SP2 and signal V SP1 and signal V SP2 . For example, signals are output from circuit 100 to each of wirings OUT[1] to [N]. The signals output to each of wirings OUT 1] to [N] (also referred to as signals V OUT [1] to [N]) are the output signals of circuit 100. As will be described later, signals V OUT [1] to N are signals that are delayed with respect to signal V SP1 or signal V SP2 .

[0029] Circuit 100 has a function of controlling the potentials of wirings OUT[1] to [N]. Specifically , circuit 100 has a function of shifting signal V SP1 and a function of shifting signal V SP2 . And circuit 100 has a function of outputting signals V that are delayed with respect to signal V SP1 to each of wirings OUT[1] to [N] and signals V OUT [1] to N] to each of wirings OUT[1] to [N]. As illustrated in FIG. 2, when signal V SP2 becomes high level (active) , signal V OUT is shifted in the direction from wiring OUT[1] to wiring OUT[N] . Therefore, signal V SP1 when it becomes high level (active) , signal V SP1 is shifted in the direction from wiring OUT[1] to wiring OUT[N] . Thus, signal V OUT[1] is delayed with respect to signal V SP1 and signal V OUT [i] (where i is any one of 2 to N - 1) is delayed with respect to signal V OUT [i - 1], and signal V O UT [N] is delayed with respect to signal V OUT [N - 1]. Also, as illustrated in FIG. 3, when signal V SP2 becomes high level (active), signal V SP2 is shifted in the direction from wiring OUT[N] to wiring OUT[1]. Therefore, signal V OUT [N] is delayed with respect to signal V SP2 and signal V OUT [i] is delayed with respect to signal V OUT [i + 1], and signal V OUT [1] is delayed with respect to signal V OUT [2]. Thus, circuit 100 has the function as a shift register, particularly a bidirectional shift register. And the shift direction of the data is selected SP1 by which of signal V SP2 or signal V is shifted. Also, which of signal V SP1 or signal V SP2 is shifted is selected by which of signal V S P1 or signal V SP2 becomes active. However, the function that circuit 100 has is not limited to this. Next, a configuration example of circuit 100 will be described with reference to FIG. 1. Circuit 100 has N circuits

[0030] SR (also referred to as circuits SR[1] to [N]). FIG. 1 shows circuits SR[1] to [5], and circuit SR[N]. Circuit SR[1] has a terminal C1 connected to wirings CK1 to wiring is connected to one corresponding wiring among CK4, and terminal C2 is among the wirings CK1 to CK4 is connected to one corresponding wiring, and terminal C3 is among the wirings CK1 to CK4 corresponding is connected to one corresponding wiring, terminal S1 is connected to wiring SP1, and terminal S2 is connected to wiring OUT[2] is connected, and terminal O is connected to wiring OUT[1]. Circuit SR[i] is different from circuit SR[1] in that terminal S1 is connected to wiring OUT[i - 1]. Circuit SR[N] is different from circuit SR[1] in that terminal S1 is connected to wiring OUT[N - 1] and terminal S2 is connected to wiring SP2. Note that in circuit SR[4m + 1] (m is 0 or a positive integer), terminal C1 is connected to wiring CK1, terminal C2 is connected to wiring CK4, and terminal C3 is connected to wiring CK2. In circuit SR[4m + 2], terminal C1 is connected to wiring CK2, terminal C2 is connected to wiring CK1, and terminal C3 is connected to wiring CK3. In circuit S R[4m + 3], terminal C1 is connected to wiring CK3, terminal C2 is connected to wiring CK2, and terminal C3 is connected to wiring CK4. In circuit SR[4m + 4] (4m + 4 ≤ N), terminal C1 is connected to wiring CK4, terminal C2 is connected to wiring CK3, and terminal C3 is connected to wiring CK1.

[0031] Circuit SR has a function of controlling the potential of terminal O. Specifically, circuit SR has a function of shifting the signal of terminal S1 and a function of shifting the signal of terminal S2. And circuit S R has a function of outputting from terminal O a signal that is delayed with respect to the signal of terminal S1 and a function of outputting from terminal O a signal that is delayed with respect to the signal of terminal S2. As illustrated in FIG. 2, signal V SP1When it is shifted, a signal that is delayed with respect to the signal input to terminal S1 is output from terminal O. For example, in circuit SR[i], a signal V OU T [i - 1] is delayed with respect to the signal V OUT [i] is output from terminal O. On the other hand, as illustrated in FIG. 3 , when the signal V SP2 is shifted, a signal that is delayed with respect to the signal input to terminal S2 is output from terminal O. For example, in circuit SR[i], a signal V that is delayed with respect to the signal V input to terminal S2 OUT [i + 1] is output from terminal O as the signal V OUT [i]. Thus, circuit SR functions as a stage of a sequential circuit, flip - flop, or shift register . However, the function of circuit SR is not limited to this .

[0032] Next, a specific example of circuit SR will be described with reference to FIG. 4. Circuit SR includes transistors 101, transistor 102, transistor 103, transistor 104, and transistor 105. The first terminal of transistor 101 is connected to terminal C1, and the second terminal is connected to terminal O. The first terminal of transistor 102 is connected to wiring VSS1 , and the second terminal is connected to terminal O. The first terminal of transistor 103 is connected to wiring VSS2 , and the second terminal is connected to the gate of transistor 101. The first terminal of transistor 10 4 is connected to terminal S1, the second terminal is connected to the gate of transistor 101, and the gate is connected to terminal C2. The first terminal of transistor 105 is connected to terminal S2 , the second terminal is connected to the gate of transistor 101, and the gate is connected to terminal C3 . is connected. Note that the gate of transistor 101, the second terminal of transistor 103, the second terminal of transistor 104, or the second terminal of transistor 105 is denoted as node ND1. The second terminal of transistor 104 or the second terminal of transistor 105 is shown as node ND1. That's all.

[0033] Each of transistors 101 to 105 has a function of controlling conduction or non - conduction between the connection destination of the first terminal (either the source or the drain) and the connection destination of the second terminal (either the source or the drain). That is, each of transistors 101 to 105 has a function as a switch. However, the functions of transistors 101 to 105 are not limited to this. The connection destination of the first terminal (also referred to as either the source or the drain) and the connection destination of the second terminal (also referred to as either the source or the drain). Each of transistors 101 to 105 has a function of controlling conduction or non - conduction between the connection destination of the first terminal (either the source or the drain) and the connection destination of the second terminal (either the source or the drain). That is, each of transistors 101 to 105 has a function as a switch. However, the functions of transistors 101 to 105 are not limited to this. Each of transistors 101 to 105 has a function as a switch. However, the functions of transistors 101 to 105 are not limited to this. The functions of transistors 101 to 105 are not limited to this.

[0034] Each of wiring VSS1 and wiring VSS2 has a function of transmitting a signal, potential, or current. That is, each of wiring VSS1 and wiring VSS2 has a function as a signal line, power supply line, or current supply line. For example, a potential is input to each of wiring VSS1 and wiring VSS2. As the potential input to wiring VSS1 and wiring VSS2, there is a potential corresponding to the low level or high level of signal V, signal V, signal V, or signal V. In particular, if transistor 101 is an N - channel type, it is preferable that a potential corresponding to the low level of signal V, signal V, signal V, or signal V is input to wiring VSS1 and wiring VSS2. On the other hand, if transistor 101 is a P - channel type, a potential corresponding to the high level of signal V, signal V, signal V, or signal V is input to wiring VSS1 and wiring VSS2. Each of wiring VSS1 and wiring VSS2 has a function of transmitting a signal, potential, or current. That is, each of wiring VSS1 and wiring VSS2 has a function as a signal line, power supply line, or current supply line. For example, a potential is input to each of wiring VSS1 and wiring VSS2. As the potential input to wiring VSS1 and wiring VSS2, there is a potential corresponding to the low level or high level of signal V, signal V, signal V, or signal V. CK1 , signal V CK2 , signal V CK3 , or signal V CK4 corresponding to the low level or high level. In particular, if transistor 101 is an N - channel type, it is preferable that a potential corresponding to the low level of signal V, signal V, signal V, or signal V is input to wiring VSS1 and wiring VSS2. On the other hand, if transistor 101 is a P - channel type, a potential corresponding to the high level of signal V, signal V, signal V, or signal V is input to wiring VSS1 and wiring VSS2. If transistor 101 is an N - channel type, it is preferable that a potential corresponding to the low level of signal V, signal V, signal V, or signal V is input to wiring VSS1 and wiring VSS2. CK1 , signal V CK2 , signal V CK3 , or signal V CK4 low level is input to wiring VSS1 and wiring VSS2. On the other hand, if transistor 101 is a P - channel type, a potential corresponding to the high level of signal V, signal V, signal V, or signal V is input to wiring VSS1 and wiring VSS2. If transistor 101 is a P - channel type, a potential corresponding to the high level of signal V, signal V, signal V, or signal V is input to wiring VSS1 and wiring VSS2. CK1 , signal V CK2 , signal V CK3 or a potential corresponding to the high level of signal V CK4 is preferably input.

[0035] Note that the potential corresponding to the low level of the signal is equal to or approximately equal to the low level of the signal. However, the potential corresponding to the low level of the signal may be lower than the high level of the signal or lower than the intermediate potential between the high level and the low level of the signal. Similarly, the potential corresponding to the high level of the signal is equal to or approximately equal to the high level of the signal. However, the potential corresponding to the high level of the signal may be higher than the low level of the signal or higher than the intermediate potential between the high level and the low level of the signal.

[0036] When the same potential is input to wiring VSS1 and wiring VSS2, wiring VSS1 and wiring VSS2 may be combined into one wiring. That is, the first terminal of transistor 102 and the first terminal of transistor 103 may be connected to the same wiring.

[0037] Next, an example of the operation of circuit SR illustrated in FIG. 4 will be described by taking circuit SR[i] as an example. For convenience, in circuit SR[i], terminal C1 is connected to wiring CK2, terminal C2 is connected to wiring CK1, and terminal C3 is connected to wiring CK3. Also, for convenience, at least transistor 101, transistor 104, and transistor 105 are assumed to be N-channel type.

[0038] The case of outputting a signal delayed with respect to the signal of terminal S1 from terminal O and the case of outputting a signal delayed with respect to the signal of terminal S2 from terminal O will be described separately.

[0039] ​​​​​​​​​ First, an example of the operation when a signal delayed with respect to the signal of terminal S1 is output from terminal O will be described with reference to FIG. 5.

[0040] An example of the operation of circuit SR in period A will be described. FIG. 6(A) is an example of a schematic diagram of the operation in period A.

[0041] Since the signal of terminal C2 (signal V CK1 ) becomes high level, transistor 104 turns on. Since the signal of terminal C3 (signal V ) becomes low level, transistor 105 turns off. Also, transistor 103 turns off. Therefore, since the signal of terminal S1 (high level signal V CK3 ) is supplied to node ND1, the potential of node ND1 rises. After that, when the potential of node ND1 becomes equal to or approximately equal to the value obtained by subtracting the threshold voltage of transistor 104 from the potential of the gate of transistor 104 (the signal of terminal C 2 (high level signal V OUT [i-1])), transistor 104 turns off. Then, node ND 1 becomes a floating state. Since the potential of node ND1 becomes a high value, transistor 101 turns on. Also, transistor 102 turns on. Therefore, since the signal of terminal C1 (low level signal V CK1 )) and the potential of wiring VSS1 are supplied to terminal O, the signal of terminal O (signal V )

[0042] becomes low level. Note that the high value of the potential of node ND1 means the value at which transistor 101 turns on. CK2 and OUT the potential of wiring VSS1 are supplied to terminal O, the signal of terminal O (signal V becomes low level.

[0043] Note that the high value of the potential of node ND1 means the value at which transistor 101 turns on. ​​​Well. Specifically, it is a value higher than the sum of the potential between the first terminal or the second terminal of the transistor 101 and the threshold voltage of the transistor 101. It is a value higher than the sum of the potential between the first terminal or the second terminal of the transistor 101 and the threshold voltage of the transistor 101.

[0044] Note that in period A, the transistor 102 may be off.

[0045] An example of the operation of the circuit SR in period B will be described. FIG. 6(B) is an example of a schematic diagram of the operation in period B. It is an example of a schematic diagram of the operation in period B.

[0046] Since the signal of terminal C2 (signal V CK1 ) becomes low level, the transistor 104 turns off. Since the signal of terminal C3 (signal V CK3 ) becomes low level, the transistor 105 turns off. Also, the transistor 103 turns off. Therefore, the node ND1 becomes a floating state and the potential of the node ND1 maintains a high value.

[0047] Since the potential of the node ND1 becomes a high value, the transistor 101 turns on. Also, the trans istor 102 turns off. Therefore, the signal of terminal C1 (high-level signal V CK2 ) is supplied to the terminal O, and the potential of the terminal O rises. The potential difference between the terminal O and the node ND1 is held by the parasitic capacitance between the gate and the second terminal of the transistor 101, and the node ND1 is in a floating state. Therefore, when the potential of the terminal O rises, the potential of the node ND1 also rises. When the potential of the node ND1 becomes higher than the sum of the potential of the first terminal of the transistor 101 (signal of terminal C 1 (high-level signal V CK2 )) and the threshold voltage of the transistor 101, the potential of the terminal O becomes the same value as the signal of terminal C1 (high-level signal V CK2 ) up to rises. Thus, the signal of terminal O (signal V OUT [i]) becomes high level.

[0048] An example of the operation of circuit SR in period C will be described. FIG. 7(A) is an example of a schematic diagram of the operation in period C. is an example of a schematic diagram of the operation.

[0049] Since the signal of terminal C2 (signal V CK1 ) becomes low level, transistor 104 turns off. Since the signal of terminal C3 (signal V CK3 ) becomes high level, transistor 105 turns on. Also, transistor 103 turns off. Therefore, since the signal of terminal S2 (high level signal V bell signal V OUT [i + 1]) is supplied to node ND1, the potential of node ND1 rises. After that, when the potential of node ND1 becomes equal to or approximately equal to the value obtained by subtracting the threshold voltage of transistor 105 from the potential of the gate of transistor 105 (signal of terminal C 3 (high level signal V CK3 ))), transistor 105 turns off. And node ND 1 becomes a floating state. Since the potential of node ND1 becomes a high value, transistor 101 turns on. Also, transistor

[0050] 102 turns on. Therefore, since the signal of terminal C1 (low level signal V CK2 ) and the potential of wiring VSS1 are supplied to terminal O, the signal of terminal O (signal V OUT [i]) becomes low level.

[0051] In period C, the signal of terminal C1 (low level signal V CK2 ) is supplied to terminal O via transistor 101. Also, the current supply capacity of transistor 101 is often large. is often large. Therefore, the fall time of the signal of terminal O (signal V OUT [i]) can be shortened.

[0052] Note that when the signal of terminal C1 (low-level signal V CK2 ) and the potential of wiring VSS1 are supplied to terminal O, when the potential of terminal O drops, the potential of node ND1 also drops. When the potential of node ND1 is lower than the value obtained by subtracting the threshold voltage of transistor 105 from the potential of the gate of transistor 105 (signal of terminal C3 (high-level signal V CK3 ), transistor 105 turns on as described above. However, when the potential of node ND1 is higher than the value obtained by subtracting the threshold voltage of transistor 105 from the potential of the gate of transistor 105 (signal of terminal C3 (high-level signal V ), transistor 105 does not turn on. CK3 )) from the threshold voltage of transistor 105, transistor 105 does not turn on.

[0053] Note that in period C, transistor 102 may be off.

[0054] An example of the operation of circuit SR in period D will be described. FIG. 7(B) is an example of a schematic diagram of the operation in period D.

[0055] Since the signal of terminal C2 (signal V CK1 ) becomes low level, transistor 104 turns off. Since the signal of terminal C3 (signal V CK3 ) becomes low level, transistor 105 turns off. Also, transistor 103 turns on. Therefore, since the potential of wiring VSS2 is supplied to node ND1, the potential of node ND1 drops.

[0056] Since the potential of node ND1 becomes a low value, transistor 101 turns off. Also, trans The transistor 102 is turned on. Therefore, the potential of the wiring VSS1 is supplied to the terminal O. The signal at terminal O (signal V OUT [i]) becomes low level.

[0057] Note that the low potential value of the node ND1 means a potential value at which the transistor 101 is turned off. Specifically, the potential of the first terminal or the second terminal of the transistor 101 and the The value is lower than the sum of the threshold voltage of the transistor 101 and the threshold voltage of the transistor 102.

[0058] In the period D, the transistor 102 may be off. In such a case, the terminal O Since it is floating, the signal at terminal O (signal V OUT [i]) remains at a low level.

[0059] In the period D, the transistor 103 may be turned off. In such a case, the node N Since D1 is in a floating state, the potential of the node ND1 remains high. Since the potential of the transistor 101 is high, the transistor 101 is turned on. CK2 is supplied to terminal O.

[0060] An example of the operation of the circuit SR in the period E will be described. FIG. 8A shows the operation of the circuit SR in the period E. 1 is an example of a schematic diagram of an operation.

[0061] The signal at terminal C2 (signal V CK1 ) goes high, so transistor 104 is turned on. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 The transistor 103 is turned on. Therefore, the signal (low level) of the terminal S1 Bell Signal V OUT [i-1]) and the potential of the wiring VSS2 are supplied to the node ND1. As a result, the potential of node ND1 becomes a low value.

[0062] Since the potential of node ND1 becomes a low value, transistor 101 turns off. Also, transistor 102 turns on. Therefore, since the potential of wiring VSS1 is supplied to terminal O, the signal of terminal O (signal V OUT [i]) becomes a low level.

[0063] During period E, wiring VSS2 and terminal S1 are in a conductive state via transistors 103 and 104. Therefore, since the potential of wiring VSS2 is supplied to wiring OUT[i - 1], the noise generated in wiring OUT[i - 1] can be reduced.

[0064] Note that, during period E, transistor 102 may be off. In such a case, since terminal O becomes a floating state, the signal of terminal O (signal V OUT [i]) maintains a low level.

[0065]

[0066] Note that, during period E, transistor 103 may be off.

[0067] An example of the operation of circuit SR during period F will be described. Fig. 8(B) is an example of a schematic diagram of the operation during period F. Since the signal of terminal C2 (signal V CK1 ) becomes a low level, transistor 104 turns off. Since the signal of terminal C3 (signal V CK3 ) becomes a low level, transistor 105 turns off. Also, transistor 103 turns on. Therefore, since the potential of wiring VSS2 is supplied to node ND1, the potential of node ND1 becomes a low value.

[0068] ​Since the potential of node ND1 becomes a low value, transistor 101 turns off. Also, trans istor 102 turns on. Therefore, since the potential of wiring VSS1 is supplied to terminal O, the signal (signal V OUT [i]) of terminal O becomes a low level.

[0069] Note that in period F, transistor 102 may be off. In such a case, since terminal O becomes floating, the signal (signal V OUT [i]) of terminal O maintains a low level.

[0070] Note that in period F, transistor 103 may be off. In such a case, since node N D1 becomes floating, the potential of node ND1 maintains a low value.

[0071] An example of the operation of circuit SR in period G will be described. FIG. 9(A) is an example of a schematic diagram of the operation in period G.

[0072] Since the signal (signal V CK1 ) of terminal C2 becomes a low level, transistor 104 turns off. Since the signal (signal V ) of terminal C3 becomes a high level, transistor 105 CK3 turns on. Also, transistor 103 turns on. Therefore, the signal (low level signal V ) of terminal S2 and the potential of wiring VSS2 are supplied to node ND1, OUT so the potential of node ND1 becomes a low value. Since the potential of node ND1 becomes a low value, transistor 101 turns off. Also, trans

[0073] istor 102 turns on. Therefore, since the potential of wiring VSS1 is supplied to terminal O, the signal (signal V ) of terminal O becomes a low level. OUT [i]) of terminal O becomes a low level.

[0074] During period G, the wiring VSS2 and the terminal S2 are connected through the transistors 103 and 105 to be in a conductive state. Therefore, since the potential of the wiring VSS2 is supplied to the wiring OUT[i + 1], the noise generated in the wiring OUT[i + 1] can be reduced. During period G, the wiring VSS2 and the terminal S2 are connected through the transistors 103 and 105 to be in a conductive state. Therefore, since the potential of the wiring VSS2 is supplied to the wiring OUT[i + 1], the noise generated in the wiring OUT[i + 1] can be reduced. During period G, the wiring VSS2 and the terminal S2 are connected through the transistors 103 and 105 to be in a conductive state. Therefore, since the potential of the wiring VSS2 is supplied to the wiring OUT[i + 1], the noise generated in the wiring OUT[i + 1] can be reduced.

[0075] Note that in period G, the transistor 102 may be off. In such a case, since the terminal O becomes a floating state, the signal of the terminal O (signal V [i]) maintains a low level. OUT [i]) maintains a low level.

[0076] Note that in period G, the transistor 103 may be off.

[0077] An example of the operation of the circuit SR in period H will be described. FIG. 9(B) is an example of a schematic diagram of the operation in period H. An example of the operation of the circuit SR in period H will be described. FIG. 9(B) is an example of a schematic diagram of the operation in period H.

[0078] Since the signal of the terminal C2 (signal V CK1 ) becomes a low level, the transistor 104 turns off. Since the signal of the terminal C3 (signal V ) becomes a low level, the transistor 105 CK3 ) becomes a low level, the transistor 105 turns off. Also, the transistor 103 turns on. Therefore, since the potential of the wiring VSS2 is supplied to the node ND1, the potential of the node ND1 becomes a low value. ) becomes a low level, the transistor 105 turns off. Also, the transistor 103 turns on. Therefore, since the potential of the wiring VSS2 is supplied to the node ND1, the potential of the node ND1 becomes a low value. ) becomes a low level, the transistor 105 turns off. Also, the transistor 103 turns on. Therefore, since the potential of the wiring VSS2 is supplied to the node ND1, the potential of the node ND1 becomes a low value.

[0079] Since the potential of the node ND1 becomes a low value, the transistor 101 turns off. The transistor 102 turns on. Therefore, since the potential of the wiring VSS1 is supplied to the terminal O, the signal of the terminal O (signal V Since the potential of the node ND1 becomes a low value, the transistor 101 turns off. The transistor 102 turns on. Therefore, since the potential of the wiring VSS1 is supplied to the terminal O, the signal of the terminal O (signal V [i]) becomes a low level. OUT [i]) becomes a low level.

[0080] Note that in period H, the transistor 102 may be off. In such a case, the terminal O In order to be in a floating state, the signal of terminal O (signal V OUT [i]) maintains a low level.

[0081] Note that during period H, transistor 103 may be off. In such a case, since node N D1 becomes a floating state, the potential of node ND1 maintains a low value.

[0082] Next, an example of the operation when a signal delayed with respect to the signal of terminal S2 is output from terminal O will be described with reference to FIG. 10. The timing chart illustrated in FIG. 10 is different from the timing chart illustrated in FIG. 5 in that the signal of terminal S1 (signal V OUT [i - 1]) becomes high level during period C, and the signal of terminal S2 ( signal V OUT [i + 1]) becomes high level during period A. Also, the timing chart illustrated in FIG. 10 is different from the timing chart illustrated in FIG. 5 in that the signal of terminal C2 (signal V ) becomes high level during periods C and G, and the signal of terminal C3 ( CK1 ) becomes high level during periods A and E. However, the description of the common part with the operation when a signal delayed with respect to the signal of terminal S1 is output from terminal O is omitted. signal V CK3 ) becomes high level during periods A and E. However, the description of the common part with the operation when a signal delayed with respect to the signal of terminal S1 is output from terminal O is omitted. chart illustrated in FIG. 5 in that the signal of terminal C2 (signal V A common description of the operation when a signal delayed with respect to the signal of terminal S1 is output from terminal O will be omitted.

[0083] An example of the operation of circuit SR in period A will be described.

[0084] Since the signal of terminal C2 (signal V CK1 ) becomes low level, transistor 104 turns off. Since the signal of terminal C3 (signal V CK3 ) becomes high level, transistor 105 turns on. Also, transistor 103 turns off. Therefore, the signal of terminal S2 (high level Bell signal V OUT [i + 1]) is supplied to node ND1, so the potential of node ND1 rises. After that, when the potential of node ND1 becomes equal to or approximately equal to the value obtained by subtracting the threshold voltage of transistor 105 from the potential of the gate of transistor 105 (signal at terminal C 3 (high-level signal V CK3 ), transistor 105 turns off. Then, node ND 1 becomes floating. Since the potential of node ND1 becomes high, transistor 101 turns on. Also, transistor

[0085] 102 turns on. Therefore, since the signal at terminal C1 (low-level signal V ) and the potential of wiring VSS1 are supplied to terminal O, the signal at terminal O (signal V CK2 ) and the signal at terminal O (signal V OUT [i]) becomes low level.

[0086] Note that in period A, transistor 102 may be off.

[0087] The operation of circuit SR in period B is the same as the operation in period B when a signal delayed with respect to the signal at terminal S1 is output from terminal O.

[0088] An example of the operation of circuit SR in period C will be described.

[0089] Since the signal at terminal C2 (signal V CK1 ) becomes high level, transistor 104 turns on. Since the signal at terminal C3 (signal V ) becomes low level, transistor 105 CK3 turns off. Also, transistor 103 turns off. Therefore, since the signal at terminal S1 (high-level bell signal V bell signal V OUT [i - 1]) is supplied to node ND1, the potential of node ND1 rises. Thereafter, when the potential of node ND1 becomes equal to or approximately equal to the value obtained by subtracting the threshold voltage of transistor 104 from the potential of the gate of transistor 104 (the signal (high-level signal V at terminal C 2)) CK1 , transistor 104 turns off. Then, node ND 1 becomes floating. Since the potential of node ND1 becomes high, transistor 101 turns on. Also, transistor

[0090] 102 turns on. Thus, since the signal at terminal C1 (low-level signal V ) and the potential of wiring VSS1 are supplied to terminal O, the signal at terminal O (signal V CK2 ) and the potential of wiring VSS1 are supplied to terminal O, the signal at terminal O (signal V OUT [i]) becomes low level.

[0091] Note that when the potential of terminal O decreases due to the signal at terminal C1 (low-level signal V CK2 ) and the potential of wiring VSS1 being supplied to terminal O, the potential of node ND1 also decreases. If the potential of node ND1 is lower than the value obtained by subtracting the threshold voltage of transistor 104 from the potential of the gate of transistor 104 (the signal (high-level signal V at terminal C2 ), transistor 104 turns on as described above. However, if the potential of node ND1 is higher than the value obtained by subtracting the threshold voltage of transistor 104 from the potential of the gate of transistor 104 (the signal (high-level signal V at terminal C2 ), transistor 104 does not turn on. ), transistor 104 does not turn on. CK1 ), transistor 104 turns on as described above. However, if the potential of node ND1 is higher than the value obtained by subtracting the threshold voltage of transistor 104 from the potential of the gate of transistor 104 (the signal (high-level signal V at terminal C2 ), transistor 104 does not turn on. ), transistor 104 does not turn on. CK1 ), transistor 104 does not turn on. ), transistor 104 does not turn on.

[0092] Note that in period C, transistor 102 may be off.

[0093] The operation of circuit SR in period D outputs a signal delayed with respect to the signal at terminal S1 from terminal O. It is the same as the operation in the period D when a force is applied.

[0094] The operation of the circuit SR in the period E outputs a signal that is delayed with respect to the signal of the terminal S1 from the terminal O. It is the same as the operation in the period G when a force is applied.

[0095] The operation of the circuit SR in the period F outputs a signal that is delayed with respect to the signal of the terminal S1 from the terminal O. It is the same as the operation in the period F or the period H when a force is applied.

[0096] The operation of the circuit SR in the period G outputs a signal that is delayed with respect to the signal of the terminal S1 from the terminal O. It is the same as the operation in the period E when a force is applied.

[0097] The operation of the circuit SR in the period H outputs a signal that is delayed with respect to the signal of the terminal S1 from the terminal O. It is the same as the operation in the period F or the period H when a force is applied.

[0098] Next, an example of a preferred embodiment of the device according to one aspect of the present invention will be described.

[0099] The transistors 101 to 105 preferably have the same polarity. That is, , the transistors 101 to 105 are preferably N-channel type. Or alternatively, the transistors 101 to 105 are preferably P-channel type. . Thereby, the manufacturing process can be simplified, so that the yield can be improved and / or the cost can be reduced. In particular, when the transistors 101 to 105 are of N-channel type, transistors having an oxide semiconductor in the channel formation region (also referred to as OS transistors) are used as the transistors 101 to 105, respectively. can be adopted. The OS transistor has a higher mobility and an extremely small off-current than a transistor having amorphous silicon in the channel formation region. Therefore, the sizes of transistors 101 to 105 can be reduced. The first conductor (also referred to as a conductive film or a conductive layer) has a region that becomes the first terminal (one of the source electrode or the drain electrode) on the terminal C1 side of the transistor 101. The second conductor has a region that becomes the second terminal (the other of the source electrode or the drain electrode) on the terminal O side of the transistor 101. The third conductor has a region that becomes the gate (gate electrode) of the transistor 101. And the third conductor has a first region overlapping the first conductor and a second region overlapping the second conductor. In such a case, it is preferable that the area of the second region is larger than the area of the first region. Thereby, since the capacitance value between the second terminal and the gate of the transistor 101 can be increased, the rising width of the potential of the node ND1 in the period B can be increased. The W (channel width) / L (channel length) of the transistor 101 is preferably larger than the W / L of the transistor 102. The W / L of the transistor 101 is preferably larger than the W / L of the transistor 103. The W / L of the transistor 101 is preferably larger than the W / L of the transistor 104.

[0100] The first conductor (also referred to as a conductive film or a conductive layer) has a region that becomes the first terminal (one of the source electrode or the drain electrode) on the terminal C1 side of the transistor 101. The second conductor has a region that becomes the second terminal (the other of the source electrode or the drain electrode) on the terminal O side of the transistor 101. The third conductor has a region that becomes the gate (gate electrode) of the transistor 101. And the third conductor has a first region overlapping the first conductor and a second region overlapping the second conductor. In such a case, it is preferable that the area of the second region is larger than the area of the first region. Thereby, since the capacitance value between the second terminal and the gate of the transistor 101 can be increased, the rising width of the potential of the node ND1 in the period B can be increased. Note that the first region is the area where the third conductor and the first conductor overlap without passing through the semiconductor layer, and the second region may be the area where the third conductor and the second conductor overlap without passing through the semiconductor layer. The semiconductor layer is the semiconductor layer having the channel formation region of the transistor 101. The W (channel width) / L (channel length) of the transistor 101 is preferably larger than the W / L of the transistor 102. The W / L of the transistor 101 is preferably larger than the W / L of the transistor 103.

[0101] Note that the first region is the area where the third conductor and the first conductor overlap without passing through the semiconductor layer, and the second region may be the area where the third conductor and the second conductor overlap without passing through the semiconductor layer. The semiconductor layer is the semiconductor layer having the channel formation region of the transistor 101. The semiconductor layer is the semiconductor layer having the channel formation region of the transistor 101. The semiconductor layer is the semiconductor layer having the channel formation region of the transistor 101.

[0102] The W (channel width) / L (channel length) of the transistor 101 is preferably larger than the W / L of the transistor 102. The W / L of the transistor 101 is preferably larger than the W / L of the transistor 103. The W / L of the transistor 101 is preferably larger than the W / L of the transistor 104. It is preferably larger than the W / L of . The W / L of transistor 101 is preferably larger than the W / L of transistor 105. That is, among transistors 101 to 105, it is preferable that the W / L of transistor 101 is the largest. Thereby, the current supply capacity of transistor 101 can be increased, so that the rise

[0103] time and fall time of the signal at terminal O can be shortened. Note that when a transistor is composed of a plurality of transistors, the W / L of the transistor is the value obtained by summing the W / L of each of the plurality of transistors. For example, when a plurality of transistors are connected in parallel, W is the sum of the W of the plurality of transistors, and L is the average value of the L of the plurality of

[0104] The W / L of transistor 104 is preferably equal to or approximately equal to the W / L of transistor 105 . That the W / L of transistor 104 is approximately equal to the W / L of transistor 105 means that the W / L of transistor 104 is 0.8 times or more and 1. 2 times or less of the W / L of transistor 105. More preferably, it is 0.9 times or more and 1.1 times or less. Thereby , circuit SR can perform the same operation whether shifting the signal at terminal S1 or shifting the signal at terminal S2 .

[0105] Here, circuit SR is not limited to the configuration illustrated in FIG. 4. A modification example of the circuit SR illustrated in FIG. 4 will be described. However, parts common to FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted .

[0106] In the circuit SR of the present embodiment described with reference to FIG. 4 or without being illustrated in FIG. 4, the The first terminal of the transistor 103 may be connected to the wiring VSS1, terminal S1, terminal S2, terminal C1, terminal C 2, terminal C3, terminal C4, terminal S3, terminal S4, or terminal O. Terminal C4 , terminal S3, and terminal S4 will be described later. FIG. 11(A) illustrates, in FIG. 4, a configuration in which the first terminal of the transistor 103 is connected to the wiring VSS1. FIG. 11(B) illustrates, in FIG. 4, a configuration in which the first terminal of the transistor 103 is connected to terminal S2. FIG. 12(A) illustrates, in FIG. 4, a configuration in which the first terminal of the transistor 103 is connected to terminal S1.

[0107] In the circuit SR of the present embodiment described with reference to FIGS. 4, 11(A), 11(B), and 12(A), etc., or described without being illustrated, the first terminal of the transistor 104 may be connected to the wiring V SS2, terminal S1, terminal S2, terminal C1, terminal C2, terminal C3, terminal C4, terminal S3, or terminal S4. FIG. 12(B) illustrates, in FIG. 4, a configuration in which the first terminal of the transistor 102 is connected to terminal S2. FIG. 13(A) illustrates, in FIG. 4, a configuration in which the first terminal of the transistor 102 is connected to terminal S1.

[0108] In the circuit SR of the present embodiment described with reference to FIGS. 4, 11(A), 11(B), 12(A), 12(B), and 13(A), etc., or described without being illustrated, the gate of the transistor 102 may be connected to the gate of the transistor 103. FIG. 13(B) illustrates, in FIG. 4, a configuration in which the gate of the transistor 102 is connected to the gate of the transistor 103.

[0109] ​​​​FIG. 4, FIGS. 11(A), 11(B), 12(A), 12(B), 13(A) and 13(B), etc., which will be described with reference to the drawings or without reference to the drawings, in the circuit SR of the present embodiment , for the transistor 104, at least one of the first terminal or the gate may be connected to the terminal S1 . Also, for the transistor 105, at least one of the first terminal or the gate may be connected to the terminal S2. FIG. 14(A) shows, in FIG. 4, that the gate of the transistor 10 4 is connected to the terminal S1 and the gate of the transistor 105 is connected to the terminal S2 . FIG. 14(B) shows, in FIG. 4, that the first terminal of the transistor 104 is connected to the terminal C2, the gate of the transistor 104 is connected to the terminal S1, and the transistor 105 has its first terminal connected to the terminal C3 and its gate connected to the terminal S2 .

[0110] In the circuit SR of the present embodiment, which will be described with reference to FIGS. 4, 11(A), 11(B), 12(A), 12(B), 13(A), and FIG. 13(B), etc., or without reference to the drawings, a configuration for controlling the potential of the gate of the transistor 104 may be added. Also, a configuration for controlling the potential of the gate of the transistor 105 may be added. FIG. 15(A ) shows, in FIG. 4, a configuration in which transistors 106, 107, 108 and 109 are added. The transistor 106 has its first terminal connected to the terminal C4, its second terminal connected to the gate of the transistor 104, and its gate connected to the terminal S3. The transistor 107 has its first terminal connected to the wiring VSS3 , its second terminal connected to the gate of the transistor 104, and its gate connected to the terminal C1 . The transistor 108 has its first terminal connected to the terminal C4, and its second terminal connected to the gate of the transistor 105, and the gate is connected to the terminal S4. The transistor 109 has its first terminal connected to the wiring VSS4, and its second terminal connected to the gate of the transistor 105 and the gate is connected to the terminal C1.

[0111] Each of the wiring VSS3 and the wiring VSS4 has a function of transmitting a signal, a potential, or a current. That is, each of the wiring VSS3 and the wiring VSS4 has a function as a signal line, a power supply line, or a current supply line. For example, a potential is input to each of the wiring VSS3 and the wiring VSS4. As the potential input to the wiring VSS3 and the wiring VSS4, there is a potential corresponding to the low level or the high level of the signal V CK1 、 signal V CK2 、signal V CK3 、or signal V CK4 . In particular, if the transistors 104 and 105 are N-channel type , it is preferable that a potential corresponding to the low level of the signal V 、signal V CK1 、signal V CK2 、signal V CK3 、or also the signal V CK4 is input to the wiring VSS3 and the wiring VSS4. Further, if the transistors 104 and 105 are P-channel type , it is preferable that a potential corresponding to the high level of the signal V 、signal V CK1 、signal V CK2 、signal V CK3 、or signal V CK4 is input to the wiring VSS3 and the wiring V SS4.

[0112] The terminal S3 is preferably connected to the wiring OUT[i - 2]. The terminal S4 is connected to the wiring OUT It is preferably connected to [i + 2]. Terminal C4 is preferably connected to the corresponding one of wirings CK1 to CK4. Specifically, the terminal C4 of circuit SR[4m + 1] is connected to wiring CK3, the terminal C4 of circuit SR[4m + 2] is connected to wiring CK4, the terminal C4 of circuit SR[4m + 3] is connected to wiring CK1, and the terminal C4 of circuit SR[4m + 4] is connected to wiring CK2. For example, when terminal C1 is connected to wiring CK2, terminal C2 is connected to wiring CK1, and terminal C3 is connected to wiring CK3, terminal C4 is connected to wiring CK4.

[0113] An example of the operation of circuit SR illustrated in FIG. 15(A) will be described. However, only an example of the operation when a signal delayed with respect to the signal of terminal S1 is output from terminal O will be described.

[0114] An example of the operation of circuit SR in period H immediately before period A will be described.

[0115] Since the signal of terminal S3 (signal V OUT [i - 2]) becomes high level, transistor 10 6 turns on. Also, since the signal of terminal C1 (signal V CK2 ) becomes low level, transistor 10 7 turns off. Therefore, the signal of terminal C4 (high-level signal V CK4 ) is supplied to the gate of transistor 104, so that the potential of the gate of transistor 104 rises. When the potential of the gate of transistor 104 reaches a value obtained by subtracting the threshold voltage of transistor 106 from the potential of the gate of transistor 106 (the signal of terminal S3 (high-level signal V OUT [i - 2])), transistor 106 turns off. Then, the gate of transistor 104 becomes floating. OUT

[0116] The signal of terminal S4 (signal V OUT [i + 2]) becomes low level, so transistor 10 8 turns off. Also, since the signal of terminal C1 (signal V CK2 ) becomes low level, tra nsistor 109 turns off. Therefore, the gate of transistor 105 becomes floating. When the initial value of the potential of the gate of transistor 105 is a low value, the potential of the gate of transistor 105 maintains a low value.

[0117] Since the potential of the gate of transistor 104 becomes a high value, transistor 104 turns on . Also, since the potential of the gate of transistor 105 becomes a low value, transistor 105 turns off. Therefore, the signal of terminal S1 (low-level signal V OUT [i - 1]) is supplied to node ND1.

[0118] An example of the operation of circuit SR in period A will be described.

[0119] Since the signal of terminal S3 (signal V OUT [i - 2]) becomes low level, transistor 10 6 turns off. Also, since the signal of terminal C1 (signal V CK2 ) becomes low level, tra nsistor 107 turns off. Therefore, the gate of transistor 104 becomes floating, so the potential of the gate of transistor 104 maintains a high value.

[0120] Since the signal of terminal S4 (signal V OUT [i + 2]) becomes low level, transistor 10 8 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes low level, transis The latch 109 is turned off. Therefore, the gate of the transistor 105 becomes floating, and thus the potential of the gate of the transistor 105 maintains a low value.

[0121] Since the potential of the gate of the transistor 104 becomes a high value, the transistor 104 is turned on. Also, since the potential of the gate of the transistor 105 becomes a low value, the transistor 105 is turned off. Therefore, the signal (high-level signal V OUT [i - 1]) of the terminal S1 is supplied to the node ND1, and the potential of the node ND1 rises. The potential difference between the gate of the transistor 104 and the second terminal is held by the parasitic capacitance between the gate of the transistor 104 and the second terminal, and the gate of the transistor 104 is in a floating state. Therefore, when the potential of the node ND1 rises, the potential of the gate of the transistor 104 also rises. When the potential of the gate of the transistor 104 becomes higher than the sum of the potential of the first terminal of the transistor 104 (the signal of the terminal S1 (high level signal V [i - 1])) and the threshold voltage of the transistor 104, OUT the potential of the node ND1 rises to the same value as the high-level signal V [i - 1]. Thus, since the potential difference between the gate of the transistor 104 and the second terminal can be increased, the drain current of the transistor 104 can be increased. Therefore, OUT the rising time of the potential of the node ND1 can be shortened. Alternatively, since the size of the transistor 104 can be reduced, the layout area can be reduced. An example of the operation of the circuit SR in the period B will be described.

[0122]

[0123] ​​​​​The signal of terminal S3 (signal V OUT [i - 2]) becomes low level, so transistor 10 6 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes high level, transistor 107 turns on. Therefore, since the potential of wiring VSS3 is supplied to the gate of transistor 104, the potential of the gate of transistor 104 drops.

[0124] The signal of terminal S4 (signal V OUT [i + 2]) becomes low level, so transistor 10 8 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes high level, transistor 109 turns on. Therefore, since the potential of wiring VSS4 is supplied to the gate of transistor 105, the potential of the gate of transistor 105 becomes a low value.

[0125] Since the potential of the gate of transistor 104 becomes a low value, transistor 104 turns off . Since the potential of the gate of transistor 105 becomes a low value, transistor 105 turns off .

[0126] An example of the operation of circuit SR in period C will be described.

[0127] The signal of terminal S3 (signal V OUT [i - 2]) becomes low level, so transistor 10 6 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes low level, transistor 107 turns off. Therefore, since the gate of transistor 104 becomes floating, the potential of the gate of transistor 104 maintains a low value.

[0128] The signal of terminal S4 (signal V OUT ​​​Since [i + 2] becomes low level, transistor 10 8 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes low level, transistor 109 turns off. Therefore, since the gate of transistor 105 becomes floating, the potential of the gate of transistor 105 maintains a low value.

[0129] Since the potential of the gate of transistor 104 becomes a low value, transistor 104 turns off. Since the potential of the gate of transistor 105 becomes a low value, transistor 105 turns off.

[0130] An example of the operation of circuit SR in period D will be described.

[0131] Since the signal of terminal S3 (signal V OUT [i - 2]) becomes low level, transistor 10 6 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes low level, transistor 107 turns off. Therefore, since the gate of transistor 104 becomes floating, the potential of the gate of transistor 104 maintains a low value.

[0132] Since the signal of terminal S4 (signal V OUT [i + 2]) becomes high level, transistor 10 8 turns on. Since the signal of terminal C1 (signal V CK2 ) becomes low level, transistor 109 turns off. Therefore, since the signal of terminal C4 (high level signal V CK4 ) is supplied to the gate of transistor 105, the potential of the gate of transistor 105 rises.

[0133] Since the potential of the gate of transistor 104 becomes a low value, transistor 104 turns off. Since the potential of the gate of transistor 105 becomes a high value, transistor 105 turns on. Thus, the signal of terminal S2 (low-level signal V OUT [i + 1]) is supplied to node ND 1.

[0134] An example of the operation in period E immediately after period D will be described.

[0135] Since the signal of terminal S3 (signal V OUT [i - 2]) becomes low level, transistor 10 6 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes low level, transistor 107 turns off. Thus, since the gate of transistor 104 becomes a floating state, the potential of the gate of transistor 104 maintains a low value.

[0136] Since the signal of terminal S4 (signal V OUT [i + 2]) becomes low level, transistor 10 8 turns off. Since the signal of terminal C1 (signal V CK2 ) becomes low level, transistor 109 turns off. Thus, since the gate of transistor 105 becomes a floating state, the potential of the gate of transistor 105 maintains a high value.

[0137] Since the potential of the gate of transistor 104 becomes a low value, transistor 104 turns off. Since the potential of the gate of transistor 105 becomes a high value, transistor 105 turns on. Thus, the signal of terminal S2 (low-level signal V OUT [i + 1]) is supplied to node ND 1.

[0138] The operation in period E except immediately after period D is the same as the operation in period C.

[0139] The operation in period F is the same as the operation in period B.

[0140] The operation in period G is the same as the operation in period C.

[0141] The operation in period H except for immediately before period A is the same as the operation in period C.

[0142] Note that for transistor 106, at least one of the first terminal or the gate may be connected to terminal S3. Also, for transistor 108, at least one of the first terminal or the gate may be connected to terminal S4. FIG. 15(B) illustrates a configuration in which, in FIG. 15(A), the first terminal of transistor 106 is connected to terminal S3 and the first terminal of transistor 108 is connected to terminal S4. FIG. 16(A) illustrates a configuration in which, in FIG. 4, the first terminal of transistor 106 is connected to terminal S3, the gate of transistor 106 is connected to terminal C4, the first terminal of transistor 108 is connected to terminal S4, and the gate of transistor 108 is connected to terminal C4.

[0143] Note that at least one of the first terminal or the gate of transistor 106 may be connected to terminal S1. Also, at least one of the first terminal or the gate of transistor 108 may be connected to terminal S 2. FIG. 16(B) illustrates a configuration in which, in FIG. 15(A), the first terminal of transistor 106 is connected to terminal C2, the gate of transistor 106 is connected to terminal S1, the first terminal of transistor 108 is connected to terminal C3, and the gate of transistor 108 is connected to terminal S2. FIG. 17(A) illustrates a configuration in which, in FIG. 15(A), the first terminal of the tra The first terminal of transistor 106 is connected to terminal S1, and the gate of transistor 106 is connected to terminal S1. The first terminal of transistor 108 is connected to terminal S2, and the gate of transistor 108 is connected to terminal S2. This configuration is illustrated. In FIG. 17(B), in FIG. 15(A ), the first terminal of transistor 106 is connected to terminal S1, and the transistor 10 6's gate is connected to terminal C2. The first terminal of transistor 108 is connected to terminal S2 and the gate of transistor 108 is connected to terminal C3. This configuration is illustrated.

[0144] Note that the first terminal of transistor 107 may be connected to wiring VSS1, wiring VSS2, wiring VSS4 , terminal S1, terminal S2, terminal S3, terminal S4, terminal C2, terminal C3 or terminal C4. Also, the first terminal of transistor 109 may be connected to wiring VSS1, wiring VSS2, wiring VSS3, terminal S1, terminal S2, terminal S3, terminal S4, terminal C2, terminal C3 or terminal C4. In FIG. 18(A), in FIG. 15(A), the first terminal of transistor 10 7 is connected to terminal S3, and the first terminal of transistor 109 is connected to terminal S4 and continued. This configuration is illustrated. In FIG. 18(B), in FIG. 15(A), the first terminal of transistor 10 7 is connected to wiring VSS1, and the first terminal of transistor 109 is connected to wiring VS S1. This configuration is illustrated.

[0145] Note that the W / L of transistor 106 is preferably equal to or approximately equal to the W / L of transistor 108. When the W / L of transistor 106 is approximately equal to the W / L of transistor 108, it means that the W / L of transistor 106 is 0.8 times or more of the W / L of transistor 108, ​​​It means 1.2 times or less, and more preferably 0.9 times or more and 1.1 times or less.

[0146] The W / L of the transistor 107 is equal to or approximately equal to the W / L of the transistor 109. It is preferable that the W / L of the transistor 107 is approximately equal to the W / L of the transistor 109. By "correct," it is meant that the W / L of transistor 107 is approximately equal to the W / L of transistor 109. , the W / L of the transistor 107 is 0.8 times or more and 1.2 times the W / L of the transistor 109. More preferably, it is 0.9 times or more and 1.1 times or less.

[0147] The transistors 106 to 109 have the same polarity as the transistor 101. It is preferable that there is.

[0148] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), As shown in Figs. 16(B), 17(A), 17(B), 18(A) and 18(B), etc. In the circuit SR of this embodiment, which will be described below or will not be shown in the figure, a terminal O and a node ND 1. In FIG. 19(A), a transistor may be added between the transistor 1 in FIG. The transistor 110 has a first terminal connected to the terminal O. The first terminal is connected to the node ND1, and the gate is connected to the terminal C1.

[0149] Note that the transistor 110 preferably has the same polarity as the transistor 101 .

[0150] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Figures 14(A), 14(B), 15(A), 15(B), 16(A), Figures 16(B), 17(A), 17(B), 18(A), 18(B), and 19( A), etc., as illustrated and described, or described without illustration, in the circuit SR of the present embodiment, the terminal between C1 and the node ND1, a transistor may be added. Figure 19(B) illustrates a configuration in which a transistor 111 is added as in Figure 4. The first terminal of the transistor 111 is connected to the terminal C1, and the second terminal is connected to the node ND1.

[0151] Note that the transistor 111 preferably has the same polarity as the transistor 101.

[0152] Note that a signal may be input to the gate of the transistor 111, and the on or off of the transistor 11 1 may be controlled by the signal.

[0153] Note that the gate of the transistor 111 may be connected to the gate of the transistor 102 . Alternatively, the gate of the transistor 111 may be connected to the gate of the transistor 103 as well. Alternatively, the gate of the transistor 111 may be connected to the gates of the transistor 102 and the trans istor 103 as well.

[0154] In Figures 4, 11(A), 11(B), 12(A), 12(B), 13(A), 1 3(B), Figures 14(A), 14(B), 15(A), 15(B), 16(A), Figures 16(B), 17(A), 17(B), 18(A), 18(B), 19(A ) and 19(B), etc., as illustrated and described, or described without illustration, in the circuit SR of the present embodiment a transistor connected in series with the transistor 103 may be added. Figure 2 In 0(A), in FIG. 4, a configuration in which transistor 112 is added is illustrated. The trans istor 112 has its first terminal connected to the second terminal of transistor 103 and its second terminal connected to node ND1.

[0155] Note that transistor 112 preferably has the same polarity as transistor 101.

[0156] Note that a signal may be input to the gate of transistor 112, and the on or off of transistor 11 2 may be controlled by the signal.

[0157] Note that transistor 112 may be connected between the first terminal of transistor 101 and wiring VSS1. connected.

[0158] In the circuit SR of the present embodiment illustrated and described in FIGS. 4, 11(A), 11(B), 12(A), 12(B), 13(A), 13(B), 14(A), 14(B), 15(A), 15(B), 16(A), 16(B), 17(A), 17(B), 18(A), 18(B), 19(A ), 19(B), and 20(A), etc., or described without illustration, a transistor connected in series with transistor 102 may be added. In FIG. 20(B), in FIG. 4, a configuration in which transistor 113 is added is illustrated. The transistor 113 has its first terminal connected to the second terminal of transistor 102 and its second terminal connected to terminal O. connected.

[0159] Note that transistor 113 preferably has the same polarity as transistor 101.

[0160] Note that a signal may be input to the gate of transistor 113, and the on or off state of transistor 11 3 may be controlled by the signal.

[0161] As shown in FIGS. 4, 11(A), 11(B), 12(A), 12(B), 13(A), 1 3(B), 14(A), 14(B), 15(A), 15(B), 16(A), 16(B), 17(A), 17(B), 18(A), 18(B), 19(A ), 19(B), 20(A), and 20(B), etc., or described without being illustrated, in the circuit SR of the present embodiment, a transistor may be added between the gate of transistor 101 and the connection point of the second terminal of transistor 1 04 and the second terminal of transistor 105. FIG. 21(A) illustrates a configuration in which transistor 114 is added in FIG. 4. The first terminal of transistor 114 is connected to the gate of transistor 101 and the second terminal is connected to the second terminal of transistor 104, the second terminal of transistor 105, and the second terminal of transistor 103.

[0162] Note that transistor 114 preferably has the same polarity as transistor 101.

[0163]

[0164] Note that, as illustrated in FIG. 21(B), the second terminal of transistor 103 may be connected to the first terminal of transistor 114.

[0164] Note that the gate of transistor 114 may be connected to terminal C1. Alternatively, a potential corresponding to the high level of the signal of terminal C1 may be input to the gate of transistor 114.

[0165] FIG. 4, FIG. 11(A), FIG. 11(B), FIG. 12(A), FIG. 12(B), FIG. 13(A), FIG. 1 3(B), FIG. 14(A), FIG. 14(B), FIG. 15(A), FIG. 15(B), FIG. 16(A), FIG. 16(B), FIG. 17(A), FIG. 17(B), FIG. 18(A), FIG. 18(B), FIG. 19(A ), FIG. 19(B), FIG. 20(A), FIG. 20(B), FIG. 21(A) and FIG. 21(B), etc., which will be described with reference to the drawings or without reference to the drawings. In the circuit SR of the present embodiment, the gate of the transistor 1 03 may be connected to the terminal S3, the terminal S4, or the terminal C4. FIG. 22(A) illustrates a configuration in which the gate of the transistor 103 is connected to the terminal C4 in FIG. 4 .

[0166] FIG. 4, FIG. 11(A), FIG. 11(B), FIG. 12(A), FIG. 12(B), FIG. 13(A), FIG. 1 3(B), FIG. 14(A), FIG. 14(B), FIG. 15(A), FIG. 15(B), FIG. 16(A), FIG. 16(B), FIG. 17(A), FIG. 17(B), FIG. 18(A), FIG. 18(B), FIG. 19(A ), FIG. 19(B), FIG. 20(A), FIG. 20(B), FIG. 21(A), FIG. 21(B) and FIG. 2 2(A), etc., which will be described with reference to the drawings or without reference to the drawings. In the circuit SR of the present embodiment, a configuration for controlling the potential of the gate of the transistor 103 may be added. FIG. 22(B) illustrates a configuration in which the transistors 115 and 116 are added in FIG. 4 . The transistor 115 has its first terminal connected to the terminal C4, its second terminal connected to the gate of the transistor 103, and its gate connected to the terminal C4. The transistor 116 has its first terminal connected to the wiring VSS2, its second terminal connected to the gate of the transistor 103, and its gate connected to the node ND1.

[0167] ​During period A, period B, and period C, since the signal of terminal C4 (signal V CK4 ) becomes low level , transistor 115 turns off. Since the potential of node ND1 becomes a high value, transistor 116 turns on. Thus, since the potential of wiring VSS2 is supplied to the gate of transistor 103, the potential of the gate of transistor 103 becomes a low value. Since the potential of the gate of transistor 103 becomes a low value, transistor 103 turns off.

[0168] During period D, since the signal of terminal C4 (signal V CK4 ) becomes high level, transistor 115 turns on. Since the potential of node ND1 becomes a low value, transistor 116 turns off. Thus, since the signal of terminal C4 (high-level signal V CK4 ) is supplied to the gate of transistor 103, the potential of the gate of transistor 103 becomes a high value. Since the potential of the gate of transistor 103 becomes a high value, transistor 103 turns on.

[0169] During period E, period F, and period G, since the signal of terminal C4 (signal V CK4 ) becomes low level , transistor 115 turns off. Since the potential of node ND1 becomes a low value, transistor 116 turns off. Thus, since the gate of transistor 103 becomes in a floating state , the potential of the gate of transistor 103 is maintained at a high value. Since the potential of the gate of transistor 103 becomes a high value, transistor 103 turns on.

[0170] During period H, since the signal of terminal C4 (signal V CK4 ) becomes high level, transistor ​Transistor 115 is turned on. Since the potential of node ND1 becomes a low value, transistor 116 is turned off. Thus, the signal of terminal C4 (high-level signal V CK4 ) is supplied to the gate of transistor 10 3, so that the potential of the gate of transistor 103 becomes a high value. Since the potential of the gate of transistor 103 becomes a high value, transistor 103 is turned on.

[0171] Note that for transistor 115, at least one of the first terminal or the gate may be connected to terminal C4. For example, the first terminal of transistor 115 may be connected to terminal C4, and the gate of transistor 115 may be connected to a wiring (not shown) to which a potential corresponding to the high level of signal V CK1 CK1 CK2 CK2 CK3 CK3 C C K4 K4

[0172] Note that the gate of transistor 116 may be connected to terminal C1, terminal C2, terminal C3, terminal S1, terminal S2 or terminal O. Fig. 23(A) illustrates a configuration in which the gate of transistor 116 is connected to terminal S1 in Fig. 22(B). Fig. 23(B) illustrates a configuration in which the gate of transistor 116 is connected to terminal C1 in Fig. 2

[0173] Note that the first terminal of transistor 116 may be connected to wiring VSS1, wiring VSS3, wiring VSS4

[0174]

[0175] ​ FIG. 4, FIGS. 11(A), 11(B), 12(A), 12(B), 13(A), 13(B), FIGS. 14(A), 14(B), 15(A), 15(B), 16(A), 16(B), FIGS. 17(A), 17(B), 18(A), 18(B), 19(A ), 19(B), FIGS. 20(A), 20(B), 21(A), 21(B), 22 (A), 22(B), FIGS. 23(A) and 23(B), etc., which will be described with reference to the drawings or described without being illustrated. In the circuit SR of the present embodiment, the gate of the transistor 102 may be connected to the terminal S1 , terminal S2, terminal S3, terminal S4, terminal C2, terminal C3 or terminal C4. FIG. 24(A) illustrates a configuration in which, in FIG. 4, the gate of the transistor 102 is connected to the terminal C4 . FIG. 24(B) illustrates a configuration in which, in FIG. 4, the gate of the transistor 102 is connected to the terminal S1 . In FIGS. 4, 11(A), 11(B), 12(A), 12(B), 13(A), 13(B), FIGS. 14(A), 14(B), 15(A), 15(B), 16(A),

[0176] 16(B), FIGS. 17(A), 17(B), 18(A), 18(B), 19(A ), 19(B), FIGS. 20(A), 20(B), 21(A), 21(B), 22 22(A), FIGS. 22(B), 23(A), 23(B), 24(A) and 24(B), etc., which will be described with reference to the drawings or described without being illustrated. In the circuit SR of the present embodiment, when a plurality of configurations can be applied to each transistor , a transistor corresponding to any two or more of the plurality of configurations may be provided. That is, a certain transistor has a first configuration and a second configuration . In the circuit SR of the present embodiment described with reference to FIGS. 4, 11(A), 11(B), 12(A), 12(B), 13(A), 13(B), FIGS. 14(A), 14(B), 15(A), 15(B), 16(A), 16(B), FIGS. 17(A), 17(B), 18(A), 18(B), 19(A), 19(B), FIGS. 20(A), 20(B), 21(A), 21(B), 22(A), FIGS. 22(B), 23(A), 23(B), 24(A) and 24(B), etc., or described without being illustrated, when a plurality of configurations can be applied to each transistor, a transistor corresponding to any two or more of the plurality of configurations may be provided. That is, a certain transistor has a first configuration and a second configuration . That is, a certain transistor has a first configuration, a second configuration And when the application of the third configuration is possible, among the transistor corresponding to the first configuration, the transistor corresponding to the second configuration, and the transistor corresponding to the third configuration, two or more transistors may be provided. Among the transistor corresponding to the first configuration, the transistor corresponding to the second configuration, and the transistor corresponding to the third configuration, two or more transistors may be provided.

[0177] For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided. For example, regarding the first terminal of the transistor 103, there are configurations connected to the wiring VSS2 (see Fig. 4), configurations connected to the wiring VSS1 (see Fig. 11(A)), configurations connected to the terminal S2 (see Fig. 11(B)), configurations connected to the terminal S1 (see Fig. 12(A)), configurations connected to the terminal C1, configurations connected to the terminal C2, configurations connected to the terminal C3, configurations connected to the terminal C4, configurations connected to the terminal S3, configurations connected to the terminal S4, and configurations connected to the terminal O. In Fig. 25(A), in the circuit SR illustrated in Fig. 4, the transistor 103A corresponding to the transistor 103 whose first terminal is connected to the terminal S2 and the transistor 103B corresponding to the transistor 103 whose first terminal is connected to the terminal S1 are provided.

[0178] For example, regarding the gate of the transistor 103, there are configurations connected to the terminal S3, configurations connected to the terminal S4, configurations connected to the terminal C2, configurations connected to the terminal C3, and configurations connected to the terminal C4 (see Fig. 22(A)). In Fig. 25(B), in the circuit SR illustrated in Fig. 4, the transistor 103C corresponding to the transistor 103 whose gate is connected to the terminal S2 and the transistor 103D corresponding to the transistor 103 whose gate is connected to the terminal S1 are provided. For example, regarding the gate of the transistor 103, there are configurations connected to the terminal S3, configurations connected to the terminal S4, configurations connected to the terminal C2, configurations connected to the terminal C3, and configurations connected to the terminal C4 (see Fig. 22(A)). In Fig. 25(B), in the circuit SR illustrated in Fig. 4, the transistor 103C corresponding to the transistor 103 whose gate is connected to the terminal S2 and the transistor 103D corresponding to the transistor 103 whose gate is connected to the terminal S1 are provided. For example, regarding the gate of the transistor 103, there are configurations connected to the terminal S3, configurations connected to the terminal S4, configurations connected to the terminal C2, configurations connected to the terminal C3, and configurations connected to the terminal C4 (see Fig. 22(A)). In Fig. 25(B), in the circuit SR illustrated in Fig. 4, the transistor 103C corresponding to the transistor 103 whose gate is connected to the terminal S2 and the transistor 103D corresponding to the transistor 103 whose gate is connected to the terminal S1 are provided. For example, regarding the gate of the transistor 103, there are configurations connected to the terminal S3, configurations connected to the terminal S4, configurations connected to the terminal C2, configurations connected to the terminal C3, and configurations connected to the terminal C4 (see Fig. 22(A)). In Fig. 25(B), in the circuit SR illustrated in Fig. 4, the transistor 103C corresponding to the transistor 103 whose gate is connected to the terminal S2 and the transistor 103D corresponding to the transistor 103 whose gate is connected to the terminal S1 are provided. For example, regarding the gate of the transistor 103, there are configurations connected to the terminal S3, configurations connected to the terminal S4, configurations connected to the terminal C2, configurations connected to the terminal C3, and configurations connected to the terminal C4 (see Fig. 22(A)). In Fig. 25(B), in the circuit SR illustrated in Fig. 4, the transistor 103C corresponding to the transistor 103 whose gate is connected to the terminal S2 and the transistor 103D corresponding to the transistor 103 whose gate is connected to the terminal S1 are provided. For example, regarding the gate of the transistor 103, there are configurations connected to the terminal S3, configurations connected to the terminal S4, configurations connected to the terminal C2, configurations connected to the terminal C3, and configurations connected to the terminal C4 (see Fig. 22(A)). In Fig. 25(B), in the circuit SR illustrated in Fig. 4, the transistor 103C corresponding to the transistor 103 whose gate is connected to the terminal S2 and the transistor 103D corresponding to the transistor 103 whose gate is connected to the terminal S1 are provided.

[0179] ​For example, regarding the gate of transistor 116, there are configurations connected to node ND1 (refer to Fig. 2 refer to 2(B)), a configuration connected to terminal C1 (refer to Fig. 23(B)), a configuration connected to terminal C2 , a configuration connected to terminal C3, a configuration connected to terminal S1 (refer to Fig. 23(A)), , a configuration connected to terminal S2, and a configuration connected to terminal O. Fig. 26(A) shows, in the circuit SR exemplified in Fig. 22 (B), transistor 116A corresponding to transistor 116 whose gate is connected to terminal S1, and transistor 11 6 corresponding to transistor 116 whose gate is connected to terminal S2 are provided.

[0180] Figs. 4, 11(A), 11(B), 12(A), 12(B), 13(A), Fig. 1 3(B), 14(A), 14(B), 15(A), 15(B), 16(A), Fig. 16(B), 17(A), 17(B), 18(A), 18(B), 19(A ), Fig. 19(B), 20(A), 20(B), 21(A), 21(B), 22 (A), Fig. 22(B), 23(A), 23(B), 24(A), 24(B), Fig 25(A), Fig. 25(B), and Fig. 26(A), etc., which are illustrated and described, or described without illustration , can be combined in whole or in part with the circuit SR of this embodiment.

[0181] For example, Fig. 26(B) shows that in Fig. 4, as in Fig. 11(A), the first terminal of transistor 103 is connected to wiring VSS1, as in Fig. 15(A), transistors 106 to transistor 109 are added, as in Fig. 18(B), the first terminal of transistor 107 is connected to wiring VSS1, and as in Fig. 18(B), the first terminal of transistor 109 is connected to the wiring VSS1 An example of a configuration connected to VSS1 is illustrated.

[0182] For example, in FIG. 27(A), in FIG. 4, as in FIG. 19(A), transistor 110 is added, and a configuration in which transistor 111 is added as in FIG. 19(B) is illustrated.

[0183] For example, in FIG. 27(B), in FIG. 4, the gate of transistor 104 is connected to terminal S1 as in FIG. 14(A), and the gate of transistor 105 is connected to terminal S2 as in FIG. 14(A), transistor 103A is provided as in FIG. 25(A), and transistor 103B is provided as in FIG. 25(A) is illustrated. In the circuit SR of the present embodiment described with reference to FIGS. 4, 11(A), 11(B), 12(A), 12(B), 13(A), 1

[0184] 3(B), 14(A), 14(B), 15(A), 15(B), 16(A), 16(B), 17(A), 17(B), 18(A), 18(B), 19(A ), 19(B), 20(A), 20(B), 21(A), 21(B), 22 (A), 22(B), 23(A), 23(B), 24(A), 24(B), 2 (A), 25(A), 25(B), 26(A), 26(B), 27(A) and 27(B ), etc., all or at least one of the plurality of transistors in the circuit SR of the present embodiment described with or without illustration may have a double-gate structure. The transistor with a double-gate structure has a first gate and a second gate. And the channel formation region or the semiconductor layer having the channel formation region of the transistor with the double-gate structure has a region sandwiched between the first gate and the second gate. The first gate is below the second gate. ​​It may be provided thereon or provided above. The first gate corresponds to the "gate" described above, and the connection destination of the first gate is the same as the connection destination of the "gate" described above. The second gate may be connected to the first gate or may be connected to a dedicated wiring. When the second gate is connected to the first gate, the mobility of the transistor increases, and the on-current of the transistor becomes large. Therefore, the W / L of the transistor can be reduced. When the second gate is connected to dedicated wiring, the electrical characteristics of the transistor can be controlled by the potential or signal of the dedicated wiring. For example, in Fig. 38(A), in Fig. 4, transistors 101 to 105 have a double-gate structure, and a configuration in which the first gate and the second gate are connected is illustrated. For example, in Fig. 38(B), in Fig. 4, transistors 101 to 105 have a double-gate structure, and a configuration in which the second gate is connected to wiring BG is illustrated. In this specification and the like, switches of various forms can be used. A switch has a function of becoming a conductive state (on state) or a non-conductive state (off state) and controlling whether to allow current to flow or not. Alternatively, a switch has a function of selecting and switching a path through which current flows. For example, it has a function of selecting and switching whether to allow current to flow through path 1 or path 2.

[0185] As an example of a switch, an electrical switch or a mechanical switch can be used.

[0186]

[0187] ​​​​​​​​​​​That is, the switch only needs to be able to control current and is not limited to a specific one. As an example of the switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology like a digital micromirror device (DMD). That switch has electrodes that can be mechanically moved, and by moving the electrodes, it operates by controlling conduction and non-conduction. When using a transistor as the switch, since the transistor operates simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited. However, when wanting to suppress the off-current, it is desirable to use a transistor with the polarity having a lower off-current. Examples of transistors with a low off-current include transistors having an LDD region or transistors having a multi-gate structure.

[0188] When using a transistor as the switch, when the potential of the source of the transistor operating as the switch operates at a value close to the potential of the low-potential side power supply (Vss, GND, 0V, etc.), it is desirable to use an N-channel type transistor as the switch. Conversely, when the potential of the source of the transistor operating as the switch operates at a value close to the potential of the high-potential side power supply (Vdd, etc.),

[0189] when using a transistor as the switch, when the potential of the source of the transistor operating as the switch operates at a value close to the potential of the high-potential side power supply (Vdd, etc.), it is desirable to use a P-channel type transistor as the switch. , when the potential of the source operates at a value close to the potential of the high-potential side power supply (such as Vdd), it is desirable to use a P-channel transistor as the switch. This is because when an N-channel transistor operates with the source at a value close to the potential of the low-potential side power supply, and when a P-channel transistor operates with the source at a value close to the potential of the high-potential side power supply, the absolute value of the voltage between the gate and the source can be increased. Therefore, as a switch, more accurate operation can be performed. Or, because the transistor is less likely to operate in source follower mode, the magnitude of the output voltage is less likely to decrease. That's why.

[0190] Note that as a switch, both an N-channel transistor and a P-channel transistor can be used to form a CMOS-type switch. When using a CMOS-type switch, when either the P-channel transistor or the N-channel transistor conducts, current flows, making it easier to function as a switch. Therefore, whether the voltage of the input signal to the switch is high or low, the voltage can be appropriately output. Or, since the voltage amplitude value of the signal for turning the switch on or off can be reduced, the power consumption can be reduced.

[0191] Note that when using a transistor as a switch, the switch may have an input terminal (either the source or one of the drains), an output terminal (the other of the source or drain), and a terminal for controlling conduction (the gate). On the other hand, when using a diode as a switch, the switch may not have a terminal for controlling conduction. Therefore, a transistor It is possible to reduce the wiring for controlling the terminals by using a diode as a switch rather than doing so.

[0192] For example, in this specification and the like, transistors with various structures can be used as transistors. Therefore, there is no limitation on the type of transistor to be used. As an example of a transistor, a transistor having single-crystalline silicon, or a transistor having a non-single-crystalline semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. Alternatively, a thin-film transistor (TFT) obtained by thinning these semiconductors can be used. When using a TFT, there are various advantages. For example, since it can be manufactured at a temperature lower than that in the case of single-crystalline silicon, it is possible to reduce the manufacturing cost or reduce the size of the manufacturing apparatus. Since the manufacturing apparatus can be made larger, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured simultaneously, it can be manufactured at low cost. Alternatively, since the manufacturing temperature is low, a substrate with poor heat resistance can be used. Therefore, a transistor can be manufactured on a substrate having light transmittance. Alternatively, the transmission of light in a display element can be controlled using a transistor on a substrate having light transmittance. Alternatively, since the film

[0193] thickness of the transistor is thin, a part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved. As a result, a gate driver circuit (scanning line driving circuit), a source driver circuit (signal line driving circuit) , and a signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on a substrate .

[0194] Note that when manufacturing microcrystalline silicon, by using a catalyst (such as nickel), the crystallinity can be further improved, and it becomes possible to manufacture transistors with good electrical characteristics. In this case, it is also possible to improve the crystallinity only by applying heat treatment without performing laser irradiation . As a result, a part of the source driver circuit (such as an analog switch) and a gate driver circuit (scanning line driving circuit) can be integrally formed on a substrate. Note that when laser irradiation is not performed for crystallization, unevenness in the crystallinity of silicon can be suppressed . Therefore, an image with improved image quality can be displayed. However, it is possible to manufacture polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel) . Note that although it is desirable to improve the crystallinity of silicon to polycrystalline or microcrystalline, etc. throughout the entire panel, it is not limited thereto. The crystallinity of silicon may be improved only in a part of the region of the panel. Selectively improving the crystallinity is possible by selectively irradiating laser light, etc. For example, laser light may be irradiated only to the peripheral circuit region which is a region other than the pixels, only to the regions such as the gate driver circuit and the source driver circuit, or only to the region of a part of the source driver circuit (for example, an analog switch) . As a result, crystallization of silicon is improved only in the regions where it is necessary to operate the circuit at high speed

[0195] ​​​​​​​​It can be made to do so. Since the pixel region does not need to operate at high speed, even if the crystallinity is not improved, the pixel circuit can operate without problems. By doing so, since the area for improving the crystallinity can be reduced, the manufacturing process can also be shortened. Therefore, the throughput is improved and the manufacturing cost can be reduced. Or, since the number of manufacturing apparatuses required can also be reduced to a small number, the manufacturing cost can be reduced. As an example of a transistor, a transistor having a compound semiconductor (for example, SiGe, GaAs, etc.) or an oxide semiconductor (for example, Zn - O, In - Ga - Zn - O, In - Zn - O, In - Sn - O (ITO), Sn - O, Ti - O, Al - Zn - Sn - O (AZTO), In

[0196] - Sn - Zn - O, etc.) can be used. Or, a thin - film transistor in which these compound semiconductors or these oxide semiconductors are thinned can be used. By these, the manufacturing temperature can be lowered, so that, for example, it becomes possible to manufacture a transistor at room temperature. As a result, it becomes possible to directly form a transistor on a substrate with low heat resistance, such as a plastic substrate or a film substrate. In addition, these compound semiconductors or oxide semiconductors can be used not only for the channel portion of the transistor but also for other applications. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistance elements, pixel electrodes, or electrodes having translucency. Since it is possible to form them simultaneously with the transistor by film formation or formation, the cost can be reduced. As an example of a transistor, a transistor formed using an ink - jet method or a printing method can be used. Moreover, since the pixel region does not need to operate at high speed, even if the crystallinity is not improved, the pixel circuit can operate without problems. By doing so, since the area for improving the crystallinity can be reduced, the manufacturing process can also be shortened. Therefore, the throughput is improved and the manufacturing cost can be reduced. Or, since the number of manufacturing apparatuses required can also be reduced to a small number, the manufacturing cost can be reduced. As an example of a transistor, a transistor having a compound semiconductor (for example, SiGe, GaAs, etc.) or an oxide semiconductor (for example, Zn - O, In - Ga - Zn - O, In - Zn - O, In - Sn - O (ITO), Sn - O, Ti - O, Al - Zn - Sn - O (AZTO), In - Sn - Zn - O, etc.) can be used. Or, a thin - film transistor in which these compound semiconductors or these oxide semiconductors are thinned can be used.

[0197] By these, the manufacturing temperature can be lowered, so that, for example, it becomes possible to manufacture a transistor at room temperature. As a result, it becomes possible to directly form a transistor on a substrate with low heat resistance, such as a plastic substrate A transistor or the like can be used. By these means, it can be manufactured at room temperature, at a low vacuum level, or manufactured on a large substrate. Therefore, it becomes possible to manufacture without using a mask (reticle), so that the layout of the transistor can be easily changed. Also, since it can be manufactured without using a resist, the material cost can be reduced and the number of processes can be reduced. Or, since it is possible to apply a film only to the necessary parts, it is possible to avoid wasting materials compared to the manufacturing method of etching after forming a film over the entire surface, and the cost can be

[0198] lowered. As an example of a transistor, a transistor having an organic semiconductor or a carbon nanotube or the like can be used. By these means, a transistor can be formed on a substrate that can be bent. A device using a transistor having an organic semiconductor or a carbon nanotube can be made resistant to shock.

[0199] In addition, as the transistor, various other-structured transistors can also be used. For example, as the transistor, a MOS transistor, a junction transistor, a bipolar transistor, etc. can be used. By using a MOS transistor as the transistor, the size of the transistor can be reduced. Therefore, a large number of transistors can be mounted. By using a bipolar transistor as the transistor, a large current can be passed. Therefore, the circuit can be operated at high speed. Note that a MOS transistor and a bipolar transistor may be mixed and formed on one substrate. Thereby, low power consumption, miniaturization, high-speed operation, etc. can be realized.

[0200] For example, in this specification and the like, as an example of a transistor, a transistor having a multi-gate structure with two or more gate electrodes can be used. When a multi-gate structure is adopted, since the channel regions are connected in series, a structure in which a plurality of transistors are connected in series is formed. Therefore, with the multi-gate structure, reduction of the off-current and improvement of the breakdown voltage (improvement of reliability) of the transistor can be achieved. Alternatively, with the multi-gate structure, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and a voltage-current characteristic with a flat slope can be obtained. By utilizing the voltage-current characteristic with a flat slope, an ideal current source circuit or an active load having a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0201] In addition, as an example of a transistor, a transistor having a structure in which gate electrodes are arranged above and below the channel can be applied. By arranging gate electrodes above and below the channel, a circuit configuration is formed in which a plurality of transistors are connected in parallel. Therefore, since the channel region increases, an increase in the current value can be achieved. Alternatively, by arranging gate electrodes above and below the channel, depletion layers are likely to be formed, so that the S value can be improved.

[0202] In addition, as an example of a transistor, a structure in which a gate electrode is arranged above the channel region, a structure in which a gate electrode is arranged below the channel region, a positive stagger structure, and a reverse stagger structure , a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a transistor such as a structure in which the channel regions are connected in series can be used. Alternatively, as the transistor, a planar type, FIN type (fin type), TRI-GATE type (tri-gate type), top gate type, bottom gate type, double gate type (with gates arranged above and below the channel), etc., can take various configurations.

[0203] Note that as an example of the transistor, a transistor having a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof) can be used. By forming a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof), it is possible to prevent the operation from becoming unstable due to the accumulation of charges in a part of the channel region.

[0204] Note that as an example of the transistor, a structure provided with an LDD region can be applied. By providing the LDD region, it is possible to reduce the off-current or improve the breakdown voltage (improve the reliability) of the transistor. Alternatively, by providing the LDD region, when operating in the saturation region, even if the voltage between the drain and the source changes, the drain current does not change much, and a flat voltage-current characteristic can be obtained. voltage-current characteristic can be obtained.

[0205] For example, in this specification and the like, transistors can be formed using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil can be used. Substrates include silicon wafers, tungsten substrates, substrates with tungsten foils, flexible substrates, bonded films, papers containing fibrous materials, or base films. An example of a glass substrate includes barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, bonded films, base films, etc. include the following. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Or, as an example, there are synthetic resins such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Or, as an example, there are polyamides, polyimides, aramids, epoxies, inorganic vapor-deposited films, or papers. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, etc., variations in characteristics, size, or shape are small, a transistor with high current capacity and small size can be manufactured. When a circuit is configured with such a transistor, low power consumption or high integration of the circuit can be achieved. Also, as the substrate, a flexible substrate can be used, and a transistor can be directly formed on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer is used to separate from the substrate after partially or fully completing a semiconductor device thereon and transfer it to another substrate. At that time, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the above-mentioned release layer includes, for example, an inorganic film of a tungsten film and a silicon oxide film.

[0206] Also, as the substrate, a flexible substrate can be used, and a transistor can be directly formed on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer is used to separate from the substrate after partially or fully completing a semiconductor device thereon and transfer it to another substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer is used to separate from the substrate after partially or fully completing a semiconductor device thereon and transfer it to another substrate. The release layer can be used to separate from the substrate after partially or fully completing a semiconductor device thereon and transfer it to another substrate. When doing so, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the above-mentioned release layer includes, for example, an inorganic film of a tungsten film and a silicon oxide film. ​​​​​​​​​Configurations of the stacked structure, configurations in which an organic resin film such as polyimide is formed on a substrate, etc. can be used. This is possible.

[0207] That is, a transistor can be formed using a certain substrate, and then the transistor can be transferred to another substrate and arranged on the other substrate. As an example of the substrate to which the transistor is transferred, in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is difficult to break, impart heat resistance, reduce weight, or make it thinner.

[0208] Note that all of the circuits necessary to realize a predetermined function can be formed on the same substrate (for example, a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, etc.). In this way, it is possible to reduce costs by reducing the number of parts, or improve reliability by reducing the number of connection points with circuit components.

[0209] Note that it is also possible not to form all of the circuits necessary to realize a predetermined function on the same substrate. That is, a part of the circuits necessary to realize a predetermined function can be formed on a certain substrate, and another part of the circuits necessary to realize a predetermined function can be formed on another substrate. For example, a part of the circuits necessary to realize a predetermined function is formed on a glass ​​​​​​​​​​​​​​ Another part of the circuit formed on the substrate and necessary to achieve a predetermined function is formed on a single crystal substrate (or SOI substrate). And, a single crystal substrate (also referred to as an IC chip) on which another part of the circuit necessary to achieve a predetermined function is formed is connected to the glass substrate by COG( Chip On Glass), and the IC chip can be arranged on the glass substrate. Or, the IC chip can be connected to the glass substrate using TAB (Tape Aut omated Bonding), COF (Chip On Film), SMT (Su rface Mount Technology), or a printed circuit board, etc. Thus, by forming a part of the circuit on the same substrate as the pixel portion, cost reduction due to reduction in the number of components or improvement in reliability due to reduction in the number of connection points with circuit components can be achieved. In particular, circuits in parts where the driving voltage is large or circuits in parts where the driving frequency is high often consume a large amount of power. Therefore, such a circuit is formed on a substrate different from the pixel portion (for example, a single crystal substrate) to form an IC chip p. By using this IC chip, an increase in power consumption can be prevented

[0210] For example, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source . And, there is a channel region between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow through the drain, the channel region, and the source ​​​​​​​​​​ Since it varies depending on components etc., it is difficult to limit which one is the source or the drain Therefore, the part that functions as the source and the part that functions as the drain may not be called the source or the drain. In that case, as an example, one of the source and the drain may be denoted as the first terminal, the first electrode, or the first region, and the other of the source and the drain may be denoted as the second terminal, the second electrode, or the second region

[0211] Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly in this case, as an example, one of the emitter and the collector may be denoted as the first terminal, the first electrode, or the first region, and the other of the emitter and the collector may be denoted as the second terminal, the second electrode, or the second region. Note that when a bipolar transistor is used as the transistor, it is possible to rephrase the notation of the gate as the base

[0212] For example, in this specification etc., when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and includes those other than the connection relationship shown in the figure or the text

[0213] Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.)

[0214] ​​​​​​​​​As an example of the case where X and Y are electrically connected, an element (e.g., a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y can be connected by one or more between X and Y. Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching the path through which current flows. The case where X and Y are functionally connected, an example is a circuit (e.g., a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between X and Y can be connected by one or more between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. When it is explicitly described that X and Y are connected, it means the case where X and Y are electrically connected (i.e., connected with another element or another circuit interposed between X and Y). For example, when an element (such as a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y is connected by one or more between X and Y. The switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching the path through which current flows. For example, a circuit (such as a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between X and Y can be connected by one or more between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. When it is explicitly described that X and Y are connected, it means the case where X and Y are electrically connected (i.e., connected with another element or another circuit interposed between X and Y). For example, when an element (such as a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y is connected by one or more between X and Y. The switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching the path through which current flows.

[0215] As an example of the case where X and Y are functionally connected, an element (e.g., a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the functional connection between X and Y can be connected by one or more between X and Y. Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching the path through which current flows. The case where X and Y are functionally connected, an example is a circuit (e.g., a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between X and Y can be connected by one or more between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. When it is explicitly described that X and Y are connected, it means the case where X and Y are electrically connected (i.e., connected with another element or another circuit interposed between X and Y). For example, when an element (such as a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y is connected by one or more between X and Y. The switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching the path through which current flows. The case where X and Y are functionally connected, an example is a circuit (e.g., a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between X and Y can be connected by one or more between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. When it is explicitly described that X and Y are connected, it means the case where X and Y are electrically connected (i.e., connected with another element or another circuit interposed between X and Y). For example, when an element (such as a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y is connected by one or more between X and Y. The switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching the path through which current flows. The case where X and Y are functionally connected, an example is a circuit (e.g., a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between X and Y can be connected by one or more between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. When it is explicitly described that X and Y are connected, it means the case where X and Y are electrically connected (i.e., connected with another element or another circuit interposed between X and Y).

[0216] When it is explicitly described that X and Y are connected, it means the case where X and Y are electrically connected (i.e., connected with another element or another circuit interposed between X and Y). That is, when X and Y are connected with another element or another circuit interposed between them. the case where), and the case where X and Y are functionally connected (i.e., where X and Y are functionally connected with another element or another circuit interposed therebetween), and the case where X and Y are directly connected (i.e., where X and Y are connected without another element or another circuit interposed therebetween) shall be included. That is, when it is explicitly described as being electrically connected, it shall be the same as when it is only explicitly described as being connected.

[0217] Note that, for example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X with (or without) Z1 interposed therebetween, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y with (or without) Z 2 interposed therebetween, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, "The source (or the first

[0218] terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." X is electrically connected to the drain of the transistor (or the second terminal, etc.) and Y in this order. It can be expressed as "". Or, "X is electrically connected to Y via the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.). X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc. ), and Y are provided in this connection order." It can be expressed like this. Similar to these examples By using the same expression method to define the connection order in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0219] Even when components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode components. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components in its scope.

[0220] Note that this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in this embodiment (even some of the content) is another described in that embodiment Content (which may be part of the content), and / or apply, combine, or replace, etc. with respect to the content (which may be part of the content) described in one or more other embodiments It is possible to perform operations such as application, combination, or replacement on the content (which may be part of the content). Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification. Moreover, the figure (which may be part of it) described in a certain embodiment can be combined with another part of that figure, another figure (which may be part of it) described in that embodiment, and / or a figure (which may be part of it) described in one or more other embodiments to form even more figures. This is the same in the following embodiments.

[0221] (Embodiment 2) In this embodiment, a display device having an apparatus according to an aspect of the present invention will be described.

[0222] The display device illustrated in FIG. 28(A) has a circuit 100 and a pixel section 130. The pixel section 13 0 is provided with N (where N is a natural number of 3 or more) wiring lines OUT and M (where M is a natural number) wiring lines SL ( also shown as wiring lines SL[1] to SL[M]). And corresponding to the N wiring lines OUT and the M wiring lines SL, pixels 131 are provided. The circuit 100 functions as a gate driver ( also referred to as a gate line driving circuit, a gate signal line driving circuit, or a scanning line driving circuit). The N wiring lines OUT function as gate lines ( also referred to as gate signal lines or scanning lines). The M wiring lines SL have a function of transmitting video signals. That is, the M wiring lines SL function as source lines (also referred to as source signal lines or signal lines). Also, the M wiring lines SL The line SL is connected to a source driver (a source line driving circuit, a source signal line driving circuit, or a signal line driving circuit). It is connected to a circuit that functions as a signal processing circuit (also called a path).

[0223] The selection or non-selection of the pixel 131 is controlled based on the potential of the wiring OUT. The selection or non-selection of pixel 131 is controlled by circuit 100. When pixel 131 is selected, A video signal is written to the pixel 131 from the line SL. The pixel 131 displays the video signal. When the pixel 131 is deselected, the pixel 131 continues to display according to the held video signal.

[0224] Next, a specific example of the configuration of the pixel 131 will be described.

[0225] The pixel 131 illustrated in FIG. 28B includes a transistor 132, a liquid crystal element 133, and a capacitor. The transistor 132 has a first terminal connected to the line SL and a second terminal The first electrode of the liquid crystal element 133 and the first electrode of the capacitor element 134 (also called a pixel electrode) The second electrode ( The common electrode (also called a common electrode) is common to all or two or more of the multiple pixels 131. That is, the conductor having a region that becomes the second electrode of the liquid crystal element 133 of the first pixel 131 is The second electrode of the liquid crystal element 133 of the second pixel 131 is provided. The second electrode of the capacitor 134 is connected to a wiring that functions as a capacitor line. The electrodes are connected to the same wiring in all or two or more of the pixels 131. The second electrode of the liquid crystal element 134 may be connected to the second electrode of the liquid crystal element 133. The switch 132 is controlled to be turned on or off by the potential of the wiring OUT. Transistor 1 When 32 is turned on, the video signal of the wiring SL is input to the pixel 131. The liquid crystal element 133 has a liquid crystal material. The alignment of the liquid crystal material is controlled by the potential difference between the first electrode of the liquid crystal element 133 and the second electrode of the liquid crystal element 13 3. The capacitor element 134 has a function of accumulating charges according to the video signal. That is, the capacitor element 134 has a function of maintaining the potential of the first electrode of the liquid crystal element 133 at a value according to the video signal.

[0226] The pixel 131 illustrated in FIG. 28(C) has a transistor 135, a transistor 136, and an EL element 137. The transistor 135 has its first terminal connected to the wiring SL, its second terminal connected to the gate of the transistor 136, and its gate connected to the wiring OUT. The tra nsistor 136 has its first terminal connected to a wiring that has a function of supplying a current flowing through the EL element 137, and its second terminal connected to the first electrode (also referred to as a pixel electrode) of the EL element 137. The second electrode (also referred to as a common electrode) of the EL element 137 is common to all or two or more of the plurality of pixels 131. That is, a conductor having a region that becomes the second electrode of the EL element 137 of the first pixel 131 has a region that becomes the second electrode of the EL element 137 of the second pixel 131. The transistor 135 is controlled to be turned on or off by the potential of the wiring OUT. When the transistor 135 is turned on, the video signal of the wiring SL is input to the pixel 131. The transistor 136 has a function of supplying a current to the EL element 137. The current supplied by the transistor 136 to the EL element 137 becomes a value according to the video signal. The EL element 137 has a function of emitting light according to the current supplied from the transistor 136.

[0227] The configuration of the pixel 131 is not limited to FIGS. 28(B) and 28(C). The pixel 131 includes a transistor having a gate connected to the wiring OUT and a first terminal connected to the wiring SL, and a display element that performs display based on a video signal input through the transistor. That's all. Alternatively, the pixel 131 may include a transistor having a gate connected to the wiring OUT and a first terminal connected to the wiring SL, and a pixel electrode to which a potential or current based on a video signal input through the transistor is supplied. Alternatively, the pixel 131 may include a transistor having a gate connected to the wiring OUT and a first terminal connected to the wiring SL, and a transistor that supplies a current based on a video signal input through the transistor to the display element or the pixel electrode. That's all.

[0228] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. That's all.

[0229] (Embodiment 3) In this embodiment, a configuration example of the transistor will be described with reference to the drawings. The transistor described in this embodiment can be adopted for the transistors 101 to 116 described in Embodiment 1, the transistor 132, the transistor 135, and the transistor 136 described in Embodiment 2. That's all.

[0230] <Configuration Example of Transistor> FIG. 29(A) shows a schematic top view of the transistor 600 exemplified below. Also, FIG. 29( B) shows a schematic cross-sectional view of the transistor 600 along the cutting line A-B shown in Fig. 29(A). The transistor 600 illustrated in Figs. 29(A) and (B) is a bottom-gate type transistor .

[0231] The transistor 600 includes a gate electrode 602 provided on a substrate 601, an insulating layer 603 provided on the substrate 601 and on the gate electrode 602, an oxide semiconductor layer 604 provided so as to overlap the gate electrode 602, and a pair of electrodes 605a and 605b in contact with the upper surface of the oxide semiconductor layer 604 . Further, an insulating layer 606 covering the insulating layer 603, the oxide semiconductor layer 604 , and the pair of electrodes 605a and 605b, and an insulating layer 607 is provided on the insulating layer 606 .

[0232] There are no major restrictions on the material of the substrate 601, etc., but at least a material having heat resistance sufficient to withstand subsequent heat treatment is used . For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate , a YSZ (yttria-stabilized zirconia) substrate, etc. may be used as the substrate 601 . Also, a single-crystalline semiconductor substrate having silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate having silicon germanium , an SOI substrate, etc. can also be applied . Also, those with semiconductor elements provided on these substrates may be used as the substrate 601 .

[0233] Further, as the substrate 601, a flexible substrate such as plastic may be used, and the transistor 600 may be directly formed on the flexible substrate . Alternatively, a release layer may be provided between the substrate 601 and the transistor 600 . The release layer forms part or all of the transistor on its upper layer ​After that, it can be separated from the substrate 601 and used for transfer to another substrate. Therefore, the transistor 600 can be transferred to a substrate having low heat resistance or a flexible substrate.

[0234] The gate electrode 602 may be made of any of aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, etc. A metal selected from the group consisting of tin, tin, tin alloys, and tin alloys containing the above-mentioned metals. In addition, it can be formed by using an alloy of manganese and zirconium. The gate electrode 602 may be a single layer. For example, a silicon-containing aluminum film may be used. Single layer structure, two-layer structure with titanium layer laminated on aluminum layer, titanium layer on titanium nitride layer a two-layer structure in which a tungsten film is laminated on a titanium nitride film; A two-layer structure in which a tungsten film is laminated on a titanium film or a tungsten nitride film, and a titanium film and A three-layer structure in which an aluminum film is laminated on a titanium film, and a titanium film is further formed on the aluminum film. In addition, titanium, tantalum, tungsten, molybdenum, chromium, , neodymium, scandium or a combination of two or more of these. A film containing fluorine may also be used.

[0235] The gate electrode 602 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. It is also possible to form a laminated structure of the above-described conductive material having translucency and the above-described metal.

[0236] Further, an In-Ga-Zn-based oxynitride semiconductor film , an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. Since these films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when an In-Ga-Zn-based oxynitride semiconductor film is used, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor layer 604, specifically 7 atomic% or more, is used.

[0237] The insulating layer 603 functions as a gate insulating film. The insulating layer 603 in contact with the lower surface of the oxide semiconductor layer 604 is preferably an oxide insulating film.

[0238] The insulating layer 603 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or a Ga-Zn-based metal oxide, and may be provided in a laminated or single-layer form.

[0239] Further, as the insulating layer 603, hafnium silicate (HfSiO x ), hafnium silicate (HfSi x O y N z ) to which nitrogen is added, hafnium aluminate to which nitrogen is added HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide can reduce the gate leakage of transistors.

[0240] A pair of electrodes 605a and 605b function as the source electrode or drain electrode of the transistor. function.

[0241] A pair of electrodes 605a and 605b can be used as a single-layer structure or a laminated structure with a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy having this as a main component. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. ckel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten can be used. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. titanium film, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. gnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. or a titanium nitride film, and an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. There are three-layer structures, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. may be used.

[0242] The insulating layer 606 is preferably made of an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. An oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition is preferably used. An oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition Some oxygen desorbs upon heating. An oxide insulating film containing more oxygen than the stoichiometric composition has an oxygen desorption amount, in terms of oxygen atoms, of 1.0×10 atoms / cm or more, preferably 3.0×10 atoms / cm 18 or more, as determined by temperature programmed desorption spectroscopy (TDS) analysis. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. 3 20 3 As the insulating layer 606, silicon oxide, silicon oxynitride, etc. can be used. In addition, the insulating layer 606 also functions as a damage mitigation film for the oxide semiconductor layer 604 when forming the insulating layer 607 formed later.

[0243]

[0244]

[0245] Also, an oxide film that permeates oxygen may be provided between the insulating layer 606 and the oxide semiconductor layer 604.

[0246] As the oxide film that permeates oxygen, silicon oxide, silicon oxynitride, etc. can be used. In this specification, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen in its composition, and a silicon nitride oxide film refers to a film having a higher nitrogen content than oxygen in its composition.

[0247] As the insulating layer 607, an insulating film having a blocking effect on oxygen, hydrogen, water, etc. can be used. By providing the insulating layer 607 on the insulating layer 606, oxygen from the oxide semiconductor layer 604 ​​​​​​​​​​It is possible to prevent diffusion to the outside and intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor layer 604. Examples of insulating films having a blocking effect on oxygen, hydrogen, water, etc. include silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc.

[0248] <Example of method for manufacturing a transistor> Subsequently, an example of a method for manufacturing the transistor 600 illustrated in FIG. 29 will be described.

[0249] First, as shown in FIG. 30(A), a gate electrode 602 is formed on a substrate 601, and an insulating layer 603 is formed on the gate electrode 602. Here, a glass substrate is used as the substrate 601.

[0250]

[0251] The method for forming the gate electrode 602 is shown below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, etc., and a resist mask is formed on the conductive film by a photolithography process using a first photomask. Next, a part of the conductive film is etched using the resist mask to form the gate electrode 602. Then, the resist mask is removed.

[0252] Note that the gate electrode 602 may be formed by an electroplating method, a printing method, an inkjet method, etc. instead of the above-described formation method.

[0253] The insulating layer 603 is formed by a sputtering method, a PECVD method, an evaporation method, etc.

[0254] As the insulating layer 603, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is used. ​​​​​​​When forming, as the source gas, a depositable gas containing silicon and an oxidizing gas are preferably used. Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silicon fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0255] Also, when forming a silicon nitride film as the insulating layer 603, it is preferable to use a two-step forming method. First, a first silicon nitride film with few defects is formed by the plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as the source gas. Next, the source gas is switched to a mixed gas of silane and nitrogen to form a second silicon nitride film with low hydrogen concentration and capable of blocking hydrogen. By such a forming method, a silicon nitride film with few defects and having hydrogen blocking property can be formed as the insulating layer 603.

[0256] Also, when forming a gallium oxide film as the insulating layer 603, it can be formed using the MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0257] Next, as shown in FIG. 30(B), an oxide semiconductor layer 604 is formed on the insulating layer 603.

[0258] The method of forming the oxide semiconductor layer 604 is shown below. First, an oxide semiconductor film is formed. Subsequently, a resist mask is formed by a photolithography process using a second photomask on the oxide semiconductor film. Next, a part of the oxide semiconductor film is etched using the resist mask. ​​​Then, etching is performed to form the oxide semiconductor layer 604. After that, the resist mask is removed.

[0259] After this, a heat treatment may be performed. When the heat treatment is performed, it is performed in an atmosphere containing oxygen. The temperature of the heat treatment is preferably, for example, 150° C. or higher and 600° C. or lower. and preferably, the heating temperature is set to 200° C. or higher and 500° C. or lower.

[0260] Next, as shown in FIG. 30(C), a pair of electrodes 605a and 605b are formed.

[0261] The method for forming the pair of electrodes 605a and 605b will be described below. First, a sputtering method is used. A conductive film is formed by a PECVD method, a vapor deposition method, etc. Next, a third photomask is applied to the conductive film. A resist mask is formed by a photolithography process using the resist mask. The conductive film is partially etched using a etch mask to form a pair of electrodes 605a and 605b. Thereafter, the resist mask is removed.

[0262] Note that as shown in FIG. 30C, when the conductive film is etched, the upper part of the oxide semiconductor layer 604 is Therefore, the oxide semiconductor layer 604 may be partially etched and thinned. When the oxide semiconductor film is formed, the thickness of the oxide semiconductor film is preferably set to be large in advance.

[0263] Next, as shown in FIG. 30D, the oxide semiconductor layer 604 and the pair of electrodes 605a and 60 An insulating layer 606 is formed on 5b, and then an insulating layer 607 is formed on the insulating layer 606.

[0264] When a silicon oxide film or a silicon oxynitride film is formed as the insulating layer 606, the source gas As the gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Typical examples of the depositable gas include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0265] For example, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is maintained at 180 °C or higher and 260 °C or lower, more preferably 200 °C or higher and 240 °C or lower. A raw material gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 100 Pa or higher and 250 Pa or lower, more preferably 1 00 Pa or higher and 200 Pa or lower. High-frequency power of 0.17 W / cm 2 or higher and 0.5 W / cm 2 or lower, more preferably 0.25 W / cm 2 or higher and 0.35 W / cm 2 or lower is supplied under the condition that a silicon oxide film or a silicon oxynitride film is formed.

[0266] As the film formation condition, by supplying high-frequency power with the above power density in the processing chamber with the above pressure, the decomposition efficiency of the raw material gas increases in the plasma, the oxygen radicals increase, and the oxidation of the raw material gas proceeds. Therefore, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is the above temperature, since the bonding force between silicon and oxygen is weak, a part of oxygen desorbs due to heating. As a result, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and in which a part of oxygen desorbs due to heating can be formed.

[0267] When an oxide insulating film is provided between the oxide semiconductor layer 604 and the insulating layer 606, in the formation step of the insulating layer 606, the oxide insulating film serves as a protective film for the oxide semiconductor layer 604. ​As a result, while reducing the damage to the oxide semiconductor layer 604, the insulating layer 606 can be formed using high-frequency power with a high power density.

[0268] For example, a substrate placed in a vacuum-exhausted processing chamber of a PECVD apparatus is held at 180°C or higher and 40 0°C or lower, more preferably 200°C or higher and 370°C or lower. A raw material gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 20 Pa or higher and 250 Pa or lower, more preferably 100 P a or higher and 250 Pa or lower. Under the condition of supplying high-frequency power to an electrode provided in the processing chamber, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film. Moreover, by setting the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, it is possible to reduce the damage to the oxide semiconductor layer 604 when forming the oxide insulating film.

[0269] As the raw material gas for the oxide insulating film, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0270] The insulating layer 607 can be formed by a sputtering method, a PECVD method, or the like.

[0271] When forming a silicon nitride film or a silicon oxynitride film as the insulating layer 607, as the raw material gas, it is preferable to use a depositable gas containing silicon, an oxidizing gas, and a gas containing nitrogen. Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc. ​​​​​​​There is nitrogen or the like. Examples of the gas containing nitrogen include nitrogen, ammonia, and the like.

[0272] Through the above steps, the transistor 600 can be formed.

[0273] <Modification example of transistor> Hereinafter, a configuration example of a transistor that is partially different from the transistor 600 will be described.

[0274] FIG. 31(A) shows a schematic cross-sectional view of a transistor 610 exemplified below. The transistor 610 is different from the transistor 600 in that the structure of the oxide semiconductor layer is different.

[0275] The oxide semiconductor layer 614 included in the transistor 610 is formed by laminating an oxide semiconductor layer 614a and an oxide semiconductor layer 614b.

[0276] Note that since the boundary between the oxide semiconductor layer 614a and the oxide semiconductor layer 614b may be unclear in some cases, in the drawings such as FIG. 31(A), these boundaries are indicated by broken lines.

[0277] The oxide semiconductor layer 614a typically uses In-Ga oxide, In-Zn oxide, In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). Also, when the oxide semiconductor layer 614a is In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 75 atomic% or more for M. For example, the oxide semiconductor layer 614a uses a material having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more.

[0278] The oxide semiconductor layer 614b contains In or Ga, and typically, it is an In-Ga oxide, I n-Zn oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce , Nd or Hf), and the energy of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor layer 614a. Typically, the difference between the energy of the lower end of the conduction band of the oxide semiconductor layer 614b and the energy of the lower end of the conduction band of the oxide semiconductor layer 614a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, which is preferable.

[0279] Also, when the oxide semiconductor layer 614b is an In-M-Zn oxide, the atomic ratio of In to M excluding Zn and O is preferably such that In is 25 atomic% or more and M is less than 75 at omic%, more preferably, In is 34 atomic% or more and M is less than 66 atom ic%.

[0280] For example, as the oxide semiconductor layer 614a, an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:1:1, In:Ga:Z n = 1:1:1.2, or In:Ga:Zn = 3:1:2 can be used. Also, as the oxide semiconductor layer 614b, an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2, 1:6:4, or 1:9:6 can be used. Note that the atomic ratio of the oxide semiconductor layer 614a and the oxide semiconductor layer 614b each includes a variation of plus or minus 20% of the above atomic ratio as an error.

[0281] The oxide semiconductor layer 614b provided in the upper layer contains Ga that functions as a stabilizer. By using an oxide with a large amount of Ga, the release of oxygen from the oxide semiconductor layer 614a and the oxide semiconductor layer 61 4b can be suppressed.

[0282] Note that the present invention is not limited to these, and those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Also, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal elements and oxygen, interatomic distance, density, etc. of the oxide semiconductor layer 614a and the oxide semiconductor layer 61 4b appropriate.

[0283] Note that in the above, as the oxide semiconductor layer 614, a configuration in which two oxide semiconductor layers are stacked is illustrated, but a configuration in which three or more oxide semiconductor layers are stacked may also be used.

[0284] FIG. 31(B) shows a schematic cross-sectional view of a transistor 620 exemplified below. The transistor 620 is different from the transistor 600 and the transistor 6 10 in that the configuration of the oxide semiconductor layer is different.

[0285] The oxide semiconductor layer 624 included in the transistor 620 is configured by stacking an oxide semiconductor layer 624a, an oxide semiconductor layer 624b, and an oxide semiconductor layer 624c in this order.

[0286] The oxide semiconductor layer 624a and the oxide semiconductor layer 624b are stacked on the insulating layer 603. The oxide semiconductor layer 624c is provided in contact with the upper surface of the oxide semiconductor layer 624b, and the upper surfaces and side surfaces of the pair of electrodes 605a and 605b.

[0287] For example, as the oxide semiconductor layer 624b, the oxide semiconductor layer 614 exemplified in the above Modification 1 can be used. Also, for example, the oxide semiconductor layers 624a, 624c can use the same configuration as the oxide semiconductor layer 614b exemplified in the above Modification 1. This is possible.

[0288] For example, for the oxide semiconductor layer 624a provided under the oxide semiconductor layer 624b and the oxide semiconductor layer 624c provided above it, by using an oxide with a high Ga content that functions as a stabilizer, the release of oxygen from the oxide semiconductor layer 624a, the oxide semiconductor layer 624b, and the oxide semiconductor layer 624c can be suppressed.

[0289] Also, for example, when a channel is mainly formed in the oxide semiconductor layer 624b, by using an oxide with a high In content for the oxide semiconductor layer 624b and providing a pair of electrodes 605a, 605b in contact with the oxide semiconductor layer 624b, the on-current of the transistor 620 can be increased. This is possible.

[0290] <Another configuration example of the transistor> Hereinafter, a configuration example of a top-gate type transistor to which the oxide semiconductor film of one aspect of the present invention can be applied will be described.

[0291] Note that hereinafter, for components having the same configuration or the same function as the above, the same reference numerals are given, and duplicate explanations are omitted.

[0292] Fig. 32(A) shows a schematic cross-sectional view of a top-gate type transistor 650 exemplified below.

[0293] The transistor 650 is an oxide semiconductor provided on a substrate 601 on which an insulating layer 651 is provided. a pair of electrodes 605a and 605b in contact with an upper surface of the oxide semiconductor layer 604; an insulating layer 603 provided over an oxide semiconductor layer 604 and a pair of electrodes 605 a and 605 b; A gate electrode 602 is provided over the insulating layer 603 so as to overlap with the oxide semiconductor layer 604. In addition, an insulating layer 652 is provided to cover the insulating layer 603 and the gate electrode 602. do.

[0294] The insulating layer 651 has a function of suppressing diffusion of impurities from the substrate 601 to the oxide semiconductor layer 604. For example, the insulating layer 607 may have the same structure as the insulating layer 607. 651 does not have to be provided if it is not necessary.

[0295] The insulating layer 652 has a blocking effect against oxygen, hydrogen, water, etc., similar to the insulating layer 607. Note that the insulating layer 607 is not required if it is not necessary. stomach.

[0296] An example of the structure of a transistor that is partially different from the transistor 650 will be described below.

[0297] FIG. 32B is a schematic cross-sectional view of a transistor 660, which is described below. The transistor 660 differs from the transistor 650 in the structure of the oxide semiconductor layer.

[0298] The oxide semiconductor layer 664 in the transistor 660 includes an oxide semiconductor layer 664a, an oxide The semiconductor layer 664b and the oxide semiconductor layer 664c are stacked in this order.

[0299] Among the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide semiconductor layer 664c, It is possible to apply the oxide semiconductor film described above to any one, any two, or all of them. It can be done.

[0300] For example, as the oxide semiconductor layer 664b, the same configuration as the oxide semiconductor layer 614a exemplified in the above Modification 1 can be used. Also, for example, as the oxide semiconductor layers 664a and 664c, the same configuration as the oxide semiconductor layer 614b exemplified in the above Modification 1 can be used. Also, for example, as the oxide semiconductor layers 664a and 664c, the same configuration as the oxide semiconductor layer 614b exemplified in the above Modification 1 can be used. It can be done. It can be done.

[0301] Also, by using an oxide with a high Ga content that functions as a stabilizer for the oxide semiconductor layer 664a provided under the oxide semiconductor layer 664b and the oxide semiconductor layer 664c provided above, the release of oxygen from the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide semiconductor layer 664c can be suppressed. Also, by using an oxide with a high Ga content that functions as a stabilizer for the oxide semiconductor layer 664a provided under the oxide semiconductor layer 664b and the oxide semiconductor layer 664c provided above, the release of oxygen from the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide semiconductor layer 664c can be suppressed. Also, by using an oxide with a high Ga content that functions as a stabilizer for the oxide semiconductor layer 664a provided under the oxide semiconductor layer 664b and the oxide semiconductor layer 664c provided above, the release of oxygen from the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide semiconductor layer 664c can be suppressed. It can be suppressed.

[0302] Hereinafter, a configuration example of a transistor that is partially different from the transistor 650 will be described.

[0303] FIG. 32(C) shows a schematic cross-sectional view of a transistor 670 exemplified below. The transistor 670 is different from the transistor 650 in the shapes of a pair of electrodes 605a and 605b in contact with the oxide semiconductor layer 604 and the shape of the gate electrode 602. The transistor 670 is different from the transistor 650 in the shapes of a pair of electrodes 605a and 605b in contact with the oxide semiconductor layer 604 and the shape of the gate electrode 602. The transistor 670 is different from the transistor 650 in the shapes of a pair of electrodes 605a and 605b in contact with the oxide semiconductor layer 604 and the shape of the gate electrode 602.

[0304] The transistor 670 includes an oxide semiconductor layer 604 provided on a substrate 601 provided with an insulating layer 651, an insulating layer 603 on the oxide semiconductor layer 604, a gate electrode 602 on the insulating layer 603, an insulating layer 654 on the insulating layer 651 and the oxide semiconductor layer 604, an insulating layer 656 on the insulating layer 654, and an oxide semiconductor layer 6 through openings provided in the insulating layers 654 and 656. The transistor 670 includes an oxide semiconductor layer 604 provided on a substrate 601 provided with an insulating layer 651, an insulating layer 603 on the oxide semiconductor layer 604, a gate electrode 602 on the insulating layer 603, an insulating layer 654 on the insulating layer 651 and the oxide semiconductor layer 604, an insulating layer 656 on the insulating layer 654, and an oxide semiconductor layer 6 through openings provided in the insulating layers 654 and 656. The transistor 670 includes an oxide semiconductor layer 604 provided on a substrate 601 provided with an insulating layer 651, an insulating layer 603 on the oxide semiconductor layer 604, a gate electrode 602 on the insulating layer 603, an insulating layer 654 on the insulating layer 651 and the oxide semiconductor layer 604, an insulating layer 656 on the insulating layer 654, and an oxide semiconductor layer 6 through openings provided in the insulating layers 654 and 656. The transistor 670 includes an oxide semiconductor layer 604 provided on a substrate 601 provided with an insulating layer 651, an insulating layer 603 on the oxide semiconductor layer 604, a gate electrode 602 on the insulating layer 603, an insulating layer 654 on the insulating layer 651 and the oxide semiconductor layer 604, an insulating layer 656 on the insulating layer 654, and an oxide semiconductor layer 6 through openings provided in the insulating layers 654 and 656. A pair of electrodes 605a and 605b electrically connected to 04, an insulating layer 656, and an insulating layer 652 on the pair of electrodes 605a and 605b. It has.

[0305] The insulating layer 654 is formed of, for example, an insulating film containing hydrogen. Examples of the insulating film containing hydrogen include a silicon nitride film. The hydrogen contained in the insulating layer 654 combines with oxygen vacancies in the oxide semiconductor layer 604 to become carriers in the oxide semiconductor layer 604. Therefore, in the configuration shown in FIG. 32(C), the regions where the oxide semiconductor layer 604 and the insulating layer 654 are in contact are represented as an n-type region 604b and an n-type region 604c. Note that the region sandwiched between the n-type region 604b and the n-type region 604c becomes a channel region 604a. By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 605a and 605b can be reduced. Note that the n-type regions 604b and 604c can be formed self-alignedly when the gate electrode 602 is formed and by using the insulating layer 654 that covers the gate electrode 602. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. Thus, in the configuration shown in FIG. 32(C), the regions where the oxide semiconductor layer 604 and the insulating layer 654 are in contact are represented as an n-type region 604b and an n-type region 604c. Note that the region sandwiched between the n-type region 604b and the n-type region 604c becomes a channel region 604a. Thus, in the configuration shown in FIG. 32(C), the regions where the oxide semiconductor layer 604 and the insulating layer 654 are in contact are represented as an n-type region 604b and an n-type region 604c. Note that the region sandwiched between the n-type region 604b and the n-type region 604c becomes a channel region 604a. By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 605a and 605b can be reduced. Note that the n-type regions 604b and 604c can be formed self-alignedly when the gate electrode 602 is formed and by using the insulating layer 654 that covers the gate electrode 602. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 605a and 605b can be reduced. Note that the n-type regions 604b and 604c can be formed self-alignedly when the gate electrode 602 is formed and by using the insulating layer 654 that covers the gate electrode 602. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced.

[0306] By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 605a and 605b can be reduced. Note that the n-type regions 604b and 604c can be formed self-alignedly when the gate electrode 602 is formed and by using the insulating layer 654 that covers the gate electrode 602. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 605a and 605b can be reduced. Note that the n-type regions 604b and 604c can be formed self-alignedly when the gate electrode 602 is formed and by using the insulating layer 654 that covers the gate electrode 602. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 605a and 605b can be reduced. Note that the n-type regions 604b and 604c can be formed self-alignedly when the gate electrode 602 is formed and by using the insulating layer 654 that covers the gate electrode 602. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 605a and 605b can be reduced. Note that the n-type regions 604b and 604c can be formed self-alignedly when the gate electrode 602 is formed and by using the insulating layer 654 that covers the gate electrode 602. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced. The transistor 670 shown in FIG. 32(C) is a so-called self-aligned top-gate type transistor. By adopting a self-aligned top-gate type transistor structure, no overlap occurs between the gate electrode 602 and the pair of electrodes 605a and 605b that function as source and drain electrodes, so the parasitic capacitance generated between the electrodes can be reduced.

[0307] In addition, the insulating layer 656 included in the transistor 670 can be formed of, for example, a silicon oxynitride film or the like. It can be formed by, for example, a silicon oxynitride film or the like.

[0308] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. It can be.

[0309] (Embodiment 4) In this embodiment, an oxide semiconductor layer that can be used for the semiconductor layer of the transistor with low off-current described in the above embodiment will be described. The oxide semiconductor that can be used for the channel formation region in the semiconductor layer of the transistor will be described.

[0310] As the oxide semiconductor used for the channel formation region in the semiconductor layer of the transistor, it is preferably to contain at least indium (In) or zinc (Zn). In particular, it is preferably to contain In and Zn. In addition to those, it is preferably to have a stabilizer that strongly binds oxygen. As the stabilizer, it may have at least any one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al). That's all.

[0311] Also, as another stabilizer, it may have any one or more of lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), which are lanthanoids.

[0312] Examples of the oxide semiconductor used as the semiconductor layer of the transistor include indium oxide , tin oxide, zinc oxide, In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide , Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide substances, In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, S n-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-Zr-Zn-based oxides, In -Ti-Zn-based oxides, In-Sc-Zn-based oxides, In-Y-Zn-based oxides, In-L a-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd -Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd- Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Z n-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn -based oxides, In-Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides, In-Hf- Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides such as In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides exist.

[0313] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1, In:Ga:Zn = 3:1:2, or In :Ga:Zn = 2:1:3 and oxides in the vicinity of their compositions may be used.

[0314] When a large amount of hydrogen is contained in the oxide semiconductor film constituting the semiconductor layer, by combining with the oxide semiconductor, part of the hydrogen becomes a donor and generates electrons as carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the formation of the oxide semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen from the oxide semiconductor film. ​​、or it is preferable to remove moisture to highly purify so that impurities are not contained as much as possible.

[0315] Note that, due to the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, oxygen may decrease from the oxide semiconductor film. Therefore, in order to compensate for the oxygen deficiency increased by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, it is preferable to perform a treatment of adding oxygen to the oxide semiconductor film. In this specification etc., the case of supplying oxygen to the oxide semiconductor film may be referred to as an oxygen addition treatment, or the case of making the oxygen contained in the oxide semiconductor film more than the stoichiometric composition may be referred to as a peroxide treatment. 、due to the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, oxygen may decrease from the oxide semiconductor film. Therefore, in order to compensate for the oxygen deficiency increased by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, it is preferable to perform a treatment of adding oxygen to the oxide semiconductor film. ). In this specification etc., the case of supplying oxygen to the oxide semiconductor film may be referred to as an oxygen addition treatment, or the case of making the oxygen contained in the oxide semiconductor film more than the stoichiometric composition may be referred to as a peroxide treatment.

[0316] Thus, the oxide semiconductor film can be made into an oxide semiconductor film that is i-type (intrinsic) or substantially i-type approaching i-type infinitely by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and compensating for oxygen deficiency by oxygen addition treatment. Note that, substantially intrinsic means that carriers derived from donors are extremely few (close to zero) in the oxide semiconductor film, and the carrier density is 1×10 / cm or less, 1×10 / cm 17 or less, 1× 3 10 16 / cm 3 or less, 1× 10 15 / cm 3 or less, 1×10 14 / cm 3 or less, 1×10 13 / cm 3 or less.

[0317] Also, thus, a transistor including an i-type or substantially i-type oxide semiconductor film can achieve extremely excellent off-current characteristics. For example, for a transistor using an oxide semiconductor film, The drain current when the transistor is in the off state is 1×10 -18 A or less at room temperature (about 25°C), preferably 1×10 -21 A or less, more preferably 1×10 -24 A or less, or 1×10 A or less at 85°C, -15 preferably 1×10 -18 A or less, more preferably 1×10 - 21 A or less. Note that the off state of the transistor means a state where the gate voltage is sufficiently smaller than the threshold voltage in the case of an n-channel type transistor. Specifically, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more smaller than the threshold voltage, the transistor is in the off state. In the following, the structure of the oxide semiconductor film will be described. The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like. First, the CAAC-OS film will be described.

[0318] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction.

[0319] By a transmission electron microscope (TEM: Transmission Electron Microscope), a composite analysis image of the bright field image and the diffraction pattern of the CAAC-OS film The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0320] First, the CAAC-OS film will be described.

[0321] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction.

[0322] By a transmission electron microscope (TEM: Transmission Electron Microscope), a composite analysis image of the bright field image and the diffraction pattern of the CAAC-OS film By a transmission electron microscope (TEM: Transmission Electron Microscope), a composite analysis image of the bright field image and the diffraction pattern of the CAAC-OS film It is also called a high-resolution TEM image. By observing (), a plurality of crystal parts can be confirmed. On the other hand, even with a high-resolution TEM image, the boundary between distinct crystal parts, that is, the grain boundary (also called grain boundary undary) cannot be confirmed. Therefore, it can be said that in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is less likely to occur.

[0323] When observing a high-resolution TEM image of the cross-section of a CAAC-OS film from a direction approximately parallel to the sample surface, it can be confirmed that in the crystal part, metal atoms are arranged in layers. Each layer of metal atoms reflects the unevenness of the surface (also called the formed surface) or the upper surface of the CAAC-OS film and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0324] On the other hand, when observing a high-resolution TEM image of the plane of a CAAC-OS film from a direction approximately perpendicular to the sample surface, it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is seen in the arrangement of metal atoms between different crystal parts.

[0325] When performing structural analysis on a CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the out-of-plane method analysis of a CAAC-OS film having a crystal of InGaZnO 4 a peak may appear at a diffraction angle (2θ) near 31°. This peak is attributed to the (009) plane of the crystal of InGaZnO From this, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. 4

[0326] Note that InGaZnO4 Out-of-plane method of CAAC-OS film having the crystal In the analysis by, in addition to the peak around 2θ of 31°, a peak also appears around 2θ of 36° . The peak around 2θ of 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation . The CAAC-OS film preferably shows a peak around 2θ of 31° and does not show a peak around 2θ of 36° .

[0327] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon , silicon, and transition metal elements. In particular, elements with a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, such as silicon , disrupt the atomic arrangement of the oxide semiconductor film by taking oxygen from the oxide semiconductor film, resulting in a decrease in crystallinity . Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), and when contained inside the oxide semiconductor film, they become factors that disrupt the atomic arrangement of the oxide semiconductor film and reduce crystallinity . Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources .

[0328] Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen vacancies in the oxide semiconductor film may become carrier traps or carrier generation sources by capturing hydrogen .

[0329] A low impurity concentration and a low defect level density (few oxygen vacancies) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic Since the number of carrier generation sources is small, the carrier density can be lowered. Therefore, a transistor using the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative ( also referred to as normally-on).). In addition, an oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using the oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier traps of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0330] In addition, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0331] Next, the microcrystalline oxide semiconductor film will be described.

[0332] The microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed in a high-resolution TEM image. The crystal parts included in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc -OS (nanocrystalline Oxide Semiconductor) film. Further, the nc-OS film, for example, in a high-resolution TEM image, clearly shows grain boundaries. ​​​​​​​​There may be cases where it cannot be recognized.

[0333] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystalline parts. Therefore, no orientation is observed in the whole film. Thus, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystalline part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, for the nc-OS film, electron diffraction (also referred to as restricted-view electron diffraction) using an electron beam with a probe diameter larger than that of the crystalline part (for example, 50 nm or more) is performed, and a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on the nc-OS film using an electron beam with a probe diameter close to or smaller than that of the crystalline part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film, regions with high luminance may be observed in a circular (ring-shaped) manner. Also, when performing nano-beam electron diffraction on the nc-OS film, a plurality of spots may be observed within the ring-shaped region. There may be cases where spots are observed.

[0334] The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, the nc-OS film has no regularity in the crystal orientation between different crystalline parts. Therefore, the nc-O S film has a higher density of defect levels than the CAAC-OS film.

[0335] Next, the amorphous oxide semiconductor film will be described.

[0336] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and which has no crystalline part. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0337] In the high-resolution TEM image, no crystalline part can be confirmed for the amorphous oxide semiconductor film.

[0338] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

[0339] Note that the oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (amorphous-like OS: amorphous-like Oxide Semiconductor) film.

[0340] In the high-resolution TEM image of the amorphous-like OS film, voids (also called voids) may be observed. Further, in the high-resolution TEM image, there are regions where a crystalline part can be clearly confirmed and regions where a crystalline part cannot be confirmed. The amorphous-like OS film is crystallized by a very small amount of electron irradiation to the extent observable by TEM. ​​​Crystallization may occur, and growth of the crystalline portion may be observed. On the other hand, in the case of a high-quality nc-OS film , crystallization due to a small amount of electron irradiation to the extent observable by TEM is hardly seen.

[0341] In addition, the measurement of the size of the crystalline portion of the amorphous-like OS film and the nc-OS film can be performed using a high-resolution TEM image. For example, the crystal of InGaZnO 4 has a layered structure and has two Ga-Zn-O layers between the In-O layers. The crystal of InGaZnO has a layered structure with three In-O layers and six Ga-Zn-O layers, a total of nine 4 layers overlapping in the c-axis direction. Therefore, the distance between these adjacent layers is , about the same as the lattice plane spacing of the (009) plane (also referred to as the d value). From crystal structure analysis, the value is determined to be 0.29 nm. Therefore, paying attention to the lattice fringes in the high-resolution TEM image , at locations where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less, the respective lattice fringes correspond to the a-b plane of the crystal of InGaZnO . 4

[0342] In addition, the oxide semiconductor film may be a laminated film having two or more of, for example, an amorphous oxide semiconductor film, an amorphous-like e OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0343] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular " means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Thus , the case of 85° or more and 95° or less is also included.

[0344] In the present specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system. 。

[0345] Note that the configurations and methods shown in this embodiment, such as the configurations and methods shown in other embodiments can be used in appropriate combination.

[0346] (Embodiment 5) In this embodiment, an example of the display module will be described below with reference to FIGS. 33 and 34. 。

[0347] FIG. 33 is a top view showing an example of the display module. The display module 700 shown in FIG. 33 includes a pixel portion 702 provided on a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided on the first substrate 701, a sealing material 712 disposed so as to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealing material 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in FIG. 33, a display element is provided between the first substrate 701 and the second substrate 705. Further, the display module 700 is surrounded by the sealing material 712 on the first substrate 701 in a region different from the region surrounded by the sealing material 712, the pixel portion 702, the source driver circuit portion 704, and the gate driver

[0348] circuit portion 706. ​An FPC terminal section 708 (FPC: Flexible printed circuit) that is electrically connected to the driver circuit section 706 is provided. Also, an FPC 716 is connected to the FPC terminal section 708, and various signals and the like are supplied to the pixel section 702, the source driver circuit section 7 04, and the gate driver circuit section 706 through the FPC 716. Also, various signals and the like supplied through the FPC 716 are given to the pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, and the FPC terminal section 708 via signal lines 710. Moreover, a plurality of gate driver circuit sections 706 may be provided in the display module 700. Also, as the display module 700, an example is shown in which the source driver circuit section 704 and the gate driver circuit

[0349] section 706 are formed on the same first substrate 701 as the pixel section 702, but the configuration is not limited to this. For example, only the gate driver circuit section 706 may be formed on the first substrate 701, or only the source driver circuit section 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit or a gate driver circuit or the like is formed (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 70 1. Note that the connection method of the separately formed driving circuit substrate is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

[0350] ​​​​​​In addition, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display module 700 each have a plurality of transistors. As the plurality of transistors, the transistors described in the previous embodiments can be applied.

[0351] In addition, the display module 700 can have various elements. As an example of the elements, there are a liquid crystal element, an EL (electroluminescence) element (including an organic and inorganic EL element, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.), a transistor (a transistor that emits light according to current), an electron emission element, electron ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using MEMS (micro-electro-mechanical system), a digital micromirror device (DMD), a DMS (digital micro shutter), an IMOD (interference modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electro-wetting element, a piezoelectric ceramic display, a display element using carbon nanotubes, and at least one of these. In addition to these, it may have a display medium whose contrast, brightness, reflectance, transmittance, etc. change due to an electrical or magnetic action. As an example of a display device using an EL element, there is an EL display. As an example of a display device using an electron emission element, there is a field emission display (FED) or a surface-conduction electron-emitter display (SED). -emitter Display), etc. As an example of a display device using a liquid crystal element There are liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using electronic ink or electrophoretic elements, there is electronic paper, etc. Note that when realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may be made to have the function of a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, etc. Furthermore, in that case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode . Thereby, further power consumption can be reduced. Note that in this embodiment, a configuration using a liquid crystal element as a display element will be described below.

[0352] Note that the display method in the display module 700 can use a progressive method, an interlace method, etc. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels of an R pixel, a G pixel, a B pixel, and a W (white) pixel. Or, like a pentile arrangement, one color element is configured with two of RGB, and different two colors are selected and configured by the color elements. Or one or more colors such as yellow, cyan, and magenta may be added to RGB. Note that the size of the display area may be different for each dot of the color elements. However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device.

[0353] In addition, in order to cause a display device to perform full-color display using white light (W ) from a backlight (such as an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp), a coloring layer (also referred to as a color filter. ) may be used. The coloring layer can be appropriately combined and used, for example, with red (R), green (G), blue (B), yellow (Y), etc. By using the coloring layer, the color reproducibility can be made higher than in the case where no coloring layer is used. At this time, by arranging a region having a coloring layer and a region not having a coloring layer, the white light in the region not having a coloring layer may be directly used for display. By arranging a region that does not have a coloring layer in part, the decrease in luminance due to the coloring layer can be reduced during bright display, and the power consumption may be reduced by about 20% to 30%. However, when performing full-color display using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be caused to emit light from elements having their respective emission colors. By using a self-luminous element, the power consumption may be further reduced in some cases compared to the case where a coloring layer is used. Note that in this embodiment , a configuration in which no backlight or the like is provided, that is, a so-called reflective liquid crystal display module, will be described below. emission colors. By using a self-luminous element, the power consumption may be further reduced in some cases compared to the case where a coloring layer is used. Note that in this embodiment emission colors. By using a self-luminous element, the power consumption may be further reduced in some cases compared to the case where a coloring layer is used. Note that in this embodiment emission colors. By using a self-luminous element, the power consumption may be further reduced in some cases compared to the case where a coloring layer is used. Note that in this embodiment , a configuration in which no backlight or the like is provided, that is, a so-called reflective liquid crystal display module, will be described below.

[0354] A cross-sectional view taken along the dashed-dotted line Q-R shown in FIG. 33 is shown in FIG. 34. Details of the display module shown in FIG. 34 will be described below.

[0355] <Description of display module> The display module 700 shown in FIG. 34 includes a routing wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the routing wiring portion 7 11 has a signal line 710. The pixel section 702 has a transistor 750 and a capacitor element 790. The source driver circuit section 704 has a transistor 752 .

[0356] The transistor 750 and the transistor 752 can use the transistors shown above. It is possible.

[0357] The transistor used in this embodiment has a high-purity oxide semiconductor film with the formation of oxygen vacancies suppressed. The transistor can reduce the current value (off-current value) in the off state. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the writing interval can also be set long in the power-off state. Therefore, the frequency of the refresh operation can be reduced, resulting in an effect of suppressing power consumption.

[0358] In addition, since the transistor used in this embodiment can obtain a relatively high field-effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display device, the switching transistor of the pixel section and the driver transistor used in the driver circuit section can be formed on the same substrate. That is, since there is no need to use a semiconductor device formed by a silicon wafer or the like as a separate driver circuit, the number of parts of the semiconductor device can be reduced. Also, in the pixel section, by using a transistor capable of high-speed driving, a high-quality image can be provided.

[0359] The capacitor element 790 has a structure having a dielectric between a pair of electrodes. More specifically, the capacitor element As one of the electrodes of the capacitor 790, a conductive film that functions as the gate electrode of the transistor 750 is used, and as the other electrode of the capacitor element 790, a conductive film formed in the same process and functioning as the source and drain electrodes of the transistor 750 is used. Further, as the dielectric sandwiched between the pair of electrodes, an insulating film that functions as the gate insulating film of the transistor 750 is used.

[0360] Also, in FIG. 34, insulating films 764, 768, and planarization insulating film 770 are provided over the transistor 750, transistor 752, and capacitor element 790.

[0361] As the insulating film 764, for example, a silicon oxide film, a silicon oxynitride film, etc. may be formed using a PECVD apparatus. Also, as the insulating film 768, for example, a silicon nitride film etc. may be formed using a PECVD apparatus. Further, as the planarization insulating film 770, a heat-resistant organic material such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, epoxy resin, etc. can be used. Note that the planarization insulating film 770 may be formed by laminating a plurality of insulating films formed of these materials. Also, a configuration without providing the planarization insulating film 770 may be adopted.

[0362] Also, the signal line 710 is formed in the same process as the conductive film that functions as the source and drain electrodes of the transistors 750 and 752. Note that the signal line 710 may be a conductive film formed in the same process as a conductive film formed in a process different from the source and drain electrodes of the transistors 750 and 752, for example, a conductive film that functions as a gate electrode. The signal line 710 and Thus, for example, when a material containing copper elements is used, signal delays and the like due to wiring resistance are small. This enables display on a large screen.

[0363] Also, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed in the same process as the conductive film that functions as the source electrode and drain electrode of the transistors 750 and 752. Also, the connection electrode 760 is electrically connected to the terminals of the FPC 716 via the anisotropic conductive film 780.

[0364] For the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Also, as the first substrate 701 and the second substrate 705, a flexible substrate may be used. Examples of the flexible substrate include a plastic substrate.

[0365] Also, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure 778. Also, in this embodiment, a configuration in which the structure 778 is provided on the first substrate 701 side is illustrated, but the present invention is not limited to this. For example, a configuration in which the structure 778 is provided on the second substrate 705 side, or a configuration in which the structure 778 is provided on both the first substrate 701 and the second substrate 705 may be used.

[0366] On the second substrate 705 side, a light-shielding film 738 that functions as a black matrix and a color filter are provided.A coloring film 736 that functions as a light diffusing filter, a light shielding film 738, and an insulating film 734 in contact with the coloring film 736 are provided.

[0367] <Configuration example using a liquid crystal element as a display element> The display module 700 shown in FIG. 34 has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. As the liquid crystal layer 776, a liquid crystal material having a dielectric anisotropy of 2 or more and 3.8 or less, which was described above, is used. The conductive film 774 is provided on the side of the second substrate 705 and functions as a counter electrode. The display module 700 shown in FIG. 34 can display an image by controlling the transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 according to the voltage applied to the conductive film 772 and the conductive film 774.

[0368] Also, the conductive film 772 is connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element. Further, the conductive film 772 has a function as a reflective electrode. The display module 700 shown in FIG. 34 is a so-called reflective color liquid crystal display device that uses external light, reflects light with the conductive film 772, and displays it through the coloring film 736.

[0369] As the conductive film 772, a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is transparent to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film that is reflective to visible light, for example, aluminum ​ It is advisable to use a material containing aluminum or silver. In this embodiment, as the conductive film 772, a reflective conductive film is used in visible light.

[0370] Also, when a reflective conductive film in visible light is used as the conductive film 772, the conductive film may have a laminated structure. For example, an aluminum film with a thickness of 100 nm is formed on the lower layer, and a silver alloy film (for example, an alloy film containing silver, palladium, and copper) with a thickness of 30 nm is formed on the upper layer. By adopting the above structure, the following excellent effects can be achieved.

[0371] (1) The adhesion between the base film and the conductive film 772 can be improved. (2) It is possible to etch the aluminum film and the silver alloy film together with a chemical solution. (3) The cross-sectional shape of the conductive film 772 can be made into a good shape (for example, a tapered shape). The reason for (3) is that the etching rate of the aluminum film by the chemical solution is slower than that of the silver alloy film, or when the lower aluminum film is exposed after etching the upper silver alloy film, electrons are drawn from aluminum, which is a base metal, or in other words, a metal with a high ionization tendency, compared with the silver alloy film, so the etching of the silver alloy film is suppressed and the etching of the lower aluminum film proceeds faster.

[0372] Also, in the display module 700 shown in FIG. 34, unevenness is provided in a part of the planarization insulating film 77 0 of the pixel portion 702. The unevenness can be formed, for example, by forming the planarization insulating film 770 with an organic resin film or the like and providing unevenness on the surface of the organic resin film. Further, the conductive film 772 that functions as a reflective electrode is formed along the above unevenness. Therefore, external light ​​​​​​When incident on the conductive film 772, it is possible to diffusely reflect light on the surface of the conductive film 772, and the visibility can be improved. As shown in FIG. 34, by using a reflective color liquid crystal display device, it becomes possible to display without using a backlight, so that power consumption can be reduced. Note that the display module 700 shown in FIG. 34 is an example of a reflective color liquid crystal display module, but is not limited thereto. For example, by using a conductive film having light transmittance in visible light for the conductive film 772, a transmissive color liquid crystal

[0373] display module may be used. In the case of a transmissive color liquid crystal display module, the unevenness provided on the planarization insulating film 770 may not be provided. That is, it may be configured not to have it. Although not shown in FIG. 34, a configuration in which alignment films are provided on the sides of the conductive films 772 and 774 in contact with the liquid crystal layer 776 may be employed. Also, although not shown in FIG. 34, optical members (optical substrates) such as polarizing members, retardation members, and antireflection members may be appropriately provided.

[0374] For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, in the case of a transmissive display module or a transflective display module, a backlight, a side light, or the like may be provided as a light source. As the liquid crystal element, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, and the like depending on conditions.

[0375]

[0376] phases depending on conditions.

[0376] Also, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. . The blue phase is one of the liquid crystal phases. When the cholesteric liquid crystal is heated, it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range. Therefore, in order to improve the temperature range, a liquid crystal composition mixed with several weight percent or more of a chiral agent is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and is optically isotropic. Therefore, alignment treatment is not required and the viewing angle dependence is small. . Also, since an alignment film does not need to be provided, rubbing treatment is not required either. Therefore, electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and damage of the liquid crystal display device during the manufacturing process can be reduced.

[0377] Also, when using a liquid crystal element as a display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmet ric aligned Micro-cell) mode, OCB (Optical C ompensated Birefringence) mode, FLC (Ferroel ectric Liquid Crystal) mode, AFLC (AntiFerro electric Liquid Crystal) mode, etc. can be used.

[0378] Also, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Examples of the vertical alignment mode include several, but For example, the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode , the ASV mode, etc. can be used.

[0379] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. It can be done.

[0380] (Embodiment 6) In this embodiment, a touch sensor ( contact detection device) is provided in the display module described in the previous embodiment, so that it can function as an input / output device (also referred to as a touch panel). The configuration will be described with reference to FIGS. 35 and 36. In the following, the description of the parts overlapping with the above embodiments may be omitted.

[0381] FIG. 35 is a projection view for explaining the configuration of the input / output device.

[0382] FIG. 35(A) is a projection view of the input / output device 800, and FIG. 35(B) is a projection view for explaining the configuration of the detection unit 820U included in the input / output device 800.

[0383]

[0384] FIG. 36 is a cross-sectional view of the input / output device 800 shown in FIG. 35(A) taken along the line Z1-Z2. <Configuration Example 1 of the Input / Output Device> The input / output device 800 described in this embodiment includes a window portion 834 that transmits visible light and a plurality of detection units 820U arranged in a matrix, a scanning line G1 electrically connected to the plurality of detection units 820U arranged in the row direction (indicated by the arrow Rx in the figure ), and a signal electrically connected to the plurality of detection units 820U arranged in the column direction (indicated by the arrow Ry in the figure ) The line DL, and the input device 850 including a first substrate 836 that supports the detection unit 820U, the scanning line G1, and the signal line DL, and the display module 801 including a plurality of pixels 802 arranged in a matrix and a second substrate 810 that supports the pixels 802 and overlaps the window portion 834 (see FIGS. 35(A) to 35(C)). have (see FIGS. 35(A) to 35(C)).

[0385] The detection unit 820U includes a detection element Ca that overlaps the window portion 834 and a detection circuit 839 that is electrically connected to the detection element Ca (see FIG. 35(B)).

[0386] The detection element Ca includes a first electrode 821 and a second electrode 822 that sandwich an insulating layer 823 and an insulating layer 823 (not shown in FIG. 35(B)) (see FIG. 35(B)).

[0387] The detection circuit 839 is supplied with a selection signal and supplies a detection signal DATA based on a change in the capacitance of the detection element Ca.

[0388] The scanning line G1 can supply a selection signal, the signal line DL can supply a detection signal DATA, and the detection circuit 839 is arranged so as to overlap the gaps between the plurality of window portions 834.

[0389] In addition, the input / output device 800 described in this embodiment includes a coloring layer between the detection unit 820U and the pixels 802 that overlap the window portion 834 of the detection unit 820U.

[0390] The input / output device 800 described in this embodiment includes an input device 850 including a plurality of detection units 820U each having a window portion 834 that transmits visible light, and a plurality of pixels 802 that overlap the window portion 834. A display module 801 including a plurality of pixels 802 and a color layer between the window portion 834 and the pixel 802. It is composed of:

[0391] In this way, the input / output device receives a detection signal based on the change in capacitance and a detection unit that supplies the detection signal. and providing position information of the sensing unit, and image information associated with the position information of the sensing unit. As a result, a novel input / output device with excellent convenience and reliability can be provided. can be provided.

[0392] The input / output device 800 is also a flexible board that receives signals from the input device 850. A flexible printed circuit board (FPC) 1 or / and a flexible printed circuit board (FPC) 2 that supplies a signal including image information to the display module 801 It may also include a flexible substrate FPC2.

[0393] In addition, a protective substrate 837 and a protective layer 837p are provided to protect the input / output device 800 by preventing scratches. Or / and the input / output device 800 is provided with an anti-reflection layer 867p that reduces the intensity of reflected external light. It is also possible to do so.

[0394] The input / output device 800 also includes a scanning line for supplying a selection signal to the scanning line of the display module 801. The driving circuit 803g, the wiring 811 for supplying signals, and the flexible substrate FPC2 are electrically The input terminal 819 is connected to the

[0395] The individual elements constituting the input / output device 800 will be described below. are not clearly separable, and one component may also be part of another. For example, the input device 850 having a colored layer at a position overlapping the multiple window portions 834 is The device 850 is also a color filter.

[0396] The input / output device 800 includes an input device 850 and a display module 801 (see Fig. 35( A)).

[0397] The input device 850 includes a first substrate 836 that supports a plurality of detection units 820U and detection units 820U. For example, a plurality of detection units 820U are arranged on the first substrate 836 in a matrix of 40 rows and 15 columns.

[0398] The window portion 834 transmits visible light.

[0399] A colored layer that transmits light of a predetermined color is provided at a position overlapping the window portion 834. For example, a colored layer CFB that transmits blue light, a colored layer CFG that transmits green light, or a colored layer CFR that transmits red light is provided (see Fig. 35(B)).

[0400] In addition to blue, green, and / or red, a colored layer that transmits white light or a colored layer that transmits yellow light, etc., can be provided with colored layers that transmit various colors of light.

[0401] A metal material, a pigment, a dye, etc. can be used for the colored layer.

[0402] A light-shielding layer BM is provided so as to surround the window portion 834. The light-shielding layer BM is less likely to transmit light than the window portion 834.

[0403] Carbon black, metal oxides, composite oxides containing solid solutions of a plurality of metal oxides, etc. can be used for the light-shielding layer BM.

[0404] A scanning line G1, a signal line DL, a wiring VPI, a wiring RES, and a wiring VRES and a detection circuit 839 are provided at a position overlapping the light-shielding layer BM.

[0405] ​​​​​​​ In addition, a light-transmissive overcoat layer covering the coloring layer and the light-shielding layer BM can be provided. It is possible.

[0406] The detection element Ca has a first electrode 821, a second electrode 822, and an insulating layer 823 between the first electrode 821 and the second electrode 822 (see FIG. 36). The first electrode 821 is formed, for example, in an island shape so as to be separated from other regions. In particular, in order for the first electrode 821 not to be recognized by the user of the input / output device 800, a layer that can be manufactured in the same process as the first electrode 821 is preferably arranged close to the first electrode 821.

[0407] More preferably, the number of window portions 834 arranged in the gap between the first electrode 821 and the layer arranged close to the first electrode 821 is reduced as much as possible. In particular, a configuration in which no window portion 834 is arranged in the gap is preferable. When an object having a dielectric constant different from that of the atmosphere approaches the first electrode 821 or the second electrode 822 of the detection element Ca placed in the atmosphere, for example, the capacitance of the detection element Ca changes. Specifically, when a finger or the like approaches the detection element Ca, the capacitance of the detection element Ca changes. Thus, it can be used as a proximity detector. The first electrode 821 and the second electrode 822 include a conductive material. For example, an inorganic conductive material, an organic conductive material, a metal, or a conductive ceramic can be used for the first electrode 821 and the second electrode 822. Specifically, as the first electrode 821 and the second electrode 822, aluminum, chromium, copper etc.

[0408] For example, when an object having a dielectric constant different from that of the atmosphere approaches the first electrode 821 or the second electrode 822 of the detection element Ca placed in the atmosphere, the capacitance of the detection element Ca changes. Specifically, when a finger or the like approaches the detection element Ca, the capacitance of the detection element Ca changes. Thus, it can be used as a proximity detector. When an object having a dielectric constant different from that of the atmosphere approaches the first electrode 821 or the second electrode 822 of the detection element Ca placed in the atmosphere, the capacitance of the detection element Ca changes. Specifically, when a finger or the like approaches the detection element Ca, the capacitance of the detection element Ca changes. Thus, it can be used as a proximity detector. When an object having a dielectric constant different from that of the atmosphere approaches the first electrode 821 or the second electrode 822 of the detection element Ca placed in the atmosphere, the capacitance of the detection element Ca changes. Specifically, when a finger or the like approaches the detection element Ca, the capacitance of the detection element Ca changes. Thus, it can be used as a proximity detector. When an object having a dielectric constant different from that of the atmosphere approaches the first electrode 821 or the second electrode 822 of the detection element Ca placed in the atmosphere, the capacitance of the detection element Ca changes. Specifically, when a finger or the like approaches the detection element Ca, the capacitance of the detection element Ca changes. Thus, it can be used as a proximity detector.

[0409] The first electrode 821 and the second electrode 822 include a conductive material.

[0410] For example, an inorganic conductive material, an organic conductive material, a metal, or a conductive ceramic can be used for the first electrode 821 and the second electrode 822. Specifically, as the first electrode 821 and the second electrode 822, aluminum, chromium, copper

[0411] Specifically, as the first electrode 821 and the second electrode 822, aluminum, chromium, copper , a metal element selected from tantalum, titanium, molybdenum, tungsten, nickel, silver or manganese, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements can be used. For example, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements can be used. For example, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements can be used.

[0412] Alternatively, as the first electrode 821 and the second electrode 822, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide added with gallium can be used. For example, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide added with gallium can be used. For example, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide added with gallium can be used.

[0413] Alternatively, as the first electrode 821 and the second electrode 822, graphene or graphite can be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. Examples of the reduction method include a method of applying heat and a method of using a reducing agent. Alternatively, as the first electrode 821 and the second electrode 822, graphene or graphite can be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. Examples of the reduction method include a method of applying heat and a method of using a reducing agent. Alternatively, as the first electrode 821 and the second electrode 822, graphene or graphite can be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. Examples of the reduction method include a method of applying heat and a method of using a reducing agent. Alternatively, as the first electrode 821 and the second electrode 822, graphene or graphite can be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape. Examples of the reduction method include a method of applying heat and a method of using a reducing agent.

[0414] Alternatively, as the first electrode 821 and the second electrode 822, a conductive polymer can be used. Alternatively, as the first electrode 821 and the second electrode 822, a conductive polymer can be used.

[0415] The detection circuit 839 includes, for example, transistors M1 to M3. The detection circuit 839 also includes wiring for supplying a power potential and a signal. For example, it includes a signal line DL, a wiring VPI, a wiring CS, a scanning line G1, a wiring RES, and a wiring VRES. The detection circuit 839 includes, for example, transistors M1 to M3. The detection circuit 839 also includes wiring for supplying a power potential and a signal. For example, it includes a signal line DL, a wiring VPI, a wiring CS, a scanning line G1, a wiring RES, and a wiring VRES. The detection circuit 839 includes, for example, transistors M1 to M3. The detection circuit 839 also includes wiring for supplying a power potential and a signal. For example, it includes a signal line DL, a wiring VPI, a wiring CS, a scanning line G1, a wiring RES, and a wiring VRES.

[0416] Note that the detection circuit 839 may be arranged in a region that does not overlap with the window portion 834.

[0417] A material having conductivity can be applied to the wiring (for example, the signal line DL, the wiring VPI, the wiring CS, the scanning line G1, the wiring RES, and the wiring VRES). For example, an inorganic conductive material or an organic conductive material can be used. A material having conductivity can be applied to the wiring (for example, the signal line DL, the wiring VPI, the wiring CS, the scanning line G1, the wiring RES, and the wiring VRES). For example, an inorganic conductive material or an organic conductive material can be used. Conductive materials, metals, or conductive ceramics can be used for the wiring. Alternatively, the same material as that used for the first electrode 821 and the second electrode 822 can be applied as the wiring.

[0418] In addition, metal materials such as aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molyb denum, iron, cobalt, copper, or palladium, and alloy materials containing the metal materials can be used for the scanning line G1, signal line DL, wiring VPI, wiring RES, and wiring VRES.

[0419] Also, the detection circuit 839 may be formed on the first substrate 836. Alternatively, the detection circuit 839 formed on another substrate may be transferred to the first substrate 836.

[0420] As the first substrate 836 and the second substrate 810, a glass substrate or a flexible material (e.g., resin, resin film, or plastic film, etc.) can be used.

[0421] More specifically, as the first substrate 836 and the second substrate 810, non-alkali glass, soda lime glass, potash glass, or crystal glass, etc. can be used. Also, as the first substrate 836, a resin film or resin plate such as polyester, polyolefin, polyamide, polyimide d, polycarbonate, or acrylic resin can be used.

[0422] As the protective substrate 837 or / and the protective layer 837p, for example, glass, polyester , polyolefin, polyamide, polyimide, polycarbonate, or acrylic resin, etc. resin film, resin plate, or laminate, etc. can be used.​​​​

[0423] As the protective layer 837p, for example, a hard coat layer or a ceramic coat layer can be used. Specifically, a layer containing a UV curable resin or aluminum oxide may be formed at a position overlapping with the second electrode 8 22.

[0424] The display module 801 includes a plurality of pixels 802 arranged in a matrix (see FIG. 35 (C)).

[0425] For example, the pixel 802 includes a sub-pixel 802B, a sub-pixel 802G, and a sub-pixel 802R, and each sub-pixel includes a display element and a pixel circuit for driving the display element.

[0426] Note that the sub-pixel 802B of the pixel 802 is arranged at a position overlapping with the color filter layer CFB, and the sub-pixel 80 2G is arranged at a position overlapping with the color filter layer CFG, and the sub-pixel 802R is arranged at a position overlapping with the color filter layer CFR.

[0427] The color filter layer CFR is located at a position overlapping with the liquid crystal element 880. Note that the liquid crystal element 880 has a reflective electrode 872 as one electrode (see FIG. 36). Thus, a part of the external light reflected by the reflective electrode 872 passes through the color filter layer CFR and is emitted in the direction of the arrow shown in the figure. As the reflective electrode 872, it can have the same configuration as the conductive film 772 that functions as the reflective electrode shown in the previous embodiment. Also, the liquid crystal element 880 has a liquid crystal layer with a dielectric anisotropy of 2 or more and 3.8 or less.

[0428] In addition, there is a light-shielding layer BM surrounding the color filter layer (for example, the color filter layer CFR).

[0429] The scanning line drive circuit 803g includes a transistor 803t and a capacitor 803c (see Fig. 36). ).

[0430] The converter CONV can use various circuits that can convert the detection signal DATA supplied by the detection unit 820U and supply it to the flexible substrate FPC1 . (See Figs. 35(A) and 36). ).

[0431] For example, the transistor M4 can be used as the converter CONV.

[0432] The display module 801 is provided with an antireflection layer 867p at a position overlapping the pixels. As the antireflection layer 867p, for example, a circular polarizing plate can be used.

[0433] As shown in Fig. 35(A), the display module 801 includes a wiring 811 capable of supplying signals, and a terminal 819 is provided on the wiring 811. Note that a flexible substrate FPC2 capable of supplying signals such as an image signal and a synchronization signal is electrically connected to the terminal 819 . .

[0434] Note that a printed wiring board (PWB) may be attached to the flexible substrate FPC2 .

[0435] The display module 801 has wirings such as scanning lines, signal lines, and power lines. Various conductive films can be used for the wirings.

[0436] Examples of the wirings included in the display module 801 include metal elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, nickel, yttrium, zirconium, silver or manganese, alloys containing the above-described metal elements as components, or the above-described ​​ An alloy or the like combining metal elements can be used. In particular, it is preferable to contain one or more elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. In particular, an alloy of copper and manganese is suitable for microfabrication using a wet etching method.

[0437] As a specific configuration of the wiring included in the display module 801, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a titanium film, and a three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed thereon can be used. Alternatively, a laminated structure in which an alloy film or a nitride film formed by combining one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium is laminated on an aluminum film can be used. Alternatively, a conductive material having translucency and containing indium oxide, tin oxide, or zinc oxide may be used.

[0438] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0439] (Embodiment 7) In this embodiment, a specific example of an electronic device manufactured using the liquid crystal display device described in the above embodiment will be described with reference to FIG. 37.

[0440] As an example of an electronic device to which the present invention is applicable, a television device (TV or television receiver) ​​​​​​​​​​​​(also called a tuner receiver), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, music players, gaming machines (such as pachinko machines and slot machines), and game cabinets. Specific examples of these electronic devices are shown in Fig. 37.

[0441] Fig. 37(A) shows a portable information terminal 1400 having a display unit. The portable information terminal 14 00 has a display unit 1402 and operation buttons 1403 incorporated in a housing 1401. The liquid crystal display device according to one aspect of the present invention can be used for the display unit 1402.

[0442] Fig. 37(B) shows a mobile phone 1410. The mobile phone 1410 has a display unit 141 2, operation buttons 1413, a speaker 1414, and a microphone 1415 incorporated in a housing 141 1. The liquid crystal display device according to one aspect of the present invention can be used for the display unit 1412. It can be used.

[0443] Fig. 37(C) shows a music player 1420. The music player 1420 has a display unit 142 2, operation buttons 1423, and an antenna 1424 incorporated in a housing 1 421. Also, information can be transmitted and received by a radio signal from the antenna 1424. The liquid crystal display device according to one aspect of the present invention can be used for the display unit 1422.

[0444] The display units 1402, 1412, and 1422 have a touch input function, and display buttons (not shown ) displayed on the display units 1402, 1412, and 1422 can be touched with a finger or the like to perform screen operations and input information.

[0445] By using the liquid crystal display device shown in the previous embodiment for the display unit 1402, the display unit 1412, and the display unit 14 22, it is possible to achieve an improvement in display quality for the display unit 1402, the display unit 1412, and the display unit 1422.

[0446] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0447] Regarding the content not defined in the drawings and text in the specification, one aspect of the invention excluding that content can be constituted. Or, for a certain value, when a numerical range indicated by an upper limit value and a lower limit value, etc. is described, by arbitrarily narrowing that range, or by excluding a point within that range, one aspect of the invention excluding a part of that range can be defined.

[0448] For example, it can be defined that the prior art does not fall within the technical scope of one aspect of the present invention.

[0448] As a specific example, assume that a circuit diagram using the first to fifth transistors is described in a certain circuit. In that case, it is possible to define as the invention that the circuit does not have a sixth transistor. Or, it is possible to define that the circuit does not have a capacitive element. Furthermore, the invention can be constituted by defining that the circuit does not have a sixth transistor having a certain specific connection structure. Or, the invention can be constituted by defining that the circuit does not have a capacitive element having a certain specific connection structure. For example, it is possible to define the invention as not having a sixth transistor whose gate is connected to the gate of the third transistor. Alternatively, for example, the invention can be defined as not having a capacitive element in which the first electrode is connected to the gate of the third transistor. and not having.

[0449] As another specific example, for a certain value, for example, it is described that "it is preferable that a certain voltage is 3V or more and 10V or less". In that case, for example, one aspect of the invention can be defined as excluding the case where a certain voltage is -2V or more and 1V or less. Alternatively, for example, one aspect of the invention can be defined as excluding the case where a certain voltage is 13V or more. It is possible. Note that, for example, the invention can also be defined such that the voltage is 5V or more and 8V or less. Note that, for example, the invention can also be defined such that the voltage is approximately 9V. Note that, for example, the invention can also be defined such that the voltage is 3V or more and 10V or less, but excluding the case where it is 9V. Note that even if it is described for a certain value that "it is preferable to be within such a range", "it is preferable to satisfy these", etc., a certain value is not limited to those descriptions. That is, even if it is described as "preferable", "suitable", etc., it is not necessarily limited to those descriptions. Another specific example is that for a certain value, for example, it is described that "it is preferable that a certain voltage is 10V". In that case, for example, one aspect of the invention can be defined as excluding the case where a certain voltage is -2V or more and 1V or less. Alternatively, for example, one aspect of the invention can be defined as excluding the case where a certain voltage is 13V or more. Another specific example is that for a property of a certain substance, for example, it is described that "a certain film is an insulating film".

[0450] it is described that "it is preferable that a certain voltage is 10V". In that case, for example, one aspect of the invention can be defined as excluding the case where a certain voltage is -2V or more and 1V or less. Alternatively, for example, one aspect of the invention can be defined as excluding the case where a certain voltage is 13V or more. Alternatively, for example, one aspect of the invention can be defined as excluding the case where a certain voltage is 13V or more. It is possible.

[0451] As another specific example, for a property of a certain substance, for example, it is described that "a certain film is an insulating film". Assume that it is described. In that case, for example, except when the insulating film is an organic insulating film , it is possible to define one aspect of the invention. Or, for example, except when the insulating film is an inorganic insulating film, it is possible to define one aspect of the invention. Or, for example, except when the film is a conductive film, it is possible to define one aspect of the invention. Also for example, except when the film is a semiconductor film, it is possible to define one aspect of the invention.

[0452] As another specific example, for a certain laminated structure, for example, assume that it is described that "a certain film is provided between film A and film B". In that case, for example, except when the film is a laminated film of four or more layers , it is possible to define the invention. Or, for example, except when a conductive film is provided between film A and that film, it is possible to define the invention.

[0453] Note that one aspect of the invention described in this specification and the like can be implemented by various people. However, the implementation may be carried out by a plurality of people. For example in the case of a transmission / reception system, company A may manufacture and sell a transmitter, and company B may manufacture and sell a receiver. As another example, in the case of a light-emitting device having a TFT and a light-emitting element, a semiconductor device on which the TFT is formed is manufactured and sold by company A. Then company B may purchase the semiconductor device and form a light-emitting element on the semiconductor device to complete it as a light-emitting device.

[0454] In such a case, for either company A or company B, an invention for which a patent infringement claim can be made ​​One aspect can be configured. That is, one aspect of the invention can be configured to be implemented only by Company A, and as another aspect of the invention, one aspect of the invention can be configured to be implemented only by Company B. Also, for Company A or Company B, one aspect of the invention for which patent infringement can be claimed is clear, and it can be determined that it is described in this specification and the like. For example, in the case of a transmission and reception system, even if the description for only the transmitter or only the receiver is not in this specification and the like, one aspect of the invention can be configured by only the transmitter, and another aspect of the invention can be configured by only the receiver. One aspect of those inventions is clear and it can be determined that it is described in this specification and the like. As another example, in the case of a light-emitting device having a TFT and a light-emitting element, even if the description for only the semiconductor device on which the TFT is formed or only the light-emitting device having a light-emitting element is not in this specification and the like, one aspect of the invention can be configured by only the semiconductor device on which the TFT is formed, and one aspect of the invention can be configured by only the light-emitting device having a light-emitting element. One aspect of those inventions is clear and it can be determined that it is described in this specification and the like.

[0455] In addition, in this specification and the like, for all terminals of active elements (such as transistors and diodes), passive elements ( such as capacitive elements and resistive elements), etc., even if the connection destination is not specified, a person skilled in the art may be able to configure one aspect of the invention. That is, it can be said that one aspect of the invention is clear even without specifying the connection destination. And when the content of the specified connection destination is described in this specification and the like, one aspect of the invention without specifying the connection destination is also described in this specification. There may be cases where it can be determined that it is described in a document or the like. In particular, when there are multiple cases to consider for the connection destination of a terminal, it is not necessary to limit the connection destination of that terminal to a specific location. Thus for some terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., by specifying their connection destinations, it may be possible to constitute an aspect of the invention.

[0456] In this specification and the like, for a certain circuit, if at least the connection destination is specified, a person skilled in the art may be able to specify the invention. Or, for a certain circuit, if at least the function is specified, a person skilled in the art may be able to specify the invention. That is, it can be said that if the function is specified, an aspect of the invention is clear. And, if an aspect of the invention for which the function is specified can be determined to be described in this specification and the like. Therefore, for a certain circuit, even if the function is not specified, if the connection destination is specified, it is disclosed as an aspect of the invention and can constitute an aspect of the invention. Or for a certain circuit, even if the connection destination is not specified, if the function is specified, it is disclosed as an aspect of the invention and can constitute an aspect of the invention.

[0457] In this specification and the like, in a figure or text described in a certain embodiment, it is possible to extract a part of it to constitute an aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by extracting a part of that figure or text is also disclosed as an aspect of the invention and constitutes an aspect of the invention. ​​​​It is assumed to be possible. And one aspect of the invention can be said to be clear. Therefore, for example, in drawings or texts that describe one or more of active elements (such as transistors and diodes), wirings, passive elements (such as capacitor elements and resistor elements), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc., it is assumed that a part thereof can be extracted to constitute one aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), M ( M is an integer and M < N) circuit elements (such as transistors and capacitor elements) can be extracted to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, M (M is an integer and M < N) layers can be extracted to constitute one aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, M (M is an integer and M < N) elements can be extracted to constitute one aspect of the invention. As yet another example, from a text that describes "A has B, C, D, E, or F", some elements can be arbitrarily extracted to obtain "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E", etc., to constitute one aspect of the invention. It is possible. Furthermore, in this specification, etc., when at least one specific example is described in the drawings or texts described in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of the specific example. Therefore, in a certain embodiment, when described in the drawings or texts, it is possible to constitute one aspect of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E". It is possible.

[0458] Note that in this specification, etc., in the drawings or texts described in a certain embodiment, when at least one specific example is described, it is easily understood by those skilled in the art to derive the upper concept of the specific example. Therefore, in a certain embodiment, when described in the drawings or texts, In the drawings or the text, when at least one specific example is described, the general concept of that specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And it can be said that one aspect of the invention is clear. Moreover, in this specification, etc., at least the content described in the drawings (which may be a part of the drawings) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, for a certain content, if it is described in the drawings, even if it is not described using the text, that content is disclosed as one aspect of the invention and can constitute one aspect of the invention. Similarly, for a drawing obtained by extracting a part of the drawing, it is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And it can be said that one aspect of the invention is clear.

[0459]

Explanation of Reference Numerals

[0460] Terminal C1 Terminal C2 Terminal C3 Terminal C4 Wiring CK1 Wiring CK2 Wiring CK3 Wiring CK4 Scanning Line G1 Transistor M1 Transistor M3 Transistor M4 Node ND1 Terminal S1 Terminal S2 Terminal S3 Terminal S4 Wiring SP1 Wiring SP2 Wiring VSS1 Wiring VSS2 Wiring VSS3 VSS4 Wiring FPC1 Flexible Substrate FPC2 Flexible Substrate SR Circuit Period A Period B Period C Period D Period E Period F Period G Period H OUT Wiring O Terminal SL Wiring DL Signal Line CS Wiring RES Wiring VPI Wiring VRES Wiring Ca Detection Element BG Wiring 100 Circuit 101 Transistor 102 Transistor 103 Transistor 103A Transistor 103B Transistor 103C Transistor 103D Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 113 Transistor 114 Transistor 115 Transistor 116 Transistor 116A Transistor 116B Transistor 130 Pixel Section 131 Pixel 132 Transistor 133 Liquid crystal element 134 Capacitive element 135 Transistor 136 Transistor 137 EL element 600 Transistor 601 Substrate 602 Gate electrode 603 Insulating layer 604 Oxide semiconductor layer 604a Channel region 604b n-type region 604c n-type region 605a Electrode 605b Electrode 606 Insulating layer 607 Insulating layer 610 Transistor 614 Oxide semiconductor layer 614a Oxide semiconductor layer 614b Oxide semiconductor layer 620 Transistor 624 Oxide semiconductor layer 624a Oxide semiconductor layer 624b Oxide semiconductor layer 624c Oxide semiconductor layer 650 Transistor 651 Insulating layer 652 Insulating layer 654 Insulating layer 656 Insulating layer 660 Transistor 664 Oxide semiconductor layer 664a Oxide semiconductor layer 664b Oxide semiconductor layer 664c Oxide semiconductor layer 670 Transistor 700 Display module 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal line 711 Wiring part 712 Sealing material 716 FPC 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistor 752 Transistor 760 Connection electrode 764 Insulating film 768 Insulating film 770 Planarization insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 790 Capacitor element 800 Input / output device 801 Display module 802 Pixel 802B Sub-pixel 802G Sub-pixel 802R Sub-pixel 803c Capacitance 803g Scanning line drive circuit 803t Transistor 810 Substrate 811 Wiring 819 Terminal 820U Detection unit 821 Electrode 822 Electrode 823 Insulating layer 834 Window part 836 Substrate 837 Protective substrate 837p Protective layer 839 Detection circuit 850 Input device 867p Anti-reflection layer 872 Reflective electrode 880 Liquid crystal element 1400 Portable information terminal 1401 Housing 1402 Display unit 1403 Operation button 1410 Mobile phone 1411 Housing 1412 Display unit 1413 Operation button 1414 Speaker 1415 Microphone 1420 Music player 1421 Housing 1422 Display unit 1423 Operation button 1424 Antenna

Claims

1. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate signal line; one of the source and the drain of the second transistor is always electrically connected to the first gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second gate signal line; a gate of the fourth transistor is always electrically connected to the second gate signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a third gate signal line; a gate of the fifth transistor is always electrically connected to the third gate signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; when the other of the source or the drain of the sixth transistor is in a conductive state with the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, a potential that turns on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, the fourth transistor has a channel width W / channel length L of 0.9 to 1.1 times the channel width W / L of the fifth transistor; At least one of the first to seventh transistors is a first conductive layer having a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; a semiconductor layer having a region located above the first insulating layer and having a channel formation region; a second conductive layer having a region on the semiconductor layer and functioning as a source electrode; a third conductive layer having a region on the semiconductor layer and functioning as a drain electrode; a second insulating layer having a region located above the semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer.

2. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate signal line; one of the source and the drain of the second transistor is always electrically connected to the first gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second gate signal line; a gate of the fourth transistor is always electrically connected to the second gate signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a third gate signal line; a gate of the fifth transistor is always electrically connected to the third gate signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; when the other of the source or the drain of the sixth transistor is in a conductive state with the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, a potential that turns on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, the fourth transistor has a channel width W / channel length L of 0.9 to 1.1 times the channel width W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the second transistor; the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; At least one of the first to seventh transistors is a first conductive layer having a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; a semiconductor layer having a region located above the first insulating layer and having a channel formation region; a second conductive layer having a region on the semiconductor layer and functioning as a source electrode; a third conductive layer having a region on the semiconductor layer and functioning as a drain electrode; a second insulating layer having a region located above the semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer.

3. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate signal line; one of the source and the drain of the second transistor is always electrically connected to the first gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second gate signal line; a gate of the fourth transistor is always electrically connected to the second gate signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a third gate signal line; a gate of the fifth transistor is always electrically connected to the third gate signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; when the other of the source or the drain of the sixth transistor is in a conductive state with the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, a potential that turns on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, the fourth transistor has a channel width W / channel length L of 0.9 to 1.1 times the channel width W / L of the fifth transistor; At least one of the first to seventh transistors is a first conductive layer having a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; a semiconductor layer having a region located above the first insulating layer and having a channel formation region; a second conductive layer having a region on the semiconductor layer and functioning as a source electrode; a third conductive layer having a region on the semiconductor layer and functioning as a drain electrode; a second insulating layer having a region located above the semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer; The semiconductor device, wherein the semiconductor layer is indium oxide.

4. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate signal line; one of the source and the drain of the second transistor is always electrically connected to the first gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second gate signal line; a gate of the fourth transistor is always electrically connected to the second gate signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a third gate signal line; a gate of the fifth transistor is always electrically connected to the third gate signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; when the other of the source or the drain of the sixth transistor is in a conductive state with the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, a potential that turns on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, the fourth transistor has a channel width W / channel length L of 0.9 to 1.1 times the channel width W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the second transistor; the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; At least one of the first to seventh transistors is a first conductive layer having a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; a semiconductor layer having a region located above the first insulating layer and having a channel formation region; a second conductive layer having a region on the semiconductor layer and functioning as a source electrode; a third conductive layer having a region on the semiconductor layer and functioning as a drain electrode; a second insulating layer having a region located above the semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer; The semiconductor device, wherein the semiconductor layer is indium oxide.

5. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate signal line; one of the source and the drain of the second transistor is always electrically connected to the first gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second gate signal line; a gate of the fourth transistor is always electrically connected to the second gate signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a third gate signal line; a gate of the fifth transistor is always electrically connected to the third gate signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; when the other of the source or the drain of the sixth transistor is in a conductive state with the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, a potential that turns on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, the fourth transistor has a channel width W / channel length L of 0.9 to 1.1 times the channel width W / L of the fifth transistor; At least one of the first to seventh transistors is a first conductive layer having a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; an oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region; a second conductive layer having a region on and in contact with the oxide semiconductor layer and functioning as a source electrode; a third conductive layer having a region which is in contact with the oxide semiconductor layer and functions as a drain electrode; a second insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer.

6. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate signal line; one of the source and the drain of the second transistor is always electrically connected to the first gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second gate signal line; a gate of the fourth transistor is always electrically connected to the second gate signal line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a third gate signal line; a gate of the fifth transistor is always electrically connected to the third gate signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; when the other of the source or the drain of the sixth transistor is in a conductive state with the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, a potential that turns on the second transistor and the third transistor is input to the gate of the second transistor and the gate of the third transistor at least via a channel formation region of the sixth transistor, the fourth transistor has a channel width W / channel length L of 0.9 to 1.1 times the channel width W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the second transistor; the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; At least one of the first to seventh transistors is a first conductive layer having a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; an oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region; a second conductive layer having a region on and in contact with the oxide semiconductor layer and functioning as a source electrode; a third conductive layer having a region which is in contact with the oxide semiconductor layer and functions as a drain electrode; a second insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer.

7. In claim 5 or claim 6, The oxide semiconductor layer is an In--Zn oxide.

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