Semiconductor device

Abstract

To provide a semiconductor device in which heat generated from a semiconductor element is effectively dissipated, which therefore can be improved in reliability.SOLUTION: A semiconductor device is provided which includes a laminate having at least one semiconductor element arranged between a first substrate and a second substrate. The semiconductor device comprises: a first conductive layer comprising a first region opposed to the second substrate, a second region opposed to the second substrate and arranged more apart from the second substrate than the first region, and a third region connecting the first region and second region to each other; and a heat-dissipative second layer arranged on the side, opposite to the second substrate side, of the first layer and laminated on the first layer in the first, second and third regions, wherein the semiconductor element has one surface connected to the first layer in the second region and also has the other surface connected to the second substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device on which a semiconductor element is mounted. In particular, the present invention relates to a semiconductor device capable of effectively guiding heat generated from a semiconductor element to the outside.

Background Art

[0002] A so-called technology of incorporating electronic components into a module, in which a circuit board on which electronic components such as semiconductor elements are mounted is laminated to three-dimensionally and densely mount a semiconductor device, is known. In particular, when modularizing semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) having a switching function, the semiconductor elements and the components of their electric circuits have a relatively large amount of heat generation. Therefore, studies are underway on how to dissipate this heat to the outside of the module. For example, in the module disclosed in Patent Document 1, an electronic component 30 such as a transistor is placed on one surface of a metal frame 22 made of copper, and a ceramic layer 14 is provided on the other surface via a solder layer 20 and a metal layer 16. Then, heat generated from the electronic component 30 can be effectively dissipated to the outside of the module through the metal frame 22 and the ceramic layer 14 having excellent heat dissipation (thermal conductivity).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Gallium oxide (α-Ga) having a corundum structure with a high bandgap2 O 3 ) or, as represented by semiconductor materials such as gallium oxide having a β-gallium structure (β-Ga 2 O 3 ), in recent years, semiconductor materials with a very large amount of heat generation have been used in semiconductor devices. Also, for example, high-performance modules with a large amount of heat generation, such as those equipped with MOSFETs and SBDs (Schottky Barrier Diodes), have been proposed. Thus, with the progress of the development of semiconductor materials and modules, the required heat dissipation performance has also become high. Even in the semiconductor device disclosed in Patent Document 1, since there is no specific disclosure about the semiconductor material and it is premised on the semiconductor element being mounted alone, there is still room for improvement in terms of structure. Therefore, an object of the present invention is to provide a semiconductor device capable of improving reliability by effectively dissipating heat generated from a semiconductor element.

Means for Solving the Problems

[0005] The inventors of the present invention have found that the semiconductor device shown below can solve the above-described conventional problems. A semiconductor device according to an embodiment of the present invention is a semiconductor device including a laminate in which at least one semiconductor element is disposed between a first substrate and a second substrate, wherein the first substrate includes a first region facing the second substrate, a second region spaced apart from the second substrate relative to the first region and facing the second substrate, and a third region connecting the first region and the second region, a first layer having conductivity; and a second layer having heat dissipation properties disposed on the opposite side of the first layer from the second substrate and laminated on the first layer in the first, second, and third regions, and the semiconductor element is characterized in that one surface thereof is connected to the first layer in the second region and the other surface is connected to the second substrate.

Effects of the Invention

[0006] According to the embodiment of the present invention configured as described above, heat generated from the semiconductor element is transmitted to the first layer through at least the second and third regions. Further, the heat transmitted to the first layer is transmitted to the second layer through at least the second and third regions. Therefore, since the heat generated by the semiconductor element can be transferred over a larger area, effective heat dissipation is performed and the reliability of the semiconductor device is improved.

Brief Description of the Drawings

[0007]

Figure 1

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, several embodiments according to the present invention will be described with reference to the drawings. The same reference numerals are given to the same components, and redundant descriptions are omitted.

[0009] FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. As shown in FIG. 1, the semiconductor device 110 includes a first substrate 1 and a second substrate, and a first semiconductor element 3 and a second semiconductor element 4 disposed between the first and second substrates 1 and 2, and has a stacked structure as a whole.

[0010] The first substrate 1 has a first layer 1a having conductivity and a second layer 1b having heat dissipation. As the first layer 1a, a material excellent in both electrical conductivity and thermal conductivity (for example, a material mainly composed of copper (Cu)) can be used. As the second layer 1b, a material excellent in thermal conductivity (for example, aluminum oxide (Al 2 O 3 ) or the like) can be used. In the embodiment of the present invention, by configuring the second layer 1b with ceramic, the second layer 1b having high thermal conductivity and high electrical insulation (low electrical conductivity) can be obtained. The thickness of the first layer 1a can be arbitrarily determined in the range of, for example, about 5 μm to 20 μm, and the thickness of the second layer 1b can be arbitrarily determined in the range of, for example, about 100 μm to 300 μm. Of course, the thickness of the first layer 1a and the thickness of the second layer 1b are not limited to the above ranges.

[0011] In an embodiment of the present invention, the first substrate 1 has a concavo-convex surface. As shown in FIG. 1, the lower surface of the first substrate 1 forms a concavo-convex surface. As schematically shown in FIG. 2, this concavo-convex surface includes a first region facing the second substrate, a second region spaced from the second substrate and facing the second substrate farther than the first region, and a third region connecting the first region and the second region. More specifically, the concavo-convex surface includes a first region including a surface in a relationship of being close to and facing the second substrate 2, a third region including a surface bent at an angle of approximately 90° with respect to this first region, and a second region including a surface bent at an angle of approximately 90° with respect to this third region and contacting the semiconductor elements 3 and 4. Further, one surface of the semiconductor elements 3 and 4 is connected to the first layer 1a in the second region, and the other surface is connected to the second substrate 2. Also, the first region has a first surface facing the second substrate, and the second region has a second surface connected to the semiconductor elements 3 and 4. The first surface and the second surface are parallel to each other and are formed so as to be spaced apart by the thickness of the semiconductor elements 3 and 4 as shown in FIG. 2. Note that the schematic diagram in FIG. 2 is an extraction of a part of the semiconductor device 110, and in the embodiment of the present invention, there are a plurality of first to third regions. Also, according to the difference in the thicknesses of the first semiconductor element 3 and the second semiconductor element 4, the separation distance between the first region and the second region is appropriately adjusted.

[0012] The second layer 1b constituting the first substrate 1 is laminated on the first layer 1a also constituting the first substrate 1 in the first, second, and third regions. Specifically, the first layer 1a and the second layer 1b are in direct surface contact with each other without a gap across the entire first to third regions. Therefore, direct heat transfer is possible between the first layer 1a and the second layer 1b across the entire first to third regions.

[0013] On one hand, the second substrate 2 has a substantially flat plate shape. The second substrate 2 faces the first region of the first substrate 1, and the first region and the second substrate are electrically and thermally connected to each other via vias 5. Similar to the first layer 1a, the second substrate 2 and the vias 5 are made of a material excellent in both electrical conductivity and thermal conductivity (for example, a material mainly composed of copper (Cu)). In the embodiment of the present invention, it is not necessary to provide vias 5 in all of the formed plurality of first regions (regions close to and facing the second substrate 2), and it is sufficient if vias 5 are provided in at least one first region (for example, only the leftmost first region in FIG. 1).

[0014] The semiconductor element 3 is, for example, a MOSFET, and the semiconductor element 4 is, for example, an SBD. Here, an example is given in which semiconductor elements 3 and 4 having different thicknesses are arranged, but they may have the same thickness. Also, even if there is only one semiconductor element, the effects of the present invention can be expected. These semiconductor elements 3 and 4 may each be an element (vertical element) having electrodes on both the upper and lower surfaces, or an element (horizontal element) having electrodes on only one of the surfaces. In the embodiment of the present invention shown in FIG. 1, both semiconductor elements 3 and 4 are vertical elements. The semiconductor element 3 made of a MOSFET has a gate electrode and a source electrode on its lower surface and a drain electrode on its upper surface. The semiconductor element 4 made of an SBD has a Schottky electrode on its lower surface and an ohmic electrode on its upper surface. Of course, even when the circuit configuration is such that the upper and lower surfaces of one or both of the semiconductor elements 3 and 4 are arranged in reverse, the effects of the present invention can be expected.

[0015] The semiconductor elements 3 and 4 shown in FIG. 1 have element bodies 3a and 4a, first electrodes 3b and 4b, and second electrodes 3c and 4c. When the first semiconductor element 3 is a MOSFET, the first electrode 3b is a gate electrode and a source electrode, and the second electrode 3c is a drain electrode. When the second semiconductor element 4 is an SBD, the first electrode 4b is a Schottky electrode, and the second electrode 4c is an ohmic electrode.

[0016] When the semiconductor elements 3 and 4 are power semiconductors, the materials of the element bodies 3a and 4a preferably include semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga 2 O 3 ). Among them, it is more preferable to include gallium oxide (α-Ga 2 O 3 ) having a high bandgap in a corundum structure or gallium oxide (β-Ga 2 O 3 ). These materials are known for their particularly large heat generation amount, and by applying the embodiments of the present invention, the maintenance and improvement of the functions as semiconductor elements can be achieved.

[0017] The first electrodes 3b and 4b and the second electrodes 3c and 4c correspond to the electrodes of the element bodies 3a and 4a. Any of these first and second electrodes 3b, 3c, 4b, and 4c may be electrodes in a state where a metal film or the like is laminated on the surface by a method such as etching or sputtering. The thicknesses of the first electrodes 3b and 4b and the second electrodes 3c and 4c can be arbitrarily set including the state where a metal film or the like is laminated on the surface. The first electrodes 3b and 4b and the second electrodes 3c and 4c may further be formed of thin plates made of a metal mainly composed of copper (Cu) or thin plates of copper alloys (lead frame materials such as EFTEC), and may have thin plates produced in a state where one or more are arranged side by side in the in-plane direction. Further, the thin plate may be composed of a composite plate made of materials such as a laminated thin plate of copper and molybdenum (Mo) (CMC or CPC) or a PCM30 in which copper is poured into a mesh-shaped molybdenum and integrated.

[0018] An adhesive layer 3d and 4d is provided between the second electrodes 3c and 4c and the first substrate 1a. Examples of the adhesive layer 3d and 4d include materials such as silver (Ag) sintered materials, copper sintered materials, solder, silver paste, and AuGe-based alloys. Note that by adjusting the filling amount of the adhesive layer 3d and 4d to a desired amount, it is possible to adjust the distance between the lower surface of the semiconductor elements 3 and 4 and the second substrate 2.

[0019] The first electrodes 3b and 4b, the second electrodes 3c and 4c, and the adhesive layers 3d and 4d all have excellent electrical conductivity and thermal conductivity. Further, by roughening the surfaces of the second electrodes 3c and 4c by etching or the like, it is also possible to improve the adhesion and bonding strength between the second electrodes 3c and 4c and the adhesive layers 3d and 4d. Note that when the second electrodes 3c and 4c can be directly bonded (for example, diffusion bonded) to the first layer 1a, the adhesive layers 3d and 4d can be omitted.

[0020] One surface of the semiconductor elements 3 and 4 and the second substrate 2 are connected by vias 6 and 7. More specifically, the first electrodes 3b and 4b of the semiconductor elements 3 and 4 are electrically and thermally connected to the second substrate 2 via the vias 6 and 7. Similar to the via 5, the vias 6 and 7 are made of a material (for example, a material mainly composed of copper (Cu)) that is excellent in both electrical conductivity and thermal conductivity. In the vertical direction of FIG. 1, the vias 5, 6, and 7 are formed to have substantially the same dimensions.

[0021] On the upper surface of the second layer 1b of the first substrate 1 (the side opposite to the second substrate of the first substrate), a first heat dissipation layer (metal layer) 8 is laminated and arranged. Further, the first heat dissipation layer 8 is connected to a second heat dissipation layer (metal layer) 10 via a via 9. The first heat dissipation layer 8, the via 9, and the second heat dissipation layer 10 are each made of a material having excellent thermal conductivity (for example, a material mainly composed of copper (Cu)). In the embodiment of the present invention, it is preferable that the first heat dissipation layer 8 and the second heat dissipation layer 10 have high thermal conductivity. Further, when the second layer 1b of the first substrate 1 has electrical insulation, electrical connection to the semiconductor elements 3 and 4 is not required for the first heat dissipation layer 8 and the second heat dissipation layer 10. The materials of the first heat dissipation layer 8 and the second heat dissipation layer 10 are not limited to the above-mentioned copper (Cu) from the viewpoint of electrical conductivity (insulation). A material having high thermal conductivity and low electrical conductivity (for example, a ceramic-based material) may be used. Also, the dimensions of the via 9 are substantially the same as those of the vias 5, 6, and 7 in the vertical direction of FIG. 1. Note that a heat sink for promoting heat dissipation to the outside of the semiconductor device 110 can also be configured by attaching a heat dissipation portion such as a heat dissipation fin (not shown) to the upper part of the second heat dissipation layer 10.

[0022] The space formed by the first substrate 1 and the second substrate 2, that is, the periphery of the vias 5, 6, and 7 and the gap between the first substrate 1 and the semiconductor elements 3 and 4 is filled with an electrical insulating material 11 (for example, prepreg). Similarly, the space formed by the first heat dissipation layer 8 and the second heat dissipation layer 10, that is, the periphery of the via 9 is also filled with an electrical insulating material 12. These electrical insulating materials 11 and 12 preferably have anisotropy in strength by mixing glass fiber or carbon fiber or the like. Also, the workability can be easily improved by mixing the electrical insulating materials 11 and 12 with a thermosetting resin. Known materials can be appropriately used as the electrical insulating materials 11 and 12, but in particular, a material having excellent electrical insulation and high thermal conductivity is preferable, and for example, a material containing prepreg is preferably used. Note that in the embodiment of the present invention, it is preferable that the constituent material of the second layer 1b contains a material having a higher thermal conductivity than the electrical insulating materials 11 and 12.

[0023] In the semiconductor device 110 configured as described above, when both the first semiconductor element 3 and the second semiconductor element 4 are vertical elements, power is transferred between the first substrate 1 (first layer 1a) and the electric circuit provided on the second substrate 2 via the electrodes 3b, 3c, 4b, and 4c provided on the upper and lower surfaces of the semiconductor elements 3 and 4, respectively. Specifically, a first closed loop of power connected to the second substrate 2, via 6, the first semiconductor element 3, the first substrate 1 (first layer 1a), via 5, and the second substrate 2, and a second closed loop of power connected to the second substrate 2, via 7, the second semiconductor element 4, the first substrate 1 (first layer 1a), via 5, and the second substrate 2 are formed. On the other hand, when both the first semiconductor element 3 and the second semiconductor element 4 are lateral elements and the electrodes are on the upper surface, power is transferred between the first substrate 1 (first layer 1a) and the electric circuit provided on the second substrate 2 via the plurality of electrodes provided on the upper surfaces of the semiconductor elements 3 and 4, respectively. Specifically, a first loop of power connected to the second substrate 2, via 5, the first substrate (first layer 1a), the first semiconductor element 3, the first substrate 1 (first layer 1a), via 5, and the second substrate 2, and a second closed loop of power connected to the second substrate, via 5, the first substrate (first layer 1a), the second semiconductor element 4, the first substrate 1 (first layer 1a), via 5, and the second substrate 2 are formed for each electrode. Further, when both the first semiconductor element 3 and the second semiconductor element 4 are lateral elements and the electrodes are on the lower surface, power is transferred between the electric circuits provided on the second substrate 2 via the plurality of electrodes provided on the lower surfaces of the semiconductor elements 3 and 4, respectively. Specifically, a first loop of power connected to the second substrate, via 6, the first semiconductor element 3, via 6, and the second substrate 2, and a second closed loop of power connected to the second substrate, via 7, the second semiconductor element 4, via 7, and the second substrate 2 are formed for each electrode. Of course, when one of the first semiconductor element 3 and the second semiconductor element 4 is a vertical element and the other is a lateral element, an appropriate one of the plurality of first closed loops and the plurality of second closed loops is adopted and then connected to the electric circuit provided on the second substrate 2.

[0024] Also, the heat generated by the first semiconductor element 3 and the second semiconductor element 4 has a path of being radiated from their respective lower surfaces to the second substrate 2 via vias 6 and 7, and a path of being radiated from their respective upper surfaces to the heat dissipation layer 10 via the first substrate 1 and via 8. In the embodiment of the present invention, it is characterized by a structure for radiating the heat generated from the upper surfaces of the first semiconductor element 3 and the second semiconductor element 4, and the details will be described later.

[0025] Further, as shown in FIG. 1, in the semiconductor device 110 configured as described above, the first substrate 1 is disposed on substantially the center line in the vertical direction. Also, on the upper side and the lower side of the first substrate 1, structures composed of substantially the same components such as the electrical insulating materials 11 and 12 and vias 5, 6, 7, and 9 are provided with substantially the same thickness. By thus forming the semiconductor device 110 having a substantially symmetric structure in the vertical direction, the thermal expansion in the vertical direction is balanced, and it is possible to prevent the semiconductor device 110 from being excessively warped or bent in either the upper or lower direction due to the heat generated by the semiconductor elements 3 and 4, and to suppress problems such as peeling of the connection portions of the stacked components.

[0026] Generally, semiconductor elements may have different outer shapes and dimensions depending on their specifications. When manufacturing a semiconductor device by mounting semiconductor elements with different outer shapes and dimensions, the dimensional error has a significant impact on the assembly accuracy and high-density mounting. In particular, in a semiconductor device including a power semiconductor element having a power conversion function (switching function), a plurality of semiconductor elements with different specifications and dimensions, such as IGBT, MOSFET, and SBD, are arranged side by side between wiring portions including a circuit board. When configuring a semiconductor device by mounting a plurality of semiconductor elements from different manufacturers, the dimensional difference in the thickness direction between the semiconductor elements cannot be ignored. When performing high-density mounting by laminating a circuit board in a state where there is a dimensional difference in the thickness direction between the semiconductor elements, one of the circuit boards arranged above and below the semiconductor element will be in a tilted or bent state and will be connected to the semiconductor element with a small thickness. This hinders the ideal surface contact between the electrode of the semiconductor element and the circuit board. In particular, when the semiconductor element is a power semiconductor, the current conduction becomes insufficient, resulting in unstable output, and the risk of peeling between the electrode and the circuit board increases due to the generation of thermal stress caused by heat generation. As a result, not only does it reduce the function and lifespan of the semiconductor device, but it also has an adverse effect on the reliability of the system or equipment equipped with the semiconductor device.

[0027] In contrast, in the present embodiment, for the first semiconductor element 3 with a large thickness and the second semiconductor element 4 with a small thickness, the positions of the mounting surfaces of the first substrate 1 are formed at different heights. That is, the first semiconductor element 3 and the second semiconductor element 4 with different thicknesses are mounted, and the depth of the concave portion on the uneven surface of the first substrate 1 (the distance between the first surface of the first region and the second surface of the second region) is substantially the same as the thicknesses of the first semiconductor element 3 and the second semiconductor element 4 placed in each concave portion. Therefore, even when a plurality of semiconductor elements with different specifications and dimensions are arranged side by side, high-density mounting can be performed satisfactorily. And, as will be described later, the first substrate 1 having mounting surfaces (grooves 13a, 13b) with arbitrary depths can be easily manufactured.

[0028] Next, the manufacturing process of the first substrate 1 will be described with reference to FIGS. 3 to 6. First, a second layer 1b is fabricated using a ceramic flat plate (ceramic substrate) made of aluminum oxide (Al 2 O 3 ), etc. After preparing the ceramic flat plate, as shown in FIG. 3, a plurality of grooves 13a, 13b are formed. This process is performed by known methods such as etching, sputtering, dicing, and grinding on ceramics. Also, by using a 3D printer, it is possible to three-dimensionally print the second layer 1b having the cross-sectional shape of FIG. 3 without preparing a ceramic flat plate. The thickness of the fabricated second layer 1b is, for example, about 100 μm to 300 μm.

[0029] Here, the groove 13a is a space where the first semiconductor element 3 is disposed, and the groove 13b is a space where the second semiconductor element 4 is disposed. Then, the grooves 13a, 13b are formed such that the difference (Ha - Hb) between the height Ha of the groove 13a and the height Hb of the groove 13b corresponds to the difference in thickness between the semiconductor element 3 and the semiconductor element 4. In any of the above methods, it is possible to reproduce the difference in height (Ha - Hb) of the grooves 13a, 13b to the order of several nm.

[0030] In addition to aluminum oxide (Al 2 O 3 ), the second layer 1b may also be fabricated using a material mainly composed of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or Si.

[0031] Next, copper (Cu) is deposited as the first layer 1a on the entire surface of the second layer 1b fabricated in FIG. 3. For this process, known methods such as electroless plating or mist CVD can be used. When using the electroless plating method, after roughening the surface of the second layer 1b made of aluminum oxide, a catalyst layer of copper (Cu), silver (Ag), palladium (Pd), etc. is deposited, and then copper (Cu) is deposited for thickening. Such a procedure can be adopted. Also, by using a 3D printer, copper (Cu) particles can be continuously printed and formed around the second layer 1b. Through these processes, as shown in FIG. 4, the first layer 1a is laminated on the entire surface of the second layer 1b, and the prototype of the first substrate 1 is completed. The thickness of the first layer 1a is, for example, about 5 μm to 20 μm. Note that before depositing the first layer 1a on the entire surface of the second layer 1b, a material with high electrical insulation can be deposited as an intermediate layer on the surface of the second layer 1b, and then the first layer 1a can be deposited. By adopting such a manufacturing method, even when the second layer 1b contains a material with low electrical insulation, the intermediate layer suppresses electrical conduction from the first layer 1a to the second layer 1b. By manufacturing the intermediate layer, electrical insulation can also be achieved between the second layer 1b and the first heat dissipation layer (metal layer) 8 shown in FIG. 1. Of course, by depositing the intermediate layer on only one of the interfaces between the first layer 1a and the second layer 1b and between the second layer 1b and the first heat dissipation layer 8, the necessary electrical insulation can also be achieved. Examples of the material for the intermediate layer include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), boron nitride (BN), polyimide, PBO (polybenzoxazole), BCB (benzocyclobutene), etc. can be deposited.

[0032] Next, semiconductor elements 3 and 4 are mounted in the grooves 13a and 13b of the first substrate 1 fabricated in FIG. 4. This process is also performed by a known method, and electrical and thermal connections between the first substrate 1 and the semiconductor elements 3 and 4 are achieved. Further, in the embodiment of the present invention, adjustment is made such that the upper surfaces of the first substrate 1 and the semiconductor elements 3 and 4 are substantially at the same height. That is, in the process shown in FIG. 3, since the grooves 13a and 13b having a depth corresponding to the difference in thickness between the semiconductor element 3 and the semiconductor element 4 are formed, fine adjustment of the height is performed while mounting the semiconductor elements 3 and 4 at this process stage. For example, when fixing the semiconductor elements 3 and 4 in the grooves 13a and 13b, handling control is performed to keep the semiconductor elements 3 and 4 at a predetermined height in the grooves until the adhesive layers 3d and 4d are solidified, and the handling is released after the solidification is completed.

[0033] Next, the first substrate 1 fabricated in FIG. 5 is separated for each functional unit and individualized as the first substrate 1 on which a set of semiconductor elements 3 and 4 are mounted. This process is performed by a known method such as ultrasonic dicing or water jet dicing, for example. By separating the first substrate 1 that has undergone the process of FIG. 5 at its center, it is individualized into a plurality of first substrates 1 as shown in FIG. 6. Also, when the both side surfaces are also film-formed as in the first substrate 1 shown in FIG. 5, dicing is performed to remove the film formation on the both side surfaces, whereby unnecessary electrical conduction on the upper and lower surfaces of the first substrate 1 can be interrupted. Then, as shown in FIG. 6, the lower surface of the individualized first substrate 1 becomes the first heat dissipation layer 8 in FIG. 1. That is, by these processes, the first layer 1a and the first heat dissipation layer (metal layer) 8 made of the same material and having the same thickness are easily fabricated.

[0034] Subsequently, the operation of the semiconductor device according to the embodiment of the present invention will be described. As shown in FIG. 2, in the semiconductor device 110 according to an embodiment of the present invention, first to third regions are formed on a first substrate 1. When the semiconductor elements 3 and 4 generate heat by being switched and controlled, the heat is mainly radiated from the upper and lower surfaces of the semiconductor elements 3 and 4. When electrodes 3b, 3c, 4b, and 4c are formed on the upper and lower surfaces of the semiconductor elements 3 and 4, the amount of heat generated also becomes large.

[0035] Here, heat radiation from the upper surfaces of the semiconductor elements 3 and 4 will be described. The heat radiated from the upper surfaces of the semiconductor elements 3 and 4 first reaches the first layer 1a in the second region. Most of the heat that has reached the first layer 1a in the second region is transmitted to the second layer 1b having heat dissipation properties and radiated upward, and a part of the remainder is transmitted through the first layer 1a and reaches the third region. Further, most of the heat that has reached the first layer 1a in the third region is transmitted to the second layer 1b having heat dissipation properties and radiated laterally (upward), and a part of the remainder is transmitted through the first layer 1a and reaches the first region. Furthermore, most of the heat that has reached the first layer 1a in the first region is transmitted to the second layer 1b having heat dissipation properties and radiated upward, and almost all of the remainder is transmitted to the second substrate 2 through the via 5 and radiated downward. That is, in the embodiment of the present invention, direct heat transfer from the first layer 1a to the second layer 1b is performed in each of the first to third regions. And it is used for heat radiation upward from the second layer 1b.

[0036] In an embodiment of the present invention, in the first region, the distance between the first substrate 1 and the second substrate is close, and in the second region, the distance between the first substrate 1 and the second substrate is separated. Such a relative positional relationship between the two is determined by the cross-sectional shape of the first substrate 1. Further, a third region connecting these two regions is formed between the first region and the second region. Thus, since the distance of the first substrate with respect to the second substrate 2 is different between the first region and the second region, a third region connecting these regions is necessarily provided. And, compared with the case where the first region and the second region are formed as the same plane (a continuous single plane), the overall surface area of the first substrate 1 can be easily expanded by the amount of the third region formed. Therefore, heat generated from the semiconductor elements 3 and 4 can be effectively radiated by heat radiation in this third region, and the heat radiation efficiency of the entire semiconductor device 110 is increased. Accordingly, the reliability of the semiconductor device 110 can be improved.

[0037] As described above, in addition to the first region and the second region, by providing the third region so as to connect these two regions, the heat radiation surface composed of the first to third regions is three-dimensionally expanded. This can easily expand the surface area compared to securing the heat radiation surface by extending it in the two-dimensional direction (the direction of the substrate surface of the second substrate 2), and significantly increases the area of the heat radiation surface that can be secured per unit volume. At the same time, since the contact area between the first layer 1a and the second layer 1b is also expanded, heat transferred from the semiconductor elements 3 and 4 to the first layer 1a can be efficiently heat-transferred to the second layer 1b. By selecting a material for the second layer 1b having a higher heat transfer rate than that of the first layer 1a, heat transferred from the semiconductor elements 3 and 4 to the first layer 1a can be radiated more efficiently.

[0038] Also, as can be seen from FIG. 2, the third region is configured to face the side surfaces of the semiconductor elements 3 and 4. The third region is parallel to the side surfaces of the semiconductor elements 3 and 4. Further, a material with high thermal conductivity such as prepreg is filled between the third region and the side surfaces of the semiconductor elements 3 and 4. Therefore, the heat that is transferred to the prepreg instead of being transferred to the second region from the semiconductor elements 3 and 4 can also be effectively absorbed from the third region and used for heat dissipation.

[0039] Also, when an electrically insulating material is used as the second layer 1b, or when an electrically insulating material is formed between the second layer 1b and the heat dissipation layer (metal layer) 8, for example, on the first layer 1b of FIG. 1, a heat dissipation layer can be provided directly without using a TIM (Thermal Interface Material) or the like. Therefore, in combination with the improvement in heat dissipation due to the increase in the heat dissipation area described above, heat dissipation from the upper surface of the semiconductor element can be performed even better.

[0040] Furthermore, as shown in FIGS. 1 and 2, since the first layer 1a having the first region, the second region, and the third region configured as described above has conductivity, it is also possible to simplify the process for electrical connection between the first substrate and the second substrate. For example, since there is no need to separately form through holes or the like for making electrical connection between the substrates, the process for forming through holes, which generally has a high manufacturing cost, is omitted. And in the embodiment of the present invention, electrical connection between the substrates can be suitably performed only with vias without using through holes. Therefore, the effect due to the increase in the heat dissipation surface described above can be enjoyed without increasing the manufacturing process of the semiconductor device.

[0041] FIG. 7 is a cross-sectional view of a semiconductor device 120 according to another embodiment of the present invention. As shown in the figure, the semiconductor device 120 in the present embodiment has a different cross-sectional shape of the uneven surface on the lower surface of the first substrate compared to the semiconductor device 110 in the previous embodiment. That is, in the first substrate 1', the angle formed by the third region with respect to the first and second regions is an obtuse angle greater than 90°. And the space for mounting the semiconductor elements 3 and 4 has a trapezoidal cross-sectional shape. That is, the side surfaces of the semiconductor elements 3 and 4 and the third region are in a non-parallel relationship, and the dimension of the gap between the semiconductor elements 3 and 4 and the third region gradually decreases from the first region (near the lower surface of the semiconductor element) toward the second region (near the upper surface of the semiconductor element).

[0042] Even in the embodiment of the present invention having such a configuration, the same effects as those of the previous embodiment can be expected. Further, since the area of the third region is enlarged compared to the previous embodiment, more heat generated from the semiconductor elements 3 and 4 can be used for heat dissipation through the third region. Also, when mounting the semiconductor elements 3 and 4 on the first layer 1' (see FIG. 5), since the opening area of the entrances of the grooves 13a and 13b becomes larger, the semiconductor elements 3 and 4 can be easily mounted in the grooves 13a and 13b. Also, the filling of the adhesive layers 3d and 4d into the grooves can be easily performed.

[0043] Note that the angle formed by the third region with respect to the first and second regions can be arbitrarily set. For example, when Si is used as the material of the second layer 1b', by setting it to 54.7°, the etching process shown in FIG. 3 can be easily realized.

[0044] Of course, it is also possible to combine a plurality of embodiments according to the present invention described above or apply some components to other embodiments, and such things also belong to the embodiments of the present invention.

[0045] In the embodiments of the present invention, a semiconductor device in which two semiconductor elements (the first semiconductor element 3 and the second semiconductor element 4) are mounted is exemplified. However, even in a semiconductor device in which only one semiconductor element is mounted, the effects of the present invention can be expected. Further, in the case where two semiconductor elements (the first semiconductor element 3 and the second semiconductor element 4) or three or more semiconductor elements are mounted, if the semiconductor device has a configuration in which the first to third regions are provided for any one of the semiconductor elements, the effects of the present invention can be expected. Of course, it is most preferable that the semiconductor device has a configuration in which the first to third regions are provided for all the mounted semiconductor elements. Further, in addition to the first semiconductor element 1 and the second semiconductor element, other electronic components other than the semiconductor elements may be further incorporated. The other electronic components may be passive components such as the resistors, capacitors, condensers, coils, etc. described above, or may be active components such as amplifiers (for example, switching elements) and rectifiers (for example, diodes). Further, it may be a transistor, IC, operational amplifier, diode that combines active components and passive components. Further, in the embodiments of the present invention, after using the above-described semiconductor devices 110 and 120 as sub-modules respectively, a plurality of these sub-modules may be combined to form and use a new functional module.

[0046] The semiconductor device according to the above-described embodiment of the present invention can be applied to a power conversion device such as an inverter or a converter in order to exhibit the above-described functions. FIG. 8 is a block configuration diagram showing an example of a control system using the semiconductor device according to the embodiment of the present invention, and FIG. 9 is a circuit diagram of the control system, and it is a control system particularly suitable for mounting on an electric vehicle.

[0047] As shown in FIG. 8, the control system 500 includes a battery (power source) 501, a boost converter 502, a buck converter 503, an inverter 504, a motor (object to be driven) 505, and a drive control unit 506, and these are mounted on an electric vehicle. The battery 501 is composed of a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, stores electric power by charging at a charging station or regenerative energy during deceleration, etc., and can output a DC voltage required for the operation of the drive system and electrical equipment system of the electric vehicle. The boost converter 502 is a voltage conversion device equipped with a chopper circuit, for example, and can boost a DC voltage of, for example, 200V supplied from the battery 501 to, for example, 650V by the switching operation of the chopper circuit and output it to the drive system such as a motor. The buck converter 503 is also a voltage conversion device equipped with a chopper circuit, but can output a DC voltage of, for example, 200V supplied from the battery 501 to the electrical equipment system including a power window, a power steering, or in-vehicle electrical equipment, etc. by stepping it down to about 12V.

[0048] The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by a switching operation and outputs it to the motor 505. The motor 505 is a three-phase AC motor that constitutes the drive system of the electric vehicle, is rotationally driven by the three-phase AC voltage output from the inverter 504, and transmits the rotational driving force to the wheels of the electric vehicle via a transmission (not shown), etc.

[0049] On one hand, using various sensors (not shown), measured values such as the rotational speed and torque of the wheels, and the depression amount of the accelerator pedal (accelerator amount) are measured from an electric vehicle during running, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 has the function of a controller equipped with an arithmetic unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. By using the input measurement signals to generate a control signal and outputting it as a feedback signal to the inverter 504, the switching operation by the switching element is controlled. As a result, the AC voltage applied by the inverter 504 to the motor 505 is instantaneously corrected, so that the driving control of the electric vehicle can be accurately executed, and the safe and comfortable operation of the electric vehicle is realized. Note that by applying the feedback signal from the drive control unit 506 to the boost converter 502, it is also possible to control the output voltage to the inverter 504.

[0050] FIG. 9 shows a circuit configuration excluding the buck converter 503 in FIG. 8, that is, a circuit configuration including only the configuration for driving the motor 505. As shown in the figure, the semiconductor device according to the embodiment of the present invention is used for switching control by being adopted in the boost converter 502 and the inverter 504 as, for example, a Schottky barrier diode. In the boost converter 502, it is incorporated into a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated into a switching circuit including an IGBT to perform switching control. Note that the current is stabilized by interposing an inductor (such as a coil) between the output of the battery 501, and the voltage is stabilized by interposing a capacitor (such as an electrolytic capacitor) between each of the battery 501, the boost converter 502, and the inverter 504.

[0051] Further, as shown by the dotted line in FIG. 9, an arithmetic unit 507 composed of a CPU (Central Processing Unit) and a storage unit 508 composed of a non-volatile memory are provided in the drive control unit 506. The signal input to the drive control unit 506 is given to the arithmetic unit 507, and a feedback signal for each semiconductor element is generated by performing programmed arithmetic operations as necessary. The storage unit 508 temporarily holds the arithmetic results by the arithmetic unit 507, accumulates physical constants, functions, etc. necessary for drive control in the form of a table, and appropriately outputs them to the arithmetic unit 507. The arithmetic unit 507 and the storage unit 508 can adopt known configurations, and their processing capabilities, etc. can also be arbitrarily selected.

[0052] As shown in FIGS. 8 and 9, in the control system 500, diodes, thyristors which are switching elements, power transistors, IGBTs, MOSFETs, etc. are used for the switching operations of the boost converter 502, the buck converter 503, and the inverter 504. By using gallium oxide (Ga 2 O 3 ), particularly colossal gallium oxide (α-Ga 2 O 3 ) as the material, the switching characteristics are significantly improved. Furthermore, by applying the semiconductor device according to the embodiment of the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, each of the boost converter 502, the buck converter 503, and the inverter 504 can be expected to have the effects of the present invention, and the effects of the present invention can be expected in any one of these, or any combination of two or more, or in any form including the drive control unit 506.

[0053] Note that the above-described control system 500 can be applied not only to the control system of an electric vehicle for the semiconductor device according to the embodiment of the present invention, but also to control systems for all applications such as boosting and bucking the power from a DC power source and converting the power from DC to AC. It is also possible to use a power source such as a solar cell as the battery.

[0054] FIG. 10 is a block configuration diagram showing another example of a control system employing the semiconductor device according to an embodiment of the present invention, and FIG. 11 is a circuit diagram of the control system, which is a control system suitable for mounting on infrastructure devices, home appliances, etc. that operate with power from an AC power source.

[0055] As shown in FIG. 10, the control system 600 inputs power supplied from an external, for example, three-phase AC power source (power source) 601, and includes an AC / DC converter 602, an inverter 604, a motor (driving target) 605, and a drive control unit 606, and these can be mounted on various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.) of an electric power company, and its output is supplied as an AC voltage while being stepped down through a substation. Also, for example, it is installed in a building or a neighboring facility in the form of a self-generator and supplied through a power cable. The AC / DC converter 602 is a voltage conversion device that converts an AC voltage into a DC voltage, and converts an AC voltage of 100V or 200V supplied from the three-phase AC power source 601 into a predetermined DC voltage. Specifically, it is converted into a desired DC voltage generally used, such as 3.3V, 5V, or 12V, by voltage conversion. When the driving target is a motor, conversion to 12V is performed. Note that it is also possible to employ a single-phase AC power source instead of the three-phase AC power source, and in that case, if the AC / DC converter is a single-phase input type, the same system configuration can be achieved.

[0056] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by a switching operation and outputs it to the motor 605. The motor 604 has a different form depending on the control target. When the control target is a train, it is a three-phase AC motor for driving wheels, when it is factory equipment, it is a pump or various power sources, and when it is a home appliance, it is a compressor or the like. It is rotationally driven by the three-phase AC voltage output from the inverter 604, and transmits the rotational driving force to a driving target (not shown).

[0057] Incidentally, in the case of home appliances, for example, there are many drive targets that can be directly supplied with the DC voltage output from the AC / DC converter 602 (such as personal computers, LED lighting devices, video devices, audio devices, etc.). In this case, the inverter 604 is not required in the control system 600, and as shown in FIG. 10, a DC voltage is supplied from the AC / DC converter 602 to the drive target. In this case, for example, a 3.3V DC voltage is supplied to a personal computer, etc., and a 5V DC voltage is supplied to an LED lighting device, etc.

[0058] On the other hand, using various sensors (not shown), measured values such as the rotational speed and torque of the drive target, or the temperature and flow rate of the surrounding environment of the drive target are measured, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 gives a feedback signal to the inverter 604 and controls the switching operation by the switching element. As a result, the AC voltage applied by the inverter 604 to the motor 605 is instantaneously corrected, so that the operation control of the drive target can be accurately executed, and a stable operation of the drive target is realized. Also, as described above, when the drive target can be driven by a DC voltage, it is also possible to perform feedback control on the AC / DC converter 602 instead of feedback to the inverter.

[0059] FIG. 11 shows the circuit configuration of FIG. 10. As shown in the figure, the semiconductor device according to the embodiment of the present invention is used for switching control by being adopted in the AC / DC converter 602 and the inverter 604 as, for example, a Schottky barrier diode. The AC / DC converter 602 uses, for example, a circuit configuration in which Schottky barrier diodes are arranged in a bridge shape, and performs DC conversion by converting and rectifying the negative voltage component of the input voltage into a positive voltage. In the inverter 604, it is incorporated into the switching circuit of the IGBT to perform switching control. Note that a capacitor (such as an electrolytic capacitor) is interposed between the AC / DC converter 602 and the inverter 604 to stabilize the voltage.

[0060] Also, as shown by the dotted line in FIG. 11, an arithmetic unit 607 composed of a CPU and a storage unit 608 composed of a non-volatile memory are provided in the drive control unit 606. The signal input to the drive control unit 606 is given to the arithmetic unit 607, and a feedback signal for each semiconductor element is generated by performing programmed arithmetic operations as necessary. The storage unit 608 temporarily holds the arithmetic results by the arithmetic unit 607, accumulates physical constants, functions, etc. necessary for drive control in the form of a table, and appropriately outputs them to the arithmetic unit 607. The arithmetic unit 607 and the storage unit 608 can adopt known configurations, and their processing capabilities, etc. can also be arbitrarily selected.

[0061] Even in such a control system 600, similar to the control system 500 shown in FIGS. 5 and 6, diodes and switching elements such as thyristors, power transistors, IGBTs, MOSFETs, etc. are used for the rectification operation and switching operation of the AC / DC converter 602 and the inverter 604. By using gallium oxide (Ga 2 O 3 )、particularly corundum-type gallium oxide (α-Ga 2 O 3 ) as its material, the switching characteristics are improved. Furthermore, by applying the semiconductor device according to the embodiment of the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, each of the AC / DC converter 602 and the inverter 604 can be expected to have the effects of the present invention, and the effects of the present invention can be expected in any form including any one of these, or a combination, or the drive control unit 606.

[0062] In FIGS. 10 and 11, the motor 605 is exemplified as the driving target. However, the driving target is not necessarily limited to a mechanically operating device, and many devices that require an AC voltage can be targeted. In the control system 600, it is applicable as long as power is input from an AC power source to drive the driving target, and it can be mounted for drive control of devices such as infrastructure devices (e.g., power facilities, communication facilities, traffic control devices, water and sewage treatment facilities, system devices, labor-saving devices, trains, etc. in buildings and factories) and household electrical appliances (e.g., refrigerators, washing machines, personal computers, LED lighting devices, video devices, audio devices, etc.).

Explanation of Signs

[0063] 1,1‘ First substrate 1a,1a‘ First layer 1b,1b‘ Second layer 2 Second substrate 3,4 Semiconductor element 5,6,7,9 Via 8 First heat dissipation layer (metal layer) 10 Second heat dissipation layer (metal layer) 11,12 Electrically insulating material 13a,13b Groove 110, 120 Semiconductor device 500 Control system 501 Battery (power source) 502 Boost converter 503 Buck converter 504 Inverter 505 Motor (driving target) 506 Drive control unit 507 Arithmetic unit 508 Memory unit 600 Control system 601 Three-phase AC power source (power source) 602 AC / DC converter 604 Inverter 605 Motor (driving target) 606 Drive control unit 607 Arithmetic unit 608 Memory unit

Claims

1. A semiconductor device including a laminate in which at least one semiconductor element is disposed between a first substrate and a second substrate, wherein the first substrate includes, a first conductive layer having a first region facing the second substrate, a second region facing the second substrate and spaced apart from the second substrate more than the first region, and a third region connecting the first region and the second region, a second heat dissipating layer disposed on the opposite side of the first layer from the second substrate and laminated on the first layer in the first, second, and third regions, the semiconductor element having one surface connected to the first layer in the second region and the other surface connected to the second substrate, characterized in that.

2. The semiconductor device according to claim 1, wherein the thickness of the second layer is greater than the thickness of the first layer.

3. The semiconductor device according to claim 1, wherein the first layer is connected to the semiconductor element through an adhesive layer in the second region.

4. The semiconductor device according to claim 1, wherein the first region has a first surface facing the second substrate, the second region has a second surface connected to the semiconductor element, and the first surface and the second surface are formed in parallel.

5. The semiconductor device according to claim 1, wherein the third region faces a side surface of the semiconductor element.

6. The semiconductor device according to claim 1, wherein the third region is formed to be non-parallel to a side surface of the semiconductor element.

7. The semiconductor device according to claim 6, wherein the third region is formed such that a distance from a side surface of the semiconductor element increases as it approaches the second substrate.

8. The semiconductor device according to claim 1, wherein the first region and the second substrate are connected by vias.

9. The semiconductor device according to claim 1, wherein the first region is substantially at the same height as the other surface of the semiconductor element.

10. The semiconductor device according to claim 1, wherein the second substrate and the one surface of the semiconductor element are connected by vias.

11. The semiconductor device according to claim 1, wherein an electrically insulating material is provided in a gap between the first substrate and the second substrate.

12. The semiconductor device according to claim 11, wherein the electrical insulating material is thermosetting.

13. The semiconductor device according to claim 11, wherein the electrical insulating material is a prepreg.

14. The semiconductor device according to claim 11, wherein the constituent material of the second layer includes a material having a higher thermal conductivity than the electrical insulating material.

15. The semiconductor device according to claim 1, wherein the constituent material of the second layer has electrical insulation.

16. The semiconductor device according to claim 15, wherein the constituent material of the second layer is ceramic.

17. The constituent material of the second layer is aluminum oxide (Al ２ O ３ ), and the semiconductor device according to claim 15 is characterized in that it contains aluminum oxide (Al ２ O ３ ) as a main component.

18. The constituent material of the second layer is silicon nitride (Si ３ N ４ ), and the semiconductor device according to claim 15 is characterized in that it contains the above as a main component.

19. The constituent material of the second layer is silicon oxide (SiO ２ ), and the semiconductor device according to claim 15 is characterized in that it contains silicon oxide (SiO ２ ) as a main component.

20. The semiconductor device according to claim 1, wherein a metal layer is provided on the side of the first substrate opposite to the second substrate.

21. The semiconductor device according to claim 20, wherein a heat radiating portion is connected to the metal layer.

22. The semiconductor device according to claim 1, wherein the semiconductor element is a vertical element.

23. The semiconductor device according to claim 1, wherein the semiconductor element is a lateral element that is electrically connected to the second substrate.

24. The semiconductor device according to claim 1, wherein the semiconductor element includes a first semiconductor element and a second semiconductor element.

25. The semiconductor device according to claim 24, wherein the thicknesses of the first semiconductor element and the second semiconductor element are different.

26. A power conversion device using the semiconductor device according to claim 1.

27. A control system using the semiconductor device according to claim 1.

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