Photoelectric conversion device, photoelectric conversion system, and moving body

Abstract

To provide a specific layout of a pixel region and an outer peripheral region for a wiring pattern supplied with a reference potential, in a photoelectric conversion device in which a plurality of semiconductor element layers are laminated.SOLUTION: A photoelectric conversion device comprises: a first chip that has a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged and an outer peripheral region, and a first wiring structure including a first wiring layer; and a second chip that has a second semiconductor element layer on which an electric circuit is arranged, and a second wiring structure. The first chip and the second chip are laminated. A pad part that supplies a reference potential to the pixel circuits is arranged, having a trench penetrating through the first semiconductor element layer. The first wiring layer has a first wiring pattern supplied with the reference potential. In a plan view, the wiring density of the first wiring pattern arranged in a region overlapped with the pixel region is higher than that of the first wiring pattern arranged in a region overlapped with the outer peripheral region.SELECTED DRAWING: Figure 5A

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] Patent Document 1 discloses a photoelectric conversion device in which a chip having a plurality of pixel circuits and a chip having an electric circuit are stacked.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a photoelectric conversion device in which a chip having a pixel circuit and a chip having an electric circuit are stacked and the pixel circuit and the electric circuit are electrically connected, the reference potential supplied to the pixel circuit is supplied from a pad. The reference potential is, for example, a ground voltage (GND voltage) or a power supply voltage (VDD voltage).

[0005] Patent Document 1 does not disclose a specific layout of a wiring pattern to which a reference potential is supplied between a pixel region and an outer peripheral region outside the pixel region.

Means for Solving the Problems

[0006] A photoelectric conversion device according to one embodiment includes a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged and an outer peripheral region arranged outside the pixel region in a plan view, and a first wiring structure including a first wiring layer, a first chip having the first wiring structure, a second semiconductor element layer in which an electric circuit is arranged, and a second wiring structure, a second chip having the second wiring structure, wherein the first chip and the second chip are stacked, the first semiconductor element layer has a trench penetrating therethrough, a pad portion for supplying a reference potential to the pixel circuit is arranged, the first wiring layer has a first wiring pattern to which the reference potential is supplied, and in a plan view, the wiring density of the first wiring pattern arranged in a region overlapping the pixel region is higher than the wiring density of the first wiring pattern arranged in a region overlapping the outer peripheral region. The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer. The first wiring layer is a wiring layer adjacent to the wiring layer in which the wiring pattern constituting the metal joint is arranged. The first wiring pattern has a portion arranged in a region overlapping with one of the plurality of metal joints. In a plan view, the wiring density of the first wiring pattern arranged in the region overlapping with the one metal joint is higher than the wiring density of the first wiring pattern arranged in the region overlapping with the outer peripheral region. 。 Moreover, a photoelectric conversion device according to another embodiment includes a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged and an outer peripheral region arranged outside the pixel region in a plan view, a first wiring structure including a first wiring layer and a second wiring layer, a first chip having the first wiring structure, a second semiconductor element layer in which an electric circuit is arranged, and a second chip having a second wiring structure. The first chip and the second chip are stacked. The first semiconductor element layer has a trench penetrating therethrough, and a pad portion for supplying a reference potential to the pixel circuit is arranged. The first wiring layer has a first wiring pattern to which the reference potential is supplied. In a plan view, the wiring density of the first wiring pattern arranged in the region overlapping with the pixel region is higher than the wiring density of the first wiring pattern arranged in the region overlapping with the outer peripheral region. The second wiring layer has a second wiring pattern connected to the first wiring pattern. The second wiring pattern has a plurality of first partial wirings arranged in a region overlapping with the pixel region and a second partial wiring arranged in a region overlapping with the outer peripheral region and connected to the plurality of first partial wirings. The plurality of first partial wirings extend such that a length along a first direction is longer than a length along a second direction intersecting the first direction. The second partial wiring extends such that a length along the second direction is longer than a length along the first direction. The width of the second partial wiring along the first direction is longer than the width of each of the plurality of first partial wirings along the second direction.

Advantages of the Invention

[0007] According to the present invention, in a photoelectric conversion device in which a plurality of semiconductor element layers are stacked, a specific layout of a pixel region and an outer peripheral region can be provided for a wiring pattern to which a reference potential is supplied.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 7

Figure 8A

Figure 8B

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0009] The embodiments shown below are for embodying the technical idea of the present invention and do not limit the present invention. The sizes and positional relationships of the members shown in each drawing may be exaggerated for clarity of explanation. In the following description, the same components may be given the same numbers and the description thereof may be omitted.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating a specific direction or position (for example, "up", "down", "right", "left", and other terms including those terms) are used as necessary. The use of those terms is for facilitating the understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of those terms.

[0011] In this specification, "plan view" means viewing from a direction perpendicular to the light incident surface of the semiconductor element layer described later. Further, a cross section means a plane in a direction perpendicular to the light incident surface of the semiconductor element layer. When the light incident surface of the semiconductor element layer is a rough surface when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor element layer when viewed macroscopically.

[0012] (Embodiment 1) The photoelectric conversion device according to Embodiment 1 will be described with reference to FIGS. 1 to 5. FIG. 1 is a schematic perspective view of the photoelectric conversion device in the present embodiment. The photoelectric conversion device is, for example, a semiconductor device that can be used as an image sensor, a photometric sensor, or a distance measuring sensor.

[0013] The photoelectric conversion device is a laminate of Chip 1 and Chip 2. Chip 1 has a semiconductor element layer 11 (first semiconductor element layer) including pixel circuits included in pixel 10, and a wiring structure 12 (first wiring structure) including an M-layer wiring layer. In this specification, the “semiconductor element layer” includes not only a semiconductor layer but also a gate of a transistor formed on the semiconductor layer. The wiring layer of the wiring structure is not included in the “semiconductor element layer”. Chip 2 has a wiring structure 24 (second wiring structure) including an N-layer wiring layer and a semiconductor element layer 23 (second semiconductor element layer) including an electric circuit. The first wiring structure 12 and the second wiring structure 24 are disposed between the semiconductor element layer 11 and the semiconductor element layer 23.

[0014] Although details will be described later, at least a part of the elements constituting pixel 10 is disposed in semiconductor element layer 11. Note that a part of the configuration of pixel 10 may be disposed in semiconductor element layer 11 and another part of the configuration may be disposed in semiconductor element layer 23. In this case, examples of the configuration of the pixel circuit disposed in semiconductor element layer 11 among pixel 10 include a photoelectric conversion element such as a photodiode. The pixel circuit including the photoelectric conversion element is disposed in a two-dimensional array in a plan view in semiconductor element layer 11. Semiconductor element layer 11 has a pixel region in which a plurality of pixel circuits are disposed in a two-dimensional array in a plan view. In FIG. 1, a plurality of photoelectric conversion elements constituting a plurality of pixel circuits are disposed in a two-dimensional array in the row direction and the column direction in semiconductor element layer 11.

[0015] Wiring structure 12 includes an M (M is an integer of 1 or more) -layer wiring layer and an interlayer insulating material. Wiring structure 24 includes an N (N is an integer of 1 or more) -layer wiring layer and an interlayer insulating material.

[0016] The semiconductor element layer 23 includes an electric circuit. For convenience of explanation, in FIG. 1, the configuration illustrated on the upper surface of the chip 2 is the configuration arranged in the semiconductor element layer 23. The electric circuit is, for example, any one of the transistors constituting the row scanning circuit 20, the column scanning circuit 21, the signal processing circuit 22, etc. shown in FIG. 1. The signal processing circuit 22 is, for example, at least any one or a combination of a part of the configuration of the pixel 10, an amplifier circuit, a selection circuit, a logical operation circuit, an AD conversion circuit, a memory, a circuit performing compression processing or synthesis processing, etc. A part of the configuration of the pixel 10 is, for example, an amplification transistor, a selection transistor, and a reset transistor.

[0017] The pixel 10 can refer to the minimum unit of a circuit repeatedly arranged to form an image. And the pixel circuit included in the pixel 10 and arranged in the semiconductor element layer 11 only needs to include at least a photoelectric conversion element. The pixel circuit may include a configuration other than the photoelectric conversion element. For example, the pixel circuit may further include at least any one of a transfer transistor, an FD, a reset transistor, an amplification transistor, a capacitive addition transistor, and a selection transistor. Typically, a selection transistor and a group of elements connected to a signal line via the selection transistor constitute the pixel 10. That is, the selection transistor can be the outer edge of the pixel circuit. Alternatively, a combination of a photoelectric conversion element and a transfer transistor may constitute the pixel 10. Additionally, a combination of one or more photoelectric conversion elements and one amplifier circuit or one AD conversion circuit may also constitute the pixel 10.

[0018] FIG. 2 shows an example of a pixel circuit that constitutes pixel 10. The pixel circuit is composed of photoelectric conversion elements 301A and 301B, transfer transistors 302A and 302B, a reset transistor 304, an amplification transistor 305, selection transistors 306A and 306B, and capacitance addition transistors 307A and 307B. The capacitance addition transistor 307A includes a switch transistor 309 and a capacitor 308. A reference potential is supplied to the pixel circuit. In FIG. 2, a power supply voltage (for example, VDD voltage) is supplied as the reference potential to the drain of the amplification transistor 305, the drain of the reset transistor 304, and the gate of the capacitor 308. Also, a ground voltage (for example, GND voltage) is supplied as the reference potential to the photoelectric conversion elements 301A and 301B and the well of the semiconductor element layer. The VDD voltage is, for example, 3.3V, and the GND voltage is, for example, 0V.

[0019] As shown in FIG. 2, a single pixel circuit may include a plurality of photoelectric conversion elements, or may include a single photoelectric conversion element.

[0020] Each component included in the pixel circuit will be described below. In the following description, when the description is common, subscripts such as A and B will be omitted.

[0021] The photoelectric conversion element 301 is an element that generates electrons and holes by photoelectric conversion. As the photoelectric conversion element 301, for example, a photodiode can be used. The transfer transistor 302 controls whether to transfer the signal charges generated in the photoelectric conversion element 301 to the floating diffusion (FD) 303. The reset transistor 304 controls whether to set the potential of the FD 303 or the potential of the photoelectric conversion element 301 to the VDD voltage with reference to the reference potential. The capacitive addition transistor 307 controls whether to add a capacitor to the FD 303. The amplification transistor 305 amplifies and outputs a signal based on the signal charges transferred to the FD. The selection transistor 306 is connected to the amplification transistor 305 and the output line 17. When the selection transistor 306 is turned on, the signal output from the amplification transistor 305 is transmitted to the output line 17. When the pixel circuit does not include a selection transistor, the on / off of the amplification transistor is controlled to control whether to output a signal to the signal line. The output line 17 is connected to the signal processing circuit 22 in FIG. 1. Further, signals from the row scanning circuit 20 in FIG. 1 are supplied to the gates of the transfer transistor 302, the reset transistor 304, the amplification transistor 305, the selection transistor 306, and the capacitive addition transistor 307. Thereby, the on / off of each transistor is controlled.

[0022] A rolling shutter function for sequentially reading out pixel by pixel from one side of the pixel region to the opposite side may be provided, or a global shutter function for simultaneously transferring and accumulating charges throughout the pixel region may be provided. Also, within the pixel region, the exposure time may be different for each block including a plurality of pixels.

[0023] In the following embodiments, it will be described assuming that the pixel circuit shown in FIG. 2 is arranged on the chip 1. Note that, in order to secure the area of the photoelectric conversion element 301 without increasing the area of the chip 1, the configuration other than the photoelectric conversion element of the pixel may be arranged on the chip 2.

[0024] FIG. 3 is a plan schematic view of the semiconductor element layer 11 and the light-shielding film 13 of chip 1. The semiconductor element layer 11 has a pixel region 100, an outer peripheral region 102 arranged outside the pixel region 100 in plan view, and a pad region 103 arranged between the outer peripheral region 102 and the end of the semiconductor element layer 11 in plan view. In FIG. 3, the outer peripheral region 102 and the pad region are arranged above and below the pixel region 100 in plan view, but it is not limited thereto. The outer peripheral region 102 may be arranged at least between one side of the pixel region 100 and the end of the semiconductor element layer 11 in plan view.

[0025] In FIG. 3, the pixel region 100 has an OB pixel region 100B in which a plurality of optical black pixels (OB pixels) are arranged, and an effective pixel region 100A in which a pixel where the light-shielding film 13 is not arranged and light is incident is arranged. A light-shielding film 13 that shields light incident on the photoelectric conversion element is arranged in the OB pixel region 100B. The light-shielding film 13 is arranged so as to overlap a plurality of pixels 10 arranged in the vicinity of the outer peripheral region 102 in plan view. The OB pixel is a pixel that overlaps the light-shielding film 13 in plan view and detects the reference value of the black level. Note that the OB pixel region 100B is not essential, and the outer peripheral region 102 may be arranged adjacent to the effective pixel region 100A.

[0026] In the outer peripheral region 102, wirings to which a reference potential is supplied are arranged.

[0027] In the pad region 103, a plurality of trenches constituting a pad portion 16 for inputting and outputting an electrical signal are arranged. The plurality of pad portions 16 include a pad portion 16A to which a VDD voltage supplied to the pixel circuit is supplied, and a pad portion 16B to which a GND voltage supplied to the pixel circuit is supplied.

[0028] The boundary between the pad region 103 and the outer peripheral region 102 can be defined by, for example, a light-shielding film 13. As shown in FIG. 3, the region where the light-shielding film 13 is disposed without the photoelectric conversion element is defined as the outer peripheral region 102, and the region from the end of the light-shielding film 13 to the end of the semiconductor element layer 11 can be defined as the pad region 103. Further, for example, on the back surface of the semiconductor element layer 11, the region from the end of the semiconductor element layer 11 to the end on the pixel region 100 side of the trench constituting the pad portion 16 can be defined as the pad region 103, and the inner side thereof can be defined as the outer peripheral region 102. As shown in FIG. 3, it is preferable but not essential that the light-shielding film 13 is disposed in the outer peripheral region 102 so that light does not enter the OB pixel region 100B. Further, it is not necessary to dispose the light-shielding film 13 over the entire outer peripheral region 102, and the light-shielding film 13 may be disposed on the side closer to the OB pixel region 100B and not disposed on the far side.

[0029] FIG. 4 is a schematic cross-sectional view taken along line A-A' in FIG. 3 for showing the concept of the structure of the photoelectric conversion device. The chip 1 and the chip 2 are bonded and laminated at the bonding surface 3. The wiring structure 12 of the chip 1 and the wiring structure 24 of the chip 2 are located between the semiconductor element layer 11 of the chip 1 and the semiconductor element layer 23 of the chip 2. In FIG. 4, the wiring structure 12 of the M layer has four wiring layers of wiring layers 120, 121, 122, and 123. Further, the wiring structure 24 of the N layer has four wiring layers of wiring layers 240, 241, 242, and 243. The number of each wiring layer is not limited to this, and may be more or less than this.

[0030] Each wiring layer has one or a plurality of wiring patterns and an insulating material disposed between the wiring patterns. For example, the wiring layer 122 includes a wiring pattern 122A (first wiring pattern). The wiring pattern included in each wiring layer is a wiring pattern of wiring in the same layer. In this specification, two separate wiring patterns in the same layer may be referred to as wiring pattern XA and wiring pattern XB. From one viewpoint, the wiring pattern XA and the wiring pattern XB may be wirings that transmit different potentials, respectively.

[0031] Hereinafter, a case will be described by taking as an example the case where the wiring pattern 122A is a wiring that supplies the VDD voltage supplied to the reset transistor and the amplification transistor, and the wiring pattern 122B is a wiring that supplies the GND voltage supplied to the well of the semiconductor element layer 11.

[0032] Each wiring pattern of the wiring layers 120, 121, 122, 123, 240, 241, 242, 243 is made of a metal material. It is preferable that the main component of each wiring pattern of the wiring layers 120, 121, 122, 123, 240, 241, 242, 243 is copper. That the main component is copper means that more than 50% of the total components are copper. It is preferable that more than 90% of the total components of each wiring pattern of the wiring layers 120, 121, 122, 123, 240, 241, 242, 243 are copper. Note that each wiring layer may be made of a metal such as aluminum or tungsten. Also, the wiring layers 123, 243 including the wiring pattern forming the metal junction may be mainly composed of copper, and the wiring layers other than the wiring layers 123, 243 may be mainly composed of a metal such as aluminum or tungsten. The via plugs connecting the respective wiring layers and the contact plugs connecting the wiring layer and the gate of the transistor or the wiring layer and the semiconductor element layer are also made of a metal such as copper, aluminum, or tungsten.

[0033] Each wiring pattern of the wiring layers 123, 243 is embedded in a recess formed in the interlayer insulating layer. Each wiring pattern of the wiring layers 123, 243 can be formed by a damascene process. The wiring pattern of the wiring layer 123 and the wiring pattern of the wiring layer 243 constitute the metal junction 30 when they are joined together. Also, the insulating material constituting the wiring layer 123 and the insulating material constituting the wiring layer 243 are in contact and joined.

[0034] In this embodiment, the plurality of metal joints 30 includes at least a metal joint (first metal joint) that connects the semiconductor element layer 11 and the semiconductor element layer 23. The plurality of metal joints 30 may include a metal joint (second metal joint) that is connected to one of the semiconductor element layer 11 and the semiconductor element layer 23 and not connected to the other. Further, the plurality of metal joints 30 may include a metal joint (third metal joint) that is not connected to the semiconductor element layer 11 and the semiconductor element layer 23.

[0035] In FIG. 4, each wiring layer has via plugs disposed in an insulating material. The wiring pattern of a certain wiring layer and the wiring pattern of the wiring layer above or below it are electrically connected via the via plugs. The via plug 124 disposed in the insulating material of the wiring layer 123 conducts between the metal joint 30 and the wiring pattern included in the wiring layer 122. The via plug 125 disposed in the insulating material of the wiring layer 122 conducts between the wiring pattern of the wiring layer 122 and the wiring pattern of the wiring layer 121. The via plug 244 disposed in the insulating material of the wiring layer 243 conducts between the wiring pattern of the wiring layer 243 that constitutes the metal joint 30 and the wiring pattern of the wiring layer 242. Note that the via plugs are not essential, and the wiring pattern of a certain layer's wiring layer and the wiring pattern of the wiring layer above or below it may be directly in contact without passing through the via plugs. Also, the via plugs may be formed integrally with the wiring pattern of the wiring layer 123 that constitutes the metal joint 30. For example, the via plug 244 may be formed integrally with the wiring pattern of the wiring layer 243 that constitutes the metal joint 30. By using a dual damascene process, the wiring pattern and the via plugs can be formed integrally. The dual damascene process can also be applied to other metal joints.

[0036] The pad portion 16 has at least a part of the trench and the wiring pattern disposed in the wiring layer. In FIG. 4, the wiring pattern 242A of the wiring layer 242 of the chip 2 serves as a pad electrode to which the VDD voltage is supplied. Although not shown in FIG. 4, similarly, a pad electrode to which the GND voltage is supplied is disposed in the wiring layer 242.

[0037] The trench penetrates through chip 1 and wiring layer 243 and is formed to a depth at which wiring pattern 242A is exposed. The trench only needs to penetrate at least semiconductor element layer 11. The wiring pattern 242A can be configured to contain, for example, Al. Note that in pad region 103, at least a part of the trench of pad portion 16 and the pad electrode are arranged. That is, a part of the pad electrode may be arranged in pad region 103, and another part may be arranged in outer peripheral region 102. In each plan view diagram, the region where the trench is arranged is shown as pad portion 16 for convenience in plan view. Wire bonding through which input / output voltage is transmitted is connected to wiring layer 242 formed on chip 2.

[0038] Note that in FIG. 4, an example of wire bonding is shown, but it may also be a through-silicon via (TSV) filled with metal in the trench. When using a TSV, signals may be transmitted through metal joint 30 as shown in FIG. 4, or signals may be transmitted through a via plug without passing through metal joint 30. In the latter case, joint surface 3 is formed of an insulating material, and then the wiring structure of chip 1 and the wiring structure of chip 2 are connected by the TSV.

[0039] FIG. 5A is a plan view diagram that details the vicinity of pad portions 16A and 16B in the plan view diagram of semiconductor element layer 11 shown in FIG. 3. FIG. 5A mainly schematically shows the wiring pattern of wiring layer 122. Further, FIG. 5A shows the layout of via plug 125, metal joint 30, and via plug 124 of wiring layer 123 connected to the wiring pattern of wiring layer 122 in outer peripheral region 102. Via plugs 124 and 244 are not shown in metal joint 30 arranged in pixel region 100, but in pixel region 100, at least one of the metal joints 30 has via plug 124 connected thereto. Furthermore, FIG. 5A shows light-shielding film 13 of OB pixel region 100B.

[0040] In FIG. 5A, the metal joint 30 is shown as a quadrilateral in plan view, but is not limited thereto, and may have rounded corners of the quadrilateral or may be circular. The via plug 124 connects the wiring pattern 122A of the wiring layer 122 and the metal joint 30.

[0041] In FIG. 5A, the wiring pattern 242A constituting the pad portion 16A to which the VDD voltage is supplied is indicated by a dashed line. Also, the wiring pattern 242B constituting the pad portion 16B to which the GND voltage is supplied is indicated by a dotted line as the wiring pattern 242B. The pad portions 16A and 16B may be arranged alternately.

[0042] As shown in FIG. 5A, in the outer peripheral region 102, the wiring pattern 242A to which the VDD voltage is supplied and the wiring pattern 242B to which the GND voltage is supplied are arranged. The VDD voltage is supplied to the wiring pattern 122A via the wiring pattern 242A, and the GND voltage is supplied to the wiring pattern 122B via the wiring pattern 242B. That is, in the outer peripheral region 102, the wiring layer 122 has the wiring pattern 122A to which the VDD voltage is supplied and the wiring pattern 122B to which the GND voltage is supplied arranged. On the other hand, the wiring pattern 122 of the wiring layer 122 in the pixel region 100 has the wiring pattern 122A to which the VDD voltage is supplied arranged. That is, in the pixel region 100, the wiring layer 122 does not have the wiring pattern 122B arranged. In other words, the wiring pattern 122A of the wiring layer 122 in the pixel region 100 has a uniform wiring layout. Thus, the wiring pattern 122A in the pixel region 100 has a higher wiring density than the wiring pattern 122A in the outer peripheral region 102. In this specification, the wiring density of a wiring pattern refers to the total wiring area of the wiring pattern per unit area.

[0043] Among the plurality of pad portions 16, it is preferable that the pad portions 16A and 16B to which the reference potential is supplied are joined at a location where the voltage drop is small. That is, it is preferable that a wiring pattern for supplying the reference potential is arranged in the outer peripheral region 102 close to the pad region 103. Therefore, in the vicinity of the pad region 103 of the chip 1 where the pixel circuit is arranged, there are restrictions on the wiring patterns for supplying the GND voltage and the VDD voltage. On the other hand, in the pixel region arranged in an array in the chip 1, in order to reduce the influence of coupling due to the potential fluctuation of the electric circuit chip, it is preferable to increase the density of the wiring pattern rather than the outer peripheral region 102. This is because a low-impedance wiring pattern can be obtained, and deterioration of characteristics due to smear and shading can be reduced.

[0044] In the present embodiment, as described above, the density of the wiring pattern for supplying the reference potential in the pixel region 100 is made higher than the density of the wiring pattern for supplying the reference voltage in the outer peripheral region. Thereby, while arranging a wiring pattern for supplying the reference potential at a location where the voltage drop is small, the influence of coupling due to the potential fluctuation of the electric circuit chip can be reduced.

[0045] In FIG. 4, pad electrodes are arranged on the chip 2, and the wiring layer 123, which is the lowermost wiring layer of the chip 1, is a wiring pattern constituting the metal joint 30. Therefore, in the wiring layer 122, which is next to the pad electrode and close to it, a wiring layout that satisfies the relationship of the wiring density as described above is adopted. That is, in the wiring layer 122 adjacent to the wiring layer 123 constituting the metal joint 30, the relationship of the wiring density is set as the relationship as described above.

[0046] When there are pad electrodes on the chip 2 and the chip 1 and the chip 2 are joined by the metal joint 30, in order to reduce the influence of the voltage drop, it is necessary to connect the metal joint 30 near the pad electrode and each of the wiring patterns 122A and 122B. That is, when there are pad electrodes on the chip 2 and the chip 1 and the chip 2 are joined by the metal joint 30, the wiring pattern of the wiring layer 122 is likely to be restricted. Therefore, the effect of the present embodiment becomes more remarkable.

[0047] In addition, when pad electrodes are arranged on the chip 1, it is preferable that the wiring layer where the pad electrodes are arranged satisfies the relationship of the wiring density as described above.

[0048] As shown in FIG. 5A, the wiring pattern 242A constituting the pad electrode is continuously arranged from the pad region 103 to a position overlapping the outer peripheral region 102 in a plan view. That is, in the outer peripheral region 102 in a plan view, the wiring pattern 242A constituting the pad electrode is arranged overlapping the wiring pattern 122A. The wiring pattern 242A is connected to the wiring pattern 122A of the chip 1 via the via plug 244, the metal joint 30, and the via plug 124 in the outer peripheral region 102. Similarly, in the wiring layer 242, the wiring pattern 242B to which the GND voltage is supplied is connected to the wiring pattern constituting the GND power supply of the chip 1 via a via plug, a metal joint 30, and a via plug in the outer peripheral region. Thus, since the reference potential of the pixel circuit is connected at the shortest distance, the voltage drop from the pad portion 16 is further reduced, and the influence due to the voltage drop can be reduced.

[0049] In Embodiment 1, the width of the wiring pattern 122A in the pixel region 100 is made larger than the width of the wiring pattern 122A in the outer peripheral region 102 to increase the wiring density, but the present invention is not limited to this.

[0050] The wiring density in the pixel region 100 is higher when compared with the same area as the wiring density in the outer peripheral region 102. For example, in the wiring layer 122, a first region including three or more pixel circuits in the pixel region 100 in a plan view and a second region having the same area as the first region in the outer peripheral region 102 are compared. Three or more pixels are, for example, ten pixels. Further, in the pixel region 100, the area of the wiring pattern 122A when looking at a region of 1000 μm × 1000 μm may be compared with the area of the wiring pattern 122A when looking at a region of 1000 μm × 1000 μm in the outer peripheral region 102.

[0051] The wiring density of the wiring pattern 122A in the pixel region 100 is preferably 1.5 times or more, and more preferably 2 times or more, than the wiring density of the wiring pattern 122A in the outer peripheral region 102.

[0052] It is preferable, but not limited thereto, that the wiring pattern 122A is uniformly arranged in the pixel region 100 so that the effects of reducing impedance and the coupling effect due to potential fluctuations of the chip 2 become more prominent. As long as the relationship of the wiring density is satisfied, the wiring pattern 122B may be partially arranged in the pixel region 100. Even in this case, compared with the case where the wiring density is the same, a certain effect can be obtained for reducing the impedance and the coupling effect due to potential fluctuations of the chip 2. Also, in the pixel region 100, a wiring pattern through which a signal from the pixel circuit is transmitted may be included in a part of the wiring layer 122.

[0053] FIG. 5B shows a schematic plan view of the wiring pattern of the wiring layer 121. In the outer peripheral region 102, a wiring pattern 121A to which a VDD voltage is supplied and a wiring pattern 121B to which a GND voltage is supplied are arranged. The wiring pattern 121A is connected to the wiring pattern 121A of the wiring layer 121 via a via plug 125. Also, the wiring pattern 121B is connected to the wiring pattern 121B of the wiring layer 121 via a via plug 125. In the outer peripheral region 102, the voltage received from the pad portion 16A can be supplied in the lateral direction of the chip by the wiring pattern 121A. Similarly, in the outer peripheral region 102, the voltage received from the pad portion 16B can be supplied in the lateral direction of the chip by the wiring pattern 121B. Further, the wiring pattern 121B is arranged in a mesh shape in the pixel region 100. Thus, in the pixel region 100, by making the wiring pattern 121B continuous in the vertical and horizontal directions, the voltage received from the pad portion 16B can be supplied in the lateral direction of the chip.

[0054] Note that in FIGS. 5A and 5B, the case where the wiring pattern 122A of the wiring layer 122 is a wiring for supplying a VDD voltage and the wiring pattern 121B of the wiring layer 121 is a wiring for supplying a GND voltage has been described. Since the wiring layer closer to the metal junction 30 has relatively fewer design constraints, the VDD voltage for which more voltage drop suppression is desired is arranged on the side closer to the wiring pattern 242A constituting the pad electrode, and the GND voltage is arranged on the farther side. As a result, the width of the wiring pattern 122A can be increased, and the wiring resistance can be reduced, so that a high voltage can be supplied. However, a wiring pattern for supplying a GND voltage may be arranged in the wiring layer 122, and a wiring pattern for supplying a VDD voltage may be arranged in the wiring layer 121. Even in such a case, even when the wiring pattern of the wiring layer 122 is a wiring for supplying a GND voltage, the impedance of the wiring can be reduced, and the influence of coupling due to potential fluctuations of the chip 2 can be reduced. Therefore, the case where a wiring pattern for supplying a GND voltage is arranged in the wiring layer 122 is also included in the present embodiment.

[0055] (Embodiment 2) The photoelectric conversion device according to Embodiment 2 will be described with reference to FIGS. 6A and 6B. FIG. 6A is a schematic plan view mainly showing the wiring pattern of the wiring layer 122. Further, FIG. 6A shows the layout of the via plug 125, the metal junction 30, and the via plug 124 of the wiring layer 123 connected to the wiring pattern of the wiring layer 122 in the outer peripheral region 102. Although the via plugs 124 and 244 are not shown in the metal junction 30 arranged in the pixel region 100, in the pixel region 100, at least one of the metal junctions 30 has the via plug 124 connected thereto. Furthermore, FIG. 6A shows the light shielding film 13. FIG. 6B is a schematic plan view mainly showing the wiring pattern of the wiring layer 121.

[0056] The photoelectric conversion device according to Embodiment 2 is different from Embodiment 1 in that the wiring pattern of the wiring layer 122 is arranged in a mesh shape in a region overlapping the pixel region 100 in a plan view. Since the configuration other than this point and the following description is the same as that of Embodiment 1, the description may be omitted.

[0057] When forming a wiring pattern by the damascene method, after embedding copper that constitutes the wiring pattern in the recess, CMP is performed. In the case of a recess with a thick width, in the CMP process, a formation defect such as the wiring pattern of copper being recessed may occur. On the other hand, according to the present embodiment, since the wiring pattern 122A is laid out in a mesh shape in the pixel region 100, the local copper density in the wiring pattern can be reduced. Thereby, the formation defect in the CMP process can be suppressed.

[0058] Also, in the present embodiment, the wiring layers 122 in the OB pixel region 100B and the effective pixel region 100A are connected horizontally. That is, the wiring pattern arranged so as to overlap the pixels 10 in a certain column and the wiring pattern arranged so as to overlap the pixels in the adjacent column are connected in the row direction to form one wiring pattern 122A. Thereby, the impedance in the wiring pattern for supplying the reference potential can be further reduced. Therefore, the influence of coupling due to the potential fluctuation of the chip 2 on the pixel 10 can be further reduced.

[0059] As shown in FIG. 6B, in the outer peripheral region 102, the wiring patterns 121A and 121B of the wiring layer 121 are connected horizontally. As shown in FIG. 6B, in the outer peripheral region 102, the wiring patterns 121A and 121B of the wiring layer 121 are arranged in a mesh shape.

[0060] According to the present embodiment, similar to the first embodiment, while arranging a wiring pattern for supplying a reference potential to a location where voltage drop hardly occurs, the impedance of the wiring can be reduced, and the influence of coupling due to the potential fluctuation of the chip 2 can be reduced. Also, compared with the first embodiment, it becomes possible to reduce the impedance.

[0061] (Embodiment 3) With reference to FIGS. 7, 8A, and 8B, a photoelectric conversion device according to Embodiment 3 will be described. FIG. 7 shows a plan schematic view of the semiconductor element layer 11 and the light shielding film 13 in the present embodiment. In FIG. 7, a horizontal OB pixel region 100C arranged in the horizontal direction is shown. FIGS. 8A and 8B are plan schematic views of wiring patterns that describe in detail the vicinity of the boundary between the effective pixel region 100A and the horizontal OB pixel region 100C. FIG. 8A is a plan schematic view mainly showing the wiring pattern of the wiring layer 122. Further, FIG. 8A shows the layout of the via plug 125, the metal junction 30, and the via plug 124 of the wiring layer 123 that are connected to the wiring pattern of the wiring layer 122 in the outer peripheral region 102. Although the via plugs 124 and 244 are not shown in the metal junction 30 arranged in the pixel region 100, in the pixel region 100, at least one of the metal junctions 30 is connected to the via plug 124. Further, FIG. 8A shows the light shielding film 13. FIG. 8B is a plan schematic view mainly showing the wiring pattern of the wiring layer 121.

[0062] The photoelectric conversion device according to the present embodiment is different from Embodiment 2 in that the wiring pattern 122A is divided by the horizontal OB pixel region 100C and the effective pixel region 100A. Since the configuration other than this point and the following description is the same as that of Embodiment 2, the description may be omitted.

[0063] As shown in FIG. 7, the horizontal OB pixel region 100C is arranged on the left side of the effective pixel region 100A in FIG. 7. And the light shielding film 13 is also arranged in the horizontal OB pixel region 100C. The horizontal OB pixel region 100C is the same as the OB pixel region 100B described in Embodiment 1 except for the arranged position.

[0064] Also, as shown in FIG. 7, a pad portion 16C to which a VDD voltage is applied is arranged between the horizontal OB pixel region 100C and the end of the semiconductor element layer 11. In FIG. 7B, the pad portion 16C is arranged on the left side of the horizontal OB pixel region 100C, but it may be placed below the horizontal OB pixel region 100C.

[0065] In this embodiment, as shown in FIG. 8A, in the effective pixel region 100A, the wiring pattern 122A of the wiring layer 122 is arranged in a mesh shape. And this mesh-shaped wiring pattern 122A is arranged in the horizontal OB pixel region 100C and is divided between the wiring pattern 122C to which the same potential as the wiring pattern 122A is supplied. In other words, the same potential is applied to the wiring pattern 122A arranged in the effective pixel region 100A and the wiring pattern 122C arranged in the horizontal OB pixel region 100C, but the wiring patterns are not connected in the wiring layer 122. Also, the pad portion 16 is also divided into a pad portion 16A that applies a voltage to the wiring pattern 122A arranged in the effective pixel region 100A and a pad portion 16C that applies a voltage to the wiring pattern 122C arranged in the horizontal OB pixel region 100C. For example, a VDD voltage is applied to each of the pad portions 16A and 16C, and the VDD voltage is supplied to each of the wiring patterns 122A and 122C.

[0066] Also, as shown in FIG. 8B, in the outer peripheral region 102, the wiring pattern 121A to which the VDD voltage of the wiring layer 121 is applied is separated from the wiring pattern 121C arranged in the vertical direction of the horizontal OB pixel and to which the VDD voltage is applied.

[0067] When the pixel 10 in the effective pixel region 100A is irradiated with strong light, the voltage of the signal line drops significantly, the circuit operation range of the constant current source becomes narrow, and the current from the constant current source may be cut off. In this case, through the wiring pattern 122 to which the VDD voltage is supplied, the potential of the wiring pattern 122C to which the VDD voltage of the horizontal OB pixel region 100C is supplied may fluctuate, and the dark signal may fluctuate depending on the incident light. When the dark signal fluctuates depending on the incident light, image quality degradation such as smear may occur in the correction process using the dark signal.

[0068] In this embodiment, the pad portion 16A of the effective pixel region 100A is separated from the pad portion 16C of the horizontal OB pixel region 100C. Also, the wiring patterns 122A and 121A to which the VDD voltage of the effective pixel region 100A is supplied are separated from the wiring patterns 122C and 121C to which the VDD voltage of the horizontal OB pixel region 100C is supplied. Therefore, even if strong light is irradiated and the VDD voltage of the pixel 10 in the effective pixel region 100A fluctuates, the potential fluctuation of the dark signal to the horizontal OB pixel region 100C can be reduced. Thus, more accurate correction processing becomes possible.

[0069] Note that it is preferable that a bypass capacitor or the like is arranged around the horizontal OB pixel region 100C. Thereby, the potential fluctuation of the VDD voltage of the horizontal OB pixel region 100C can be further reduced. As a result, a stable dark signal not affected by the incident light can be obtained from the horizontal OB pixel region 100C.

[0070] In the above description, the case where the voltage supplied from the pad portions 16C and 16A is the VDD voltage has been described. However, the same effect can be obtained when the voltage supplied from the pad portions 16A and 16C is the GND voltage.

[0071] According to this embodiment, similar to Embodiment 2, while arranging a wiring pattern for supplying a reference potential to a location where voltage drop is unlikely to occur, the impedance of the wiring is reduced, and the influence of coupling due to potential fluctuation of the chip 2 can be reduced. Also, according to this embodiment, image quality degradation such as smear can be reduced compared to Embodiment 2.

[0072] (Embodiment 4) FIG. 9 is a block diagram showing the configuration of a photoelectric conversion system 500 according to the present embodiment. The photoelectric conversion system 500 of the present embodiment includes a photoelectric conversion device 2000 to which any of the configurations of the above-described photoelectric conversion devices is applied. In FIG. 9, an imaging system is shown as the photoelectric conversion system 500. Specific examples of the imaging system include a digital still camera, a digital camcorder, a surveillance camera, and the like. The photoelectric conversion system 500 includes a photoelectric conversion device 2000, a lens 5020, a diaphragm 504, and a barrier 506 for protecting the lens 5020. The photoelectric conversion system 500 includes a signal processing unit 5080 (image signal generation unit) that processes an output signal output from the photoelectric conversion device 2000. The signal processing unit 5080 performs signal processing operations of performing various corrections and compressions on the input signal and outputting the result as necessary. The signal processing unit 5080 may have a function of performing AD conversion processing on the output signal output from the photoelectric conversion device 2000. The photoelectric conversion system 500 further includes a buffer memory unit 510 for temporarily storing image data, and an external interface unit (external I / F unit) 512 for communicating with an external computer or the like. Further, the photoelectric conversion system 500 includes a recording medium 514 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 516 for recording or reading from the recording medium 514.

[0073] Furthermore, the photoelectric conversion system 500 includes an overall control and arithmetic unit 518 that performs various operations and controls the entire digital still camera, and a timing generation unit 520 that outputs various timing signals to the photoelectric conversion device 2000 and the signal processing unit 5080. The photoelectric conversion device 2000 outputs an image signal to the signal processing unit 5080. The signal processing unit 5080 performs predetermined signal processing on the image signal output from the photoelectric conversion device 2000 and outputs image data. Also, the signal processing unit 5080 generates an image using the image signal.

[0074] By configuring a photoelectric conversion system using the photoelectric conversion device of each of the above-described embodiments, an imaging system capable of acquiring higher-quality images can be realized.

[0075] (Embodiment 5) The photoelectric conversion system and the moving body of this embodiment will be described with reference to FIG. 10. In this embodiment, an example of an imaging system for an in-vehicle camera is shown. FIG. 10 shows an example of a vehicle system and an imaging system mounted thereon. The photoelectric conversion system 701 includes a photoelectric conversion device 702, an image preprocessing unit 715, an integrated circuit 703, and an optical system 714. The optical system 714 forms an optical image of a subject on the photoelectric conversion device 702. The photoelectric conversion device 702 converts the optical image of the subject formed by the optical system 714 into an electrical signal. The photoelectric conversion device 702 is any of the photoelectric conversion devices of the above-described embodiments. The image preprocessing unit 715 performs predetermined signal processing on the signal output from the photoelectric conversion device 702. At least two sets of the optical system 714, the photoelectric conversion device 702, and the image preprocessing unit 715 are provided in the photoelectric conversion system 701, and the output from each set of the image preprocessing units 715 is input to the integrated circuit 703.

[0076] The integrated circuit 703 is an integrated circuit for photoelectric conversion system applications and includes an image processing unit 704 including a memory 705, an optical distance measurement unit 706, a parallax calculation unit 707, an object recognition unit 708, and an abnormality detection unit 709. The image processing unit 704 performs image processing such as development processing and defect correction on the output signal of the image preprocessing unit 715. The memory 705 stores the primary storage of the captured image and the defective positions of the captured pixels. The optical distance measurement unit 706 performs focusing and distance measurement of the subject. The parallax calculation unit 707 calculates the parallax (phase difference of the parallax image) from a plurality of image data acquired by a plurality of photoelectric conversion devices 702. The object recognition unit 708 recognizes subjects such as vehicles, roads, signs, and people. When the abnormality detection unit 709 detects an abnormality in the photoelectric conversion device 702, it reports the abnormality to the main control unit 713.

[0077] The integrated circuit 703 may be implemented by dedicatedly designed hardware, may be implemented by software modules, or may be implemented by a combination thereof. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc., or may be implemented by a combination thereof.

[0078] The main control unit 713 comprehensively controls the operations of the photoelectric conversion system 701, the vehicle sensor 710, the control unit 720, etc. Note that it is also possible to adopt a method in which the photoelectric conversion system 701, the vehicle sensor 710, and the control unit 720 do not have the main control unit 713 and each has a communication interface, and each performs transmission and reception of control signals via a communication network (for example, the CAN standard).

[0079] The integrated circuit 703 has a function of receiving a control signal from the main control unit 713 or transmitting a control signal and a set value to the photoelectric conversion device 702 by its own control unit. For example, the integrated circuit 703 transmits settings for signal-driving a voltage switch in the photoelectric conversion device 702, settings for switching the voltage switch for each frame, etc.

[0080] The photoelectric conversion system 701 is connected to the vehicle sensor 710 and can detect the running state of the host vehicle such as vehicle speed, yaw rate, and steering angle, as well as the state of the environment outside the host vehicle and the state of other vehicles / obstacles. The vehicle sensor 710 is also a distance information acquisition means for acquiring distance information from the parallax image to the object. In addition, the photoelectric conversion system 701 is connected to a driving support control unit 711 that performs various driving supports such as automatic steering, automatic cruise, and collision prevention functions. In particular, regarding the collision determination function, based on the detection results of the photoelectric conversion system 701 and the vehicle sensor 710, the collision estimation and the presence or absence of a collision with other vehicles / obstacles are determined. Thereby, avoidance control when a collision is estimated and activation of a safety device at the time of a collision are performed.

[0081] In addition, the photoelectric conversion system 701 is also connected to an alarm device 712 that alarms the driver based on the determination result of the collision determination unit. For example, when the determination result of the collision determination unit indicates a high possibility of collision, the main control unit 713 performs vehicle control to avoid collision and reduce damage, such as applying brakes, returning the accelerator, and suppressing engine output. The alarm device 712 warns the user by sounding an alarm such as a sound, displaying alarm information on a display screen of a car navigation system or a meter panel, or applying vibration to the seat belt or steering wheel.

[0082] In this embodiment, the photoelectric conversion system 701 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 10(b) shows an example of the arrangement of the photoelectric conversion system 701 when imaging the front of the vehicle with the photoelectric conversion system 701.

[0083] In addition, in this embodiment, although the control for not colliding with other vehicles has been described, it is also applicable to controls such as automatic driving following other vehicles and automatic driving so as not to deviate from the lane. Furthermore, the photoelectric conversion system 701 can be applied not only to vehicles such as the host vehicle, but also to moving bodies (moving devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving bodies, but also to devices that widely utilize object recognition, such as advanced road traffic systems (ITS).

[0084] (Other Embodiments) As described above, each embodiment has been described, but the present invention is not limited to these embodiments, and various changes and modifications are possible. In addition, each embodiment can be applied to each other.

Description of Reference Numerals

[0085] 1 Chip 1 2 Chip 2 3 Bonding surface 11 First semiconductor element layer 23 Second semiconductor element layer 122A Wiring pattern 100 Pixel region 102 Peripheral region

Claims

1. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged and an outer peripheral region arranged outside the pixel region in a plan view, and a first wiring structure including a first wiring layer; A second chip having a second semiconductor element layer in which an electric circuit is arranged and a second wiring structure; The first chip and the second chip are stacked; It has a trench penetrating the first semiconductor element layer, and a pad portion for supplying a reference potential to the pixel circuit is arranged; The first wiring layer has a first wiring pattern to which the reference potential is supplied; In a plan view, the wiring density of the first wiring pattern arranged in a region overlapping the pixel region is higher than the wiring density of the first wiring pattern arranged in a region overlapping the outer peripheral region; The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer; The first wiring layer is a wiring layer adjacent to a wiring layer in which a wiring pattern constituting the metal joint is arranged; The first wiring pattern has a portion arranged in a region overlapping one of the plurality of metal joints; A photoelectric conversion device, wherein in a plan view, the wiring density of the first wiring pattern arranged in a region overlapping the one metal joint is higher than the wiring density of the first wiring pattern arranged in a region overlapping the outer peripheral region.

2. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged and an outer peripheral region arranged outside the pixel region in a plan view, and a first wiring structure including a first wiring layer and a second wiring layer; A second chip having a second semiconductor element layer in which an electric circuit is arranged and a second wiring structure; The first chip and the second chip are stacked; It has a trench penetrating the first semiconductor element layer, and a pad portion for supplying a reference potential to the pixel circuit is arranged; The first wiring layer has a first wiring pattern to which the reference potential is supplied; In a plan view, the wiring density of the first wiring pattern arranged in a region overlapping the pixel region is higher than the wiring density of the first wiring pattern arranged in a region overlapping the outer peripheral region; The second wiring layer has a second wiring pattern connected to the first wiring pattern; The second wiring pattern includes a plurality of first partial wirings arranged in a region overlapping the pixel region, and a second partial wiring arranged in a region overlapping the outer peripheral region and connected to the plurality of first partial wirings. The plurality of first partial wirings extend such that a length along a first direction is longer than a length along a second direction intersecting the first direction. The second partial wiring extends such that a length along the second direction is longer than a length along the first direction. A width of the second partial wiring along the first direction is longer than a width of each of the plurality of first partial wirings along the second direction. A photoelectric conversion device characterized by the above.

3. The pad portion includes a pad electrode. The photoelectric conversion device according to claim 1 or 2, wherein the pad electrode is arranged on a second chip.

4. In a region overlapping the outer peripheral region, a part of the pad electrode is arranged overlapping the first wiring pattern. The photoelectric conversion device according to claim 3.

5. The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer. The photoelectric conversion device according to claim 2.

6. The first wiring layer is a wiring layer adjacent to a wiring layer in which a wiring pattern constituting the metal joint is arranged. The photoelectric conversion device according to claim 5.

7. Each of the plurality of pixel circuits includes a photoelectric conversion element. The photoelectric conversion device according to any one of claims 1, 5, and 6, wherein one of the metal joints is arranged for one of the photoelectric conversion elements.

8. The first wiring layer is a wiring layer in which the pad electrode of the pad portion is arranged in the first wiring structure. The photoelectric conversion device according to claim 1 or 2.

9. The region overlapping the pixel region is a first region including three or more pixel circuits. The photoelectric conversion device according to any one of claims 1 to 8, wherein the region overlapping the outer peripheral region is a second region having the same area as the first region.

10. The photoelectric conversion device according to any one of claims 1 to 9, wherein a power supply voltage or a GND voltage is supplied to the first wiring pattern as the reference potential.

11. The photoelectric conversion device according to claim 10, wherein a power supply voltage is supplied to the first wiring pattern as the reference potential.

12. The first wiring layer includes a second wiring pattern disposed in a region overlapping the outer peripheral region, and a GND voltage is supplied to the second wiring pattern. The photoelectric conversion device according to claim 11.

13. The photoelectric conversion device according to claim 12, wherein the second wiring pattern is not disposed in a region overlapping the pixel region.

14. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are disposed and an outer peripheral region disposed outside the pixel region in plan view, and a first wiring structure including a first wiring layer; A second chip having a second semiconductor element layer in which an electric circuit is disposed and a second wiring structure; The first chip and the second chip are stacked; It has a trench penetrating the first semiconductor element layer, and a pad portion for supplying a reference potential to the pixel circuit is disposed. The first wiring layer has a first wiring pattern to which the reference potential is supplied. In plan view, the wiring density of the first wiring pattern disposed in a region overlapping the pixel region is higher than the wiring density of the first wiring pattern disposed in a region overlapping the outer peripheral region. A power supply voltage is supplied to the first wiring pattern as the reference potential. The first wiring layer includes a second wiring pattern disposed in a region overlapping the outer peripheral region, and a GND voltage is supplied to the second wiring pattern. The photoelectric conversion device, wherein the second wiring pattern is not disposed in a region overlapping the pixel region.

15. The photoelectric conversion device according to any one of claims 1 to 14, wherein the main component of the first wiring pattern is copper.

16. The photoelectric conversion device according to any one of claims 1 to 15, wherein the first wiring pattern is disposed in a mesh shape in a region overlapping the pixel region.

17. The photoelectric conversion device according to any one of claims 1 to 16, wherein the electric circuit is a circuit that processes a signal from the pixel circuit.

18. A photoelectric conversion device according to any one of claims 1 to 17; A photoelectric conversion system comprising: a signal processing unit that processes a signal obtained by the photoelectric conversion device.

19. The photoelectric conversion device according to any one of claims 1 to 17, distance information acquisition means for acquiring distance information to an object based on a signal from the photoelectric conversion device, and control means for controlling a moving body based on the distance information, wherein the moving body is characterized by comprising the above.

Images