Mechanical Punching Via Formation in an Electronic Device Package and the Electronic Device Package Formed Thereby

Abstract

The electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer disposed on the first surface of the electrically insulating substrate, and an electrical component having a top surface bonded to the adhesive layer on an opposite surface of the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer by a mechanical punching operation at locations corresponding to the contact pads, each of the vias having via walls extending from the second surface of the electrically insulating substrate to a respective contact pad. In each via, the electrically insulating substrate includes a protrusion extending outward from its first surface to cover at least a portion of the adhesive layer when forming a portion of the via wall.

Description

Background Art

[0001] Embodiments of the present invention generally relate to structures and methods for packaging semiconductor devices, and more particularly, to a power electronics device package structure having vias formed by a mechanical punching operation, the vias providing for the formation of metal interconnects to power devices, such as by a power over - lay (POL) interconnect formation process.

[0002] Electronic packaging is a method of constructing an electronic circuit package or module in which one or more semiconductor devices and / or passive devices are incorporated into a package structure that provides electrical connection and protection to the devices, such that, for example, a "multi - chip module" (MCM) can be provided. The package structure then enables connection of the package / module to the surface of, for example, a printed circuit board (PCB) or other similar external circuit. An example of such an electronic device package structure is a power electronics device package structure or module formed using a POL process.

[0003] Techniques for packaging semiconductor devices and passive devices using a POL process typically begin by placing one or more semiconductor devices or passive devices on a dielectric layer by an adhesive, the dielectric layer covering the active side of each device. Before or after device attachment, vias are formed through the dielectric layer and the adhesive, and then metal interconnects are electroplated (i.e., metallized vias) on and within / through the vias in the dielectric layer to form direct metal connections to the devices. In embodiments where the device is a power semiconductor device, the metal interconnects may be formed as thicker POL interconnects. The interconnects may be routed through additional laminated redistribution layers, as needed, and an input / output system is provided to enable surface mounting of the package onto a PCB or external circuit. Then, an encapsulation compound can be applied around the devices to enclose them therein.

[0004] The formation of vias within the package structure may be performed according to any of several known techniques. In embodiments where the vias are formed before the attachment of electronic components, the vias may be formed through only the dielectric layer, or may be formed through both the dielectric layer and an adhesive layer applied thereto. In embodiments where vias are formed through only the dielectric layer, such as when fabricating a double-sided flex circuit, the vias may be formed by processes such as laser drilling or ablation, plasma etching, wet etching, water jet, photolithography, mechanical punching, or mechanical drilling. In embodiments where vias are formed through both the dielectric layer and the adhesive layer, the vias may be formed by processes such as laser drilling or ablation, plasma etching, wet etching, water jet, or photolithography, but mechanical punching and / or mechanical drilling are avoided due to problems of adhesive accumulation on the mechanical punching / drilling tools. Also, with regard to via formation using mechanical punching, it is recognized that mechanical punching is limited to "larger" via diameters and pitches.

[0005] In each of the above-described techniques currently used to form vias through a dielectric layer or through both a dielectric layer and an adhesive layer, there are drawbacks with respect to the throughput achievable using such a system / technique. That is, it has been recognized that using techniques such as laser drilling or ablation (for larger diameter vias), plasma etching, wet etching, water jet, or photolithography results in a lower throughput than that achievable by mechanical punching / drilling techniques. Further, when existing mechanical punching / drilling techniques are currently used, such techniques are not suitable for punching / drilling through both the dielectric layer and the adhesive layer. Rather, only the dielectric layer is punched / drilled, and then an adhesive must be applied to the dielectric layer, thereby also reducing / limiting the throughput rate. As semiconductor chip packaging technology continues to evolve, such limitations on throughput rate are considered a major obstacle.

[0006] Accordingly, it is desirable to provide a system / technique for forming vias that penetrate a dielectric layer and an adhesive layer and that provides high throughput. It is further desirable that such a system / technique provide a package structure in which the vias are free of burrs and in which ingress of the adhesive into the vias is restricted in order to provide a package structure having acceptable performance and reliability. SUMMARY OF THE INVENTION

[0007] According to one aspect of the present invention, an electronic device package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer disposed on the first surface of the electrically insulating substrate, and an electrical component having an upper surface coupled to the adhesive layer on the surface opposite to the electrically insulating substrate, the electrical component having one or more contact pads on the upper surface. One or more vias are formed through the electrically insulating substrate and the adhesive layer at positions corresponding to each of the one or more contact pads, and each of the one or more vias has a via wall extending from the second surface of the electrically insulating substrate to the respective contact pad. In each via, the electrically insulating substrate includes a protrusion extending outward from its first surface so as to cover at least a portion of the adhesive layer when forming a part of the via wall.

[0008] According to another aspect of the present invention, a method for manufacturing an electronic device package includes providing an electrically insulating substrate, applying or forming an adhesive layer on the first surface of the electrically insulating substrate, and forming one or more vias penetrating the electrically insulating substrate and the adhesive layer, wherein each of the one or more vias is defined by a via wall. The one or more vias are formed by mechanically punching one or more vias through the electrically insulating substrate and the adhesive layer using a mechanical punching tool, and the one or more vias are mechanically punched from the second surface side of the electrically insulating substrate, through the electrically insulating substrate, then through the adhesive layer, and through the electrically insulating substrate and the adhesive layer.

[0009] According to yet another aspect of the present invention, there is provided an electrical insulating substrate having a first surface and a second surface, an adhesive layer is applied or formed on the first surface of the electrical insulating substrate, and a mechanical punching tool disposed on the second surface side of the electrical insulating substrate is used to mechanically punch one or more vias through the electrical insulating substrate and the adhesive layer, thereby forming one or more vias through the electrical insulating substrate and the adhesive layer. An electronic device package is provided, each of the one or more vias being defined by a via wall. The mechanical punching of one or more vias through the electrical insulating substrate and the adhesive layer from the second surface side of the electrical insulating substrate forms protrusions on the electrical insulating substrate at each via extending outward from the first surface so as to cover at least a portion of the adhesive layer and form a portion of the via wall.

[0010] These and other advantages and features will be more readily understood from the following detailed description of the preferred embodiments of the invention provided in connection with the accompanying drawings.

Brief Description of the Drawings

[0011] The drawings illustrate embodiments currently contemplated for practicing the invention.

[0012] The drawings are as follows.

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Mode for Carrying Out the Invention

[0018] Embodiments of the present invention provide an electronic device package structure having vias formed by a mechanical punching operation. The electronic device package includes an electrical insulating substrate and an adhesive layer in which vias each defined by a via wall are formed. In each via, the electrical insulating substrate includes a protrusion extending outward from its surface around the periphery of the via and covering at least a part of the adhesive layer when forming a part of the via wall.

[0019] The various embodiments of the electronic device package referred to below are shown and described as including a particular arrangement of one or more semiconductor devices, vias, and interconnecting wirings, but alternative arrangements and configurations can also be implemented, and thus it is understood that the embodiments of the present invention are not limited only to the specifically shown devices and package structures. That is, it is understood that other combinations of electrical components of different configurations can be replaced within the electronic device package, and thus the embodiments of the present invention are not limited only to the illustrated embodiments. As used herein, the term "electrical component" may be understood to include any of the various types of semiconductor devices described above, as well as resistors, capacitors, inductors, filters, and other circuit devices, and it should be understood that mechanically punched vias can be used to interconnect any of these devices, as will be described in more detail below.

[0020] Referring now to FIG. 1, a schematic cross-sectional view of an electronic device package 10 including at least one electrical component 12 according to one embodiment is shown. The electrical component 12 can be a power semiconductor component or chip 12 (hereinafter described as such) having an active surface 14 with at least one contact pad or I / O pad 16, 18 thereon. The active surface 14 of the power semiconductor chip 12 is coupled to a first surface 20 of an electrical insulating substrate 22 or support substrate via an adhesive layer 24. According to various embodiments, the insulating substrate 22 may be provided in the form of an insulating film or dielectric substrate such as, for example, a Kapton(R) laminate flex, polyimide, epoxy, BT resin-containing organic film or substrate, but as non-limiting examples, Ultem(R), polytetrafluoroethylene (PTFE), or another polymer film such as a liquid crystal polymer (LCP) or polyimide substrate, or other suitable materials such as an inorganic substrate of Si, SiC, AlN, ceramic, or glass may also be used. The adhesive layer 24 is preferably composed of a bonding material that is a non-conductive polymer material (e.g., epoxy, liquid crystal polymer, ceramic or metal-filled polymer) or other organic material as non-limiting examples. Examples of suitable bonding materials include, for example, ePDA or other Henkel adhesives.

[0021] As shown in FIG. 1, at least one via 26 extends through the adhesive layer 24 between the first surface 20 and the second surface 28 of the insulating substrate 22, and two vias are shown in FIG. 1. Each via 26 is defined by a via wall 30. The vias 26 are aligned with the I / O pads 16, 18 of the power semiconductor chip 12. A conductive first interconnect layer 32 or power interconnect layer is disposed on a portion of the second surface 28 of the insulating substrate 22. The first interconnect layer 32 extends into the vias 26 to form conductive vias 34 and also extends over the I / O pads 16, 18 of the power semiconductor chip 12. In the illustrated embodiment, the power semiconductor chip 12 includes two I / O pads 16, 18 on the active surface 14. In some preferred embodiments, the I / O pad 16 is a gate pad and covers a smaller area than the I / O pad 18 which can be a source pad. In such an embodiment, the via 26 formed up to the gate I / O pad 16 can have a diameter of 300 micrometers, and the via 26 formed up to the source I / O pad 18 can have a diameter of 500 micrometers.

[0022] The power semiconductor chip 12 is shown in FIG. 1 as including two I / O pads 16, 18, but in some alternative embodiments, it may have three or more I / O pads, or in another alternative embodiment, it may include only one upper I / O pad. For example, the device 12 is a power diode. In alternative embodiments, the electrical component 12 is provided as a logic semiconductor chip, and the chip may have as few as four I / O pads, or may have ten, hundreds, or thousands or more I / O pads. In another alternative embodiment, the electrical component 12 is provided as a resistor, capacitor, or feed-through via, for example, which can have one contact pad or a plurality of contact pads.

[0023] The first interconnect layer 32 is a conductive material and preferably consists of one or more metals such as, by way of non-limiting example, aluminum, copper, gold, silver, nickel, or combinations thereof, i.e., metallization vias. Alternatively, the first interconnect layer 32 may be a conductive polymer or may be formed using an ink containing conductive metal particles. The first interconnect layer 32 can be composed of a barrier or adhesion layer, a seed layer, and a relatively thick layer of bulk material plated over the seed layer and barrier layer to achieve the desired thickness of the conductive layer. In an alternative embodiment, the barrier layer and / or the seed layer may be omitted from the first interconnect layer 32. The barrier layer, when used, is applied to the insulating substrate 22 prior to the application of the seed layer and bulk material. The barrier layer can include, by way of non-limiting example, titanium or chromium. When used, the seed metal layer may be a conductive material such as, by way of non-limiting example, copper. The layer of bulk material is plated to achieve the desired thickness of the first interconnect layer 32. The bulk material portion of the first interconnect layer 32 includes at least one conductive material such as copper, aluminum, or other standard wiring materials. In some embodiments, the barrier layer may have a thickness in the range of about 0.1 to 0.4 microns, the seed metal layer may have a thickness in the range of about 1 to 3 microns, and the bulk layer may have a thickness in the range of about 10 to 100 microns. However, other materials of other thicknesses can be used to form the first interconnect layer 32 based on the design requirements.

[0024] In some embodiments, a solder mask layer or other insulating material 36 can be applied over the exposed top surfaces of the first interconnect layer 32 and the insulating layer 22 to provide a protective coating and define the locations of the interconnect pads. Next, a capping layer 38 can be applied over the top surfaces of these interconnect pads (e.g., an electroless Ni / Au or ENIPG) to provide a solderable and wire bondable finish. Next, a series of input / output (I / O) connections 40 are formed to provide a path for electrical connection between the power semiconductor chip 12 and an external component (not shown), such as a bus bar or a printed circuit board (PCB). Such I / O connections may be provided, by way of non-limiting example, in the form of plated bumps or pillar bumps.

[0025] Although not shown in FIG. 1, it is recognized that when the electronic device package 10 is a power module, a DBC substrate can be attached to the back surface of the power semiconductor chip 12. Next, an encapsulating material or an insulating material may be used to underfill between the insulating substrate 22 and the DBC substrate. It is also recognized that additional insulating layers and interconnect layers, such as a second insulating layer and a second interconnect layer, can be provided within the electronic device package 10. Such insulating layers and interconnect layers can be applied over the first interconnect layer 32 to provide further redistribution of electrical connections between the power semiconductor chip 12 and the external components.

[0026] A more detailed view of via 26 formed through insulating substrate 22 and adhesive layer 24 is shown in FIG. 2. As can be seen in FIG. 2, the formation of via 26 through insulating substrate 22 and adhesive layer 24 results in deformation of insulating substrate 22. At a position corresponding to each of vias 26, insulating substrate 22 includes a protrusion or “tooth” artifact 42 that extends outwardly from first surface 20 of insulating substrate 22 toward adhesive layer 24, and protrusion 42 is formed around the perimeter of punched via 26. According to an embodiment of the present invention, protrusion 42 may extend outwardly from first surface 20 so as to cover all, substantially all, or most of adhesive layer 24 when forming at least a portion of via wall 30. For example, protrusion 42 may extend outwardly from first surface 20 so as to cover 50% or more of thickness 44 of adhesive layer 24, and for example, the thickness of adhesive layer 24 is from 5 to 50 micrometers. Thus, via wall 30 may be entirely formed from insulating substrate material or may be substantially formed from insulating substrate material. Protrusion 42 functions as a dam to prevent the flow or intrusion of adhesive into via 26, thereby enabling the formation of via 26 having a consistent shape and preventing adhesive intrusion from reducing the via metal contact area, and thus providing a more robust and reliable metal connection to I / O pads 16, 18.

[0027] Referring now to FIGS. 3 - 15, techniques for manufacturing the electronic device package 10 of FIG. 1 according to embodiments of the present invention are shown. To facilitate visualization of the build-up process, cross-sections of the build-up process for a single electronic device package 10 are shown in each of FIGS. 3 - 15. However, one of ordinary skill in the art will recognize that multiple electronic device packages can be manufactured in a similar manner at the panel level and then isolated into individual electronic device packages as needed.

[0028] Referring initially to FIG. 3, the manufacture of the electronic device package 10 begins by securing the insulating substrate 22 onto the surrounding frame 46 that provides support during the construction of the electronic device package 10, and it is recognized that the frame 46 can hold an array of multiple electronic device packages for batch processing.

[0029] Once the insulating substrate 22 is secured onto the surrounding frame 40, as shown in FIG. 4, an adhesive layer 24 (i.e., a layer of bonding material) is applied to the first surface 20 of the insulating substrate 22. In the illustrated embodiment, the adhesive layer 24 is applied so as to cover the entire first surface 20. In an alternative embodiment, the adhesive layer 24 may be applied so as to cover only selected portions of the first surface 20 of the insulating substrate 22. The adhesive layer 24 may be applied using, as non-limiting examples, a lamination or spray process, or by using coating techniques such as spin coating or slot die coating. Although the adhesive layer 24 is illustrated / described as being applied to the first surface 20 of the insulating substrate, according to embodiments of the present invention, it is recognized that the adhesive layer 24 may instead be applied to the second surface 28 of the insulating substrate 22, i.e., in either a “frame up” or “frame down” configuration.

[0030] Once the adhesive layer 24 is applied, as shown in FIG. 5, a release liner 48 is applied over the adhesive. The release liner 48 provides for subsequent steps of via formation that penetrate the insulating substrate 22 and the adhesive layer 24, as will be described in more detail below.

[0031] Referring now to FIGS. 6 and 7, once the adhesive layer 24 and the release liner 48 are applied, the method continues by forming vias 26 that penetrate the insulating substrate 22 and the adhesive layer 24 (and the release liner 48). The size, shape, and location of the vias 26 are determined based on the design of the power circuit, as well as the location, size, and current requirements of the electrical components to be included in the electronic device package, such as the power semiconductor chip 12 (FIG. 1) or other logic chips or passive devices.

[0032] According to an exemplary embodiment, via 26 is formed by a mechanical punching tool 50 that operates to punch through layers 22, 24, 48, thereby forming the via. As shown in FIG. 6, the mechanical punching tool 50 is disposed adjacent to the second surface 28 of the insulating substrate 22 (to which the frame is attached) such that the via 26 is punched from the insulating substrate side, i.e., first through the insulating substrate 22 and then through the adhesive layer 24 and the release liner 48. The mechanical punching tool 50 is shown in FIG. 6 as including only a single punch 52 that moves relative to the electronic device package 10 to form the via 26 at a desired location in one pass (as shown by arrow 54, the mechanical punching tool 50 is moved in perspective to the next location), but the punching tool 50 may be a multi-punching tool that forms multiple vias 26 simultaneously, an example of which will be described later. Further, although the mechanical punching tool 50 is shown and described below as being arranged to punch through the insulating substrate 22, the adhesive layer 24, and the release liner 48, it is recognized that the mechanical punching tool 50 may be arranged to punch through the insulating substrate 22, the adhesive layer 24, and the release liner 48 depending on whether a "frame up" or "frame down" configuration is used.

[0033] As further shown in FIG. 6, on the opposite side of the electronic device package 10, adjacent to the release liner 48, one or more dies 56 are disposed that interact with the punching tool 50 to provide stability during via formation. The die 56 includes a hollow central region 58 that is aligned with the punching tool 50 at a location where it is desired to form the via 26.

[0034] As shown in FIG. 7, the mechanical punching tool 50 is operated to form vias 26 that penetrate layers 22, 24, 48, and the punch 52 is actuated downward to penetrate the insulating substrate 22, the adhesive layer 24, and the release liner 48. According to one embodiment, the punch 52 is configured to form a via 26 shaped as a straight circular hole, but it is recognized that the via 26 can have other alternative configurations such as a circular via with inclined sides or vias of different shapes such as elliptical, square, or triangular. When the punch 52 is actuated to punch through layers 22, 24, 48, a (layer) plug 60 cut from the via location is punched out and exits through the hollow central region 58 of the die 56.

[0035] Forming the via 26 by punching from the insulating substrate side causes not only the removal of the plug 60 but also further deformation of the insulating substrate 22 in the region corresponding to the via 26. That is, at the position corresponding to each via 26, as shown in FIG. 2, the insulating substrate material is pushed downward by the punch 52 to form a protrusion 42 (tooth artifact) that extends outward from the first surface 20 of the insulating substrate 22 toward the adhesive layer 24. According to an embodiment of the present invention, the protrusion 42 may extend outward from the first surface 20 so as to cover all or substantially all (e.g., more than 50% of the thickness 44 of the adhesive layer 24) of the adhesive layer 24 when forming at least a part of the via wall 30. Thus, the via wall 30 may be entirely formed from the insulating substrate material or may be substantially formed from the insulating substrate material. The protrusion 42 functions as a dam around the via 26 that prevents / minimizes the flow or intrusion of adhesive into the via.

[0036] As described above, the size of via 26 can be determined based on the design of the electronic device package 10 and the requirements of electrical components included in the electronic device package such as the power semiconductor chip 12 (FIG. 1) or other logic chips or passive devices. For example, in an embodiment where the power semiconductor chip 12 includes gate I / O pads 16 and source I / O pads 18, the via 26 formed up to the gate I / O pad 16 can have a diameter of 300 micrometers, and the via 26 formed up to the source I / O pad 18 can have a diameter of 500 micrometers. In an embodiment where the logic semiconductor chip 12 includes I / O pads with a narrower pitch, the via 26 formed up to these pads can have a diameter of, for example, 80 to 100 micrometers. In such smaller vias 26, it is recognized that a follow-up laser drilling operation (not shown) may be desirable to form a via 26 of appropriate quality (e.g., deburring, etc.) when the diameter of the via is small following the punching of the via 26.

[0037] Referring now to FIG. 8, during the formation of via 26, the release liner 48 is removed from the adhesive layer 24, the power semiconductor chip 12 is attached to the adhesive layer 24, and cured in place. The active surface 14 of the power semiconductor chip 12 is attached to the adhesive layer 24 such that the I / O pads 16, 18 face the adhesive layer 24 and the insulating substrate 22. The second surface 28 of the insulating substrate 22, the via 26, and the exposed regions of the I / O pads 16, 18 are then cleaned by, for example, reactive ion etching (RIE), plasma etching, or chemical etching, and a desmear process is performed.

[0038] Although not shown in FIG. 8, after the curing of the adhesive layer 24, a laser drilling step can be subsequently performed using known techniques to form finer vias (e.g., having a diameter <50 micrometers) to provide connections to devices such as digital ASICs or driver circuits having a finer pad pitch or even smaller pad sizes, and it is recognized that mechanical punching cannot be accommodated.

[0039] The manufacturing process continues by forming and patterning a first interconnect layer 32. According to one embodiment, as shown in FIGS. 9-12, the first interconnect layer 32 is formed using semi-additive plating technology. The manufacture of the first interconnect layer 32 begins in FIG. 9 by applying a seed metal 62 to a second surface 28 of the insulating substrate 22, a via wall 30 of the via 26, and exposed portions of the I / O pads 16, 18. The seed metal 62 can be applied by sputtering, evaporation, electroless plating, or any other standard metal deposition process. An optional barrier coating (not shown) can be applied prior to the seed metal 62 to enhance adhesion and reliability. When used, the barrier metal may likewise be applied by sputtering, evaporation, or any other standard metal deposition process.

[0040] As shown in FIG. 10, a photoresist mask 64 is applied over the seed metal 62 and photopatterned to form openings. The photoresist mask 64 can be applied by spray coating, spin coating, or electroplating (electrophoretic resist). In the next step of the manufacturing process shown in FIG. 11, the exposed regions of the seed metal 62 are patterned with a bulk material (e.g., copper) by electroplating technology until the first interconnect layer 32 reaches the desired thickness.

[0041] Referring now to FIG. 12, after the patterned plating of the first interconnect layer 32, the remaining photoresist mask 64 is removed using a stripping technique to expose the portions remaining below the unplated seed metal 62, and the exposed portions of the seed metal 62 are removed by a subtractive etching process or the like, leaving the completed first interconnect layer 32. The first interconnect layer 32 may then be capped by a capping layer 38 such as an electroless nickel / immersion gold (ENIG) or electroless nickel / palladium / gold (ENIPG) to provide a solderable and wire bondable finish.

[0042] According to another embodiment, the first interconnect layer 32 is formed using a subtractive process as shown in FIGS. 13-15. When performing the subtractive process, the fabrication of the first interconnect layer 32 begins in FIG. 13 by applying a seed metal 62 to the second surface 28 of the insulating substrate 22, the via walls 30 of the vias 26, and the exposed portions of the I / O pads 16, 18. The seed metal 62 can be applied by sputtering, evaporation, electroless plating, or any other standard metal deposition process. Optionally, a barrier coating (not shown) can be applied prior to the seed metal 62 to enhance adhesion and reliability. If used, the barrier metal may likewise be applied by sputtering, evaporation, or any other standard metal deposition process.

[0043] Next, as shown in FIG. 14, the seed metal 62 is plated with a bulk material (e.g., copper) by an electroplating technique until the first interconnect layer 32 reaches the desired thickness. After completion of the plating process, a portion of the first interconnect layer 32 is selectively removed using a subtractive etching process, resulting in the selectively patterned and completed first interconnect layer 32 as shown in FIG. 15. Next, the first interconnect layer 32 may be capped with a capping layer such as electroless E-free Ni / Au or ENIPG to provide a solderable and wire bondable finish.

[0044] The semi-additive manufacturing technique described with reference to FIGS. 9-12 and the subtractive manufacturing technique described with reference to FIGS. 13-15 show only two exemplary techniques for manufacturing the first interconnect layer 32, and it should be understood that any known metallization and patterning techniques can be used. In yet other embodiments, the first interconnect layer 32 is a printed conductive material formed using deposition techniques such as, by way of non-limiting example, inkjet printing, screen printing, or dispensing. In yet another alternative embodiment, the manufacture of the electronic device package 10 can be initiated by providing an insulating substrate 22 that includes a pre-plated layer of conductive material.

[0045] Although not shown in the techniques of FIGS. 3-15, the manufacturing technique of the electronic device package 10 can further include the application / formation of additional insulating layers and interconnect layers that provide further redistribution of the electrical connections between the power semiconductor chip 12 and external components. Further, as shown in FIG. 1, one or more encapsulating materials or insulating materials can be implemented over the sides and back of the power semiconductor chip 12, and / or over the exposed top surfaces of the first interconnect layer 32 and the insulating layer 22, and / or a series of input / output (I / O) connections can be formed to provide a path for electrical connection between the power semiconductor chip 12 and external components.

[0046] Referring now to FIG. 16, shown is the use of a multi-punch mechanical punching tool 50 operable to simultaneously form a plurality of vias 26 in a single mechanical punching operation, according to another embodiment of the present invention. The multi-punch punching tool 50 includes a plurality of punches 52 that can be actuated simultaneously to punch through layers 22, 24, 48 to form vias 26. The multi-punch punching tool is shown as including two punches 52 in FIG. 16, although it will be recognized that a greater number (e.g., 3, 4, etc.) of punches 52 can be used. On the opposite side of the electronic device package 10, adjacent to the release liner 48, a die 56 is disposed that interacts with the multi-punch punching tool 50 to provide stability during via formation. Each of the dies 56 includes a hollow central region 58 that is aligned with a respective punch 52 of the punching tool 50 at a location where it is desired to form a via 26. According to one embodiment, a punching mold or "stripper" 66 is disposed on the second surface 28 side of the insulating substrate 22. The punching mold 66 functions to hold the electrical insulating substrate 22 during punching and also enables improved alignment of the punches 52 with respect to the dies 56.

[0047] During operation, the punches 52 are actuated downward simultaneously to punch through the insulating substrate 22, the adhesive layer 24, and the release liner 48. When the punches 52 are actuated to punch through layers 22, 24, 48, a (layer) plug 60 cut from the via location is punched out and exits through the hollow central region 58 of the die 56, and the resulting via 26 / via wall 30 has a structure as shown in FIG. 2 (i.e., the protrusion 42 is formed on the insulating substrate 22 extending outwardly from the first surface 20 so as to cover all or substantially all of the adhesive layer 24). Using such a multi-punch mechanical punching tool 50, the manufacturing throughput of the electronic device package 10 can be further increased as compared to the use of a mechanical punching tool 50 that includes only a single punch (FIG. 1).

[0048] Referring now to FIG. 17, an embodiment of the present invention is shown in which a laser drilling step is performed after via formation using mechanical punching to provide formation of vias of smaller diameter as may be required to provide connections to devices such as digital ASICs or driver circuits having finer pad pitches or even smaller pad sizes. That is, after formation of via 26 by mechanical punching tool 50 (FIGS. 6 and 7), the mechanical punching tool 50 is removed and a separate laser drilling tool 68 is added, having the laser drilling tool 68 (and the state where punching tool 50 is removed) shown in FIG. 17. After attachment of the power and logic device 12 and curing of the adhesive layer 24, a laser drilling step is performed using the laser drilling tool 68 to create finer vias 70 (e.g., having a diameter <50 micrometers).

[0049] Thus, advantageously, embodiments of the present invention provide an electronic device package having vias formed by a mechanical punching operation. Forming vias from the substrate side of the package by a mechanical punching operation through both the insulating substrate and the adhesive layer results in improved throughput and yield in the manufacture of electronic device packages as compared to prior art processes. The manufactured electronic device package includes an electrically insulating substrate and an adhesive layer in which vias, each defined by a via wall, are formed, and in each via, the electrically insulating substrate includes a protrusion extending outwardly from its surface and covering at least a portion of the adhesive layer when forming a portion of the via wall. These protrusions have a consistent shape and function as dams to prevent the flow or intrusion of adhesive into the vias, enabling more stable via formation at high temperatures.

[0050] Accordingly, according to one embodiment of the present invention, an electronic device package includes an electrical insulating substrate having a first surface and a second surface, an adhesive layer disposed on the first surface of the electrical insulating substrate, and an electrical component having an upper surface bonded to the adhesive layer on the surface opposite to the electrical insulating substrate, the electrical component having one or more contact pads on the upper surface. One or more vias are formed through the electrical insulating substrate and the adhesive layer at positions corresponding to each of the one or more contact pads, and each of the one or more vias has a via wall extending from the second surface of the electrical insulating substrate to the respective contact pad. In each via, the electrical insulating substrate includes a protrusion extending outward from its first surface so as to cover at least a part of the adhesive layer when forming a part of the via wall.

[0051] According to another embodiment of the present invention, a method for manufacturing an electronic device package includes providing an electrical insulating substrate, applying or forming an adhesive layer on the first surface of the electrical insulating substrate, and forming one or more vias penetrating the electrical insulating substrate and the adhesive layer, wherein each of the one or more vias is defined by a via wall. The one or more vias are formed by mechanically punching the one or more vias through the electrical insulating substrate and the adhesive layer using a mechanical punching tool, and the one or more vias are mechanically punched through the electrical insulating substrate and the adhesive layer from the second surface side of the electrical insulating substrate, through the electrical insulating substrate, and then through the adhesive layer.

[0052] According to yet another embodiment of the present invention, there is provided an electrical insulating substrate having a first surface and a second surface, applying or forming an adhesive layer on the first surface of the electrical insulating substrate, and using a mechanical punching tool disposed on the second surface side of the electrical insulating substrate to mechanically punch one or more vias through the electrical insulating substrate and the adhesive layer to form one or more vias through the electrical insulating substrate and the adhesive layer. An electronic device package is provided, each of the one or more vias being defined by a via wall. The mechanical punching of the one or more vias through the electrical insulating substrate and the adhesive layer from the second surface side of the electrical insulating substrate forms protrusions on the electrical insulating substrate in each via extending outward from the first surface so as to cover at least a portion of the adhesive layer and form a portion of the via wall.

[0053] Although the present invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the present invention is not limited to such disclosed embodiments. Rather, the present invention can be modified to incorporate any number of variations, alternatives, substitutions or equivalent configurations that have not heretofore been described but are commensurate with the spirit and scope of the present invention. Further, although various embodiments of the present invention have been described, it should be understood that aspects of the present invention may include only a portion of the described embodiments. Accordingly, the present invention should not be regarded as limited by the foregoing description, but only by the appended claims.

Claims

1. An electronic device package (10), comprising: an electrical insulating substrate (22) having a first surface (20) and a second surface (28); an adhesive layer (24) disposed on the first surface (20) of the electrical insulating substrate (22); an electrical component (12) having an upper surface (14) coupled to the adhesive layer (24) on a surface opposite to the electrical insulating substrate (22), the electrical component (12) having one or more contact pads (16, 18) on the upper surface (14); one or more vias (26) are formed through the electrical insulating substrate (22) and the adhesive layer (24) at positions corresponding to each of the one or more contact pads (16, 18), and each of the one or more vias (26) has a via wall (30) extending from the second surface (28) of the electrical insulating substrate (22) to the respective contact pad (16, 18); In each via (26), the electrical insulating substrate (22) includes a protrusion (42) extending outward from the first surface (20) thereof so as to cover at least a part of the adhesive layer (24) when forming a part of the via wall (30). The electronic device package (10).

2. The protrusion (42) is formed around the via and extends outward from the first surface (20) of the electrical insulating substrate (22) so as to cover all or substantially all of the adhesive layer (24) as a part of the via wall (30). The electronic device package (10) according to claim 1.

3. The protrusion (42) covers at least 50% of the thickness of the adhesive layer (24) as a part of the via wall (30). The electronic device package (10) according to claim 2.

4. The diameter of each of the one or more vias (26) is 80 micrometers or more. The electronic device package (10) according to claim 1.

5. The protrusion (42) blocks the flow of the adhesive layer (24) into the via (26). The electronic device package (10) according to claim 1.

6. The electronic device package (10) according to claim 1, further comprising an interconnect layer (32) formed on the second surface (28) of the electrical insulating substrate (22) and within the one or more vias (26), the interconnect layer (32) being electrically coupled to the one or more contact pads (16, 18) of the electrical component (12).

7. A method for manufacturing an electronic device package (10), comprising: providing an electrical insulating substrate (22); applying or forming an adhesive layer (24) on a first surface (20) of the electrical insulating substrate (22); forming one or more vias (26) that penetrate the electrical insulating substrate (22) and the adhesive layer (24), each of the one or more vias (26) being defined by a via wall (30); wherein forming the one or more vias (26) includes mechanically punching the one or more vias (26) through the electrical insulating substrate (22) and the adhesive layer (24) using a mechanical punching tool (50); wherein the one or more vias (26) are mechanically punched through the electrical insulating substrate (22) and the adhesive layer (24) from a second surface (28) side of the electrical insulating substrate (22), through the electrical insulating substrate (22), and then through the adhesive layer (24).

8. The method according to claim 7, wherein mechanically punching the one or more vias (26) through the electrical insulating substrate (22) and the adhesive layer (24) from a second surface (28) side of the electrical insulating substrate (22) includes forming a protrusion (42) on the electrical insulating substrate (22) around each via (26), the protrusion (42) covering at least a portion of the adhesive layer (24) and forming a portion of the via wall (30), and extending outward from a first surface (20) of the electrical insulating substrate (22).

9. The method according to claim 8, wherein the protrusion (42) extends outward from a first surface (20) of the electrical insulating substrate (22) so as to cover all or substantially all of the adhesive layer (24) as a portion of the via wall (30).

10. The method according to claim 8, wherein the protrusion (42) blocks the flow of the adhesive layer (24) into the via (26).

11. The method according to claim 7, further comprising laser drilling at least some of the one or more vias (26) after forming the one or more vias (26) using the mechanical punching.

12. Further comprising laser drilling an additional via (26) through the electrical insulating substrate (22), the additional via (26) being formed by laser drilling having a diameter smaller than the diameter of the one or more vias (26) mechanically punched through the electrical insulating substrate (22), the method according to claim 7.

13. Further comprising applying a release liner (48) to the adhesive layer (24) on the surface opposite the electrical insulating substrate (22), the one or more vias (26) being mechanically punched through the electrical insulating substrate (22), the adhesive layer (24), and the release liner (48), and the release liner (48) being removed after forming the one or more vias (26) using the mechanical punching, the method according to claim 7.

14. Placing one or more punch dies (56) on the surface of the release liner (48) opposite the adhesive layer (24), each of the one or more punch dies (56) being aligned with a respective via to be formed, the placing; Attaching a frame (40) to the second surface (28) side of the electrical insulating substrate (22); The method according to claim 13, further comprising.

15. Bonding the upper surface (14) of the electrical component (12) to the surface of the adhesive layer (24) opposite the electrical insulating substrate (22), the electrical component (12) having one or more contact pads (16, 18) on the upper surface (14), the bonding; Forming an interconnect layer (32) on the second surface (28) of the electrical insulating substrate (22) and within the one or more vias (26), the interconnect layer (32) being electrically coupled to the one or more contact pads (16, 18) of the electrical component (12), the forming; Further comprising, The one or more vias (26) being formed at positions corresponding to each of the one or more contact pads (16, 18), the method according to claim 7.

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