Subtractive metals and subtractive metal semiconductors

Abstract

Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and processes for forming such semiconductor structures and interconnects. In one embodiment, a process for manufacturing a semiconductor structure is provided. The process includes performing a degassing process on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputtering process on the semiconductor structure and depositing a metal layer on the liner layer by physical vapor deposition, the liner layer including Ti, Ta, TaN, or a combination thereof, and the resistivity of the metal layer is about 30 μΩ·cm or less.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and processes for forming such semiconductor structures and interconnects.

Background Art

[0002] An interconnect is a structure that electrically connects circuit elements. Conventionally, on-chip interconnects have been fabricated by a damascene process in which vias are formed through various layers of a device structure, the vias are filled with a conductive material such as copper, and interconnects between the layers and between the features of the devices located in the individual layers are formed. However, the copper damascene process may not be practical for chips having feature sizes less than 50 nm. For example, as the line width decreases due to grain boundary scattering, the resistance of the metal increases, and the risk of electromigration increases in Cu interconnects with thin lines. To overcome this problem, subtractive metals including tungsten (W) and other metal interconnects have been proposed. The fabrication of such interconnects typically involves depositing a W layer on a metal etch stop / liner layer (e.g., TiN), followed by subtractive etching of the W layer and the TiN layer, and filling the newly formed metal trench with a dielectric material. However, the W and other metals deposited on TiN have a resistivity that is high, e.g., 40 μΩ·cm or more.

[0003] There is a need for improved subtractive metal semiconductor structures, subtractive metal interconnects, and processes for forming them.

Summary of the Invention

[0004] Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and processes for forming such semiconductor structures and interconnects.

[0005] In one embodiment, a process for manufacturing a semiconductor structure is provided. The process includes performing a degassing process on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputtering process on the semiconductor structure and depositing a metal layer on the liner layer by physical vapor deposition, where the liner layer includes Ti, Ta, TaN, or a combination thereof, and the resistivity of the metal layer is about 30 μΩ·cm or less.

[0006] In another embodiment, a process for manufacturing a semiconductor structure is provided. The process includes performing a degassing process on the semiconductor structure and depositing an etch stop layer on the semiconductor structure by physical vapor deposition after the degassing process. The process further includes performing a sputtering process on the semiconductor structure and depositing a metal layer on the semiconductor structure by physical vapor deposition after the sputtering process is performed.

[0007] In another embodiment, a process for manufacturing an interconnect structure is provided. The process includes performing a degassing process on a semiconductor structure, where the semiconductor structure includes a dielectric material and a via hole that is at least partially filled with a metal material. The process further includes depositing an etch stop layer on the semiconductor structure by chemical vapor deposition after the degassing process. The process further includes depositing a metal layer on the semiconductor structure by physical vapor deposition after the deposition of the etch stop layer to form an interconnect structure.

[0008] To better understand the above features of the present disclosure in detail, a more detailed description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show exemplary embodiments and should not be considered as limiting the scope, and other equally valid embodiments may also be acceptable.

Brief Description of the Drawings

[0009]

Figure 1A

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DETAILED DESCRIPTION OF THE INVENTION

[0010] For ease of understanding, where possible, the same reference numbers are used to denote the same elements common to the drawings. It is contemplated that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further recitation.

[0011] Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and processes for forming such semiconductor structures and interconnects. The inventors have found, for example, a new and improved etch stop material / liner material on which a low resistivity metal layer can be actively formed. The inventors have also found a new and improved process that can modify one or more properties of a conventional etch stop material / liner material (e.g., TiN) such that the metal layer formed thereon has a low resistivity. The inventors have also found a new and improved process that enables selective deposition of an etch stop liner material such that the metal layer formed thereon has a low resistivity.

[0012] Line resistance and via resistance are important characteristics for interconnects. As described above, conventional materials for forming small feature size interconnects using subtractive processes exhibit too high a resistivity. In addition, metal etch stop materials / liner materials useful in such subtractive processes need to ensure adhesion between the dielectric material and the metal material of the semiconductor structure to avoid delamination, and also need to sufficiently prevent etching from reaching vias in the underlying layer and / or other features of the semiconductor structure. The embodiments described herein enable materials to meet these and other requirements.

[0013] FIG. 1A is an example of a processing chamber 50 useful for carrying out one or more processes described herein. The processing chamber 50 includes a vacuum chamber 52 disposed around a central axis 54. A target 56 providing a source of sputtered metal is on the central axis 54 and is supported through an isolator 58. The isolator 58 seals the target 56 from the vacuum chamber 52 and electrically insulates the target 56 from the electrically grounded vacuum chamber 52. A DC power source 60 applies a negative bias to the target 56 with respect to the grounded vacuum chamber 52 to excite the plasma processing gas into a plasma. The plasma processing gas can be any suitable non-reactive gas such as He, Ne, Ar, Kr, Xe, N 2 , or a combination thereof. The plasma processing gas is supplied from a gas source 62 into the vacuum chamber 52 via a mass flow controller 64. The target power excites the plasma processing gas into a plasma, and the ions of the plasma are accelerated towards the target 56 from which metal atoms are sputtered. The density of the plasma can be increased by disposing a magnetron 66 having an inner pole 68 surrounded by an outer pole 70 of opposite magnetic polarity. The poles 68, 70 project a magnetic field parallel to the surface of the target 56 within the vacuum chamber 52 to trap electrons, thereby increasing the plasma density and the resulting sputtering rate. The poles 68, 70 are supported on an arm 72 connected to a shaft 74 extending along the central axis 54. A motor 76 rotates the shaft 74 and the magnetron 66 about the central axis 54 to provide, for example, azimuthal uniformity.

[0014] A pedestal 80 within the vacuum chamber 52 supports a substrate 82 facing the target 56. An RF power source 84 biases the pedestal 80 via a capacitive coupling circuit 86. The RF bias in the presence of the plasma within the vacuum chamber 52 generates a negative DC self-bias on the pedestal 80, as a result of which the sputtered metal ions are accelerated towards the substrate 82 and their trajectories enter deep into the high aspect ratio holes formed in the substrate 82.

[0015] The processing chamber 50 may be part of a cluster tool. The cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can store a robot capable of reciprocally transporting substrates between the processing chamber and the load lock chamber. The transfer chamber is typically maintained under reduced pressure conditions and provides an intermediate stage for reciprocating substrates from one chamber to another and / or to a load lock chamber disposed at the front end of the cluster tool. An example of a cluster tool that can be adapted to the present disclosure is the Endura® cluster tool available from Applied Materials, Inc., Santa Clara, California, USA. However, the exact arrangement and combination of the chambers can be changed for the purpose of performing specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or other substrate processing. By performing the process within a chamber on the cluster tool, surface contamination of the substrate by impurities in the air can be avoided without oxidizing prior to depositing subsequent films.

[0016] Figure 1B is an example of a cluster tool 100 that can be used to implement one or more processes described herein. The cluster tool 100 includes central transfer stations 121, 131 with multiple sides. Robots 125, 135 are positioned within the central transfer stations 121, 131 and are configured to move robot blades between the processing chambers 102, 104, 106, 108, 110, 112, 114, 116, and 118 and the transfer chambers 122 and 124. The processing chambers 102, 104, 106, 108, 110, 112, 114, 116, and 118 provide separate processing areas isolated from adjacent processing stations. The cluster tool 100 can include one or more PVD chambers, one or more CVD chambers, and / or other chambers connected to the central transfer station. At least one of the processing chambers 102, 104, 106, 108, 110, 112, 114, 116, and 118 is the processing chamber 50. A factory interface 150 is connected to the load lock chambers 160, 162. The factory interface 150 includes a loading chamber 154 and an unloading chamber 156. A robot 152 transfers substrates from the loading chamber 154 to the load lock chamber 160 and from the load lock chamber 162 to the unloading chamber 156.

[0017] Controller 190 communicates with and controls robots 125, 135, and processing chambers 102, 104, 106, 108, 110, 112, 114, 116, and 118. Controller 190 can be a computer including a central processing unit (CPU) 192, a memory 194, an input / output (I / O) 196, and a support circuit 198. The memory 194 of controller 190 or a computer-readable medium can be one or more of readily available memories such as non-transitory memory (e.g., random access memory (RAM)), read-only memory (ROM), floppy disks, hard disks, optical storage media (e.g., compact disks or digital video disks), flash drives, or any other form of digital storage, local or remote. The memory 194 can hold an instruction set operable by a processor (e.g., CPU 192) to control the parameters and components of cluster tool 100. Support circuit 198 is connected to CPU 192 to assist the processor in a conventional manner. One or more operations of the processes described herein can be stored in memory 194 as software routines that, when executed by a processor, cause the processor to control the operation of cluster tool 100 or individual processing units in the manner described herein.

[0018] Embodiments of the present disclosure generally relate to a new and improved liner layer and a process for forming such a liner layer. FIG. 2 shows a semiconductor structure 200 with a liner layer 206 disposed on a substrate 202. The substrate 202 can be any suitable material, such as, for example, a dielectric material, particularly silicon, germanium, quartz, and glass, or can include them. The semiconductor structure 200 can be used in a reactive ion etching (RIE) process to remove at least a portion of a metal layer 210 when forming an interconnect structure.

[0019] In some embodiments, the liner layer 206 comprises any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or combinations thereof. In at least one embodiment, the liner layer 206 has a thickness of about 50 Å or less, such as about 30 Å or less, such as about 25 Å or less, such as about 20 Å or less, such as about 15 Å or less, such as about 10 Å or less, such as about 5 Å or less. In some embodiments, the metal layer 210 comprises any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or combinations thereof. The metal layer 210 can have a resistivity of about 40 μΩ·cm or less, such as about 35 μΩ·cm or less, such as about 30 μΩ·cm or less, such as about 25 μΩ·cm or less, such as about 20 μΩ·cm or less, such as about 15 μΩ·cm or less, such as about 10 μΩ·cm or less, such as about 5 μΩ·cm or less. The resistance values provided herein are measured using a four-point probe. The liner layer 206 and the metal layer 210 can be formed, for example, by process 305 (FIG. 3B) or process 355 (FIG. 3D) discussed below.

[0020] The liner layer 206 described herein represents a new material useful as a liner layer. Further, the metal layer 210 deposited thereon has an improved resistivity compared to conventional metal layers deposited on a conventional TiN liner.

[0021] Conventional metal liners typically exhibit a resistivity exceeding 40 μΩ·cm. Such a high resistivity is due to the crystalline structure of the TiN liner, where the metal layer grows into small particles with a size of less than about 100 nm. Additionally, conventional PVD deposition of thin (e.g., about 20 Å or less) liners / etch stop layers such as TiN-containing layers is difficult because nucleation sites are generated during deposition. Furthermore, when performing conventional CVD deposition of thin liners / etch stop layers, impurities may be introduced. Such nucleation sites and impurities in the liner can cause the metal layer to have high line resistance and high via resistance. In contrast, the embodiments described herein enable the deposition of a low-resistivity metal layer 210 (e.g., about 40 μΩ·cm or less) onto the liner layer 206. Furthermore, little or no metal interdiffusion is observed in the liner layer 206.

[0022] Embodiments of the present disclosure generally also relate to a process for improving conventional materials such as TiN used as a liner / etch stop layer. Briefly, in some embodiments, the process can be used to treat a conventional etch stop layer made of, for example, TiN such that the subsequently deposited metal layer has an improved resistivity. Additionally, or alternatively, the process can be used to treat a metal seed layer deposited on a conventional etch stop layer such that the resistivity of the subsequently deposited metal layer is improved over the prior art.

[0023] FIG. 3A shows a semiconductor structure 300 in which a metal layer 303 is disposed on an etch stop layer 302. The etch stop layer 302 is disposed on a substrate 301. The substrate 301 is any suitable material, such as, for example, a dielectric material, especially silicon, germanium, quartz, and glass, or can include them. In some embodiments, when an interconnect structure is required, or when connected to a front end of line (FEOL) device such as a transistor, capacitor, or resistor, the substrate 301 can include a conductor 304 (e.g., a plug, a line, etc.). Additionally, or alternatively, when using the semiconductor structure 300 in an RIE process to form an interconnect structure, at least a portion of the metal layer 303 can be removed. As described above, since TiN itself has a crystalline structure that grows into small particles having a size of less than about 100 nm, in a conventional TiN etch stop layer, the resistance of the subsequently deposited metal layer may become insufficient. The processing process described in connection with FIG. 3B overcomes this and other problems found in the prior art.

[0024] FIG. 3B is a flowchart showing selected processing of a process 305 for forming the semiconductor structure 300. The process 305 allows for the use of conventional etch stop materials, if desired, but other etch stop materials can also be used. The process 305 includes a processing process for amorphizing the surface of the etch stop layer 302 so that the metal(s) of the metal layer 303 can grow into large particles having a size from about 100 nm to about 2 - 3 μm. The large particles of the metal(s) of the metal layer 303 result in adhesion of the metal layer 303 to the etch stop layer 302, producing a metal layer 303 having a resistance of 40 μΩ·cm or less.

[0025] One or more processes of process 305 shown in FIG. 3B can be performed without vacuum breakage so that the processes of process 305 can be integrated into a single tool. By using a process (or processes) without (one or more) vacuum breakage, oxidation of the etch stop layer is eliminated (or at least reduced), and the resistivity of the metal layer 303 deposited thereafter is improved over the prior art. Thus, in some embodiments, one or more processes of process 305 can be performed in cluster tool 100 or other suitable tool.

[0026] Process 305 includes placing substrate 301 within the processing volume of the processing chamber at process 310. Substrate 301 undergoes a degassing process at process 315 that, for example, evaporates contaminants and prevents the contaminants from adhering to substrate 301. The degassing process can include heating substrate 301 at a temperature of from about 150° C. to about 400° C. in an inert gas environment, for example, using an infrared (IR) light source and / or a hot plate heater. Wet cleaning can also be performed prior to the degassing process to assist in removing contaminants.

[0027] Next, at process 320, an etch stop layer 302 is deposited on substrate 301 by a PVD process. The PVD processing chamber shown in FIG. 1A can be used, although other PVD chambers are contemplated. The etch stop layer 302 can include any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or combinations thereof. In some embodiments, the etch stop layer 302 has a thickness of from about 5 Å to about 50 Å, such as from about 10 Å to about 30 Å, such as from about 15 Å to about 25 Å. In at least one embodiment, the etch stop layer can have a thickness of about 30 Å or less, such as about 25 Å or less, such as about 20 Å or less, such as about 15 Å or less, such as about 10 Å or less.

[0028] As an example of the PVD process of process 320, a target 56 containing an etch stop material is provided to a processing chamber 50 shown in FIG. 1A. The pedestal 80 includes an electrostatic chuck heated to a temperature of from about 100° C. to about 400° C., such as from about 200° C. to about 300° C. The pedestal 80 within the processing chamber 50 supports a substrate 301 opposite the target 56 such that it is coated with an etch stop layer 302 sputtered from the target 56. An RF power source biases the pedestal 80 that supports the substrate 301 via a capacitive coupling circuit. The pedestal is conductive and as a result functions as an electrode. Due to the RF bias in the presence of plasma within the processing chamber 50, a negative DC self-bias is generated on the pedestal 80, and as a result, the sputtered etch stop material ions are accelerated towards the substrate 301 and their trajectories enter deep into the high aspect ratio holes formed in the substrate 301. In some embodiments, the etch stop layer 302 is deposited at a pressure of from about 5 mTorr to about 20 mTorr and a substrate temperature of from about 100° C. to about 400° C., such as from about 200° C. to about 300° C. The gas flow within the processing chamber 50 can be set to a flow rate of from about 15 sccm to about 150 sccm. The RF power source can be set from 1 kW to about 10 kW, such as from about 2 kW to about 3 kW.

[0029] Next, the etch stop layer 302 is subjected to a sputtering process in process 325. Here, appropriate ions such as He ions, Ne ions, Ar ions, Kr ions, Xe ions, or combinations thereof are collided with the etch stop layer 302 to amorphize or substantially amorphize the etch stop layer 302. Since the etch stop layer 302 becomes amorphous as a result of the sputtering process, the metal layer 303 grown thereon has a resistivity of about 40 μΩ·cm or less, and adhesion is observed between the metal layer 303 and the etch stop layer 302.

[0030] The sputtering process of process 325 can be carried out in a sputtering chamber, for example, a pre-cleaning / pre-treatment chamber such as a PC XT (trademark) chamber or a PC XTe (trademark) chamber available from Applied Materials, Inc., Santa Clara, California, USA, although other chambers are also envisioned. As an example of the sputtering process of process 325, a substrate 301 with an etch stop layer 302 disposed thereon is placed in a processing chamber such as a pre-cleaning / pre-treatment chamber. The pre-cleaning / pre-treatment chamber may also include a pedestal for supporting the substrate. The pedestal includes a heated electrostatic chuck for heating the substrate 301 at a temperature of less than about 500 °C, for example, from about 200 °C to about 450 °C, for example, from about 250 °C to about 350 °C. The pressure in the pre-cleaning / pre-treatment chamber can be from about 5 mTorr to about 100 mTorr, for example, from about 5 mTorr to about 50 mTorr. A sputtering gas containing any suitable sputtering gas such as He, Ne, Ar, Kr, or Xe, or a combination thereof, is introduced into the pre-cleaning / pre-treatment chamber and excited into a plasma to cause the etch stop layer 302 to collide with ions. The gas flow rate of the sputtering gas into the sputtering chamber can be from about 3 sccm to about 100 sccm, for example, from about 10 sccm to about 50 sccm. The sputtering process of process 325 can be carried out for a time of less than about 5 minutes (min), for example, less than about 3 minutes, for example, less than about 1 minute, for example, less than about 30 seconds (s), for example, less than about 20 seconds, for example, less than about 10 seconds.

[0031] The sputtering process in Process 325 can be carried out with an F - bias power of about 500W to about 600W and a plasma output of about 200W to about 600W. Using a DC power supply, a negative bias of about 500W to about 10kW, for example about 900W to about 8kW, for example about 1kW to about 2kW, can be applied to the target with respect to the grounded pre - cleaning / pre - treatment chamber or the grounded side - wall shield to excite the sputtering gas into plasma. Using an AC power supply (not shown in FIG. 1A), a bias can be applied to the substrate 301 such that only particles of a certain nuclide having a minimum energy and a perpendicular trajectory collide with the substrate 301 on which the etch - stop layer 302 is disposed. Other nuclides with low energy and a flat angle of incidence prevent collisions with the substrate. The AC substrate bias power can be set to a power of about 0W to about 500W, for example about 200W to about 400W.

[0032] Next, in Process 330, a metal layer 303 is deposited on the etch - stop layer 302. In some embodiments, the metal layer 303 includes any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or combinations thereof. The metal layer 303 is typically deposited using a PVD process. As an example of the deposition process of Process 330, a target 56 containing a sputtered metal (e.g., W, Ru, etc.) for depositing the metal layer 303 is provided in a processing chamber such as the processing chamber 50 shown in FIG. 1A. The processing chamber 50 may also include a pedestal for supporting the substrate 301. The pedestal 80 includes a heated electrostatic chuck for heating the substrate 301 at a temperature of less than about 500°C, for example about 200°C to about 450°C, for example about 250°C to about 350°C. The pressure inside the processing chamber 50 can be from about 5mTorr to about 100mTorr, for example from about 5mTorr to about 50mTorr. A sputtering gas containing any suitable non - reactive gas such as He, Ne, Ar, Kr, Xe, or combinations thereof is introduced into the processing chamber 50 and excited into plasma to deposit the metal layer 303 on the etch - stop layer 302.

[0033] Using the DC power supply 60, a negative bias can be applied to the target 56 with respect to the grounded processing chamber 50 or the grounded sidewall shield at about 500 W to about 10 kW, for example, about 900 W to about 8 kW, for example, about 1 kW to about 2 kW to excite the sputtering gas into plasma. An AC power supply (not shown in FIG. 1A) can be used to bias the substrate. When an AC power supply is used, the AC substrate bias power can be set to a power of about 0 W to about 500 W, for example, about 200 W to about 400 W. The metal layer 303 generated from operation 330 can have a thickness of about 50 Å to about 500 Å, for example, about 100 Å to about 400 Å, for example, about 200 Å to about 300 Å. The metal layer 303 can have a resistivity of about 40 μΩ·cm or less, for example, about 35 μΩ·cm or less, for example, about 30 μΩ·cm or less, for example, about 25 μΩ·cm or less, for example, about 20 μΩ·cm or less, for example, about 15 μΩ·cm or less, for example, about 10 μΩ·cm or less, for example, about 5 μΩ·cm or less.

[0034] FIG. 3C shows a semiconductor structure 340 having a metal layer 354 disposed on an etch stop layer 351 and an etch stop layer 351 disposed on a substrate 350. The metal layer includes a metal seed layer 352 and a bulk metal layer. The substrate 350 can be any suitable material, for example, a dielectric material, especially silicon, germanium, quartz, and glass, or can include them. In some embodiments, when an interconnect structure is desired, or when connected to FEOL devices such as transistors, capacitors, or resistors, the substrate 350 can include conductors 345 (for example, plugs, lines, etc.). Additionally, or alternatively, at least a portion of the metal layer 354 can be removed when using the semiconductor structure 340 in an RIE process to form an interconnect structure.

[0035] As described above, since the etch stop layer itself has a crystalline structure that grows into small particles having a size of less than about 100 nm, in the etch stop layer deposited by the prior art method, the resistivity of the metal layer deposited thereafter may become insufficient. Process 355 shown in FIG. 3D overcomes this problem. Briefly, process 355 includes a processing step for amorphizing the surface of the metal seed layer 352 so that the materials of the metal seed layer and the bulk metal layer 353 deposited thereon can grow into large particles having a size exceeding about 100 nm and up to about 2 to 3 μm at maximum. The large particles of the metal layer 354 provide excellent adhesion of the metal layer 354 to the etch stop layer 351, resulting in a metal layer 354 having a resistivity of less than about 40 μΩ·cm. Furthermore, process 355 enables the use of conventional etch stop materials, for example, but other etch stop materials can also be used as needed.

[0036] FIG. 3D is a flowchart showing selected processing of process 355 for forming a metal layer 354 on an etch stop layer 351. Process 355 shown in FIG. 3D can be implemented without breaking vacuum so that the processing of process 355 is integrated. By utilizing a process that does not include (one or more) vacuum breaks, oxidation of the metal seed layer 352 is eliminated (or at least reduced), and the resistivity of the metal layer 354 is improved over the prior art. Thus, in some embodiments, one or more operations of process 355 of FIG. 3D can be implemented within cluster tool 100 or other suitable tool.

[0037] Process 355 includes, in process 360, placing substrate 350 within the processing volume 50 (FIG. 1A) of the processing chamber. Next, substrate 350 undergoes a degassing process in process 365. The degassing process of process 365 can be the same as, or similar to, operation 315 of FIG. 3B. Wet cleaning can also be performed prior to the degassing process to assist in removing contaminants. Next, in process 370, an etch stop layer 351 is deposited on substrate 350 by a PVD process. The deposition of the etch stop layer 351 in process 370 can be the same as, or similar to, process 320 of FIG. 3B. The etch stop layer 351 can include any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or combinations thereof.

[0038] Next, in process 375, a metal seed layer 352 is deposited on the etch stop layer 351. The deposition of the metal seed layer 352 can be carried out using a PVD process within a PVD chamber such as the processing chamber 50 of FIG. 1A or other suitable chamber. The deposition of the metal seed layer 352 (operation 375) can be the same as, or similar to, process 330 of FIG. 3B. The thickness of the metal seed layer 352 deposited in process 375 can be about 80 Å or less, for example, about 5 Å to about 50 Å, for example, about 10 Å to about 40 Å, for example, about 15 Å to about 30 Å, for example, about 20 Å to about 25 Å. In some embodiments, the metal seed layer 352 includes any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or combinations thereof.

[0039] Next, the metal seed layer 352 is subjected to a sputtering process in process 380. Here, suitable ions such as He ions, Ne ions, Ar ions, Kr ions, Xe ions, or combinations thereof are collided with the metal seed layer 352 to amorphize or substantially amorphize the metal seed layer 352. The sputtering process of process 380 can be the same as, or similar to, process 325 of FIG. 3B.

[0040] Next, in process 385, a bulk metal layer 353 is deposited on the metal seed layer 352. The deposition of the bulk metal layer 353 can be carried out using a PVD process in a PVD chamber such as the processing chamber 50 of FIG. 1A. The deposition of the bulk metal layer 353 in process 385 can be the same as, or similar to, process 330 of FIG. 3B. The thickness of the deposited bulk metal layer 353 can be about 450 Å or less, for example about 400 Å or less, for example about 100 Å to about 400 Å, for example about 150 Å to about 350 Å, for example about 200 Å to about 300 Å. In some embodiments, the deposited bulk metal layer 353 comprises any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or combinations thereof. In some embodiments, the bulk metal layer 353 comprises the same material as the metal seed layer 352. Alternatively, and in at least one embodiment, the bulk metal layer 353 comprises a material different from the metal seed layer 352.

[0041] The resulting metal layer 354 has a thickness of about 550 Å or less, for example 50 Å to about 500 Å, for example about 100 Å to about 400 Å, for example about 200 Å to about 300 Å. The metal layer 354 generated from processes 380 and 385 can have a resistivity of about 40 μΩ·cm or less, for example about 35 μΩ·cm or less, for example about 30 μΩ·cm or less, for example about 25 μΩ·cm or less, for example about 20 μΩ·cm or less, for example about 15 μΩ·cm or less, for example about 10 μΩ·cm or less, for example about 5 μΩ·cm or less.

[0042] In the process shown in FIG. 3D, the metal layer 354 comprises a metal seed layer 352 deposited first and a bulk metal layer 353 deposited thereafter. A sputtering process is carried out between the deposition of the metal seed layer 352 and the deposition of the bulk metal layer 353. Without wishing to be bound by theory, it is believed that depositing the metal seed layer 352 and subsequently depositing the bulk metal layer 353 improves the metal particle structure and the resistivity of the metal layer 354.

[0043] Embodiments of the present disclosure generally relate to a process for forming a selective metal liner on a pre-formed via, followed by depositing a metal layer having a low resistance. Such a process is useful, for example, in forming semiconductor structures such as multilayer interconnect structures.

[0044] FIG. 4A shows a semiconductor structure 400 having a substrate 405 with a via hole 410 (or via plug) formed therein. The substrate 405 can be, for example, any suitable material such as a dielectric material, particularly silicon, germanium, quartz, and glass, or can include them. The substrate 405 can represent a structure that contacts a lower semiconductor structure to connect an interconnect structure to a lower semiconductor device.

[0045] The via hole 410 can be at least partially filled with any suitable material such as a metal material, for example, Ru, W, Mo, Co, Ti, TiN, or a combination thereof. An etch stop layer 415 (or liner layer) is selectively disposed over the via hole 410. A metal layer 420 is disposed over at least a portion of the substrate 405 and over at least a portion of the etch stop layer 415. Typically, the material used to form the etch stop layer 415 is different from the material used to form the metal layer. In some embodiments, the etch stop layer 415 includes any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or a combination thereof. The metal layer 420 can include any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or a combination thereof. The semiconductor structure 400 shown in FIG. 4A can be used in a RIE process to remove at least a portion of the metal layer 420 when forming an interconnect structure.

[0046] Conventional methods for depositing an etch stop layer typically result in the residue of the etch stop material on the undesirable surfaces of the substrate. If these residual materials are not sufficiently removed, current leakage occurs. In contrast, the inventors have found a process to overcome these and other problems. For example, process 450 uses a selective metal etch stop that is deposited only on the metal vias rather than on the dielectric film, enabling low leakage integration.

[0047] Figure 4B is a flowchart showing selected processes of process 450 for manufacturing a semiconductor structure such as a multilayer interconnect structure (e.g., a metal wire in ohmic contact with a lower via). Process 450 enables the selective deposition of an etch stop layer 415 on, for example, via holes 410 formed in substrate 405 while minimizing (or eliminating) the deposition of the etch stop layer on the dielectric material of substrate 405. One or more processes of the process shown in Figure 4B can be implemented without breaking vacuum so that the process is integrated into a single tool. By utilizing a process that does not include (one or more) vacuum breaks, oxidation of the etch stop layer is eliminated (or at least reduced), and the resistivity of the subsequently deposited metal layer 420 is improved compared to the prior art. Thus, in some embodiments, one or more processes of process 450 can be implemented in cluster tool 100 or other suitable tools.

[0048] Process 450 includes placing substrate 405 within the process volume of the process chamber in process 455. Substrate 405 undergoes a degassing process in process 460 to, for example, evaporate contaminants and prevent the contaminants from adhering to substrate 405. The degassing process can include heating substrate 405 at a temperature from about 150°C to about 400°C in an inert gas environment using, for example, an IR light source and / or a hot plate heater. Wet cleaning can also be performed prior to the degassing process to assist in removing contaminants.

[0049] Next, in process 465, an etch stop layer 415 is deposited on substrate 405 by a CVD process. Here, the etch stop layer 415 is selectively deposited on the material within via hole 410 such that the dielectric material of substrate 405 does not contain or substantially does not contain the material used for the formation of the etch stop layer 415. That is, the selective deposition process does not form the etch stop layer 415 on the upper surface of substrate 405, preventing short circuits between adjacent lines / conductive elements. The etch stop layer 415 is considered to improve the electromigration performance of the underlying metal layer and the adhesion of the dielectric barrier as compared to the prior art. The etch stop layer 415 may include any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, Co, Ni, Au, Ag, Mn, Sn, Al, or combinations thereof.

[0050] The selective deposition process may depend on the precursor and the surface. The selective deposition process can be implemented using any suitable technique such as plasma treatment, plasma CVD, plasma ALD, or any combination thereof. Alternatively, the selective deposition process can be implemented using thermal surface treatment with different chemistries (without plasma) to achieve selectivity. The etch stop layer 415 may be applied using plating, electroplating, or other suitable deposition techniques such as CVD, PVD, ALD.

[0051] As an example of the CVD process of process 465, the metal-containing precursor can be introduced into the processing chamber in which the workpiece is disposed at a flow rate of from about 10 sccm to about 3,000 sccm, such as from about 20 sccm to about 1,500 sccm, such as from about 30 sccm to about 200 sccm (in the case of a 300 mm substrate). The temperature of the workpiece or substrate pedestal during processing can be from about 200 °C to about 800 °C, such as from about 350 °C to about 550 °C, such as from about 400 °C to about 500 °C. In some embodiments, the workpiece can be heated and maintained at a temperature of from about 100 °C to about 600 °C, such as from about 120 °C to about 500 °C, such as from about 150 °C to about 425 °C. The processing chamber can have a controlled environment that is pressurized from about 1 mTorr to about 100 Torr, such as from about 1 Torr to about 10 Torr, such as from about 2 Torr to about 5 Torr.

[0052] During the formation of the etch stop layer 415, the substrate can be exposed to the metal-containing precursor, doped, react with the etch stop layer 415, or form an alloy layer on the upper surface of the etch stop layer 415. Although not shown in FIG. 4A, the alloy layer can be located above the etch stop layer 415 and below the metal layer 420.

[0053] In some examples, when the etch stop layer 415 is formed from cobalt, exposing the workpiece to an aluminum-containing precursor can selectively convert the etch stop layer 415 into a cobalt-containing alloy and / or a cobalt-containing alloy, such as a cobalt-aluminum alloy, can be formed on the etch stop layer 415. In some embodiments, the etch stop layer 415 or the cobalt-aluminum alloy layer can be formed by selective Co deposition followed by selective Al deposition. In some embodiments, the etch stop layer 415 or the cobalt-aluminum alloy layer can be formed by selective Al deposition followed by selective Co deposition. In some embodiments, the cobalt-aluminum alloy can be formed by a selective cyclic process such as Co-Al-Co-Al deposition. In such cases, the substrate can be alternately exposed to a cobalt-containing precursor and an aluminum-containing precursor until the desired thickness is reached. In some embodiments, the cobalt-aluminum alloy layer can be formed by co-flowing a cobalt-containing precursor and an aluminum-containing precursor.

[0054] Suitable cobalt-containing precursors include methylcyclopentadienylcobalt bis(carbonyl) (MeCpCo(CO) 2 ), ethylcyclopentadienylcobalt bis(carbonyl) (EtCpCo(CO) 2 ), dicobalt octa(carbonyl) (Co 2 (CO) 8 ), nitrosylcobalt tris(carbonyl) ((ON)Co(CO) 3 ), or combinations thereof. Suitable cobalt-containing precursors also include cobalt carbonyl compounds or complexes such as cyclopentadienylcobalt bis(carbonyl) (CpCo(CO) 2 ), tricarbonylallylcobalt ((CO) 3 Co(CH 2 CH=CH 2 )), dicobalt hexacarbonyl butylacetylene (CCTBA, (CO) 6 Co 2(HC≡CtBu)), dicobalt hexacarbonyl methylbutylacetylene ((CO) 6 Co 2 (MeC≡CtBu)), dicobalt hexacarbonyl phenylacetylene ((CO) 6 Co2(HC≡CPh)), or combinations thereof are also included. Suitable cobalt-containing precursors also include cobalt amidinates or cobalt amide complexes, for example, bis(di(butyldimethylsilyl)amide)cobalt (((BuMe 2 Si) 2 N) 2 Co), bis(di(ethyldimethylsilyl)amide)cobalt (((EtMe 2 Si) 2 N) 2 Co), bis(di(propyl-dimethylsilyl)amide)cobalt (((PrMe 2 Si) 2 N) 2 Co), bis(di(trimethylsilyl)amide)cobalt (((Me 3 Si) 2 N) 2 Co), or combinations thereof. In some embodiments, the cobalt-containing precursor can include two or more of the above cobalt-containing precursors.

[0055] Suitable aluminum-containing precursors include dimethylaluminum hydride (DMAH), trimethylaluminum (TMA, Al 2 Me 6 or (AlMe 3 ) 2 ), triethylaluminum (Al 2 Et 6 or TEA), tri-tert-butylaluminum (TTBA), aluminum hydride (AlH 3 ), or combinations thereof. Although aluminum-containing precursors are described herein, other suitable doping precursors such as Ru, Mn, or W can also be recognized as being used to react with the etch stop layer 415 to change the etch stop layer 415 and / or form an alloy layer thereon.

[0056] Next, in process 470, a metal layer 420 is deposited on the etch stop layer 415. The metal layer 420 can be deposited to a thickness of from about 50 Å to about 500 Å, such as from about 100 Å to about 400 Å, such as from about 200 Å to about 300 Å, using a PVD process. The deposition of the metal layer 420 in process 470 can be the same as, or similar to, process 330 of FIG. 3B.

[0057] In some embodiments, the metal layer 420 comprises any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or combinations thereof. In at least one embodiment, the material used to form the metal layer 420 is different from the material used to form the etch stop layer 415. For example, if the metal layer 420 is a W layer, the etch stop layer 415 can be a Ru layer. That is, the metal layer 420 does not contain, or substantially does not contain, Ru, and the etch stop layer 415 does not contain, or substantially does not contain, W. As another example, if the metal layer 420 is a Ru layer, the etch stop layer 415 can be a W layer. In this example, the metal layer 420 does not contain, or substantially does not contain, W, and the etch stop layer 415 does not contain, or substantially does not contain, Ru. The metal layer 420 can have a resistivity of about 40 μΩ·cm or less, such as about 35 μΩ·cm or less, such as about 30 μΩ·cm or less, such as about 25 μΩ·cm or less, such as about 20 μΩ·cm or less, such as about 15 μΩ·cm or less, such as about 10 μΩ·cm or less, such as about 5 μΩ·cm or less.

[0058] FIG. 5A shows a semiconductor structure 500 having a substrate 505 with via holes 510 (or via plugs) formed therein. The substrate 505 can be any suitable material, such as, for example, a dielectric material, especially silicon, germanium, quartz, and glass, or can include them. The substrate 505 can represent a structure that contacts a lower semiconductor structure to connect an interconnect structure to the lower semiconductor device. The via holes 510 can be at least partially filled with any suitable material, such as a metal material, for example Ru, W, Mo, Co, Ti, TiN, or a combination thereof. An etch stop layer 515 (or liner layer) is selectively disposed over the via holes 510. An adhesion layer 516 is disposed over at least a portion of the etch stop layer 515 and over at least a portion of the substrate 505. A metal layer 520 is disposed over at least a portion of the adhesion layer 516. The semiconductor structure 500 can be used in an RIE process to remove at least a portion of the metal layer 520 when forming an interconnect structure.

[0059] FIG. 5B is a flowchart showing selected processing of a process 550 for manufacturing a semiconductor structure, such as a multilayer interconnect structure (e.g., a metal wire in ohmic contact with a lower via). The process 550 enables, for example, strong adhesion of the structure without degrading wire resistance or via contact resistance. One or more operations of the process shown in FIG. 5B can be performed without breaking vacuum so that the process is integrated into a single tool. By utilizing a process that does not include (one or more) vacuum breaks, oxidation of the etch stop layer is eliminated (or at least reduced), and the resistivity of the subsequently deposited metal layer 520 is improved over the prior art. Thus, in some embodiments, one or more processes of the process 550 can be performed in a cluster tool 100 or other suitable tool.

[0060] Process 550 includes placing substrate 505 within the processing volume of the processing chamber at process 555. Substrate 505 undergoes a degassing process at process 560 to, for example, evaporate contaminants and prevent contaminants from adhering to substrate 505. The degassing process can include heating substrate 505 at a temperature from about 150 °C to about 400 °C in an inert gas environment, using, for example, an IR light source and / or a hot plate heater. Wet cleaning can also be performed prior to the degassing process to assist in removing contaminants.

[0061] Next, at process 565, an etch stop layer 515 is deposited on substrate 505 by a CVD process. Here, etch stop layer 515 is selectively deposited over via hole 510 such that the dielectric material of substrate 505 does not, or substantially does not, include the material used for forming etch stop layer 515. Etch stop layer 515 can include any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or combinations thereof. The CVD deposition of process 565 can be the same as, or similar to, process 465 of FIG. 4B.

[0062] Next, at process 570, an adhesion layer 516 is deposited over at least a portion of etch stop layer 515 and at least a portion of substrate 505. Adhesion layer 516 can be deposited to a thickness from about 1 Å to about 100 Å, for example from about 1 Å to about 10 Å, for example from about 3 Å to about 5 Å, using a PVD process. Adhesion layer 516 includes any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or combinations thereof. In at least one embodiment, the material used for forming adhesion layer 516 is different from the material used for forming etch stop layer 515. For example, if adhesion layer 516 is a Ti layer, etch stop layer 515 can be a Ru layer and / or a W layer. That is, adhesion layer 516 does not, or substantially does not, include Ru and / or W, and etch stop layer 515 does not, or substantially does not, include Ti. The PVD process of process 570 for forming adhesion layer 516 can be the same as, or similar to, process 330 of FIG. 3B.

[0063] Next, in process 575, a metal layer 520 is deposited on the adhesive layer 516. The metal layer 520 is typically deposited to a thickness of from about 50 Å to about 500 Å, such as from about 100 Å to about 400 Å, such as from about 200 Å to about 300 Å, using a PVD process. The deposition of the metal layer 520 in process 575 can be the same as, or similar to, process 330 of FIG. 3B.

[0064] In some embodiments, the metal layer 520 comprises any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or combinations thereof. In at least one embodiment, the material used to form the metal layer 520 is different from the material used to form the adhesive layer 516. For example, if the metal layer 520 is a W layer, the adhesive layer 516 can be a Ru layer. That is, the metal layer 520 does not contain, or is substantially free of, Ru, and the adhesive layer 516 does not contain, or is substantially free of, W. The metal layer 520 produced from operation 575 can have a resistivity of about 40 μΩ·cm or less, such as about 35 μΩ·cm or less, such as about 30 μΩ·cm or less, such as about 25 μΩ·cm or less, such as about 20 μΩ·cm or less, such as about 15 μΩ·cm or less, such as about 10 μΩ·cm or less, such as about 5 μΩ·cm or less.

[0065] FIG. 6A shows a semiconductor structure 600 having a substrate 605 with a via hole 610 (or via plug) formed therein. The substrate 605 can be any suitable material, such as, for example, a dielectric material, especially silicon, germanium, quartz, and glass, or can include them. The substrate 605 can represent a structure that contacts a lower semiconductor structure to connect an interconnect structure to a lower semiconductor device. The via hole 610 is at least partially filled with a metal material (e.g., Ru, W, Mo, Co, Ti, TiN, and others, or a combination thereof) and at least partially filled with an etch stop layer 615 (or liner layer). An adhesion layer 616 is disposed on at least a portion of the etch stop layer 615 and on at least a portion of the substrate 605. A metal layer 620 is disposed on at least a portion of the adhesion layer 616. The semiconductor structure 600 can be used in an RIE process to remove at least a portion of the metal layer 620 when forming an interconnect structure.

[0066] FIG. 6B is a flowchart showing selected operations of a process 650 for manufacturing a semiconductor structure, such as a multi-layer interconnect structure (e.g., a metal wire in ohmic contact with a lower via). The process 650 is an alternative approach for building desirable features having low resistivity, improved etch stop characteristics, and improved adhesion characteristics. One or more operations of the process shown in FIG. 6B can be performed without breaking vacuum so that the operations are integrated into a single tool. By utilizing a process that does not include (one or more) vacuum breaks, oxidation of the etch stop layer is eliminated (or at least reduced), and the resistance of the metal layer 620 deposited thereafter is improved compared to the prior art. Thus, in some embodiments, one or more processes of the process 650 can be performed in a cluster tool 100 or other suitable tool.

[0067] Process 650 includes placing substrate 605 within the processing volume of the processing chamber in process 555. Substrate 605 undergoes a degassing process in process 660 to, for example, evaporate contaminants and prevent contaminants from adhering to substrate 605. The degassing process can include heating substrate 605 at a temperature from about 150°C to about 400°C in an inert gas environment using, for example, an IR light source and / or a hot plate heater. Wet cleaning can also be performed prior to the degassing process to assist in removing contaminants.

[0068] At this stage, at least a portion of via hole 610 is empty. Next, in process 665, an etch stop layer 615 is selectively deposited within via hole 610 by a CVD process such that the dielectric material of substrate 605 does not include, or substantially does not include, the material used to form etch stop layer 615. The CVD deposition of process 665 can be the same as, or similar to, process 465 of FIG. 4B. Etch stop layer 615 can include any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or combinations thereof.

[0069] Next, in process 670, an adhesion layer 616 is deposited over at least a portion of etch stop layer 615 and at least a portion of substrate 605. Adhesion layer 616 can be deposited to a thickness from about 1 Å to about 100 Å, for example from about 1 Å to about 10 Å, for example from about 3 Å to about 5 Å, using a PVD process. The PVD process of process 670 for forming adhesion layer 616 can be the same as, or similar to, process 570 of FIG. 5B. The adhesion layer can include any suitable material such as Ti, TiN, Ta, TaN, Mo, W, Ru, or combinations thereof. In at least one embodiment, the material used to form adhesion layer 616 is different from the material used to form etch stop layer 615. For example, if adhesion layer 616 is a Ti layer, etch stop layer 615 can be a Ru layer and / or a W layer. That is, adhesion layer 616 does not include, or substantially does not include, Ru and / or W, and etch stop layer 615 does not include, or substantially does not include, Ti.

[0070] Next, in process 675, a metal layer 620 is deposited on the adhesive layer 616. The metal layer 620 can be deposited to a thickness of from about 50 Å to about 500 Å, such as from about 100 Å to about 400 Å, such as from about 200 Å to about 300 Å, using a PVD process. The deposition of the metal layer 620 in process 675 can be the same as, or similar to, process 330 of FIG. 3B. In some embodiments, the metal layer 620 comprises any suitable material such as Ru, Mo, W, Cu, Co, Ir, metal silicides, metal alloys, or combinations thereof. In at least one embodiment, the material used to form the metal layer 620 is different from the material used to form the adhesive layer 616. For example, if the metal layer 620 is a W layer, the adhesive layer 616 can be a Ru layer. That is, the metal layer 620 does not contain, or substantially does not contain, Ru, and the adhesive layer 616 does not contain, or substantially does not contain, W.

[0071] The metal layer 620 produced from process 675 can have a resistivity of about 40 μΩ·cm or less, such as about 35 μΩ·cm or less, such as about 30 μΩ·cm or less, such as about 25 μΩ·cm or less, such as about 20 μΩ·cm or less, such as about 15 μΩ·cm or less, such as about 10 μΩ·cm or less, such as about 5 μΩ·cm or less.

[0072] For example, new and improved etch stop materials / liner materials are described herein on which a low resistivity metal layer can be actively formed. Embodiments described herein also include processes that can modify one or more properties of conventional etch stop materials / liner materials (e.g., TiN) such that the metal layer formed thereon has a low resistivity. Processes are also described herein that enable selective deposition of an etch stop liner material such that the metal layer formed thereon has a low resistivity.

[0073] Above, embodiments of the present disclosure have been referred to. However, it should be understood that the present disclosure is not limited to the specific described embodiments. Instead, any combination of the following features and elements is contemplated for implementing and practicing the present disclosure, regardless of whether they relate to different embodiments. Furthermore, embodiments of the present disclosure can achieve advantages that exceed other possible solutions and / or exceed the prior art, but whether a particular advantage is achieved by a given embodiment does not limit the present disclosure. Accordingly, the foregoing aspects, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims, except as explicitly recited in the claims. Similarly, references to "the present disclosure" should not be construed as generalizations of the inventive subject matter disclosed herein and are not to be considered elements or limitations of the appended claims, except as explicitly recited in the claims.

[0074] For purposes of the present disclosure, unless otherwise specified, the terms "liner" and "etch stop" are used interchangeably. Accordingly, embodiments described herein in relation to liner materials also include etch stop materials, and vice versa.

[0075] For the purposes of the present disclosure, unless otherwise specified, all numerical values within the detailed description and claims of this specification are modified by the indicated value of "about" or "approximately" and take into account experimental error and variations that would be expected by one of ordinary skill in the art. For the purposes of the present disclosure, unless otherwise specified, all numerical values within the detailed description and claims of this specification are modified by the indicated value of "about" or "approximately" and take into account experimental error and variations that would be expected by one of ordinary skill in the art. For the sake of brevity, only certain ranges are explicitly disclosed herein. However, to describe ranges not explicitly recited, any range from any lower limit can be combined with any upper limit, and similarly, to describe ranges not explicitly recited, any range from any lower limit can be combined with any other lower limit, and in the same way, to describe ranges not explicitly recited, any range from any upper limit can be combined with any other upper limit. In addition, within a range, all points or individual values between its endpoints are included even if not explicitly recited. Thus, to describe ranges not explicitly recited, all points or individual values can function as their own lower or upper limits in combination with other points or individual values or other lower or upper limits.

[0076] As used herein, the indefinite articles "a" or "an" shall mean "at least one" unless otherwise specified or unless the context clearly indicates otherwise.

[0077] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure can be devised without departing from the basic scope thereof, which is determined by the claims that follow.

Claims

1. A method of manufacturing a semiconductor structure, comprising: performing a degassing process on the semiconductor structure; depositing a liner layer on the semiconductor structure; performing a sputtering process on the liner layer to amorphize the liner layer; and depositing a metal layer on the liner layer by physical vapor deposition, wherein the liner layer comprises Ti, Ta, TaN, or a combination thereof, and the resistivity of the metal layer is about 30 μΩ·cm or less. A method of manufacturing a semiconductor structure.

2. The method according to claim 1, wherein the degassing process, the deposition of the liner layer, the sputtering process, and the deposition of the metal layer are performed within a single cluster tool.

3. The method according to claim 1, wherein the thickness of the liner layer is about 25 Å or less.

4. The method according to claim 1, wherein the resistivity of the metal layer is about 20 μΩ·cm or less.

5. The method according to claim 1, wherein the thickness of the liner layer is about 20 Å or less, the resistivity of the metal layer is about 15 μΩ·cm or less, or a combination thereof. The method according to claim 1.

6. A method of manufacturing a semiconductor structure, comprising: performing a degassing process on the semiconductor structure; depositing an etch stop layer on the semiconductor structure by physical vapor deposition after the degassing process; depositing a metal seed layer on the etch stop layer by physical vapor deposition; performing a sputtering process on the semiconductor structure after the deposition of the metal seed layer, including performing the sputtering process on the metal seed layer; and depositing a metal layer on the semiconductor structure by physical vapor deposition after the sputtering process. A method.

7. The method according to claim 6, wherein the degassing process, the deposition of the etch stop layer, the sputtering process, and the deposition of the metal layer are performed within a single cluster tool.

8. The method according to claim 6, wherein performing the sputtering process on the semiconductor structure includes performing the sputtering process on the etch stop layer.

9. The sputtering process is performed for about 30 seconds or less, the metal seed layer has a thickness of about 80 Å or less, the metal layer has a thickness of about 100 Å or more, or a combination thereof. The method according to claim 6.

10. The method according to claim 6, wherein the metal layer has a resistivity of about 40 μΩ·cm or less.

11. The method according to claim 10, wherein the resistivity of the metal layer is about 30 μΩ·cm or less.

12. The etching stop layer includes Ti, TiN, Ta, TaN, Mo, W, Ru, or a combination thereof, and the metal layer includes Ru, Mo, W, Cu, Co, Ir, or a combination thereof, The method according to claim 6.

13. The method according to claim 10, wherein the metal layer includes Ru, W, or both.

14. In a method of manufacturing an interconnect structure, performing a degassing process on a semiconductor structure, wherein the semiconductor structure includes a dielectric material and a via hole, and the via hole is at least partially filled with a metal material; depositing an etching stop layer on the semiconductor structure by chemical vapor deposition after the degassing process; performing a sputtering process on the etching stop layer to amorphize the etching stop layer; and depositing a metal layer on the semiconductor structure by physical vapor deposition after the deposition of the etching stop layer to form the interconnect structure A method comprising:

15. The method according to claim 14, wherein the degassing process, the deposition of the etching stop layer, and the deposition of the metal layer are performed within a single cluster tool.

16. The etching stop layer is selectively deposited on the via hole at least partially filled with the metal material, after the deposition of the etching stop layer, the method further includes depositing an adhesion layer on at least a part of the etching stop layer and at least a part of the dielectric material by physical vapor deposition, and depositing the metal layer includes depositing the metal layer on the adhesion layer. The method according to claim 14.

17. The method according to claim 14, wherein when at least a part of the via hole does not contain the metal material, the etching stop layer is formed within the via hole.

18. The etching stop layer includes Ti, TiN, Ta, TaN, Mo, W, Ru, or a combination thereof, the metal layer includes Ru, Mo, W, Cu, Co, Ir, or a combination thereof, and the etching stop layer includes a material different from the metal layer. The method according to claim 14.

19. The method according to claim 14, wherein the resistivity of the metal layer is about 30 μΩ·cm or less.

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