Semiconductor device

Abstract

To provide a semiconductor device capable of further reducing inductance.SOLUTION: A semiconductor device includes a first terminal, and a metal plate in an electrically floating state, and the first terminal includes a first flat plate portion having a first surface, and a second flat plate portion having a second surface facing the first surface and electrically connected to the first flat plate portion, and the metal plate is arranged between the first surface and the second surface.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] As a semiconductor device used in a power module, a semiconductor device in which a part of an electrode terminal is flattened into a parallel plate has been proposed for reducing inductance (Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] For further speed increase, further reduction of inductance is desired.

[0005] An object of the present disclosure is to provide a semiconductor device capable of further reducing inductance.

Means for Solving the Problems

[0006] The semiconductor device of the present disclosure includes a first terminal and a metal plate in an electrically floating state, the first terminal having a first flat plate portion provided with a first surface and a second flat plate portion provided with a second surface facing the first surface and electrically connected to the first flat plate portion, and the metal plate being disposed between the first surface and the second surface.

Effects of the Invention

[0007] According to the present disclosure, inductance can be further reduced.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for implementation will be described below.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0011] 〔1〕 A semiconductor device according to an aspect of the present disclosure includes a first terminal and a metal plate in an electrically floating state, the first terminal having a first flat plate portion having a first surface and a second flat plate portion having a second surface facing the first surface and being electrically connected to the first flat plate portion, and the metal plate being disposed between the first surface and the second surface.

[0012] Since a metal plate in an electrically floating state is disposed between the first surface of the first flat plate portion and the second surface of the second flat plate portion, the inductance of the first terminal can be reduced.

[0013] 〔2〕 In 〔1〕, the first flat plate portion and the second flat plate portion may be arranged parallel to each other. In this case, it is easy to cancel the inductance between the first flat plate portion and the second flat plate portion.

[0014] 〔3〕In 〔1〕 or 〔2〕, the first terminal may have a third flat plate portion having a first end connected to the first flat plate portion and a second end connected to the second flat plate portion. In this case, it is easy to ensure conduction between the first flat plate portion and the second flat plate portion.

[0015] 〔4〕In 〔3〕, the third flat plate portion may be orthogonal to the first flat plate portion and the second flat plate portion. In this case, it is easy to adjust the shape of the first terminal.

[0016] 〔5〕In 〔3〕 or 〔4〕, it may have a third surface facing the third flat plate portion and a second terminal in which a current displacement occurs in a direction opposite to that of the third flat plate portion during energization. In this case, it is easy to cancel out the inductance between the first terminal and the second terminal.

[0017] 〔6〕In 〔1〕 to 〔5〕, the thickness of the metal plate may be equal to the thickness of the first flat plate portion and the thickness of the second flat plate portion. In this case, the metal plate can be cut out from the same material as the first flat plate portion and the second flat plate portion.

[0018] 〔7〕In 〔1〕 to 〔6〕, the thickness of the metal plate may be 10% or more and 80% or less of the distance between the first surface and the second surface. In this case, while reducing the inductance, it is easy to fill an insulating material between the metal plate and the first terminal.

[0019] 〔8〕In 〔1〕 to 〔7〕, the distance between the metal plate and the first surface may be 0.1 mm or more and 3.0 mm or less, and the distance between the metal plate and the second surface may be 0.1 mm or more and 3.0 mm or less. In this case, while reducing the inductance, it is easy to fill an insulating material between the metal plate and the first terminal.

[0020] 〔9〕In 〔1〕 to 〔8〕, the material of the metal plate may be a diamagnetic substance. In this case, it is easy to reduce the inductance.

[0021] 〔10〕In 〔9〕, the material of the metal plate may be copper. In this case, it is easy to obtain the metal plate.

[0022] 〔11〕 In [1] to [8], the material of the metal plate may be aluminum. In this case, the metal plate is easy to obtain.

[0023] 〔12〕 In [1] to

[11] , when viewed from a direction perpendicular to the second flat plate portion, the metal plate may overlap with a portion of 20% to 98% of the area of the first flat plate portion and the second flat plate portion. In this case, it is easy to avoid electrical connection between the metal plate and the first terminal while reducing the inductance.

[0024] 〔13〕 In [1] to

[12] , an insulating member provided between each of the first flat plate portion and the second flat plate portion and the metal plate may be provided. In this case, for example, the metal plate can be arranged between the first flat plate portion and the second flat plate portion by insert molding.

[0025] 〔14〕 In [1] to

[12] , an opening for inserting a bolt for fixing an external terminal connected to the first terminal is formed in the first flat plate portion, and a nut into which the bolt is inserted is provided between the first surface and the second surface. The nut is located on the second flat plate portion side of the metal plate, and the nut and the metal plate may be electrically insulated from each other. In this case, the metal plate can be arranged so as to overlap the nut while ensuring an electrically floating state.

[0026] 〔15〕 In [1] to

[14] , a silicon carbide semiconductor element connected to the first terminal may be provided. In this case, it is easy to achieve high withstand voltage and high-speed operation.

[0027] 〔16〕 In [1] to

[15] , an insulating film covering the metal plate may be provided. In this case, it is easy to maintain the metal plate in an electrically floating state.

[0028] [Details of Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present embodiments are not limited thereto. In the present specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant descriptions.

[0029] FIG. 1 and FIG. 2 are perspective views showing a semiconductor device according to an embodiment. FIG. 3 is a top view showing the semiconductor device according to the embodiment. However, in FIGS. 2 and 3, the case is shown in a perspective view. FIG. 4 is a cross-sectional view showing the relationship between the heat sink, the first insulating substrate, and the second insulating substrate in the semiconductor device according to the embodiment. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 3.

[0030] The semiconductor device 1 according to the embodiment mainly includes a heat sink 2, a case 9, a P terminal 3, an N terminal 4, a first O terminal 5, a second O terminal 6, a first metal plate 610, and a second metal plate 620. Hereinafter, the first O terminal 5 and the second O terminal 6 may be collectively referred to as an O terminal. The P terminal 3 is a power supply terminal on the positive electrode side, the N terminal 4 is a power supply terminal on the negative electrode side, and the first O terminal 5 and the second O terminal 6 are output terminals. The P terminal 3, the N terminal 4, the first O terminal 5, and the second O terminal 6 are assembled to the case 9. The case 9 is further assembled with a first gate terminal 131, a first sense source terminal 132, a sense drain terminal 133, a second gate terminal 231, a second sense source terminal 232, a first thermistor terminal 331, a second thermistor terminal 332, a first metal plate 610, and a second metal plate 620. The P terminal 3 is an example of the first terminal, and the N terminal 4 is an example of the second terminal.

[0031] In the present disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are perpendicular to each other. The plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For the sake of convenience, the Z1 direction is defined as the upward direction and the Z2 direction is defined as the downward direction. Also, in the present disclosure, a plan view means viewing an object from the Z1 side. The X1-X2 direction is the direction along the long side of the rectangular heat sink 2 and the case 9 in plan view, the Y1-Y2 direction is the direction along the short side of the heat sink 2 and the case 9, and the Z1-Z2 direction is the direction along the normal of the heat sink 2 and the case 9.

[0032] The heat sink 2 is, for example, a plate-like body with a uniform thickness and a rectangular shape in plan view. The heat sink 2 includes a first main surface 2A and a second main surface 2B opposite to the first main surface 2A. The material of the heat sink 2 is a metal with a high thermal conductivity, such as copper (Cu), copper alloy, aluminum (Al), etc. The heat sink 2 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.

[0033] The case 9 is, for example, formed in a frame shape in plan view, and the outer shape of the case 9 is the same as that of the heat sink 2. The material of the case 9 is an insulator such as resin. The case 9 has a pair of side wall portions 91 and 92 facing each other, and a pair of end wall portions 93 and 94 connecting both ends of the side wall portions 91 and 92. The side wall portions 91 and 92 are arranged parallel to the ZX plane, and the end wall portions 93 and 94 are arranged parallel to the YZ plane. The side wall portion 92 is arranged on the Y2 side of the side wall portion 91, and the end wall portion 94 is arranged on the X2 side of the end wall portion 93. The case 9 has a terminal block 95 protruding in the X1 direction from the end wall portion 93 and a terminal block 96 protruding in the X2 direction from the end wall portion 94. The case 9 is composed of an insulating material such as a molded resin. The case 9 is an example of an insulating member.

[0034] The P terminal 3 and the N terminal 4 are arranged on the upper surface (the surface on the Z1 side) of the terminal block 95, and the first O terminal 5 and the second O terminal 6 are arranged on the upper surface (the surface on the Z1 side) of the terminal block 96. For example, the N terminal 4 is arranged on the Y2 side of the P terminal 3, and the second O terminal 6 is arranged on the Y2 side of the first O terminal 5. The P terminal 3, the N terminal 4, the first O terminal 5, and the second O terminal 6 are made of a metal plate. One end of each of the P terminal 3 and the N terminal 4 is exposed on the X2 side of the end wall portion 93, and the other end of each is drawn out to the upper surface of the terminal block 95. One end of each of the first O terminal 5 and the second O terminal 6 is exposed on the X1 side of the end wall portion 94, and the other end of each is drawn out to the upper surface of the terminal block 96. The specific configurations of the P terminal 3 and the N terminal 4 will be described later together with the descriptions of the first metal plate 610 and the second metal plate 620.

[0035] The first gate terminal 131, the first sense source terminal 132, the sense drain terminal 133, the first thermistor terminal 331, and the second thermistor terminal 332 are attached to the side wall portion 91. One end of each of the first gate terminal 131, the first sense source terminal 132, the sense drain terminal 133, the first thermistor terminal 331, and the second thermistor terminal 332 is exposed on the Y2 side of the side wall portion 91, and the other end of each protrudes outward (on the Z1 side) from the upper surface (the surface on the Z1 side) of the side wall portion 91 to the outside of the case 9. The sense drain terminal 133 is arranged near the end on the X2 side of the side wall portion 91. The first thermistor terminal 331 and the second thermistor terminal 332 are arranged near the end on the X1 side of the side wall portion 91. For example, the second thermistor terminal 332 is arranged on the X1 side of the first thermistor terminal 331. The first gate terminal 131 and the first sense source terminal 132 are arranged near the center in the X1-X2 direction of the side wall portion 91 and on the X2 side of the center in the X1-X2 direction. For example, the first sense source terminal 132 is arranged on the X2 side of the first gate terminal 131.

[0036] On the side wall portion 92, a second gate terminal 231 and a second sense source terminal 232 are attached. One end of each of the second gate terminal 231 and the second sense source terminal 232 is exposed on the Y1 side of the side wall portion 92, and the other end of each protrudes outward (Z1 side) from the upper surface (surface on the Z1 side) of the side wall portion 92 to the outside of the case 9. The second gate terminal 231 and the second sense source terminal 232 are arranged near the center in the X1-X2 direction of the side wall portion 92 and on the X1 side of the center in the X1-X2 direction. For example, the second sense source terminal 232 is arranged on the X1 side of the second gate terminal 231.

[0037] On the Z1 side of the heat sink 2, a first insulating substrate 10 and a second insulating substrate 20 are arranged. That is, the first insulating substrate 10 and the second insulating substrate 20 are arranged on the first main surface 2A of the heat sink 2. For example, the second insulating substrate 20 is arranged on the X1 side of the first insulating substrate 10.

[0038] The first insulating substrate 10 has conductive layers 11, 12, 13, 14, and 18 on the surface on the Z1 side and a conductive layer 19 on the surface on the Z2 side. The conductive layer 19 is joined to the heat sink 2 by a joining material 7 such as solder. A plurality of, for example, four first transistors 110 are mounted on the conductive layer 13. The four first transistors 110 are arranged in the X1-X2 direction. The four first transistors 110 constitute a first transistor group 110A. A plurality of, for example, eight second diodes 220 are mounted on the conductive layer 12. The eight second diodes 220 are arranged in two rows with four in each row in the X1-X2 direction. The eight second diodes 220 constitute a second diode group 220A.

[0039] The second insulating substrate 20 has conductive layers 21, 22, 23, 24, 25, 26, 27, and 28 on the surface on the Z1 side, and has a conductive layer 29 on the surface on the Z2 side. The conductive layer 29 is joined to the heat sink 2 by a joining material 8 such as solder. A plurality of, for example, four second transistors 210 are mounted on the conductive layer 23. The four second transistors 210 are arranged in the X1-X2 direction. The four second transistors 210 constitute a second transistor group 210A. A plurality of, for example, eight first diodes 120 are mounted on the conductive layer 25. The eight first diodes 120 are arranged in two rows, with four in each row in the X1-X2 direction. The eight first diodes 120 constitute a first diode group 120A.

[0040] Here, the first transistor 110, the first diode 120, the second transistor 210, and the second diode 220 will be described. FIG. 5 is a cross-sectional view showing the first transistor. FIG. 6 is a cross-sectional view showing the first diode. FIG. 7 is a cross-sectional view showing the second transistor. FIG. 8 is a cross-sectional view showing the second diode.

[0041] As shown in FIG. 5, the first transistor 110 has a first gate electrode 111, a first source electrode 112, and a first drain electrode 113. The first gate electrode 111 and the first source electrode 112 are disposed on the main surface on the Z1 side of the first transistor 110, and the first drain electrode 113 is disposed on the main surface on the Z2 side of the first transistor 110. The first drain electrode 113 is joined to the conductive layer 13 by a joining material (not shown) such as solder.

[0042] As shown in FIG. 6, the first diode 120 has a first anode electrode 121 and a first cathode electrode 122. The first anode electrode 121 is disposed on the main surface on the Z1 side of the first diode 120, and the first cathode electrode 122 is disposed on the main surface on the Z2 side of the first diode 120. The first cathode electrode 122 is joined to the conductive layer 25 by a joining material (not shown) such as solder.

[0043] As shown in FIG. 7, the second transistor 210 has a second gate electrode 211, a second source electrode 212, and a second drain electrode 213. The second gate electrode 211 and the second source electrode 212 are disposed on the main surface of the second transistor 210 on the Z1 side, and the second drain electrode 213 is disposed on the main surface of the second transistor 210 on the Z2 side. The second drain electrode 213 is joined to the conductive layer 23 by a joining material such as solder (not shown).

[0044] As shown in FIG. 8, the second diode 220 has a second anode electrode 221 and a second cathode electrode 222. The second anode electrode 221 is disposed on the main surface of the second diode 220 on the Z1 side, and the second cathode electrode 222 is disposed on the main surface of the second diode 220 on the Z2 side. The second cathode electrode 222 is joined to the conductive layer 12 by a joining material such as solder (not shown).

[0045] The semiconductor device 1 includes a plurality of wires 31, a plurality of wires 32, a plurality of wires 41, and a plurality of wires 42. The wire 31 connects the conductive layer 13 provided on the first insulating substrate 10 and the conductive layer 25 provided on the second insulating substrate 20. The wire 32 connects the conductive layer 12 provided on the first insulating substrate 10 and the conductive layer 24 provided on the second insulating substrate 20. The wire 41 connects the conductive layer 12 provided on the first insulating substrate 10 and the conductive layer 23 provided on the second insulating substrate 20. The wire 42 connects the conductive layer 14 provided on the first insulating substrate 10 and the conductive layer 22 provided on the second insulating substrate 20.

[0046] The semiconductor device 1 includes a plurality of wires 51, a plurality of wires 52, a plurality of wires 53, a plurality of wires 54, and a plurality of wires 55. The wire 51 connects the first gate electrodes 111 respectively provided on four first transistors 110 and the conductive layer 11 provided on the first insulating substrate 10. The wire 52 connects the first source electrodes 112 respectively provided on four first transistors 110 and the conductive layer 12 provided on the first insulating substrate 10. The wire 53 connects the first sense source electrodes (not shown) respectively provided on four first transistors 110 and the conductive layer 18 provided on the first insulating substrate 10. The wire 54 connects the second anode electrodes 221 respectively provided on four second diodes 220 arranged on the Y1 side among eight second diodes 220 and the conductive layer 14 provided on the first insulating substrate 10. The wire 55 connects the second anode electrodes 221 respectively provided on four second diodes 220 arranged on the Y1 side among eight second diodes 220 and the second anode electrodes 221 respectively provided on four second diodes 220 arranged on the Y2 side.

[0047] The semiconductor device 1 includes a wire 61, a plurality of wires 62, a plurality of wires 63, a wire 64, and a wire 65. The wire 61 connects the conductive layer 11 provided on the first insulating substrate 10 and the first gate terminal 131. The wire 62 connects the conductive layer 12 provided on the first insulating substrate 10 and the first O terminal 5. The wire 63 connects the conductive layer 12 provided on the first insulating substrate 10 and the second O terminal 6. The wire 64 connects the conductive layer 13 provided on the first insulating substrate 10 and the sense drain terminal 133. The wire 65 connects the conductive layer 18 provided on the first insulating substrate 10 and the first sense source terminal 132.

[0048] The semiconductor device 1 has a plurality of wires 71, a plurality of wires 72, a plurality of wires 73, a plurality of wires 74, and a plurality of wires 75. The wire 71 connects the second gate electrodes 211 respectively provided on four second transistors 210 and the conductive layer 21 provided on the second insulating substrate 20. The wire 72 connects the second source electrodes 212 respectively provided on four second transistors 210 and the conductive layer 22 provided on the second insulating substrate 20. The wire 73 connects the second sense source electrodes (not shown) respectively provided on four second transistors 210 and the conductive layer 28 provided on the second insulating substrate 20. The wire 74 connects the first anode electrodes 121 respectively provided on four first diodes 120 arranged on the Y2 side among eight first diodes 120 and the conductive layer 24 provided on the second insulating substrate 20. The wire 75 connects the first anode electrodes 121 respectively provided on four first diodes 120 arranged on the Y2 side among eight first diodes 120 and the first anode electrodes 121 respectively provided on four first diodes 120 arranged on the Y1 side.

[0049] The semiconductor device 1 has a wire 81, a plurality of wires 82, a plurality of wires 83, a wire 85, a wire 86, and a wire 87. The wire 81 connects the conductive layer 21 provided on the second insulating substrate 20 and the second gate terminal 231. The wire 82 connects the conductive layer 22 provided on the second insulating substrate 20 and the N terminal 4. The wire 83 connects the conductive layer 25 provided on the second insulating substrate 20 and the P terminal 3. The wire 85 connects the conductive layer 28 provided on the second insulating substrate 20 and the second sense source terminal 232. The wire 86 connects the conductive layer 26 provided on the second insulating substrate 20 and the first thermistor terminal 331. The wire 87 connects the conductive layer 27 provided on the second insulating substrate 20 and the second thermistor terminal 332. The semiconductor device 1 has a thermistor 330 connected to the conductive layer 26 and the conductive layer 27.

[0050] Here, the circuit configuration of the semiconductor device 1 according to the embodiment will be described. FIG. 9 is a circuit diagram showing the semiconductor device according to the embodiment.

[0051] The first cathode electrode 122 of the first diode 120 is connected to the P terminal 3 via the wire 83 and the conductive layer 25. Also, the first drain electrode 113 of the first transistor 110 is connected to the P terminal 3 via the wire 83, the conductive layer 25, the wire 31, and the conductive layer 13. The conductive layer 12 is connected to the first O terminal 5 via the wire 62 and to the second O terminal 6 via the wire 63. The first source electrode 112 of the first transistor 110 is connected to the conductive layer 12 via the wire 52. Also, the first anode electrode 121 of the first diode is connected to the conductive layer 12 via the wire 32, the conductive layer 24, and the wires 74 and 75.

[0052] The first gate electrode 111 of the first transistor 110 is connected to the first gate terminal 131 via the wire 61, the conductive layer 11, and the wire 51. The first sense source electrode of the first transistor 110 is connected to the first sense source terminal 132 via the wire 65, the conductive layer 18, and the wire 53. The first drain electrode 113 of the first transistor 110 is connected to the sense drain terminal 133 via the wire 64 and the conductive layer 13.

[0053] The second source electrode 212 of the second transistor 210 is connected to the N terminal 4 via the wire 82, the conductive layer 22, and the wire 72. Also, the second anode electrode 221 of the second diode 220 is connected to the N terminal 4 via the wire 82, the conductive layer 22, the wire 42, and the wires 54 and 55. The second cathode electrode 222 of the second transistor 210 is connected to the conductive layer 12. Also, the second drain electrode 213 of the second transistor 210 is connected to the conductive layer 12 via the wire 41 and the conductive layer 23.

[0054] The second gate electrode 211 of the second transistor 210 is connected to the second gate terminal 231 via the wire 81, the conductive layer 21, and the wire 71. The second sense source electrode of the second transistor 210 is connected to the second sense source terminal 232 via the wire 85, the conductive layer 28, and the wire 73. One electrode of the thermistor 330 is connected to the first thermistor terminal 331 via the wire 86 and the conductive layer 26. The other electrode of the thermistor 330 is connected to the second thermistor terminal 332 via the wire 87 and the conductive layer 27.

[0055] As shown in FIG. 9, the first drain electrode 113 of the first transistor 110 and the first cathode electrode 122 of the first diode 120 are commonly connected to the P terminal 3, and the first source electrode 112 and the first anode electrode 121 are commonly connected to the first O terminal 5 and the second O terminal 6. That is, the first transistor 110 and the first diode 120 are connected in parallel between the P terminal 3 and the first O terminal 5 and the second O terminal 6. As shown in FIGS. 1 to 3, a plurality of sets of the first transistor 110 and the first diode 120 are connected in parallel between the P terminal 3 and the first O terminal 5 and the second O terminal 6.

[0056] Also, the second drain electrode 213 of the second transistor 210 and the second cathode electrode 222 of the second diode 220 are commonly connected to the first O terminal 5 and the second O terminal 6, and the second source electrode 212 and the second anode electrode 221 are commonly connected to the N terminal 4. That is, the second transistor 210 and the second diode 220 are connected in parallel between the N terminal 4 and the first O terminal 5 and the second O terminal 6. As shown in FIGS. 1 to 3, a plurality of sets of the second transistor 210 and the second diode 220 are connected in parallel between the N terminal 4 and the first O terminal 5 and the second O terminal 6.

[0057] The upper arm 100 includes a first transistor 110 (first transistor group 110A) and a first diode 120 (first diode group 120A). The lower arm 200 includes a second transistor 210 (second transistor group 210A) and a second diode 220 (second diode group 220A). The upper arm 100 and the lower arm 200 are connected in series between the P terminal 3 and the N terminal 4. The upper arm 100 may include the P terminal 3 and the O terminal, and the lower arm 200 may include the N terminal and the O terminal.

[0058] The plurality of first transistors 110 included in the upper arm 100 may be provided only on the first insulating substrate 10, and the plurality of first diodes 120 included in the upper arm 100 may be provided only on the second insulating substrate 20. Also, the plurality of second transistors 210 included in the lower arm 200 may be provided only on the second insulating substrate 20, and the plurality of second diodes 220 included in the lower arm 200 may be provided only on the first insulating substrate 10.

[0059] Here, the details of the first metal plate 610, the second metal plate 620, the P terminal 3, and the N terminal 4 will be described. FIG. 10 is an exploded perspective view showing the first metal plate 610, the second metal plate 620, the P terminal 3, and the N terminal 4. FIG. 11 is a cross-sectional view showing the first metal plate 610, the second metal plate 620, the P terminal 3, and the N terminal 4.

[0060] As shown in FIGS. 10 and 11, the P terminal 3 has a first flat plate portion 410, a second flat plate portion 420, and a third flat plate portion 430. The first flat plate portion 410 and the second flat plate portion 420 are arranged parallel to the XY plane. The second flat plate portion 420 is arranged on the Z1 side of the first flat plate portion 410. The first flat plate portion 410 has a first surface 410A on the Z1 side, and the second flat plate portion 420 has a second surface 420A on the Z2 side. The first surface 410A and the second surface 420A face each other. The first flat plate portion 410 has a wire connection portion 415 that protrudes toward the X2 side from the second flat plate portion 420 in plan view. A plurality of wires 83 are connected to the wire connection portion 415. The third flat plate portion 430 is arranged parallel to the ZX plane. The third flat plate portion 430 is arranged on the Y2 side of the first flat plate portion 410 and the second flat plate portion 420. The third flat plate portion 430 has a first end portion 431 connected to the first flat plate portion 410 and a second end portion 432 connected to the second flat plate portion 420. The third flat plate portion 430 has a sixth surface 430A on the Y2 side. A through hole 425 into which a bolt is inserted is formed in the second flat plate portion 420. This bolt is used to fix an external terminal connected to the P terminal 3.

[0061] As shown in FIGS. 10 and 11, the N terminal 4 has a fourth flat plate portion 440, a fifth flat plate portion 450, and a sixth flat plate portion 460. The fourth flat plate portion 440 and the fifth flat plate portion 450 are arranged parallel to the XY plane. The fifth flat plate portion 450 is arranged on the Z1 side of the fourth flat plate portion 440. The fourth flat plate portion 440 has a fourth surface 440A on the Z1 side, and the fifth flat plate portion 450 has a fifth surface 450A on the Z2 side. The fourth surface 440A and the fifth surface 450A face each other. The fourth flat plate portion 440 has a wire connection portion 445 that protrudes to the X2 side from the fifth flat plate portion 450 in a plan view. A plurality of wires 82 are connected to the wire connection portion 445. The sixth flat plate portion 460 is arranged parallel to the ZX plane. The sixth flat plate portion 460 is arranged on the Y1 side of the fourth flat plate portion 440 and the fifth flat plate portion 450. The sixth flat plate portion 460 has a third end portion 461 connected to the fourth flat plate portion 440 and a fourth end portion 462 connected to the fifth flat plate portion 450. The sixth flat plate portion 460 has a third surface 460A on the Y1 side. A through hole 455 into which a bolt is inserted is formed in the fifth flat plate portion 450. This bolt is used to fix an external terminal connected to the N terminal 4.

[0062] The third surface 460A of the sixth flat plate portion 460 faces the P terminal 3, and the sixth surface 430A of the third flat plate portion 430 faces the N terminal 4. The third surface 460A and the sixth surface 430A face each other.

[0063] The first metal plate 610 is arranged between the first surface 410A and the second surface 420A. The second metal plate 620 is arranged between the fourth surface 440A and the fifth surface 450A. The first metal plate 610 and the second metal plate 620 are arranged parallel to the XY plane. The first metal plate 610 and the second metal plate 620 are in an electrically floating state. That is, the first metal plate 610 and the second metal plate 620 are electrically insulated from other members.

[0064] Next, the operation of the semiconductor device 1 according to the embodiment will be described. FIGS. 12 to 15 are schematic diagrams showing the operation of the semiconductor device according to the embodiment.

[0065] Figure 12 shows the path of current I1 flowing from P terminal 3 to the first O terminal 5 and the second O terminal 6. As shown in Figure 12, current I1 flows from P terminal 3 through wire 83, conductive layer 25, wire 31, conductive layer 13, the first transistor group 110A, wire 52, conductive layer 12, and wires 62 and 63 to the first O terminal 5 and the second O terminal 6.

[0066] Figure 13 shows the path of current I2 flowing from the first O terminal 5 and the second O terminal 6 to P terminal 3. As shown in Figure 13, current I2 flows from the first O terminal 5 and the second O terminal 6 through wires 62 and 63, conductive layer 12, wire 32, conductive layer 24, wires 74 and 75, the first diode group 120A, conductive layer 25, and wire 83 to P terminal 3.

[0067] Thus, the current I1 flowing from P terminal 3 to the first O terminal 5 and the second O terminal 6 flows through wire 31 but not through wire 32. On the other hand, the current I2 flowing from the first O terminal 5 and the second O terminal 6 to P terminal 3 flows through wire 32 but not through wire 31.

[0068] Figure 14 shows the path of current I3 flowing from N terminal 4 to the first O terminal 5 and the second O terminal 6. As shown in Figure 14, current I3 flows from N terminal 4 through wire 82, conductive layer 22, wire 72, the second transistor group 210A, conductive layer 23, wire 41, conductive layer 12, and wires 62 and 63 to the first O terminal 5 and the second O terminal 6.

[0069] Figure 15 shows the path of current I4 flowing from the first O terminal 5 and the second O terminal 6 to N terminal 4. As shown in Figure 15, current I4 flows from the first O terminal 5 and the second O terminal 6 through wires 62 and 63, conductive layer 12, the second diode group 220A, wires 54 and 55, conductive layer 14, wire 42, conductive layer 22, and wire 82 to N terminal 4.

[0070] Thus, the current I3 flowing from the N terminal 4 to the first O terminal 5 and the second O terminal 6 flows through the wire 41 but not through the wire 42. On the other hand, the current I4 flowing from the first O terminal 5 and the second O terminal 6 to the N terminal 4 flows through the wire 42 but not through the wire 41.

[0071] In the semiconductor device 1 according to the embodiment, the upper arm 100 includes a first transistor 110 and a first diode 120. The first transistor 110 is provided on the first insulating substrate 10, and the first diode 120 is provided on the second insulating substrate 20. Therefore, between the current I1 flowing from the P terminal 3 to the first O terminal 5 and the second O terminal 6 and the current I2 flowing from the first O terminal 5 and the second O terminal 6 to the P terminal 3, the wires 31 and 32 through which they pass are different. Accordingly, the heat generation amount in the wires 31 and 32 can be reduced as compared with the case where the current flowing between the first insulating substrate 10 and the second insulating substrate 20 passes through the same connection member.

[0072] Similarly, the lower arm 200 includes a second transistor 210 and a second diode 220. The second transistor 210 is provided on the second insulating substrate 20, and the second diode 220 is provided on the first insulating substrate 10. Therefore, between the current I3 flowing from the N terminal 4 to the first O terminal 5 and the second O terminal 6 and the current I4 flowing from the first O terminal 5 and the second O terminal 6 to the N terminal 4, the wires 41 and 42 through which they pass are different. Accordingly, the heat generation amount in the wires 41 and 42 can be reduced as compared with the case where the current flowing between the first insulating substrate 10 and the second insulating substrate 20 passes through the same connection member.

[0073] By reducing the heat generation amount in this way, it is possible to suppress the possibility that the heat generation amount of the connection member and the wire becomes excessive, and to reduce the possibility that the wire is blown.

[0074] Also, in this embodiment, since the first metal plate 610 is provided between the first flat plate portion 410 and the second flat plate portion 420 of the P terminal 3, the self-inductance in the first flat plate portion 410 and the second flat plate portion 420 of the P terminal 3 can be reduced. Furthermore, since the first flat plate portion 410 and the second flat plate portion 420 are arranged parallel to each other, it is easy to cancel out the inductance between the first flat plate portion 410 and the second flat plate portion 420.

[0075] Similarly, since the second metal plate 620 is provided between the fourth flat plate portion 440 and the fifth flat plate portion 450 of the N terminal 4, the self-inductance in the fourth flat plate portion 440 and the fifth flat plate portion 450 of the N terminal 4 can be reduced. Furthermore, since the fourth flat plate portion 440 and the fifth flat plate portion 450 are arranged parallel to each other, it is easy to cancel out the inductance between the fourth flat plate portion 440 and the fifth flat plate portion 450.

[0076] When viewed from a direction perpendicular to the second flat plate portion 420, the first metal plate 610 preferably overlaps with a portion of the first flat plate portion 410 and the second flat plate portion 420 that is 20% or more and 98% or less of the area. The more the overlapping portion in plan view, the easier it is to reduce the inductance. On the other hand, if the overlapping portion in plan view exceeds 98% of the area, the possibility that the first metal plate 610 is electrically connected to the third flat plate portion 430 increases. When viewed from a direction perpendicular to the second flat plate portion 420, the first metal plate 610 preferably overlaps with a portion of the first flat plate portion 410 and the second flat plate portion 420 that is more preferably 50% or more and 95% or less of the area, and even more preferably 70% or more and 90% or less of the area. Similarly, when viewed from a direction perpendicular to the fifth flat plate portion 450, the second metal plate 620 preferably overlaps with a portion of the fourth flat plate portion 440 and the fifth flat plate portion 450 that is 20% or more and 98% or less of the area, more preferably 50% or more and 95% or less of the area, and even more preferably 70% or more and 90% or less of the area.

[0077] Note that the operations shown in FIGS. 12 to 15 are repeated at high speed. For this reason, in the semiconductor device 1, when the first transistor 110 of the upper arm 100 turns off, the current commutes to the second diode 220 of the lower arm 200, and the current flowing through the first transistor 110 decreases. At this time, while the amount of current flowing through the third flat plate portion 430 from the Z1 side to the Z2 side decreases, the amount of current flowing through the sixth flat plate portion 460 from the Z2 side to the Z1 side may increase. Conversely, when the first transistor 110 of the upper arm 100 turns on, the current flows out to the first transistor 110, and the current commuting to the second diode 220 decreases. At this time, while the amount of current flowing through the third flat plate portion 430 from the Z1 side to the Z2 side increases, the amount of current flowing through the sixth flat plate portion 460 from the Z2 side to the Z1 side may decrease.

[0078] Furthermore, when the second transistor 210 of the lower arm 200 turns off, the current commutes to the first diode 120 of the upper arm 100, and the current flowing through the second transistor 210 decreases. At this time, while the amount of current flowing through the third flat plate portion 430 from the Z2 side to the Z1 side increases, the amount of current flowing through the sixth flat plate portion 460 from the Z2 side to the Z1 side may decrease. Conversely, when the second transistor 210 of the lower arm 200 turns on, the current flows out to the second transistor 210, and the current commuting to the first diode 120 decreases. At this time, while the amount of current flowing through the third flat plate portion 430 from the Z2 side to the Z1 side decreases, the amount of current flowing through the sixth flat plate portion 460 from the Z2 side to the Z1 side may increase.

[0079] Thus, during switching, a current displacement occurs in the opposite direction between the P terminal 3 and the N terminal 4.

[0080] Therefore, in the present embodiment, the inductance can be reduced even between the P terminal 3 and the N terminal 4. In particular, since the third flat plate portion 430 is orthogonal to the first flat plate portion 410 and the second flat plate portion 420, and the sixth flat plate portion 460 is orthogonal to the fourth flat plate portion 440 and the fifth flat plate portion 450, it is easy to reduce the inductance between the P terminal 3 and the N terminal 4. In this case, an effect that the shapes of the P terminal 3 and the N terminal 4 can be easily adjusted is also obtained.

[0081] The thickness of the first metal plate 610 is preferably 10% or more and 80% or less, more preferably 30% or more and 75% or less, and still more preferably 50% or more and 70% or less of the distance between the first surface 410A and the second surface 420A. The higher the ratio of the first metal plate 610 occupying the space between the first surface 410A and the second surface 420A, the easier it is to reduce the inductance. On the other hand, the higher this ratio, the higher the possibility that it becomes difficult to fill an insulating material such as a mold resin constituting the case 9 between the first metal plate 610 and the P terminal 3. Similarly, the thickness of the second metal plate 620 is preferably 10% or more and 80% or less, more preferably 30% or more and 75% or less, and still more preferably 50% or more and 70% or less of the distance between the fourth surface 440A and the fifth surface 450A.

[0082] Preferably, the distance between the first metal plate 610 and the first surface 410A is 0.1 mm or more and 3.0 mm or less, and the distance between the first metal plate 610 and the second surface 420A is 0.1 mm or more and 3.0 mm or less. More preferably, the distance between the first metal plate 610 and the first surface 410A is 0.3 mm or more and 2.8 mm or less, and the distance between the first metal plate 610 and the second surface 420A is 0.3 mm or more and 2.8 mm or less. Even more preferably, the distance between the first metal plate 610 and the first surface 410A is 0.5 mm or more and 2.5 mm or less, and the distance between the first metal plate 610 and the second surface 420A is 0.5 mm or more and 2.5 mm or less. Similarly, the distance between the second metal plate 620 and the fourth surface 440A is 0.1 mm or more and 3.0 mm or less, and the distance between the second metal plate 620 and the fifth surface 450A is 0.1 mm or more and 3.0 mm or less. More preferably, the distance between the second metal plate 620 and the fourth surface 440A is 0.3 mm or more and 2.8 mm or less, and the distance between the second metal plate 620 and the fifth surface 450A is 0.3 mm or more and 2.8 mm or less. Even more preferably, the distance between the second metal plate 620 and the fourth surface 440A is 0.5 mm or more and 2.5 mm or less, and the distance between the second metal plate 620 and the fifth surface 450A is 0.5 mm or more and 2.5 mm or less. As described above, this is for inductance reduction and ease of filling the insulating material.

[0083] The thicknesses of the first flat plate portion 410, the second flat plate portion 420, and the third flat plate portion 430 may be uniform. The thickness of the first metal plate 610 may be equal to the thicknesses of the first flat plate portion 410 and the second flat plate portion 420. In this case, the first metal plate 610 can be cut out from the same material as the metal plate that becomes the P terminal 3.

[0084] Similarly, the thicknesses of the fourth flat plate portion 440, the fifth flat plate portion 450, and the sixth flat plate portion 460 may be uniform. The thickness of the second metal plate 620 may be equal to the thicknesses of the fourth flat plate portion 440 and the fifth flat plate portion 450. In this case, the second metal plate 620 can be cut out from the same material as the metal plate that becomes the N terminal 4.

[0085] The metal plate that becomes the P terminal 3, the metal plate that becomes the N terminal 4, the first metal plate 610, and the second metal plate 620 may be cut out from the same material.

[0086] The materials of the first metal plate 610 and the second metal plate 620 are preferably diamagnetic materials. This is because it is easy to reduce the inductance of the P terminal 3 and the N terminal 4. For example, the materials of the first metal plate 610 and the second metal plate 620 may be copper. In this case, the first metal plate 610 and the second metal plate 620 are easy to obtain. The materials of the first metal plate 610 and the second metal plate 620 are not limited to diamagnetic materials, and may be aluminum, gold, or the like. In this case as well, the first metal plate 610 and the second metal plate 620 are easy to obtain.

[0087] The first metal plate 610 and the second metal plate 620 can be embedded in the case 9 during insert molding of the case 9. For example, as shown in FIG. 16, the first metal plate 610 and the second metal plate 620 are formed to a size that protrudes from the case 9, and the portions protruding from the case 9 are supported so that the first metal plate 610 and the second metal plate 620 do not contact the P terminal 3 and the N terminal 4. Then, insert molding is performed while supporting the portions protruding from the case 9, and after insert molding, the portions protruding from the case 9 are cut. In this way, the first metal plate 610 and the second metal plate 620 can be embedded in the case 9.

[0088] Also, the first metal plate 610 can be embedded in the case 9 by the method shown in FIGS. 17 to 20.

[0089] First, as shown in FIG. 17, when insert molding the case 9, while embedding the first metal plate 610 in the case 9, a hole 720 for inserting a nut 710 (see FIG. 19) that receives a bolt inserted into the through hole 425 of the second flat plate portion 420 is formed on the Z1 side of the first flat plate portion 410. Also, when insert molding the case 9, a hole 730 into which the first metal plate 610 is fitted via a latch 721 is formed on the side of the first flat plate portion 410 (Z2 side) closer to the hole 720. At this time, the portion that becomes the second flat plate portion 420 is in a state parallel to the ZX plane on the extension line of the third flat plate portion 430, similar to the third flat plate portion 430.

[0090] Next, as shown in FIG. 18, insert the first metal plate 610 into the hole 730 and fix the first metal plate 610 in the hole 730 with the latch 721.

[0091] Next, as shown in FIG. 19, insert the nut 710 into the hole 720. The nut 710 may be placed on the latch 721.

[0092] Next, as shown in FIG. 20, by bending the portion that becomes the second flat plate portion 420, the second flat plate portion 420 is formed. The second flat plate portion 420 functions as a lid for the hole 720 and prevents the nut 710 from falling out of the hole 720. The nut 710 is located between the first surface 410A and the second surface 420A. The nut 710 is located closer to the second flat plate portion 420 than the first metal plate 610.

[0093] In this way, the first metal plate 610 can be embedded in the case 9. The first metal plate 610 and the second metal plate 620 are electrically insulated from the nut 710 by the latch 721 provided on the case 9. Therefore, if the bolt inserted into the through hole 425 of the second flat plate portion 420 does not contact the first metal plate 610, the first metal plate 610 can be maintained in an electrically floating state. Note that the second metal plate 620 can also be embedded in the case 9 by the same method.

[0094] Note that the first metal plate 610 and the second metal plate 620 may be covered with an insulating film. For example, as shown in FIG. 21, the semiconductor device 1 may include an insulating film 611 that covers the first metal plate 610 and an insulating film 621 that covers the second metal plate 620. By forming the insulating films 611 and 621, it is easy to maintain the first metal plate 610 and the second metal plate 620 in an electrically floating state. During insert molding, the first metal plate 610 may be molded into the case 9 together with the insulating film 611, and the second metal plate 620 may be molded into the case 9 together with the insulating film 621.

[0095] The thicknesses of the insulating films 611 and 621 are preferably 10 nm or more and 2 mm or less, more preferably 100 nm or more and 1 mm or less, and still more preferably 200 nm or more and 1 mm or less.

[0096] The semiconductor device 1 does not necessarily need to include both the first metal plate 610 and the second metal plate 620. If it has at least either the first metal plate 610 or the second metal plate 620, the inductance can be reduced compared to a conventional semiconductor device.

[0097] The first transistor 110 and the second transistor 210 may be field effect transistors such as MOS (metal-oxide-semiconductor) field effect transistors configured using silicon carbide. The first diode 120 and the second diode 220 may be Schottky barrier diodes configured using silicon carbide. Thus, the first transistor 110, the second transistor 210, the first diode 120, and the second diode 220 may be silicon carbide semiconductor elements. By using silicon carbide semiconductor elements, it is easy to achieve high breakdown voltage and high-speed operation.

[0098] Although the embodiments have been described in detail above, the present invention is not limited to specific embodiments, and various modifications and changes are possible within the scope described in the claims.

Description of Reference Numerals

[0099] 1: Semiconductor device 2: Heat sink 2A: First main surface 2B: Second main surface 3: P terminal (first terminal) 4: N terminal (second terminal) 5: First O terminal 6: Second O terminal 7, 8: Bonding material 9: Case 10: First insulating substrate 11, 12, 13, 14, 18, 19: Conductive layer 20: Second insulating substrate 21, 22, 23, 24, 25, 26, 27, 28, 29: Conductive layer 31, 32, 41, 42, 51, 52, 53, 54, 55, 61, 62, 63, 64, 65, 71, 72, 73, 74, 75, 81, 82, 83, 85, 86, 87: Wire 91, 92: Side wall part 93, 94: End wall part 95, 96: Terminal block 100: Upper arm 110: First transistor (silicon carbide semiconductor element) 110A: First transistor group 111: First gate electrode 112: First source electrode 113: First drain electrode 120: First diode (silicon carbide semiconductor element) 120A: First diode group 121: First anode electrode 122: First cathode electrode 131: First gate terminal 132: First sense source terminal 133: Sense drain terminal 200: Lower arm 210: Second transistor (silicon carbide semiconductor element) 210A: Second transistor group 211: Second gate electrode 212: Second source electrode 213: Second drain electrode 220: Second Diode (Silicon Carbide Semiconductor Element) 220A: Second Diode Group 221: Second Anode Electrode 222: Second Cathode Electrode 231: Second Gate Terminal 232: Second Sense Source Terminal 330: Thermistor 331: First Thermistor Terminal 332: Second Thermistor Terminal 410: First Flat Plate Portion 410A: First Surface 415: Wire Connection Portion 420: Second Flat Plate Portion 420A: Second Surface 425: Through Hole 430: Third Flat Plate Portion 430A: Sixth Surface 431: First End 432: Second End 440: Fourth Flat Plate Portion 440A: Fourth Surface 445: Wire Connection Portion 450: Fifth Flat Plate Portion 450A: Fifth Surface 455: Through Hole 460: Sixth Flat Plate Portion 460A: Third Surface 461: Third End 462: Fourth End 610: First Metal Plate 611: Insulating Film 620: Second Metal Plate 621: Insulating Film 710: Nut 720: Hole 721: Latch 730: Hole I1, I2, I3, I4: Current

Claims

1. A first terminal, a metal plate in an electrically floating state, and having, wherein the first terminal has a first flat plate portion having a first surface, a second flat plate portion having a second surface facing the first surface and electrically connected to the first flat plate portion, and having, wherein the metal plate is disposed between the first surface and the second surface, when viewed from a direction perpendicular to the second flat plate portion, the metal plate overlaps with 20% to 98% of the areas of the first flat plate portion and the second flat plate portion, a semiconductor device.

2. The semiconductor device according to claim 1, having an insulating film covering the metal plate.

3. A first terminal, a metal plate in an electrically floating state, and having, wherein the first terminal has a first flat plate portion having a first surface, a second flat plate portion having a second surface facing the first surface and electrically connected to the first flat plate portion, and having, wherein the metal plate is disposed between the first surface and the second surface, a semiconductor device having an insulating film covering the metal plate.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first flat plate portion and the second flat plate portion are arranged parallel to each other.

5. wherein the first terminal has a third flat plate portion having a first end connected to the first flat plate portion and a second end connected to the second flat plate portion, the semiconductor device according to any one of claims 1 to 4.

6. The semiconductor device according to claim 5, wherein the third flat plate portion is perpendicular to the first flat plate portion and the second flat plate portion.

7. The semiconductor device according to claim 5 or claim 6, having a second terminal having a third surface facing the third flat plate portion and a current displacement occurring in a direction opposite to the third flat plate portion during energization.

8. The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the metal plate is equal to the thickness of the first flat plate portion and the thickness of the second flat plate portion.

9. The semiconductor device according to any one of claims 1 to 8, wherein the thickness of the metal plate is 10% to 80% of the distance between the first surface and the second surface.

10. The distance between the metal plate and the first surface is 0.1 mm or more and 3.0 mm or less, the distance between the metal plate and the second surface is 0.1 mm or more and 3.0 mm or less, the semiconductor device according to any one of claims 1 to 9.

11. The semiconductor device according to any one of claims 1 to 10, wherein the material of the metal plate is a diamagnetic substance.

12. The semiconductor device according to claim 11, wherein the material of the metal plate is copper.

13. The semiconductor device according to any one of claims 1 to 10, wherein the material of the metal plate is aluminum.

14. The semiconductor device according to any one of claims 1 to 13, comprising an insulating member provided between each of the first flat plate portion and the second flat plate portion and the metal plate.

15. An opening for inserting a bolt for fixing an external terminal connected to the first terminal is formed in the first flat plate portion, a nut into which the bolt is inserted is provided between the first surface and the second surface, the nut is located on the second flat plate portion side of the metal plate, the semiconductor device according to any one of claims 1 to 13, wherein the nut and the metal plate are electrically insulated from each other.

16. The semiconductor device according to any one of claims 1 to 15, comprising a silicon carbide semiconductor element connected to the first terminal.

Images