Wiring Substrate and Method for Manufacturing the Same

Abstract

To provide a wiring board that can be applied to a semiconductor device that requires a high operating frequency used in high-speed communications, a semiconductor device that has the wiring board, and a manufacturing methods thereof.SOLUTION: A wiring board 100 includes a base film 102 including an organic compound, first wiring 104 including copper and located on the base film and a first protective film 108 located on the first wiring and in contact with the first wiring. The first protective film includes a first inorganic compound layer 108a containing silicon nitride, a second inorganic compound layer 108b located on the first inorganic compound layer, in contact with the first inorganic compound layer, and containing silicon oxide, and a third inorganic compound layer 108c located on the second inorganic compound layer, in contact with the second inorganic compound layer, and containing silicon nitride.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a wiring board that can be used as an interposer, a semiconductor device having the wiring board, and methods for manufacturing them.

Background Art

[0002] Semiconductor chips manufactured using semiconductor substrates such as silicon are mounted on almost all electronic devices and provide various functions to the electronic devices. Terminals for inputting power and signals necessary for operation are provided on the semiconductor chips, and the semiconductor chips are mounted on a main board. At this time, a wiring board (hereinafter also referred to as an interposer) is provided between the semiconductor chip and the main board. The interposer has a substrate and a plurality of wirings as basic components, and the wirings are provided on the substrate in various forms. For example, as through-wirings formed to penetrate the substrate, or as multilayer wirings embedded in an insulating film provided on the substrate and arranged to form a plurality of wiring layers. Through such wirings, the terminals of the semiconductor chip and the wirings on the main board are electrically connected. For example, Patent Document 1 discloses an interposer having multilayer wirings in which a plurality of wirings containing copper are laminated via an insulating film and a method for manufacturing the same.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One of the problems of the present disclosure is to provide a wiring board that can be used as an interposer and a method for manufacturing the same. For example, one of the problems of the present disclosure is to provide a wiring board, a semiconductor device having the wiring board, and methods for manufacturing them that are applicable to semiconductor devices that require high operating frequencies, such as those used in high-speed communication.

Means for Solving the Problem

[0005] One embodiment of the present disclosure is a wiring board. This wiring board has a base film containing an organic compound, a first wiring located on the base film and containing copper, and a first protective film located on the first wiring and in contact with the first wiring. The first protective film includes a first inorganic compound layer containing silicon nitride, a second inorganic compound layer located on the first inorganic compound layer and in contact with the first inorganic compound layer and containing silicon oxide, and a third inorganic compound layer located on the second inorganic compound layer and in contact with the second inorganic compound layer and containing silicon nitride.

[0006] One embodiment of the present disclosure is a wiring board. This wiring board has a substrate having a first surface and a second surface facing the first surface, a base film on the substrate, a first wiring located on the first surface and embedded in the base film and containing copper, a first protective film located on the first wiring and in contact with the first wiring, a second wiring on the first protective film, and a second protective film on the second wiring. The first protective film includes a first inorganic compound layer containing silicon nitride and a second inorganic compound layer located on the first inorganic compound layer and in contact with the first inorganic compound layer and containing silicon oxide. The second protective film includes a first inorganic compound layer containing silicon nitride, a second inorganic compound layer located on the first inorganic compound layer and in contact with the first inorganic compound layer and containing silicon oxide, and a third inorganic compound layer located on the second inorganic compound layer and in contact with the second inorganic compound layer and containing silicon nitride.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings and the like. However, the present disclosure can be implemented in various modes without departing from the gist thereof, and is not to be construed as being limited to the description of the embodiments illustrated below.

[0009] For the sake of clarity in the description, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual aspect, but this is merely an example and does not limit the interpretation of the present disclosure. In this specification and each figure, elements having the same functions as those described with respect to the previously shown figures may be denoted by the same reference numerals, and redundant descriptions may be omitted.

[0010] In this specification and the claims, when expressing the manner of disposing one structure on another structure, if simply denoted as "on", unless otherwise specified, it shall include both the case of disposing another structure directly on a certain structure in contact therewith and the case of disposing another structure above a certain structure with yet another structure therebetween.

[0011] In this specification and the claims, the expression "a certain structure is exposed from another structure" means a mode in which a part of a certain structure is not covered by another structure, and the portion not covered by this other structure may also be covered by yet another structure.

[0012] (First Embodiment) 1. Basic Structure The wiring board 100 according to one embodiment of the present disclosure will be described with reference to the cross-sectional schematic views of FIGS. 1(A) and 1(B). As shown in FIG. 1(A), the wiring board 100 has a base film 102, a first wiring 104 on the base film 102, and a first protective film 108 located on the first wiring 104 and in contact with the first wiring 104.

[0013] The base film 102 contains an organic compound. The organic compound used preferably has a low dielectric constant and a low dielectric loss tangent. For example, the dielectric constant is preferably 2.0 or more and 4.0 or less, and the dielectric loss tangent is 1×10 -4 or more and 1×10 -2 or less, or 1×10 -3 or more and 1×10 -2 or less of an organic compound can be used as the base film 102. Such an organic compound is typically a polymer having a polyimide as a basic skeleton (hereinafter simply referred to as polyimide), and the polyimide may be chain-like or cross-linked between molecules. Epoxy resin, fine particles of silicon oxide, glass fiber, etc. may be mixed with the base film 102. The base film 102 may have flexibility.

[0014] The first wiring 104 can include metals such as titanium, aluminum, copper, nickel, tungsten, molybdenum, gold, silver, iron, chromium, and alloys thereof, and typically includes copper. A part of the first wiring 104 is disposed within an opening provided in the base film 102, and a part thereof is disposed so as to cover a part of the upper surface of the base film 102. The thickness of the portion of the first wiring 104 above the base film 102 can be 0.5 μm or more and 50 μm or less, 1 μm or more and 20 μm or less, or 1 μm or more and 10 μm or less. Although two first wirings 104 are illustrated in FIGS. 1(A) and 1(B), there is no restriction on the number of the first wirings 104.

[0015] There is no restriction on the planar shape of the first wiring 104, which is determined based on the required function. For example, as shown in FIG. 2(A), the first wiring 104 can be provided so as to mainly extend in one direction. In this case, the width W of the first wiring 104 can be selected in the range of 10 μm or more and 1000 μm or less. Alternatively, as shown in FIG. 2(B), the first wiring 104 may have a mesh shape. In this case, the width W (that is, the distance between adjacent openings provided in the mesh shape) can be selected in the range of 5 μm or more and 500 μm or less. Alternatively, as shown in FIG. 3, the first wiring 104 may have the same or substantially the same shape as the planar shape of the wiring substrate 100. In this case, the width W is selected from a range greater than 1000 μ and not more than 7 cm.

[0016] As shown in FIG. 1(A), the first protective film 108 is in contact with the upper surface and side surfaces of the first wiring 104 and the upper surface of the base film. Further, the first protective film 108 has a three-layer structure. Specifically, the first protective film 108 has a first inorganic compound layer 108a, a second inorganic compound layer 108b located above the first inorganic compound layer 108a and in contact with the first inorganic compound layer 108a, and a third inorganic compound layer 108c located above the second inorganic compound layer 108b and in contact with the second inorganic compound layer 108b.

[0017] The dielectric constant of the second inorganic compound layer 108b is preferably smaller than that of the first inorganic compound layer 108a and the second inorganic compound layer 108b itself. More specifically, the first inorganic compound layer 108a and the third inorganic compound layer 108c contain silicon nitride or silicon carbide. That is, the first inorganic compound layer 108a and the third inorganic compound layer 108c contain silicon and nitrogen, or silicon and carbon as main constituent elements. On the other hand, the second inorganic compound layer 108b contains silicon oxide or silicon oxynitride. That is, the second inorganic compound layer 108b contains silicon and oxygen as constituent elements and may further contain nitrogen. When nitrogen is included, its composition is smaller than that of oxygen. These first inorganic compound layer 108a, second inorganic compound layer 108b, and third inorganic compound layer 108c are formed by a chemical vapor deposition (CVD) method (plasma CVD method) in the presence of plasma.

[0018] The thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c can be arbitrarily determined. For example, the thickness of the first inorganic compound layer 108a is smaller than the thicknesses of the second inorganic compound layer 108b and the third inorganic compound layer 108c, and can be, for example, 0.05 μm or more and 0.2 μm or less, typically 0.1 μm. The thickness of the second inorganic compound layer 108b is larger than the thicknesses of the first inorganic compound layer 108a and the third inorganic compound layer 108c and can be 0.5 μm or more and 10 μm or less, or 1 μm or more and 5 μm or less. The thickness of the third inorganic compound layer 108c can be 0.2 μm or more and 1 μm or less, or 0.3 μm or more and 0.7 μm or less, typically 0.5 μm. That is, when the thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c are T 1 、T 2 、T 3 respectively, the first protective film 108 may be configured such that the following relationship holds. T 1 < T 3 < T 2

[0019] As shown in FIG. 1(B), the thickness of the second inorganic compound layer 108b may be greater than the thickness of the portion of the first wiring 104 above the base film 102. In this case, even if a plurality of first wirings 104 are close to each other, the bottom surface of the third inorganic compound layer 108c is located above the upper surface of the first wiring 104 between adjacent first wirings 104. That is, in the cross section, the third inorganic compound layer 108c is not sandwiched by the adjacent first wirings 104. Therefore, it is possible to prevent a capacitance (parasitic capacitance) from being formed by the third inorganic compound layer 108c having a relatively high dielectric constant and the adjacent first wiring 104. Also, by making the thickness of the first inorganic compound layer 108a smaller than the thickness of the second inorganic compound layer 108b, it is possible to simultaneously prevent a large capacitance from being formed by the first inorganic compound layer 108a and the adjacent first wiring 104. As a result, it is possible to prevent the generation of parasitic capacitance and the accompanying decrease in the signal transmission speed.

[0020] As shown in FIGS. 1(A) and 1(B), the first protective film 108 is provided with an opening reaching the first wiring 104. Thereby, an electrical connection is made between the first wiring 104 and other wirings or a semiconductor chip provided on the wiring substrate 100.

[0021] As an optional configuration, the wiring substrate 100 may have a second protective film 110 on the first protective film 108. The second protective film 110 can also contain a polymer, and examples of the polymer include polyimide, polyamide, polyester, polycarbonate, polysiloxane, and the like. The material contained in the second protective film 110 and the material contained in the base film 102 may be the same. In this case, due to the difference in impurity concentration, the dielectric constant and dielectric tangent of the second protective film 110 may be higher than those of the first protective film 108.

[0022] As an optional configuration, the wiring substrate 100 may have a lower wiring 112 that is located under the first wiring 104 and is electrically connected to the first wiring 104. The lower wiring 112 is covered with the base film 102. Similar to the first wiring 104, the lower wiring 112 also contains the above-described metal or alloy, and typically contains copper. By using the lower wiring 112 and the first wiring 104, an electrical connection between the semiconductor chip and the main substrate can be made.

[0023] Seed layers 106 and 114 may be provided so as to be in contact with the bottom surface and side surface of the first wiring 104 and the bottom surface of the lower wiring 112, respectively. The seed layers 106 and 114 contain metals such as titanium, nickel, chromium, copper, gold, or alloys thereof, and typically contain copper. By forming the seed layers 106 and 114, the first wiring 104 and the lower wiring 112 can be formed by an electrolytic plating method as described later. Although not shown, a barrier layer may be further provided under each of the seed layers 106 and 114. More specifically, a barrier layer may be provided between the undercoat 118 and the seed layer 114, and between the lower wiring 112 and the seed layer 106, which will be described later. The material contained in the barrier layer is selected from metals such as titanium, tantalum, molybdenum, tungsten, and alloys thereof, or nitrides thereof, and is preferably a conductive material having a melting point higher than that of the metal contained in the first wiring 104 and the lower wiring 112. By providing the barrier layer, it is possible to prevent the metal contained in the first wiring 104 and the lower wiring 112 from diffusing into the base film 102.

[0024] As an optional configuration, the wiring substrate 100 may have a substrate 116 under the base film 102. Examples of the material used for the substrate 116 include glass, silicon, gallium arsenide, gallium nitride, ceramics, or a composite material of glass and resin. Examples of the resin include epoxy resin, polyimide, polyamide, and polyester. When the substrate 116 is provided, an undercoat 118 may be provided between the substrate 116 and the base film 102. The undercoat 118 is a film having a function of preventing impurities such as metal ions from diffusing from the substrate 116 to the base film 102, and includes, for example, a silicon-containing inorganic compound such as silicon oxide or silicon nitride. The undercoat 118 may have a single-layer structure or may be composed of a plurality of films containing different materials.

[0025] When using a wiring substrate as an interposer for a semiconductor device that requires a high operating frequency (e.g., from 1 GHz to 100 GHz) such as a high-frequency element, in order to prevent signal transmission loss and delay, the insulating film surrounding the wiring of the wiring substrate is required to have a low dielectric constant and dielectric tangent. Even when an insulating film (e.g., the base film 102 in the wiring substrate 100) is formed using a material that satisfies such performance, after the formation of the wiring substrate, impurities such as water, oxygen, and metal ions from the outside penetrate into the insulating film, and the dielectric constant and dielectric tangent of the insulating film gradually increase. As a result, signal transmission loss and delay occur, which greatly affects the characteristics of the semiconductor chip mounted on the interposer.

[0026] On the other hand, in the wiring board 100 of the present embodiment, the upper surface of the base film 102 covering the first wiring 104 and the lower wiring 112 is covered with a first protective film 108 having a three-layer structure. Here, when the third inorganic compound layer 108c does not exist, since the silicon oxide contained in the second inorganic compound layer 108b has relatively high hydrophilicity, when impurities such as water enter from the outside, the impurities diffuse into the first inorganic compound layer 108a. Although the first inorganic compound layer 108a contains silicon nitride with low hydrophilicity and high blocking property against impurities, as described above, since its thickness is small, part of the impurities permeate through. Therefore, impurities enter the base film 102, increasing the dielectric constant and dielectric tangent of the base film 102.

[0027] However, the first protective film 108 is provided with a third inorganic compound layer 108c having a thickness larger than that of the first inorganic compound layer 108a and containing silicon nitride on the second inorganic compound layer 108b. For this reason, the rate at which impurities enter the first inorganic compound layer 108a and the base film 102 through the second inorganic compound layer 108b can be significantly reduced, and an increase in the dielectric constant and dielectric tangent of the base film 102 can be suppressed. Therefore, it becomes possible to prevent signal transmission loss and delay of the semiconductor chip mounted on the wiring board 100.

[0028] 2. Modification The above-described structural features can also be applied to wiring boards in various forms. Hereinafter, as the wiring board according to the present embodiment, wiring boards 120, 150, 160, and 170 having structures different from that of the wiring board 100 will be described.

[0029] As shown in FIG. 4, the wiring board 120 has a base film 102 and a plurality of laminated connection wiring layers embedded in the base film 102. Here, an example is shown in which four connection wiring layers including a first connection wiring layer 122, a second connection wiring layer 124, a third connection wiring layer 126, and a fourth connection wiring layer 128 are laminated in the base film 102.

[0030] The first connection wiring layer 122 has first connection wirings 130a and 130b embedded in the base film 102. Similarly, the second connection wiring layer 124 has a second connection wiring 132 embedded in the base film 102, and the third connection wiring layer 126 has third connection wirings 134a and 134b embedded in the base film 102. The fourth connection wiring layer 128 is provided with a first wiring 104, similar to the wiring substrate 100, and a first protective film 108 is disposed so as to contact the first wiring 104 and the base film 102. The first wiring 104 is electrically connected to the lower wiring 112 via these connection wirings 130a, 132, and 134a. Similar to the first wiring 104, in each connection wiring layer, the upper surface shape of the connection wirings 130a, 130b, 132, 134a, and 134b may be mainly in a shape extending in a one-dimensional direction, a mesh shape, or substantially the same as the planar shape of the wiring substrate 100, as shown in FIGS. 2(A), 2(B), and 3. As an optional configuration, seed layers 136a, 136b, 138, 140a, and 140b may be provided on the bottom surface and side surfaces of the respective connection wirings 130a, 130b, 132, 134a, and 134b. Also, a barrier layer may be formed under each of the seed layers 136a, 136b, 138, 140a, and 140b. Since the other configurations are the same as those of the wiring substrate 100, the description thereof is omitted.

[0031] Similar to the wiring substrate 100, the first protective film 108 of the wiring substrate 120 also has a first inorganic compound layer 108a, a second inorganic compound layer 108b, and a third inorganic compound layer 108c. Therefore, the intrusion of impurities into the base film 102 is effectively suppressed, and an increase in the dielectric constant and dielectric tangent of the organic compound contained in the base film 102 can be suppressed.

[0032] The wiring board 150 shown in FIG. 5 is different from the wiring board 120 in that a third protective film 152 having the same or a similar structure as the first protective film 108 is formed on the connection wiring embedded in the base film 102. In the example shown here, the third protective film 152 is provided so as to cover the second connection wiring 132 of the second connection wiring layer 124. The third protective film 152 has a fourth inorganic compound layer 152a, a fifth inorganic compound layer 152b located on the fourth inorganic compound layer 152a and in contact with the fourth inorganic compound layer 152a, and a sixth inorganic compound layer 152c located on the fifth inorganic compound layer 152b and in contact with the fifth inorganic compound layer 152b. The fourth inorganic compound layer 152a, the fifth inorganic compound layer 152b, and the sixth inorganic compound layer 152c respectively correspond to the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c of the first protective film 108 and can have the same structure respectively.

[0033] By adopting such a structure, even if the number of connection wiring layers increases and the thickness of the base film 102 increases, it is possible to effectively suppress the intrusion of impurities into the base film 102, and it becomes possible to prevent the characteristics of the semiconductor chip mounted on the wiring board 150 from degrading.

[0034] Note that the third protective film 152 covering the connection wiring does not necessarily have to include the sixth inorganic compound layer 152c. This is because the first protective film 108 having a three-layer structure is formed on the first wiring 104. In this case, the fifth inorganic compound layer 152b is in contact with the base film 102.

[0035] The wiring board 160 shown in FIG. 6 differs in structure from the wiring board 150 in that the first protective film 108 also covers the side surface of the base film 102. In this structure, as shown in FIG. 6, the fourth inorganic compound layer 152a and the first inorganic compound layer 108a may be in contact with each other. The first protective film 108 may cover the side surface of the substrate 116. Although not shown, the side surfaces of the base film 102 among the connection wiring layers 122, 124, 126, and 128 do not have to be in the same plane. For example, the side surface of the base film 102 of one connection wiring layer may overlap the upper surface of the base film 102 of the connection wiring layer below it. By adopting such a structure, the intrusion of impurities into the base film 102 can be more effectively prevented, so that an increase in the dielectric constant and dielectric tangent of the organic compound contained in the base film 102 can be suppressed, and a deterioration in the characteristics of the mounted semiconductor chip can be prevented.

[0036] The wiring board 170 shown in FIG. 7 differs in structure from the wiring board 150 in that the lower wiring 112 is formed as a through-wiring that penetrates the substrate 116. That is, the base film 102 and the plurality of connection wiring layers 122, 124, 126, and 128 are formed on one surface (the first surface) of the substrate 116, and the lower wiring 112 covers a part of this first surface, a part of the second surface facing the first surface, and the side wall of the through-hole 172 provided in the substrate 116. Similarly, the seed layer 114 covers a part of the first surface, a part of the second surface, and the side wall of the through-hole 172. By using the lower wiring 112 and the first wiring 104, an electrical connection between the semiconductor chip and the main substrate can be made.

[0037] As described above, the wiring boards 150, 160, and 170 shown in FIGS. 5 to 7 have a third protective film 152 that contacts one or a plurality of connection wirings (the second connection wiring 132a in the example shown here) selected from a plurality of connection wirings located inside the base film 102. That is, a metal such as copper included in the connection wiring contacts the fourth inorganic compound layer 152a. In this case, when impurities enter the base film 102, the surface of the connection wiring is oxidized, and the adhesion between the connection wiring and the fourth inorganic compound layer 152a decreases. In addition, since the coefficients of thermal expansion of the materials included in these connection wirings and the fourth inorganic compound layer 152a are greatly different, peeling occurs due to the film stress generated between them.

[0038] However, as described above, by applying this embodiment, it is possible to effectively prevent the intrusion of impurities into the base film 102. For this reason, oxidation of the connection wiring is prevented, and peeling between the connection wiring and the third protective film 152 inside the base film 102 can be effectively prevented. Therefore, not only can the signal transmission loss and delay of the semiconductor chip mounted on the wiring board be suppressed, but also the reliability of the semiconductor device including the semiconductor chip and the wiring board can be improved.

[0039] (Second Embodiment) In this embodiment, the manufacturing method of the wiring board 170 shown in FIG. 7 will be described using a cross-sectional schematic diagram. The description of configurations similar to or the same as those described in the first embodiment may be omitted.

[0040] First, a through-hole 172 is formed in the substrate 116 (FIG. 8(A)). When a glass substrate is used as the substrate 116, the through-hole 172 may be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sandblasting or ultrasonic drilling. The number and size of the through-holes 172 can be arbitrarily determined according to the design of the wiring board 170.

[0041] Thereafter, the seed layer 114 is formed so as to cover the side walls of the through holes 172 and both surfaces (the first surface and the second surface) of the substrate 116 (FIG. 8(B)). The seed layer 114 can be formed by a sputtering method, a CVD method, electroless plating, or a vapor deposition method. In particular, by applying the sputtering method, the seed layer 114 can be efficiently formed. Although not shown, before forming the seed layer 114, an insulating film containing an organic compound such as polyimide or polyamide, or an inorganic compound such as silicon oxide or silicon nitride may be formed in one or more layers on the side walls of the through holes 172 and both surfaces of the substrate 116.

[0042] Next, a resist mask 176 for protecting the regions where the lower wirings 112 are not formed is formed on the first surface and the second surface of the substrate 116 (FIG. 8(B)). The resist mask 176 may be formed by applying and curing a liquid resist. However, since the substrate 116 has the through holes 172, it can be efficiently formed by attaching a film-shaped resist to the first surface and the second surface and then performing exposure and development. Thereafter, power is supplied to the seed layer 114 to perform electroplating, and a metal film is formed on the seed layer 114 not covered by the resist mask 176, and the lower wiring 112 is formed (FIG. 8(C)).

[0043] Thereafter, the resist mask 176 is removed, and the seed layer 114 exposed from the lower wiring 112 is removed by etching (FIG. 8(D)). As the etchant, an etchant containing an acid such as sulfuric acid can be used.

[0044] Subsequently, a part of the base film 102 is formed. Specifically, a polymer such as polyimide described in the first embodiment or a solution or suspension of its precursor is applied onto the substrate 116, and then exposure, development, and baking using a photomask are performed to form a base film 102 having an opening 178 that exposes the lower wiring 112. Alternatively, the base film 102 may be formed by attaching a film of the above polymer and performing exposure, development, and baking using a photomask. The thickness of the base film 102 formed at this stage is appropriately adjusted within the range of 0.5 μm to 5 μm.

[0045] Next, the seed layer 136 is formed by applying a sputtering method, a CVD method, or the like (FIG. 9(A)). The thickness of the seed layer 136 is appropriately selected within the range of 5 μm or more and 20 μm. The seed layer 136 is formed on the base film 102 so as to partially cover the opening 178. Before forming the seed layer 136, a barrier layer (not shown) may be formed by using a sputtering method or the like so as to cover the surface of the opening 178 and the base film 102.

[0046] Next, in the same manner as the formation of the lower wiring 112, a resist mask is formed, the first connection wiring 130 is formed by an electrolytic plating method, and then the seed layer 136 not covered by the first connection wiring 130 is removed by etching (FIG. 9(B)). When a barrier layer is formed, the barrier layer is removed simultaneously with the seed layer 136. By the steps up to this point, the first connection wiring layer 122 is formed. The same process is repeated to form the second connection wiring layer 124 (FIG. 10(A)).

[0047] Next, the third protective film 152 is formed. Specifically, the plasma CVD method is applied to sequentially form a fourth inorganic compound layer 152a containing silicon nitride and a fifth inorganic compound layer 152b containing silicon oxide (FIG. 10(B)). Thereafter, the base film 102 having an opening overlapping with the second connection wiring 132a is formed on the third protective film 152 (FIG. 11(A)). The thickness of the base film 102 formed at this time (the portion of the base film 102 above the third protective film 152) is appropriately selected from the range of 1 μm to 10 μm in consideration of imparting characteristic impedance suitable for the semiconductor chip mounted on the wiring substrate 170 to the first wiring 104 and the connection wiring.

[0048] Next, in the opening provided in the topmost base film 102, the third protective film 152 is removed by plasma etching to expose the second connection wiring 132a. Thereafter, the third connection wirings 134a and 134b and the seed layers 140a and 140b are formed using the same method as for the formation of the seed layer 136 and the first connection wiring 130a (FIG. 11(B)). By repeating the same method, the first wirings 104a and 104b of the fourth connection wiring layer 128 and the seed layers 106a and 106b are formed (FIG. 12).

[0049] Subsequently, the first protective film 108 is formed (FIG. 13). The first protective film 108 is formed by sequentially forming a first inorganic compound layer 108a, a second inorganic compound layer 108b, and a third inorganic compound layer 108c using the plasma CVD method. Thereafter, in the same manner as for the formation of the base film 102 of the first connection wiring layer 122, after forming a second protective film 110 having an opening overlapping with the first wiring 104a (FIG. 13), plasma etching is performed on the first protective film 108 exposed at this opening to expose the first wiring 104a. For the plasma etching, fluorine-containing alkanes or alkenes such as CF 4 or CHF 4 may be used.

[0050] Through the above steps, the wiring substrate 170 shown in FIG. 7 can be formed.

[0051] (Third Embodiment) In this embodiment, a semiconductor device using the wiring substrates 100, 120, 150, 160, and 170 described in the first embodiment will be described. Here, for convenience, a semiconductor device using the wiring substrate 170 will be described as a representative example.

[0052] The semiconductor device 180 shown in FIG. 14 has a main substrate 182 and a plurality of wiring substrates 170 (wiring substrates 170-1, 170-2, 170-3) stacked thereon. The number of wiring substrates 170 is not limited and is determined according to the performance required for the semiconductor device 180. Various semiconductor chips (memory devices, central processing units) and semiconductor elements (such as microelectromechanical systems (MEMS)) (not shown) are connected to the main substrate 182. As described in the first embodiment, the wiring substrate 170 has lower wirings 112 that function as through-wirings, and these contribute to the vertical electrical connection in the semiconductor device 180. The lower wiring 112 of the lowermost wiring substrate 170-1 is electrically connected to a terminal 186 provided on the main substrate 182 via a bump 184-1. Also, the stacked wiring substrates 170-1, 170-2, 170-3 are electrically connected to each other by bumps 184-2, 184-3. The bumps 184 include metals such as indium, copper, and gold, or alloys such as solder.

[0053] As in the semiconductor device 190 shown in FIG. 15, the stacked wiring substrates 170 may have different sizes and shapes from each other, and the number of wiring substrates 170 stacked on the main substrate 182 may also be different. In the example shown in FIG. 15, two wiring substrates 170-4, 170-5 are stacked in some regions, and three wiring substrates 170-1, 170-2, 170-3 are stacked in some regions.

[0054] The semiconductor device 200 shown in FIG. 16 has a structure in which a plurality of semiconductor chips 202-1 and 202-2 are stacked on a main substrate 182 via a wiring substrate 170. Terminals 186 are formed on the semiconductor chips 172-1 and 172-2, respectively, and these are electrically connected to the lower wiring 112 of the wiring substrate 170 and the first wiring 104 via bumps 184. Thereby, the semiconductor chips 202-1 and 202-2 are electrically connected to each other. Also, the semiconductor chip 202-2 and the main substrate 182 may be electrically connected by wire wiring 206. In FIGS. 14 to 16, the lower wiring 112 that functions as a through wiring is shown to be directly connected to the bump 184, but other wirings such as lead wirings may be provided between the bump 184 and the lower wiring 112.

Example

[0055] In this example, the results of a reliability test on the wiring substrate of the first embodiment will be described. The wiring substrate used was the wiring substrate 170 (see FIG. 7), and the thicknesses of the fourth inorganic compound layer 152a and the fifth inorganic compound layer 152b were 0.1 μm and 2.0 μm, respectively. The thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c were 0.1 μm, 0.5 μm, and 0.4 μm, respectively.

[0056] The fabricated wiring substrate was left standing for 96 hours under the conditions of a temperature of 130° C. and a humidity of 85%, and then the first wiring 104 and the connection wirings 130a, 130b, 132, 134a, 134b were observed using an optical microscope. As a result, peeling between the second connection wiring 132 and the fourth inorganic compound layer 152a was not observed, regardless of the wiring shape and the width of the wiring.

[0057] On the other hand, as a comparative example, when a wiring board having the same structure as the wiring board 170 but without the first protective film 108 was used, it was confirmed that the surfaces of all the wirings had turned red regardless of their widths and shapes. This suggests that the wirings are oxidized by impurities that have entered from the outside. Also, between the second connection wiring 132 and the fourth inorganic compound layer 152a, peeling did not occur in regions where the width of the wiring was small (for example, wirings with a width of 10 μm or less, or mesh-shaped wirings with a width of 5 μm), but peeling was confirmed to have occurred in other regions.

[0058] As shown in this embodiment, it was confirmed that by applying a protective film having a three-layer structure, it is possible to provide a highly reliable wiring board.

[0059] As described above, the embodiments described as embodiments of the present disclosure can be implemented in appropriate combinations as long as they do not contradict each other. Also, based on each embodiment, those in which those skilled in the art have appropriately added, deleted, or changed the design of components are included in the scope of the present disclosure as long as they have the gist of the present disclosure.

[0060] Also, other operational effects different from those brought about by the above-described embodiments, which are obvious from the description in this specification or can be easily predicted by those skilled in the art, are naturally understood to be brought about by the present disclosure.

Description of Reference Numerals

[0061] 100: Wiring substrate, 102: Base film, 104: First wiring, 104a: First wiring, 104b: First wiring, 106: Seed layer, 106a: Seed layer, 106b: Seed layer, 108: First protective film, 108a: First inorganic compound layer, 108b: Second inorganic compound layer, 108c: Third inorganic compound layer, 110: Second protective film, 112: Lower wiring, 114: Seed layer, 116: Substrate, 118: Undercoat, 120: Wiring substrate, 122: First connection wiring layer, 124: Second connection wiring layer, 126: Third connection wiring layer, 128: Fourth connection wiring layer, 130: First connection wiring, 130a: First connection wiring, 130b: First connection wiring, 132: Second connection wiring, 132a: Second connection wiring, 134: Third connection wiring, 134a: Third connection wiring, 134b: Third connection wiring, 136: Seed layer, 136a: Seed layer, 136b: Seed layer, 138: Seed layer, 140a: Seed layer, 140b: Seed layer, 150: Wiring substrate, 152: Third protective film, 152a: Fourth inorganic compound layer, 152b: Fifth inorganic compound layer, 152c: Sixth inorganic compound layer, 160: Wiring substrate, 170: Wiring substrate, 172: Through hole, 176: Resist mask, 178: Opening, 180: Semiconductor device, 182: Main substrate, 184: Bump, 186: Terminal, 188: Bump, 190: Semiconductor device, 200: Semiconductor device, 202: Semiconductor chip, 206: Wire wiring

Claims

1. A substrate, a plurality of wiring layers laminated on the substrate, and a first protective film on the plurality of wiring layers, wherein each of the plurality of wiring layers has an organic film having a through hole, and a connection wiring disposed in the through hole, and the first protective film has a first inorganic compound layer, a second inorganic compound layer on the first inorganic compound layer, and a third inorganic compound layer on the second inorganic compound layer, wherein the first protective film covers a side surface of the organic film of the plurality of wiring layers and has an opening exposing the connection wiring of the uppermost wiring layer, a wiring substrate.

2. The wiring substrate according to claim 1, wherein a thickness of the third inorganic compound layer is greater than a thickness of the first inorganic compound layer and smaller than a thickness of the second inorganic compound layer.

3. The wiring substrate according to claim 1, wherein the connection wirings are electrically connected between the adjacent plurality of wiring layers.

4. The dielectric tangent of the organic film is 1×10 －４ Above 1 x 10 －２ The wiring board according to claim 1 , wherein:

5. The wiring substrate according to claim 1, wherein the organic film contains polyimide.

6. The wiring substrate according to claim 1, further comprising a lower wiring electrically connected to the connection wiring of the lowermost wiring layer between the substrate and the plurality of wiring layers.

7. The wiring substrate according to claim 6, wherein the lower wiring penetrates the substrate.

8. The first inorganic compound layer and the third inorganic compound layer contain nitrogen and silicon, and the second inorganic compound layer contains oxygen and silicon, the wiring substrate according to claim 1.

9. The wiring substrate according to claim 1, further comprising a second protective film between the adjacent wiring layers.

10. The wiring substrate according to claim 9, wherein the second protective film includes a laminated fourth inorganic compound layer and a fifth inorganic compound layer.

11. Stacking a plurality of wiring layers each having the organic film and the connection wiring by alternately performing a step of forming an organic film having a through hole on a substrate and a step of forming a connection wiring in the through hole, forming a first protective film covering a side surface of the organic film of the plurality of wiring layers on the plurality of wiring layers, and forming a first protective film having an opening exposing the connection wiring of the uppermost wiring layer, wherein the first protective film has a first inorganic compound layer, a second inorganic compound layer on the first inorganic compound layer, and a third inorganic compound layer on the second inorganic compound layer, a method for manufacturing a wiring substrate.

12. The manufacturing method according to claim 11, wherein the thickness of the third inorganic compound layer is greater than the thickness of the first inorganic compound layer and smaller than the thickness of the second inorganic compound layer.

13. The manufacturing method according to claim 11, wherein the lamination of the plurality of wiring layers is performed such that the connection wiring is electrically connected between the adjacent plurality of wiring layers.

14. The dielectric loss tangent of the organic film is 1×10 －４ or more and 1×10 －２ or less. The manufacturing method according to claim 11.

15. The manufacturing method according to claim 11, wherein the organic film contains polyimide.

16. Before laminating the plurality of wiring layers, further including forming a lower wiring on the substrate, The manufacturing method according to claim 11, wherein the lower wiring is electrically connected to the connection wiring of the lowermost wiring layer.

17. Before forming the lower wiring, further including forming a through hole in the substrate, The manufacturing method according to claim 16, wherein the lower wiring is formed in the through hole of the substrate.

18. The first inorganic compound layer and the third inorganic compound layer contain nitrogen and silicon, The manufacturing method according to claim 11, wherein the second inorganic compound layer contains oxygen and silicon.

19. The manufacturing method according to claim 11, further including forming a second protective film between the adjacent wiring layers.

20. The manufacturing method according to claim 19, wherein the second protective film contains a laminated fourth inorganic compound layer and a fifth inorganic compound layer.

21. The manufacturing method according to claim 11, wherein the organic film is formed using a polymer film.

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