Semiconductor device

Abstract

This semiconductor device comprises a board and a plurality of semiconductor elements. Each semiconductor element has first and second terminals and an internal wiring that connects the first and second terminals to each other. The first terminal of each semiconductor element is connected to the second terminal of respective one of the other semiconductor elements via a board wiring provided in the board, thereby providing a wiring path that establishes a sequential connection between the plurality of semiconductor elements. One of the plurality of semiconductor elements has a determination circuit that is located on the path of the internal wiring. The determination circuit transmits a determination signal to the first terminal and determines an abnormality of the wiring path on the basis of the determination signal received by the second terminal via the wiring path. In this way, poor connection of the plurality of semiconductor elements can be detected with the increase of cost suppressed.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A method is known for detecting delamination or cracks between insulating layers of a semiconductor chip by measuring the conductivity of a wiring monitor such as a via chain provided on the outer peripheral portion of the semiconductor chip. A multi-chip package in which a plurality of semiconductor chips are mounted on an interposer is known. In an interposer, a method is known for detecting a connection failure between the interposer and micro-bumps by measuring the conductivity of a wiring chain that connects between wiring layers.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, it is conceivable to provide a determination circuit for determining a connection failure with an interposer for each of a plurality of semiconductor chips mounted on a multi-chip package, and to individually determine a connection failure between each semiconductor chip and the interposer. However, in this case, the chip size of each semiconductor chip increases, and the cost of the multi-chip package increases.

[0005] The present invention has been made in view of the above points, and an object of the present invention is to detect a connection failure of a plurality of semiconductor elements while suppressing an increase in cost in a semiconductor device in which a plurality of semiconductor elements are mounted on a substrate.

Means for Solving the Problems

[0006] In one aspect of the present invention, a semiconductor device includes a substrate, a plurality of semiconductor elements each having a first terminal and a second terminal connected to the substrate, and an internal wiring connecting the first terminal and the second terminal to each other, a plurality of substrate wirings provided on the substrate, and a determination circuit provided on the internal wiring of one of the semiconductor elements, one of the substrate wirings being connected to the first terminal of the semiconductor element on which the determination circuit is provided and the second terminal of another semiconductor element, another of the substrate wirings being connected to the second terminal of the semiconductor element on which the determination circuit is provided, and a wiring path is provided for electrically connecting the first terminal of the semiconductor element on which the determination circuit is provided and the second terminal of the semiconductor element on which the determination circuit is provided via the one substrate wiring, the second terminal of the another semiconductor element, the first terminal of the another semiconductor element, and the another substrate wiring, The determination circuit transmits a determination signal the one semiconductor element's to the first terminal, and determines an abnormality of the wiring path based on the determination signal received at the second terminal via the wiring path. the one semiconductor element's

Effects of the Invention

[0007] According to the disclosed technology, in a semiconductor device in which a plurality of semiconductor elements are mounted on a substrate, it is possible to detect a connection failure of a plurality of semiconductor elements while suppressing an increase in cost.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] (First Embodiment) FIG. 1 shows an example of a semiconductor device of the first embodiment. The semiconductor device 100 shown in FIG. 1 includes a plurality of semiconductor chips SEM1, SEM2, SEM3, SEM4, SEM5, an interposer INTP, and a package substrate P - BRD. The semiconductor device 100 has a form of a so-called 2.5D package in which a plurality of semiconductor chips SEM1 - SEM5 are interconnected via the interposer INTP. The semiconductor chips SEM1 - SEM5 are an example of semiconductor elements. The interposer INTP is an example of a substrate.

[0011] The cross-sectional structure of FIG. 1 shows a cross-section along the A - A' line in FIG. 1. Hereinafter, the semiconductor chips SEM1 - SEM5 are also simply referred to as chips SEM1 - SEM5. Also, when the chips SEM1 - SEM5 are described without distinction, they are also referred to as chip SEM.

[0012] For example, each chip SEM can be any one of a SoC (System on a Chip), an ASIC (Application Specific Integrated Circuit), a CPU (Central Processing Unit), or memory, etc. Each chip SEM is connected to the interposer INTP via micro-bumps μBP. An underfill UF may be provided to cover the micro-bumps μBP between each chip SEM and the interposer INTP.

[0013] For example, the micro-bumps μBP are formed by mutually joining the micro-bumps provided on the surface on the interposer INTP side in each chip SEM and the micro-bumps provided on the surface on each chip SEM side in the interposer INTP. Note that the bumps connecting each chip SEM and the interposer INTP are not limited to the micro-bumps μBP.

[0014] The interposer INTP is connected to the package substrate P-BRD via bumps BP. An underfill UF may be provided to cover the bumps BP between the interposer INTP and the package substrate P-BRD. Then, the semiconductor device 100 is connected to a system substrate (not shown) etc. via solder balls SB provided on the package substrate P-BRD. The dashed frame R1 is used in the description of FIG. 2.

[0015] Although not particularly limited, the semiconductor device 100 may have a function as an image processing device that processes images captured by a camera. For example, the semiconductor device 100 that functions as an image processing device may be mounted on a moving body such as an automobile. Also, the semiconductor device 100 may be mounted on a system substrate of a mobile terminal such as a smartphone.

[0016] Figure 2 shows an overview of a detection mechanism for detecting a connection failure between the chips in Figure 1. Figure 2 shows a portion of the broken line frame R1 that straddles the chips SEM1 and SEM2 in the plan view of Figure 1. Note that Figure 2 shows a plan view from the chip SEM1 and SEM2 sides in Figure 1 toward the interposer INTP side, but some elements such as microbumps, pads, and wirings are made transparent.

[0017] Chip SEM1 has a determination circuit JDG for determining a disconnection failure. The determination circuit JDG transmits a determination signal for determining a disconnection failure to chip SEM2 and receives the determination signal transmitted via chip SEM2. The arrows shown beside each wiring in Figure 2 indicate the transmission direction of the determination signal.

[0018] Although illustration is omitted, the determination circuit JDG has, for example, a buffer circuit that outputs a high-level determination signal to wiring W11 and a pull-down resistor connected to wiring W14. The determination circuit JDG also has a detection circuit that detects the logic level (i.e., voltage level) of the determination signal returning from chip SEM2 to wiring W14. For example, the resistance value of the pull-down resistor is set so that when there is no abnormality in the wiring path through which the determination signal is transmitted, the divided voltage due to the voltage division between the resistance of the wiring path and the pull-down resistor is detected as a high level by the detection circuit.

[0019] Then, for example, when the detection circuit detects a high-level determination signal during the operation of the semiconductor device 100 in Figure 1 as a system, the determination circuit JDG determines that the wiring path through which the determination signal is transmitted is normal. On the other hand, when the detection circuit detects a low-level determination signal during the operation of the semiconductor device 100 as a system, the determination circuit JDG determines that an abnormality such as a disconnection has occurred in the wiring path through which the determination signal is transmitted. Note that the determination circuit JDG can detect an abnormality in the wiring path even when the wiring path is not completely disconnected, due to a decrease in the divided voltage caused by an increase in the resistance value of the wiring path.

[0020] When the determination circuit JDG determines a disconnection, for example, it notifies the system controller mounted on the system board together with the package board P-BRD in FIG. 1 of the occurrence of an abnormality. Note that the determination of the disconnection by the determination circuit JDG may be performed when the semiconductor device 100 has stopped the system operation.

[0021] In FIG. 2, the rectangular regions R11, R12, R21, and R22 indicated by broken lines are locations where stress tends to concentrate. When a stress equal to or greater than a predetermined value is applied, peeling of the wiring layer or cracks are more likely to occur at these locations than at other locations. For example, the corners of the chip SEM2 are locations where stress tends to concentrate. Also, in the chip SEM1, the portion facing the corner of the chip SEM2 via the interposer INTP in plan view is also a location where stress tends to concentrate.

[0022] An output terminal (not shown) that outputs a determination signal to the wiring W11 in the determination circuit JDG is connected to a wiring W12 provided in the region R11 of the chip SEM1, a via (not shown), and a pad P11 via the wiring W11. The pad P11 is connected to the transmission microbumps μBP1s. The microbumps μBP1s are connected to a wiring WI1 of the interposer INTP via pads, vias, and wirings (not shown) provided in the region R12 of the interposer INTP.

[0023] The wiring WI1 of the interposer INTP is connected to vias, wirings, and pads (not shown) provided in the region R22 of the interposer INTP that faces the corner of the chip SEM2 in plan view. Then, a pad (not shown) of the interposer INTP is connected to the reception microbumps μBP2r. The microbumps μBP2r are connected to a wiring W22 via a pad P21, vias, and a wiring W21 provided in the region R21 of the chip SEM2. The microbumps μBP1s and μBP2r provided adjacent to the regions R11 and R21 function as bumps for detecting peeling.

[0024] The wiring W22 is connected to the transmission micro bumps μBP2s via vias (not shown), wiring W23, and pad P22 within the chip SEM2. The micro bumps μBP2s are connected to the wiring WI2 of the interposer INTP via pads, vias, and wiring (not shown) within the interposer INTP. The wiring WI2 is connected to the reception micro bumps μBP1r at a position facing the end of the chip SEM1 in a plan view via vias, wiring, and pads (not shown) within the interposer INTP. The micro bumps μBP1r are connected to the reception terminal of the determination circuit JDG via pad P12, vias, and wiring W13, W14 within the chip SEM1.

[0025] The micro bumps μBP1s, μBP2s that transmit the determination signal are examples of the first terminals. The micro bumps μBP1r, μBP2r that receive the determination signal are examples of the second terminals. The wirings W11, W12, W13, W14 are examples of internal wirings provided in the chip SEM1. The wiring W12 is an example of the first wiring, the wiring W13 is an example of the second wiring, and the wirings W11, W14 are examples of the third wiring. Hereinafter, when the micro bumps μBP1s, μBP1r, μBP2s, μBP2r are described without distinction, they are also referred to as micro bumps μBP.

[0026] The wirings W21, W22, W23 are examples of internal wirings provided in the chip SEM2. The wiring W23 is an example of the first wiring, the wiring W21 is an example of the second wiring, and the wiring W22 is an example of the third wiring. The wirings WI1, WI2 are examples of substrate wirings provided in the interposer INTP and are examples of the sixth wiring.

[0027] Also, the wirings W11, W12, WI1, W21, W22, W23, WI2, W13, W14 that are electrically connected in sequence are an example of a wiring path that sequentially connects the chips SEM1 and SEM2. The determination circuit JDG is provided on the paths of the wirings W11, W14 of the chip SEM1. As shown in FIG. 8 described later, three or more chips SEM may be sequentially connected by the wiring path.

[0028] FIG. 3 shows a cross section taken along the line X-X' of FIG. 2. Chip SEM1 has a wiring region WLYR1 and a substrate SUB1. For example, the substrate SUB1 is a semiconductor substrate such as silicon on which transistors and the like are formed, and has transistors and the like included in the determination circuit JDG of FIG. 2.

[0029] The wiring region WLYR1 includes a plurality of wiring layers and insulating layers provided between adjacent wiring layers. Vias V1 for connecting wirings provided in adjacent wiring layers can be formed in the insulating layers. In the wiring region WLYR1, in a region R11 where stress is likely to be applied, vias V1 and wiring W12 are repeatedly arranged from a pad P11 provided on the chip SEM1 to a wiring W11 on the substrate SUB1 side. The wiring layers in which the wirings W11 and W12 are arranged are an example of element wiring layers.

[0030] For example, the wirings W11 and W12 for transmitting a determination signal are provided using all the wiring layers of the wiring region WLYR1. Also, the vias V1 and the wiring W12 have a meandering shape in a cross-sectional view. And the wiring W11 is electrically connected to the μBP1s via the meandering vias V1 and the wiring W12. Note that the meandering vias V1 and the wiring W12 may be provided only in a predetermined number of insulating layers and wiring layers on the microbump μBP1s side. For example, the predetermined number may be one-half or one-third of the total number of wiring layers provided in the wiring region WLYR1.

[0031] Chip SEM2 has a wiring region WLYR2 and a substrate SUB2. For example, the substrate SUB2 is a semiconductor substrate such as silicon. The wiring region WLYR2 includes a plurality of wiring layers and insulating layers provided between adjacent wiring layers. Vias V2 for connecting wirings provided in adjacent wiring layers can be formed in the insulating layers. In the wiring region WLYR2, in a region R21 where stress is likely to be applied, vias V2 and wiring W21 are repeatedly arranged from a pad P21 provided on the chip SEM2 to a wiring W22 on the substrate SUB2 side. The wiring layers in which the wirings W21 and W22 are arranged are an example of element wiring layers.

[0032] For example, the wirings W22 and W21 for transmitting the determination signal are provided using all the wiring layers in the wiring region WLYR2. Also, the via V2 and the wiring W21 have a meandering shape in a cross-sectional view. And the wiring W22 is electrically connected to μBP2r via the meandering via V2 and the wiring W21. Note that the meandering via V2 and the wiring W21 may be provided only in a predetermined number of wiring layers on the micro bump μBP2r side.

[0033] In FIG. 3, the wiring W11 is provided in the wiring layer closest to the substrate SUB1, and the wiring W22 is provided in the wiring layer closest to the substrate SUB2. However, the wiring W11 may be provided in a wiring layer other than the wiring layer closest to the substrate SUB1 and connected to the substrate SUB1 via other wiring layers on the substrate SUB1 side. The wiring W22 may be provided in a wiring layer other than the wiring layer closest to the substrate SUB2 and connected to the substrate SUB2 via other wiring layers on the substrate SUB2 side. Also, the wiring W11 may be embedded in the surface on the wiring region WLYR1 side of the substrate SUB1, and the wiring W22 may be embedded in the surface on the wiring region WLYR2 side of the substrate SUB2.

[0034] In the interposer INTP, in each of the regions R12 and R22, vias VI and wirings WI are repeatedly arranged from the pad PI provided in the interposer INTP to the wiring WI1. For example, the vias VI and the wirings WI and WI1 are provided using all the wiring layers of the interposer INTP.

[0035] Note that the wiring WI may be provided only in a predetermined number of wiring layers on the micro bump μBP1s and μBP2r sides. The wiring layers in which the wirings WI and WI1 are arranged are an example of substrate wiring layers. The wiring WI arranged on the micro bump μBP1s side is an example of a fourth wiring. The wiring WI arranged on the micro bump μBP2r side is an example of a fifth wiring. The wiring WI1 is an example of a sixth wiring.

[0036] Although illustration is omitted, a passivation film may be provided on the surface of the micro bump μBP1s side of the chip SEM1, except for the exposed portion of the pad P11. Similarly, a passivation film may be provided on the surface of the micro bump μBP2r side of the chip SEM2, except for the exposed portion of the pad P21. A passivation film may be provided on the surface of the micro bumps μBP1s and μBP2r sides of the interposer INTP, except for the exposed portion of the pad PI.

[0037] In this embodiment, in the region R11 that is easily affected by stress, by arranging the via V1 and the wirings W11 and W12 in a meandering shape in a cross-sectional view using a plurality of wiring layers, it is possible to easily determine the disconnection of the wiring path that transmits the determination signal not used for the operation of the system. Similarly, in the region R21 that is easily affected by stress, by arranging the via V2 and the wirings W22 and W21 in a meandering shape in a cross-sectional view using a plurality of wiring layers, it is possible to easily determine the disconnection of the wiring path that transmits the determination signal. This is because a meandering wiring is more likely to have a disconnection compared to a wiring that does not have a meandering shape used for the operation of the system.

[0038] Examples of disconnection include peeling of the wirings W11 and W12 from the via V1, peeling of the wirings W22 and W21 from the via V2, cracks in the wirings W11, W12, W22, and W21, etc. Also, examples of disconnection include cracks in the insulating layer (interlayer insulating film) of the wiring regions WLYR1 and WLYR2.

[0039] Also, in the interposer INTP, in the regions R12 and R22 that are easily affected by stress, by arranging the via VI and the wiring WI using a plurality of wiring layers, it is possible to easily determine the disconnection of the wiring path that transmits the determination signal not used for the operation of the system. Note that, for example, the wiring structure of the transmission path of the determination signal other than the regions R11 and R21 where stress is likely to concentrate may be the same as the wiring structure of the transmission path of the signal used for the operation of the system.

[0040] As described above, the determination circuit JDG can detect disconnection of wirings or the like for transmitting a determination signal before wirings or the like used for the operation of the system are disconnected in the chips SEM1, SEM2 or the interposer INTP. That is, the semiconductor device 100 can detect signs of disconnection of wirings or the like used for the operation of the system in the chips SEM1, SEM2 or the interposer INTP. As a result, the semiconductor device 100 can safely stop the operation of the system based on the disconnection determination by the determination circuit JDG. In other words, the determination circuit JDG can suppress a decrease in the reliability of the semiconductor device 100.

[0041] FIG. 4 shows an example of the wiring structure in the region R21 of FIG. 3. As shown in FIG. 4, the wirings W22 and W21 have an L shape that substantially overlaps each other in plan view (L-shaped wirings). In the L-shaped bent portions of the wirings W22 and W21, they are located substantially at the center of the microbump μBP2r in plan view. The vias V2 are arranged with their positions shifted alternately in plan view. Further, the vias V2 are provided at positions that substantially overlap each other in plan view at each of one end and the other end of the wiring W21. By alternately shifting the positions of the vias V2 in plan view, it is possible to more easily detect the occurrence of film peeling or the like due to stress compared to the case where the positions in plan view are the same.

[0042] Each wiring W21 is connected to a via V2 located on the side of the wiring W22 at one end of the L shape and to a via V2 located on the side of the pad P21 at the other end of the L shape. Note that the vias V2 may be provided at positions shifted from each other in plan view at each of one end and the other end of the wiring W21.

[0043] Note that the wiring structure of region R11 in Fig. 3 is the same as that in Fig. 4. That is, the wirings W11 and W12 in Fig. 3 have an L shape that almost overlaps each other in a plan view, and the bent portion of the L shape is located almost at the center of the micro bumps μBP1s in a plan view. The via V1 is provided at positions that almost overlap each other in a plan view at each of one end and the other end of the wiring W12. Each wiring W12 is connected to the via V1 located on the side of the wiring W11 at one end of the L shape and to the via V1 located on the side of the pad P11 at the other end of the L shape. That is, the vias V1 connected to each wiring W12 are arranged with their positions shifted alternately in a plan view.

[0044] With the wiring structure shown in Fig. 4, it is possible to make the connection portions between each of the wirings W22 and W21 and the via V2 susceptible to the influence of the stress applied to the chip SEM2. For this reason, it becomes possible to detect, by the determination circuit JDG, the peeling of the wirings W22 and W21 provided at positions overlapping the micro bumps μBP2r in a plan view as disconnection. Furthermore, it becomes possible to detect, by the determination circuit JDG, the separation between the micro bumps μBP2r and the pad P21 as disconnection.

[0045] Also, by forming each of the wirings W22 and W21 into an L shape with the bent portion facing the micro bumps μBP2r, it becomes possible to sensitively detect disconnection regardless of the direction of peeling of the film. Note that in the wiring structure of region R11 shown in Fig. 3, the same effect as that of the wiring structure of region R21 can be obtained.

[0046] Fig. 5 shows another example of the wiring structure of region R21 in Fig. 3. Also in Fig. 5, the wirings W22 and W21 have an L shape. However, in Fig. 5, the transmission path of the determination signal by the wirings W22 and W21 and the via V2 has a spiral shape. A part of the L-shaped wirings W22 and W21 overlaps the micro bumps μBP2r in a plan view.

[0047] In FIG. 5, via V2 may be provided at the same position in plan view at each of one end and the other end of L-shaped wiring W21, or may be provided at positions shifted from each other. Further, the L-shaped wiring W21 may be arranged such that at least a part of the wiring W21 overlaps the micro bump μBP2r in plan view.

[0048] Also in the wiring structure shown in FIG. 5, the same effects as those of the wiring structure shown in FIG. 4 can be obtained. Further, the wiring structure in region R11 of FIG. 3 may be the same as the wiring structure of FIG. 5. Note that the wiring structure in region R21 of FIG. 3 is not limited to the wiring structures shown in FIGS. 4 or 5.

[0049] FIG. 6 shows a cross section along the Y-Y' line of FIG. 2. Since the wiring structures in regions R21 and R22 have been described with reference to FIGS. 3 to 5, the description thereof is omitted. Wirings W22 and W23 that face the micro bump μBP2s in plan view in the wiring region WLYR2 have, for example, a rectangular shape similar to the wiring structure in region R22 of the interposer INTP.

[0050] As described above, in this embodiment, the common determination circuit JDG is provided only in the chip SEM1 among the plurality of chips SEM1 and SEM2. Also, wiring paths for returning the determination signal output from the determination circuit JDG to the determination circuit JDG via the chip SEM2 are provided in the chips SEM1 and SEM2 and the interposer INTP, respectively. Thereby, defects such as disconnection occurring in the plurality of chips SEM1 and SEM2 and the interposer INTP can be determined by one determination circuit JDG. That is, in the semiconductor device 100 in which a plurality of semiconductor chips SEM are mounted on the interposer INTP, it is possible to detect connection failures of the plurality of semiconductor chips SEM while suppressing an increase in cost.

[0051] The determination signal is transmitted to the wirings provided in the regions R11, R12, R21, R22 that are susceptible to the influence of stress in each chip SEM1, SEM2 and the interposer INTP, and the vias connecting the wirings. Therefore, it is possible to make it easier to detect defects such as film peeling occurring in the wiring layer than defects such as film peeling occurring in other wiring layer regions.

[0052] For example, the wiring for transmitting the determination signal is wiring not used for the operation of the system. Therefore, the determination circuit JDG can detect disconnection of the wiring for transmitting the determination signal before the wiring etc. used for the operation of the system in the chips SEM1, SEM2 or the interposer INTP is disconnected. That is, the semiconductor device 100 can detect signs of disconnection of the wiring etc. used for the operation of the system in the chips SEM1, SEM2 or the interposer INTP. As a result, the semiconductor device 100 can safely stop the operation of the system based on the disconnection determination by the determination circuit JDG. Thereby, a decrease in the reliability of the semiconductor device 100 can be suppressed.

[0053] The wiring structure in the region R11 (or R21) where it is easy to detect the occurrence of film peeling etc. is provided facing the microbump μBP. Therefore, it is possible to make it easier to detect the occurrence of film peeling etc. of the wiring close to the microbump μBP where stress is likely to be applied in the chip SEM1 (or SEM2).

[0054] In the region R11 (or R21), by alternately shifting the positions of the vias V1 (or V2) in plan view, it is possible to make it easier to detect the occurrence of film peeling etc. due to stress compared to the case where the positions in plan view are made the same.

[0055] The wiring structure formed by vias V1 (or V2) and wirings W11, W12 (or W22, W21) using a plurality of wiring layers has a meandering shape in cross-sectional view. For example, the meandering shape in cross-sectional view is the repeating shape shown in FIG. 4 or the spiral shape shown in FIG. 5. Thereby, it becomes possible to easily detect the occurrence of film peeling or the like with respect to the stress applied to the chip SEM1 (or SEM2). At this time, for example, by providing the wiring structure shown in FIG. 4 or FIG. 5 at a position facing the micro bump μBP2r provided at the corner of the chip SEM2, it becomes possible to more easily detect the occurrence of film peeling or the like of the wiring.

[0056] By forming the wirings provided in the regions R11 and R21 into an L shape, it becomes possible to sensitively detect disconnection regardless of the direction of film peeling. By arranging the L-shaped wirings W21 (or W12) at positions facing each other in plan view, the layout design of the chip SEM2 (or SEM1) can be facilitated as compared with the case where they are arranged at positions not facing each other in plan view.

[0057] By forming the wiring structure in the interposer INTP that interconnects the chips SEM1 and SEM2 into a wiring structure formed by vias VI and wirings WI, WI2 using a plurality of wiring layers, it becomes possible to easily detect film peeling or the like of the wiring of the interposer INTP.

[0058] (Second Embodiment) FIG. 7 shows an example of a semiconductor device according to the second embodiment. For elements similar to those in the above-described embodiment, the same reference numerals are given and detailed description is omitted. In FIG. 7, as in FIG. 2, some of the elements such as micro bumps, pads, and wirings are made transparent.

[0059] The semiconductor chips SEM1 and SEM2 shown in FIG. 7 are interconnected via an interposer INTP in the same manner as in FIG. 1 and are mounted on a semiconductor device 100A having a 2.5D package form. The mounting positions of the semiconductor chips SEM1 and SEM2 on the interposer INTP are the same as the mounting positions of the semiconductor chips SEM1 and SEM2 of the semiconductor device 100 on the interposer INTP in FIG. 1.

[0060] In this embodiment, for example, the determination circuit JDG can detect disconnection or the like in regions R21, R22, R23, and R24 adjacent to the micro bumps μBP2r and μBP2s2 provided at two of the four corners of the rectangular chip SEM2. The wiring structure of the transmission path of the determination signal that returns from the determination circuit JDG to the determination circuit JDG via the micro bumps μBP1s, μBP2r, μBP2s, and μBP1r is the same as the wiring structure shown in FIGS. 2 to 6.

[0061] The micro bump μBP2s2 is provided at a position on the chip SEM2 opposite to the chip SEM1 in a plan view. And the semiconductor device 100A has a transmission path of the determination signal that returns from the determination circuit JDG to the determination circuit JDG via the micro bumps μBP1s2, μBP2r2, μBP2s2, and μBP1r2. Thereby, the determination circuit JDG can detect disconnection or the like in regions R23 and R24 adjacent to the micro bump μBP2s2 provided at the corner of the chip SEM2 far from the chip SEM1.

[0062] In addition to the configuration of FIG. 2, the determination circuit JDG includes a buffer circuit that outputs a determination signal to the wiring W15, a pull-down circuit that pulls down the wiring W18, and a detection circuit that detects the logic level of the determination signal returning from the chip SEM2 to the wiring W18. The determination signals output to the wirings W11 and W15 may be shared.

[0063] An output terminal (not shown) that outputs a determination signal in the determination circuit JDG is connected to a wiring W16 provided in a region R13 of the chip SEM1 via the wiring W15 in the chip SEM1, a via (not shown), and a pad P13. The pad P13 is connected to the transmission micro bump μBP1s2. The micro bump μBP1s2 is connected to a wiring WI3 in the interposer INTP via pads, vias, and wirings (not shown) provided in a region R14 of the interposer INTP.

[0064] The wiring WI3 is connected to the receiving micro bump μBP2r2 near the corner on the opposite side of the chip SEM1 in the chip SEM2 via vias, wirings, and pads (not shown) in the interposer INTP. The micro bump μBP2r2 is connected to the wiring W24 via the pad P23, vias (not shown), and wiring in the chip SEM2.

[0065] The wiring W24 is connected to the transmitting micro bump μBP2s2 provided at the corner on the opposite side of the chip SEM1 via vias, wirings, and the pad P24 (not shown) provided in the region R23 of the chip SEM2. The micro bump μBP2s2 is connected to the wiring WI4 in the interposer INTP via pads, vias, and wirings (not shown) provided in the region R24 of the interposer INTP. Similar to the micro bumps μBP1s and μBP2r, the micro bumps μBP1s2 and μBP2s2 function as bumps for detecting peeling.

[0066] The wiring WI4 is connected to the receiving micro bump μBP1r2 via vias, wirings, and pads (not shown) in the interposer INTP at a position facing the end of the chip SEM1 on the chip SEM2 side in a plan view. The micro bump μBP1r2 is connected to the receiving terminal of the determination circuit JDG via the pad P14, vias, and wirings W17 and W18 in the chip SEM1. Note that the determination circuit JDG may include a sub-determination circuit connected to the wirings W11 and W14 and a sub-determination circuit connected to the wirings W15 and W18.

[0067] In FIG. 7, an example is shown in which micro bumps μBP2r and μBP2s through which determination signals are respectively transmitted and micro bumps μBP2r2 and μBP2s2 are provided at two corner portions corresponding to one side of chip SEM2. However, the two transmission paths shown in FIG. 7 and the wiring structures corresponding to the two transmission paths may be provided at the other two corner portions respectively. In this case, determination circuit JDG transmits and receives determination signals to and from the four transmission paths. Thereby, determination circuit JDG can detect disconnection due to film peeling or cracks or the like at all corner portions of chip SEM2 where stress is likely to concentrate.

[0068] As described above, also in this embodiment, similar to the above-described embodiment, defects such as disconnection of a plurality of chips SEM1 and SEM2 can be determined by one determination circuit JDG. Further, in this embodiment, determination circuit JDG can detect disconnection due to film peeling or cracks not only at the corner portions adjacent to chip SEM1 but also at the corner portions located on the side opposite to chip SEM1 in chip SEM2. That is, disconnection of a plurality of transmission paths can be detected by one determination circuit JDG.

[0069] (Third Embodiment) FIG. 8 shows an example of a semiconductor device according to the third embodiment. For elements similar to those in the above-described embodiment, the same reference numerals are given and detailed description is omitted. In FIG. 8, as in FIG. 2, some of the elements such as micro bumps, pads, and wirings are made transmissive.

[0070] Semiconductor chips SEM1, SEM2, and SEM4 shown in FIG. 8 are interconnected via an interposer INTP in the same manner as in FIG. 1 and are mounted on a semiconductor device 100B having a 2.5D package form. The mounting positions of semiconductor chips SEM1, SEM2, and SEM4 on interposer INTP are the same as the mounting positions of semiconductor chips SEM1, SEM2, and SEM4 of semiconductor device 100 on interposer INTP in FIG. 1.

[0071] In this embodiment, for example, the determination signal output from the determination circuit JDG returns to the determination circuit JDG via one transmission path provided in the chips SEM4 and SEM2. The determination circuit JDG can detect disconnection or the like in regions R41 and R42 adjacent to the micro bump μBP4r at the corner of the chip SEM4 with respect to FIG. 2. The wiring structure of the transmission path of the determination signal returning from the determination circuit JDG to the determination circuit JDG via the micro bumps μBP1s, μBP4r, μBP4s, μBP2r, μBP2s, and μBP1r is the same as the wiring structure shown in FIGS. 2 to 6.

[0072] The wiring structure of the chip SEM1 is the same as the wiring structure of FIG. 2 except that regions R13 and R14 where stress is likely to concentrate are set adjacent to the micro bump μBP1r. The wiring structure of each of the regions R13 and R14 is the same as the wiring structure of the regions R11 and R12 shown in FIG. 3.

[0073] The wiring WI1 of the interposer INTP that supplies the determination signal from the chip SEM1 to the chip SEM4 is connected to vias, wirings, and pads (not shown) provided in the region R42 of the interposer INTP that faces the corner of the chip SEM4 in a plan view. Then, a pad (not shown) of the interposer INTP is connected to the receiving micro bump μBP4r. The micro bump μBP4r is connected to the wiring W42 via a pad P41, vias (not shown), and a wiring provided in the region R41 of the chip SEM4. The micro bump μBP4r functions as a bump for detecting peeling.

[0074] The wiring W42 is connected to the transmitting micro bump μBP4s via vias, wirings, and a pad P42 (not shown) inside the chip SEM4. The micro bump μBP4s is connected to the wiring WI3 of the interposer INTP via pads, vias, and wirings (not shown) inside the interposer INTP.

[0075] The wiring WI3 is connected to vias, wirings, and pads (not shown) in the interposer INTP in a region R22 that faces the end of the chip SEM2 in a plan view. The pad is connected to the receiving micro bump μBP2r. The micro bump μBP2r is connected to the wiring W21 via a pad P21 provided in the region R21 of the chip SEM2, vias, and wirings (not shown). The micro bump μBP2r functions as a bump for detecting peeling.

[0076] The wiring W21 is connected to the transmitting micro bump μBP2s via vias, wirings, and a pad P22 (not shown) in the chip SEM2. The micro bump μBP2s is connected to the wiring WI2 of the interposer INTP via pads, vias, and wirings (not shown) in the interposer INTP. The wiring structure from the wiring WI2 to the wiring W14 is the same as that in FIG. 2. Note that the wiring WI3 connecting the chips SEM4 and SEM2 to each other may overlap with the wirings W42 and W21 in a plan view, but in FIG. 8, the positions in the plan view are shifted for clarity.

[0077] In the semiconductor device 100B shown in FIG. 8, disconnection due to film peeling or cracks at the corners of the two chips SEM4 and SEM2 can be detected by one determination circuit JDG mounted on the chip SEM1. Note that the transmission path of the determination signal and the wiring structure shown in FIG. 8 may be applied between the chips SEM3 and SEM5 and the chip SEM1 shown in FIG. 1. Also, the transmission path of the determination signal may be returned to the chip SEM1 via three or more chips SEM from the chip SEM1. Further, as shown in FIG. 7, the transmission path of the determination signal may include micro bumps μBP provided at a plurality of corners of each chip SEM. At this time, the transmission path may be a single continuous wiring path or may have a plurality of single continuous paths.

[0078] As described above, the same effects as those of the above-described embodiments can be obtained even in this embodiment. For example, disconnection due to film peeling or cracking of the plurality of chips SEM1, SEM2, SEM4 and the interposer can be detected by one determination circuit JDG mounted on the chip SEM1.

[0079] Note that, in the above-described embodiment, the microbump μBP included in the transmission path of the determination signal is not limited to the microbump μBP located at the corner of the semiconductor chip SEM. For example, when the position where film peeling or cracking is likely to occur is found by a reliability test or the like, the microbump μBP provided near this position may be included in the transmission path of the determination signal.

[0080] Further, the semiconductor devices 100, 100A, 100B are not limited to semiconductor devices that operate as a system, and may be semiconductor devices used only for reliability evaluation.

[0081] As described above, the present invention has been described based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiments. In this regard, it can be changed within the scope not departing from the gist of the present invention, and can be appropriately determined according to the application form.

Explanation of reference numerals

[0082] 100, 100A, 100B Semiconductor device BP Bump INTP Interposer JDG Determination circuit P11, P12, P13, P14 Pad P21, P22, P23, P24 Pad P41, P42 Pad P-BRD Package substrate PI Pad R11, R12, R13, R14 Region R21, R22, R23, R24 Region R41, R42 Region SB Solder ball SEM1, SEM2, SEM3, SEM4, SEM5 semiconductor chips SUB1, SUB2 substrates UF underfill V1, V2, VI vias W11, W12, W13, W14 wirings W15, W16, W17, W18 wirings W21, W22, W23, W24 wirings WI, WI1, WI2 wirings WLYR1, WLYR2 wiring regions μBP1r, μBP1s microbumps μBP1r2, μBP1s2 microbumps μBP2r, μBP2s microbumps μBP2r2, μBP2s2 microbumps μBP4r, μBP4s microbumps

Claims

1. A substrate, a plurality of semiconductor elements each having a first terminal and a second terminal connected to the substrate, and internal wiring connecting the first terminal and the second terminal to each other, a plurality of substrate wirings provided on the substrate, a determination circuit provided on the internal wiring of one of the semiconductor elements, and having, one of the substrate wirings is connected to the first terminal of the semiconductor element on which the determination circuit is provided and the second terminal of another semiconductor element, another one of the substrate wirings is connected to the second terminal of the semiconductor element on which the determination circuit is provided, a wiring path is provided for electrically connecting the first terminal of the semiconductor element on which the determination circuit is provided and the second terminal of the semiconductor element on which the determination circuit is provided through the one substrate wiring, the second terminal of the another semiconductor element, the first terminal of the another semiconductor element, and the another substrate wiring, the determination circuit transmits a determination signal to the first terminal of the one semiconductor element, and determines an abnormality of the wiring path based on the determination signal received at the second terminal of the one semiconductor element via the wiring path semiconductor device.

2. each of the plurality of semiconductor elements has a plurality of element wiring layers, the internal wiring includes, a first wiring connected to each other through vias provided between the element wiring layers in two or more of the plurality of element wiring layers, a second wiring connected to each other through vias provided between the element wiring layers in two or more of the plurality of element wiring layers, a third wiring provided in an element wiring layer adjacent to the substrate side opposite to the element wiring layer in which the first wiring and the second wiring are provided, and connecting the first wiring to the second wiring, and having, the first wiring is electrically connected to the first terminal, the second wiring is electrically connected to the second terminal the semiconductor device according to claim 1.

3. A substrate, a plurality of semiconductor elements each having a first terminal and a second terminal connected to the substrate, and internal wiring connecting the first terminal and the second terminal to each other, and having, a wiring path is provided for sequentially connecting between the plurality of semiconductor elements by connecting the first terminal of each of the plurality of semiconductor elements to any one of the second terminals of other semiconductor elements through a substrate wiring provided on the substrate, Any one of the plurality of semiconductor elements has a determination circuit provided on the path of the internal wiring. The determination circuit transmits a determination signal to the first terminal, and determines an abnormality of the wiring path based on the determination signal received at the second terminal via the wiring path. Each of the plurality of semiconductor elements has a plurality of element wiring layers. The internal wiring In two or more of the plurality of element wiring layers, a first wiring connected to each other via vias provided between the element wiring layers, In two or more of the plurality of element wiring layers, a second wiring connected to each other via vias provided between the element wiring layers, A third wiring provided in an element wiring layer adjacent to the substrate side opposite to the element wiring layer in which the first wiring and the second wiring are provided, and connecting the first wiring to the second wiring. The first wiring is electrically connected to the first terminal. The second wiring is electrically connected to the second terminal. Semiconductor device.

4. The first wiring is provided at a position facing the first terminal in a plan view. The second wiring is provided at a position facing the second terminal in a plan view. The semiconductor device according to claim 2 or claim 3.

5. In at least any one of the plurality of semiconductor elements, at least one of the plurality of vias connecting the plurality of first wirings to each other and the plurality of vias connecting the plurality of second wirings to each other are arranged with their positions shifted alternately in a plan view. The semiconductor device according to any one of claims 2 to 4.

6. At least one of the plurality of first wirings and the plurality of second wirings connected to vias whose positions are alternately shifted in a plan view is an L-shaped wiring having an L shape in a plan view. On one end side of the L-shaped wiring, a via connected to the L-shaped wiring on the substrate side is arranged. On the other end side of the L-shaped wiring, a via connected to the L-shaped wiring on the side opposite to the substrate is arranged. The semiconductor device according to claim 5.

7. The plurality of L-shaped wirings provided in the plurality of element wiring layers are arranged at positions facing each other in a plan view. The semiconductor device according to claim 6.

8. A spiral wiring structure is provided by the L-shaped wirings provided in the plurality of element wiring layers and the vias connecting the L-shaped wirings. The semiconductor device according to claim 6.

9. The substrate has a plurality of substrate wiring layers. The substrate wiring In two or more of the plurality of substrate wiring layers, a fourth wiring connected to each other via vias between the substrate wiring layers; In two or more of the plurality of substrate wiring layers, a fifth wiring connected to each other via vias between the substrate wiring layers; A sixth wiring provided in a substrate wiring layer adjacent to the substrate wiring layer on the opposite side of the plurality of semiconductor elements with respect to the substrate wiring layer in which the fourth wiring and the fifth wiring are provided, and connecting the fourth wiring to the fifth wiring; The fourth wiring is electrically connected to the first terminal; The fifth wiring is electrically connected to the second terminal The semiconductor device according to any one of claims 1 to 7.

10. In each of the plurality of semiconductor elements, at least one of the first terminal and the second terminal is provided at a corner portion of the semiconductor element in plan view The semiconductor device according to any one of claims 1 to 9.

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