Module configuration for an integrated group III nitride device

Abstract

The electronic module for the half-bridge circuit includes a base substrate having an insulating layer between first and second metal layers. A trench formed through the first metal layer isolates the first, second, and third portions from one another. The high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on a conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to the source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the conductive substrate, and the conductive substrate is connected to the second portion.

Description

Technical Field

[0001] The present disclosed technology relates to a semiconductor electronic module designed to achieve improved performance and reliability.

Background Art

[0002] [Background] Currently, typical power semiconductors (including devices such as transistors, diodes, power MOSFETs, insulated gate bipolar transistors (IGBTs), etc.) are manufactured from silicon (Si) semiconductor materials. More recently, wide bandgap materials (SiC, III-N, III-O, diamond) have been considered for power devices due to their excellent properties. Group III nitride or III-N semiconductor devices (such as gallium nitride (GaN) devices) are emerging as attractive candidates for carrying large currents, supporting high voltages, and providing ultra-low on-resistance with fast switching times.

[0003] FIG. 1A shows a half-bridge circuit schematic 100 including a high-side switching transistor 102 and a low-side switching transistor 103. The half-bridge circuit has a high potential node 111 and a low potential or ground node 113. The output node 112 of the half-bridge (between the source of the high-side transistor 102 and the drain of the low-side transistor 103) is connected to a load motor (inductive component 104). To ensure proper operation of the circuit of FIG. 1A, the DC high potential node 111 must be maintained as an AC ground. That is, node 111 can be capacitively coupled to the DC ground 113 by connecting one terminal of capacitor 106 to the high potential node 111 and the other terminal of the capacitor to the ground 113. Thus, when either transistor 102 or 103 is switched on or off, capacitor 106 can be appropriately charged or discharged to provide the current necessary to maintain a substantially constant voltage on the high potential side and the low potential side of the circuit.

[0004] The circuit schematic of a three-phase full-bridge circuit 120 configured to drive a three-phase motor is shown in FIG. 1B. The three half-bridges 122, 124, and 126 within the circuit 120 each include two transistors (141 to 146) (such as the half-bridge in FIG. 1A). The three half-bridges each have output nodes 137, 138, and 139. Each transistor within this circuit can block a voltage in a first direction and conduct current in the first direction (or optionally bidirectionally).

[0005] One type of transistor that exhibits promising advantages when used in the circuits of FIGS. 1A and 1B is the III-N high electron mobility transistor (HEMT). This can be used as transistor 102 and / or transistor 103 of the half-bridge in FIG. 1A, or any transistor within the bridge circuit of FIG. 1B, etc. The most common III-N HEMTs and related transistors are normally on (i.e., have a negative threshold voltage), which means conducting current at a gate voltage of zero. These devices with a negative threshold voltage are known as depletion mode (D-mode) devices. In power electronics, it is preferable to have a normally off device (i.e., a device with a positive threshold voltage) that is in an off state when zero volts is applied to the gate relative to the source in order to prevent accidental turn-on of the device (which can lead to damage to the device or other circuit components). Normally off devices are generally referred to as enhancement mode (E-mode) devices.

[0006] So far, it has been found that reliable manufacturing and operation of high-voltage III-N E-mode transistors are very difficult. One alternative to a single high-voltage E-mode transistor is to combine a high-voltage D-mode III-N transistor and a low-voltage silicon E-mode FET in a cascode configuration. As shown in Figure 2, the cascode configuration 200 includes a high-voltage D-mode transistor 223 placed in a package 205 and a low-voltage E-mode transistor 222. The source electrode 234 of the transistor 223 is connected to the drain electrode 213 of the transistor 222. The gate electrode 235 of the transistor 223 and the source electrode 211 of the transistor 222 are connected to each other and connected to the source lead 207 of the package 205. The gate electrode 212 of the transistor 222 is connected to the gate lead 208 of the package 205. The drain electrode 236 of the transistor 223 is connected to the drain lead 209 of the package 205. The E-mode FET transistor 222 includes a built-in body diode 237 formed between the source 211 and the drain 213. Each device configured in the cascode configuration 200 of Figure 2 can operate in the same way as a single high-voltage E-mode transistor, and the leads 207, 208, and 209 function as the source, gate, and drain of the device, respectively, and can often achieve the same or similar output characteristics as a single high-voltage E-mode transistor.

[0007] A general method of operation of the circuits of FIGS. 1A and 1B involves hard switching of switches (i.e., transistors or cascode switches). A hard-switching circuit configuration is one in which, as soon as each switch turns on, a high current (e.g., greater than 10 A) flows through the switch, and a high voltage is generated across them as soon as they turn off. Switches that are switched under these conditions are said to be “hard switched.” Alternative circuit configurations utilize additional passive and / or active components (alternatively signal timing techniques) to allow switches to be “soft switched.” A soft-switching circuit configuration is one in which a switch turns on during zero-current (or near-zero-current) conditions and turns off during zero-voltage (or near-zero-voltage) conditions. Methods and configurations of soft switching have been developed to address the high levels of electromagnetic interference (EMI) and associated ringing observed in hard-switched circuits (particularly high-current and / or high-voltage applications). Soft switching can often avoid these problems, but the circuits required for soft switching typically include many additional components, resulting in increased overall cost and complexity. Soft switching also typically requires that the circuit be configured to switch only at specific times when zero-current or zero-voltage conditions are met, and in many cases, this limits the applicable control signals and degrades circuit performance. Therefore, alternative configurations and methods are desirable for hard-switched power switch circuits to maintain a sufficiently low level of EMI while reducing circuit inductance and improving switching speed stability.

[0008] [Summary] In this specification, a module configuration for an integrated III-N device is described. In this module configuration, a low-voltage enhancement-mode device and a high-voltage depletion-mode III-N device are integrated into a single electronic component module to form half-bridge and full-bridge power switching circuits. The term "device" is generally used for any transistor or switch or diode when there is no need to distinguish them from each other.

[0009] In a first aspect, an electronic module is described. The electronic module includes a base substrate having an insulating layer between a first metal layer and a second metal layer, the first metal layer including a first portion, a second portion, and a third portion, and a groove formed through the first metal layer electrically insulating the first portion, the second portion, and the third portion of the first metal layer from each other. The electronic module further includes a high-side switch including an enhancement-mode transistor and a depletion-mode transistor, the depletion-mode transistor having a III-N material structure on a conductive substrate. The electronic module further includes a low-side switch. The drain electrode of the depletion-mode transistor is electrically connected to the first portion of the first metal layer, the source electrode of the enhancement-mode transistor is electrically connected to the second portion of the first metal layer, the drain electrode of the enhancement-mode transistor is electrically connected to the source electrode of the depletion-mode transistor, the gate electrode of the depletion-mode transistor is electrically connected to the conductive substrate, and the conductive substrate is electrically connected to the second portion of the first metal layer.

[0010] In a second aspect, a half-bridge circuit is described. The half-bridge circuit includes a high-side switch and a low-side switch, which are each placed in a single electronic package, and the package includes a high-voltage terminal, an output terminal, and a ground terminal. The high-side switch includes a first enhancement-mode transistor and a first depletion-mode transistor arranged in a cascode configuration. The low-side switch includes a second enhancement-mode transistor and a second depletion-mode transistor arranged in a cascode configuration. The drain electrode of the first III-N transistor is electrically connected to the high-voltage terminal, the conductive substrate of the first depletion-mode III-N transistor is electrically connected to the output terminal, the drain electrode of the second III-N transistor is electrically connected to the output terminal, and the conductive substrate of the second depletion-mode III-N transistor is electrically connected to the ground terminal.

[0011] In a third aspect, a half-bridge circuit is described. The half-bridge circuit includes a high-side switch and a low-side switch, which are each placed in a single electronic package. The high-side switch is connected to a high-voltage node, the low-side switch is connected to a ground node, and an inductor is connected to an output terminal of the package configured between the high-side switch and the low-side switch. The low-side switch includes a low-voltage enhancement-mode transistor and a high-voltage III-N depletion-mode transistor arranged in a cascode configuration. The half-bridge circuit is configured such that in a first operating mode, while the high-side switch is biased on and the low-side switch is biased off, current passes through the high-side switch in a first direction and flows through the inductor. In a second operating mode, while the high-side switch is biased off and the low-side switch is biased off, current passes through the low-side switch in a second direction and flows through the inductor. In a third operating mode, while the high-side switch is biased off and the low-side switch is biased on, current passes through the low-side switch in a second direction and flows through the inductor. During the second operating mode, the low-side switch is configured to conduct a reverse DC current greater than 50 A, and during the third operating mode, the increase in the on-resistance of the III-N depletion-mode transistor with respect to the first mode is less than 5%.

[0012] Each of the electronic modules and / or transistors described herein can include one or more of the following features. The high-side switch and the low-side switch can form a half-bridge circuit. The depletion-mode transistor can be configured to block at least 600V when the high-side switch is biased off and conduct a current greater than 30A while the high-side switch is biased on. The electronic module can include a capacitor, with a first terminal of the capacitor electrically connected to a first portion of a first metal layer and a second terminal of the capacitor electrically connected to a third portion of the first metal layer. The capacitor can be formed orthogonally above a trench. The capacitor can be a hybrid capacitor comprising resistive and capacitive components connected in series. The resistive component can be greater than 0.1 ohm, and the capacitive component can be greater than 0.1 nF. The gate electrode, source electrode, and drain electrode can be on the opposite side of the III-N material structure from the conductive substrate. The III-N material structure can include a via hole formed through the substrate, and the gate electrode of the depletion-mode transistor is electrically connected to the substrate through this via hole. The electronic module can include a package, and the substrate, high-side switch, and low-side switch are placed within the package. The electronic module can include a gate driver placed within the package, with a first terminal of the gate driver connected to the gate electrode of the high-side switch and a second terminal of the gate driver connected to the gate electrode of the low-side switch. The gate driver can be integrated with each E-mode transistor of the low-side switch and the low-side switch. A second high-side switch can be connected in parallel with the high-side switch, and a second low-side switch can be connected in parallel with the low-side switch. A second portion of the first metal layer is connected to the output node of the electronic module. The module is configured such that, during operation, a first portion of the first metal layer is connected to a DC voltage source and a third portion of the first metal layer is connected to DC ground. A ferrite bead having a first terminal and a second terminal, with the first terminal of the ferrite bead connected to the second portion of the first metal layer and the second terminal connected to the output terminal.Each substrate of the first and / or second depletion mode III-N transistor is a silicon-doped p-type substrate with a hole concentration of 1×10. 19 holes / cm 3 greater. During the second operating mode, an inverse DC current flows through the parasitic body diode of the enhancement mode transistor and through the device channel of the III-N depletion mode transistor. During the third operating mode, an inverse DC current flows through the channel of the enhancement mode transistor and through the device channel of the III-N depletion mode transistor.

[0013] As used herein, a "hybrid enhancement mode electronic device or component" (or simply "hybrid device or component") is an electronic device or component formed from a depletion mode transistor and an enhancement mode transistor, where the depletion mode transistor is capable of a higher operating voltage and / or breakdown voltage compared to the enhancement mode transistor, and the hybrid device or component is configured to operate in a manner similar to a single enhancement mode transistor having a breakdown voltage and / or operating voltage that is approximately as high as the breakdown voltage and / or operating voltage of the depletion mode transistor. That is, a hybrid enhancement mode device or component includes at least three nodes having the following characteristics. When a first node (source node) and a second node (gate node) are maintained at the same voltage, the hybrid enhancement mode device or component can block a positive high voltage (i.e., a voltage greater than the maximum voltage that an enhancement mode transistor can block) applied to a third node (drain node) with respect to the source node. When the gate node is maintained at a sufficient positive voltage (i.e., a voltage greater than the threshold voltage of the enhancement mode transistor) with respect to the source node, current passes from the source node to the drain node, or when a sufficient positive voltage with respect to the source node is applied to the drain node, current passes from the drain node to the source node. If the enhancement mode transistor is a low voltage device and the depletion mode transistor is a high voltage device, the hybrid component can operate in a manner similar to a single high voltage enhancement mode transistor. The depletion mode transistor may have a breakdown voltage and / or maximum operating voltage that is at least 2 times, at least 3 times, at least 5 times, at least 10 times, or at least 20 times the breakdown voltage and / or maximum operating voltage of the enhancement mode transistor.

[0014] As used herein, the terms group-III nitride or III-N material, layer, device, etc. refer to a material or device composed of a semiconductor composite material conforming to the stoichiometric formula B w Al x In y Ga z N, where w + x + y + z is approximately 1, and 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1. The III-N material, layer, or device can be formed or prepared by directly growing it on a suitable substrate (e.g., by metalorganic chemical vapor deposition), or by growing it on a suitable substrate, separating it from the original substrate, and bonding it to another substrate.

[0015] As used herein, when two or more contacts or other elements (such as conductive channels or components) are "electrically connected," it means that they are connected by a material with sufficient conductivity to ensure that, under any bias condition, the potentials of the respective contacts or elements are always the same (e.g., substantially the same).

[0016] As used herein, "blocking a voltage" refers to the ability of a transistor, device, or component to prevent a substantial current (e.g., a current greater than 0.001 times the operating current during normal conduction) from flowing through the transistor, device, or component when a voltage is applied thereto. In other words, while the transistor, device, or component is blocking the voltage applied thereto, the total current passing through the transistor, device, or component does not exceed 0.001 times the operating current during normal conduction. Devices having an off-state current greater than this value exhibit high losses and low efficiency and are typically not suitable for many applications (especially power-switching applications).

[0017] As used herein, a "high voltage device" (e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four quadrant switch (FQS)) is an electronic device optimized for high voltage applications. That is, when the device is off, it can block a high voltage (e.g., about 300V or more, about 600V or more, or about 1200V or more), and when the device is on, it has a sufficiently low on-resistance (R ON ) (e.g., the conduction loss experienced when a substantial current passes through the device is sufficiently low). A high voltage device can block at least a voltage equal to the high voltage supply or the maximum voltage in the circuit in which it is used. A high voltage device may be able to block 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, a high voltage device can block all voltages from 0V to V max where V max is the maximum voltage that can be supplied by the circuit or power supply, and V max may be, for example, 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. For a bidirectional switch or four quadrant switch, when the switch is off, the voltage blocked may be of any polarity less than a certain maximum value (±300V or ±600V, ±1200V, etc., of ±V max ), and when the switch is on, the current may be in either direction.

[0018] As used herein, an "III-N device" is a device having a conductive channel formed within an III-N material. The III-N device can be designed to operate as a transistor or a switch (where the state of the device is controlled by a gate terminal) or a two-terminal device (which blocks current flow in one direction and conducts in the other direction without a gate terminal). The III-N device may be a high-voltage device suitable for high-voltage applications. In such a high-voltage device, when the device is biased off (e.g., when the voltage of the gate with respect to the source is less than the device threshold voltage), the device can support at least all source-drain voltages (e.g., 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher) below the high voltage of the application for which the device is used. When the high-voltage device is biased on (e.g., when the voltage of the gate with respect to the source or the associated power terminal is greater than the device threshold voltage), the device can conduct a substantial current at a low on-voltage (i.e., a low voltage between the source and drain or between both power terminals). The maximum allowable voltage is the maximum on-state voltage that can be sustained in the application for which the device is used.

[0019] As used herein, the terms "over", "under", "between", and "on" refer to the relative position of one layer with respect to another layer. Thus, for example, a layer disposed over or under another layer may be in direct contact with that other layer or one or more layers may be interposed therebetween. Further, a layer disposed between two layers may be in direct contact with those two layers or one or more layers may be interposed therebetween. In contrast, a first layer "on" a second layer is in contact with the second layer. Further, the relative position of a layer with respect to each other layer is provided assuming that operations are performed on the substrate without considering the absolute orientation of the substrate.

[0020] In a typical power switching application where a high voltage switching transistor is used, for most of the time, the transistor is in one of two states. In the first state (commonly referred to as the "on state"), the voltage of the gate electrode with respect to the source electrode is higher than the transistor threshold voltage, and a substantial current flows through the transistor. In this state, the voltage difference between the source and drain is typically low, usually below a few volts (e.g., about 0.1 to 5 volts). In the second state (commonly referred to as the "off state"), the voltage of the gate electrode with respect to the source electrode is lower than the transistor threshold voltage, and no substantial current (except for the off-state leakage current) flows through the transistor. In this second state, the voltage difference between the source and drain can arbitrarily vary from about 0V to the value of the circuit high voltage supply (in some cases 100V, 300V, 600V, 1200V, 1700V or higher, but can be lower than the breakdown voltage of the transistor). In some applications, the inductive element in the circuit may make the voltage between the source and drain even higher than the circuit high voltage supply. In addition, there is a short time immediately after the gate is switched on or off when the transistor is in a transition mode between the above two states. When the transistor is in the off state, it is said to be "blocking the voltage". In this specification, "blocking the voltage" refers to the ability of the transistor, device or component to prevent a substantial current (e.g., a current greater than 0.001 times the average operating current during normal on-state conduction) from flowing through the transistor, device or component when a voltage is applied to the transistor, device or component. In other words, while the transistor, device or component is blocking the voltage applied to it, the total current passing through the transistor, device or component does not exceed 0.001 times the average operating current during normal on-state conduction.

[0021] In the accompanying drawings and the following description, the details of one or more disclosed implementations of the subject matter described herein are set forth. Additional features and variations may also be included in the implementations. Other features, aspects, and advantages will be apparent from the description, drawings, and claims.

Brief Description of the Drawings

[0022]

Figure 1A

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[0023] In various drawings, like reference numerals indicate like elements.

Best Mode for Carrying Out the Invention

[0024] In this specification, an electronic module suitable for maintaining low-level EMI and a method of operating the same are described, which enables high circuit stability and improved performance. The design of the module (coupled with the design of the switches used within the module) can result in reducing inductance and other parasitic elements, which leads to the above-described performance improvement. The electronic module can also have a reduced size and is easier to assemble than conventional modules, which enables a lower manufacturing cost.

[0025] Figures 3A and 3B show a plan view and a cross-sectional view of an electronic module 300, respectively. Module 300 includes cascode switches 382 and 383 connected to the half-bridge configuration shown in FIG. 1. Plan views and cross-sectional views of a cascode switch 400 that can be used for each of switches 382 and 383 are shown in FIGS. 4A and 4B, respectively (alternatively, other cascode configurations may be used instead of cascode switch 400).

[0026] Referring to FIGS. 4A and 4B, cascode switch 400 includes a low-voltage E-mode transistor 422 directly attached to a source pad 434 of a high-voltage D-mode transistor 423, and a drain pad 453 of E-mode transistor 422 is directly adhered to the source electrode 434 of D-mode transistor 423. E-mode transistor 422 may be, for example, a silicon FET, and D-mode transistor may be, for example, a III-N HEMT. Cascode switch 400 is operable in the same manner as a single high-voltage E-mode III-N transistor and, in many cases, achieves output characteristics identical or similar to those of a single high-voltage E-mode III-N transistor. D-mode transistor 423 has a breakdown voltage greater (e.g., at least three times greater) than that of E-mode transistor 422. The maximum voltage that can be blocked while cascode switch 400 is biased in the off state is at least as large as the maximum blocking voltage or breakdown voltage of D-mode transistor 423.

[0027] The E-mode transistor 422 includes a semiconductor body layer 455. The transistor 422 further includes an FET source electrode 451 and an FET gate electrode 452 on a first side of the semiconductor body layer 455, and an FET drain electrode 453 on a second side of the semiconductor body layer 455 (opposite to the FET source electrode 451).

[0028] The D-mode transistor 423 includes a III-N material structure 418 (e.g., a combination of GaN and AlGaN) grown on a suitable substrate 411, which may be a conductive semiconductor (e.g., silicon (e.g., p-type or n-type Si), GaN (e.g., p-type or n-type GaN)), or any other sufficiently conductive substrate, or an insulating (e.g., sapphire) substrate, or a semi-insulating substrate (e.g., semi-insulating silicon carbide).

[0029] The III-N material structure 418 may include a III-N buffer layer 412 (e.g., GaN or AlGaN) grown on the substrate 411. The buffer layer 412 can be rendered insulating or substantially free of unintentional n-type carriers. The buffer layer 412 may have a substantially uniform composition throughout or the composition may vary. The thickness and composition of the buffer layer 412 may be optimized for high voltage applications. That is, the buffer layer can block a voltage equal to the maximum voltage or high voltage supply in the circuit in which it is used. For example, the buffer layer 412 may be able to block a voltage greater than 600V or greater than 900V. The thickness of the buffer layer 412 can be made greater than 2μm. For example, the III-N buffer layer may have a thickness between 5μm and 10μm.

[0030] The III-N material structure may further include a III-N channel layer 413 (e.g., GaN) above the III-N buffer layer 412, and may include a III-N barrier layer 414 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 413. The bandgap of the III-N barrier layer 414 is larger than that of the III-N channel layer 413. The III-N channel layer 413 has a composition different from that of the III-N barrier layer 414, and the thickness and composition of the III-N barrier layer 414 are selected such that a two-dimensional electron gas (2DEG) channel 419 (shown by a dashed line in FIG. 4B) is induced adjacent to the interface of layers 414 and 413 in the III-N channel layer 413.

[0031] Typically, a III-N high electron mobility transistor (HEMT) is formed from an epitaxial (i.e., epi) III-N material structure grown by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) in a reactor. As shown in FIG. 4B, the III-N material structure may be grown in a group III polar (e.g., Ga polar) orientation (e.g., [0 0 0 1] (C-plane) orientation). Alternatively, the III-N HEMT may be formed on a III-N material structure grown in an N-polar (i.e., N-plane) orientation (e.g., [0 0 0 -1] orientation (not shown), etc.). In an N-polar device, the III-N barrier layer may be above the III-N buffer layer, and the III-N channel layer may be above the III-N barrier layer. The N-polar III-N material has a polarization field in the opposite direction to that of the group III polar III-N material, thus enabling the implementation of III-N device structures that cannot be formed using group III polar structures.

[0032] An insulating layer 415 (e.g., a dielectric layer) is grown or deposited above the upper surface of the III-N material structure 418. The insulating layer 415 is, for example, aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), Si x N y , Al 1-x Si xN, Al 1-x Si x O, Al 1-x Si x It may be formed of or include ON or any other wide bandgap insulator. Although the insulator 115 is shown as a single layer, alternatively, it may be formed of several layers and / or materials deposited during various processing steps to form a single composite insulating layer.

[0033] The source electrode 434 and the drain electrode 436 are formed on the side opposite to the substrate of the D-mode transistor 423 such that the device 423 is characterized as a lateral III-N device (i.e., the source and the drain are on the same side of the device, and the current flows laterally through the device between the source 434 and the drain 436). The source electrode 434 and the drain electrode 436 are in ohmic contact and are electrically connected to the 2DEG channel 419 of the device formed in the layer 413. The source and drain electrodes 434, 436 may each be formed from a stack of multiple metal layers. Each metal stack may be, for example, a stack of Ti / Al / Ni / Au, Ti / Al, or other suitable metal layers.

[0034] The D-mode transistor 423 further includes a gate electrode 435. As shown in FIG. 4B, the gate electrode 435 can be formed such that the insulating layer 415 extends between the gate electrode 435 and the III-N material structure 418 to separate them. Alternatively, the gate electrode 435 may be formed to contact the III-N material structure 418 (not shown). The gate electrode 435 may be formed from a suitable conductive material such as a metal stack (e.g., titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au)). Alternatively, the gate electrode 435 may be another conductive material or material stack including one or more materials having a large work function, such as a semiconductor material having a large work function (e.g., p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0035] The low-voltage E-mode device 422 is electrically connected to the high-voltage D-mode III-N device 423 to form the cascode switch 400. This may be a hybrid III-N device. Here, the drain electrode 453 of the E-mode transistor 422 is directly in contact with (e.g., attached to) the source electrode 434 of the III-N transistor 423 and is electrically connected. The drain electrode 453 of the E-mode transistor 422 may be connected to the source electrode 434 of the D-mode transistor 423 (e.g., by solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment methods that enable high-quality mechanical, thermal, and electrical connections between the FET drain electrode 453 and the source electrode 434 of the D-mode transistor). The E-mode transistor 422 may be attached above the 2DEG channel 419 as shown in FIG. 4B, or the device 422 may be attached, in part or in whole, to a region outside the active region of the device such that the FET 422 does not come above the 2DEG channel layer. The gate node of the cascode switch 400 may be connected to the gate electrode 452 of the E-mode device 422. The D-mode transistor and the E-mode transistor of a conventional cascode switch are typically packed together adjacent to a ceramic insulating substrate (such as an AlN shim), and an external wire connector is required to make the connection from the FET drain to the HEMT source necessary for the cascode configuration. However, as shown in FIGS. 4A and 4B, by directly attaching the E-mode device 422 onto the D-mode device 423, the external wire connector and the ceramic substrate are not needed. This can dramatically reduce the parasitic inductance of the circuit and enable higher rated currents and faster switching speeds.

[0036] The gate electrode 435 of the D-mode transistor 423, although not shown in FIGS. 4A or 4B, should be connected to the source electrode 451 of the E-mode transistor 422 (necessary for the proper operation of the cascode switch), and these two electrodes are actually electrically connected when the cascode switch 400 is attached to the module 300 in FIGS. 3A and 3B (because both of these electrodes are adhered to a common metal layer). This can be seen from FIGS. 3A and 3B and will be explained in more detail below.

[0037] Returning to FIGS. 3A and 3B, the module 300 includes a direct bonded copper (DBC) substrate 310 (best shown in FIG. 3B) that can serve as the base substrate of the module. The DBC substrate is formed by direct bonding in a high-temperature melting diffusion process of pure copper to a ceramic insulator (such as AlN or Al 2 O 3 etc.). The DBC substrate 310 includes an insulating (e.g., ceramic or AlN) substrate 315, on which an upper metal layer (e.g., copper or nickel) is patterned into at least a first portion 311 that functions as a high-voltage plate, a second portion 312 that functions as an output plate, and a third portion 313 that functions as a ground plate. Each of the portions 311, 312, and 313 is electrically insulated from each other by grooves 314 formed through the metal layer. As shown in FIG. 3B, the DBC substrate may include a backside metal layer 316 (e.g., copper or nickel) on the opposite side of the insulating substrate 315 with respect to the upper metal layer (311 / 312 / 313). Optionally, the ground plate 313 may be electrically connected to the backside metal layer 316 by forming metal via holes 317 through the insulating substrate 315. The high-side switch 382 and the low-side switch 383 are the cascode switches shown in FIGS. 4A and 4B, respectively. The high-side switch 382 is directly mounted on the output plate 312, and the low-side switch 383 is directly mounted on the ground plate 313.

[0038] Regarding the high-side switch 382, the drain electrode 436 of the D-mode transistor is electrically connected to the high-voltage plate 311 via the connector 341, and the gate electrode 435 of the D-mode transistor and the source electrode 451 of the E-mode transistor are both electrically connected to the output plate 312 via the wire connectors 340 and 342, respectively. Regarding the low-side switch 383, the drain electrode 436' of the D-mode transistor is electrically connected to the output plate 312 via the connector 343, and the gate electrode 435' of the D-mode transistor and the source electrode 451' of the E-mode transistor are both electrically connected to the ground plate 313 via the wire connectors 346 and 348, respectively.

[0039] Optionally, the electronic module 300 includes a package in which electronic components are placed, and the package includes a first input lead 372, a second input lead 373, a high-voltage lead 391, a ground lead 393, and an output lead 392. The first input lead 372 is connected to the gate electrode 452 of the E-mode transistor of the high-side switch 382, the second input lead 373 is connected to the gate electrode 452' of the E-mode transistor of the low-side switch 383, the high-voltage lead 391 is connected to the high-voltage plate 311, the ground lead 393 is connected to the ground plate 313, and the output lead 392 is connected to the output plate 312.

[0040] To ensure proper operation of the half-bridge circuit formed by the electronic module 300 of FIGS. 3A and 3B, the high voltage node 391 should be maintained at AC ground. That is, by connecting the first terminal of the capacitor 375 to the high voltage plate 311 and the second terminal of the capacitor 375 to the ground plate 393, the node 391 can be capacitively coupled to the DC ground node 393. As shown in FIG. 3A, the capacitor 375 can be placed directly above a portion of the via 314. When either switch 382 or 383 is switched on or off, the capacitor 375 can be appropriately charged and discharged to provide the current necessary to substantially maintain the voltages on the high and low sides of the circuit. Further, the capacitor 375 may be a hybrid capacitor including capacitive and resistive components. For example, the capacitor 375 may be configured as a series-connected capacitor and resistor. Due to the large di / dt required for high current operation, ringing and voltage spikes can occur during the turn-off of the high-side or low-side switch. Typically, the ringing frequency can be observed within the range of 100 mHz. This ringing is effectively attenuated by a series-connected resistor and capacitor rather than just a decoupling capacitor. For an operating current around 30 A, the capacitance value can be in the range of.01 nF to 100 nF, and the resistance value can be in the range of 0.1 ohm to 100 ohm. The designer may choose higher resistance and capacitance values to bias towards conditions of weaker attenuation.

[0041] FIGS. 5A and 5B respectively show a plan view and a cross-sectional view of another electronic module 500 that can provide improved performance, reliability, and reduced complexity compared to module 300. Module 500 utilizes the cascode switch 600 shown in FIG. 6 for its high-side switch and / or low-side switch (582 and 583). As will be described in more detail below, the design of the cascode switch 600 used for switches 582 and 583 allows for the omission of certain external connectors in module 500, resulting in both reduced complexity and improved performance and reliability of module 500.

[0042] As shown in FIG. 6, the cascode switch 600 used in module 500 is similar to the cascode switch 400 used in module 300, but new features are added. First, the substrate 611 on which the III-N material structure 618 is formed is a conductive substrate (e.g., formed from p-type silicon, n-type silicon, p-type GaN, n-type GaN, or n-type SiC), and the substrate is electrically connected (i.e., shorted) to the upper metal layer of module 500 to which the substrate is attached.

[0043] In addition, the gate electrode 635 of the high-voltage D-mode transistor 623 is electrically connected to the conductive substrate 611 by a via hole 638 (e.g., a through-epi via or TEV) formed through a portion of the III-N material structure 618. The via hole 638 can be formed through the entire thickness of the III-N material structure 618 and extend all the way to the substrate 611, as indicated by the dashed region 638 in FIG. 6. The metal of the gate electrode 635 is at least partially formed within the via hole 638 and makes an ohmic contact with the conductive substrate 611, thereby electrically connecting the gate electrode 635 of the III-N transistor 623 to the conductive substrate 611. The dashed region in FIG. 6 shows the via hole 638 passing through the 2DEG channel 619, but the via hole 638 is formed in such a way that the 2DEG channel 619 is continuous between the source and drain electrodes 634 and 636 of the D-mode device (e.g., the via hole may be formed within a portion of the III-N material that is outside the active region of the III-N transistor).

[0044] Finally, a backside metal layer 617 (e.g., Ti / Ni / Ag) may optionally be formed on the side of the conductive substrate 611 opposite to, i.e., on the backside of, the III-N material structure 618. The backside metal layer 617 can be used as an adhesive layer to enable the substrate 611 to be attached to the underlying metal plate within the module 500 by solder, solder paste, conductive epoxy, conductive tape, or any other suitable attachment method that provides high-quality mechanical, thermal, and electrical connection to the metal layer of the device substrate 611.

[0045] Returning to FIGS. 5A and 5B, to form the half-bridge module 500, a first cascode switch (such as switch 600) is directly attached to the output plate 512 to form the high-side switch 582, and a second cascode switch (such as switch 600) is directly attached to the ground plate 513 to form the low-side switch 583. For the high-side switch 582, the gate electrode 635 of the D-mode transistor is electrically connected to the conductive substrate 611 by the via hole 638, and since the conductive substrate is directly attached to the output plate 512, the gate electrode 635 is electrically attached to the output plate 512 without the need for an external connector (such as connector 340 in FIGS. 3A and 3B). Similarly, for the low-side switch 583, the gate electrode 635' of the D-mode transistor is electrically connected to the conductive substrate by a via hole, and since the conductive substrate is directly attached to the ground plate 513, the gate electrode 635' is electrically attached to the ground plate 513 without the need for an external connector (such as connector 346 in FIGS. 3A and 3B). As a result, the assembly of the module 500 is simplified, the circuit inductance is reduced, and the switching noise and EMI are reduced.

[0046] For completeness, other aspects and features of module 500 and the cascode switch 600 used in module 500 are as follows. Referring to FIG. 6, the cascode switch 600 includes a low-voltage E-mode transistor 622 directly mounted on the source pad 634 of a high-voltage D-mode transistor 623, and the drain pad 653 of the E-mode transistor 622 is directly adhered to the source electrode 634 of the D-mode transistor 623. The E-mode transistor 622 is, for example, a silicon FET, and the D-mode transistor is, for example, a III-N HEMT. The cascode switch 600 is operable to behave like a single high-voltage E-mode III-N transistor and, in many cases, achieve the same or similar output characteristics as a single high-voltage E-mode III-N transistor. The D-mode transistor 623 has a breakdown voltage larger (e.g., at least three times larger) than that of the E-mode transistor 622. The maximum voltage that can be blocked while the cascode switch 600 is biased in the off state can be at least as large as the maximum blocking voltage or breakdown voltage of the D-mode transistor 623.

[0047] The E-mode transistor 622 includes a semiconductor body layer 655. The transistor 622 further includes an FET source electrode 651 and an FET gate electrode 652 on a first side of the semiconductor body layer 655, and an FET drain electrode 653 on a second side of the semiconductor body layer 655 (opposite the FET source electrode 651).

[0048] The D-mode transistor 623 includes a III-N material structure 618 (e.g., a combination of GaN and AlGaN) grown on a conductive substrate 611, which may be, for example, silicon (e.g., p-type or n-type Si), GaN (e.g., p-type or n-type GaN), n-type SiC, or any other sufficiently conductive substrate.

[0049] The III-N material structure 618 may include a III-N buffer layer 612 (e.g., GaN or AlGaN) grown on a substrate 611. The buffer layer 612 can be rendered insulating or substantially free of unintentional n-type carriers. The buffer layer 612 may have a substantially uniform composition throughout or the composition may vary. The thickness and composition of the buffer layer 612 may be optimized for high voltage applications. That is, the buffer layer can block a voltage equal to the maximum voltage or high voltage supply in the circuit in which it is used. For example, the buffer layer 612 may be capable of blocking a voltage greater than 600V or greater than 900V. The thickness of the buffer layer 612 can be greater than 2μm. For example, the III-N buffer layer may have a thickness between 5μm and 10μm.

[0050] The III-N material structure may further include a III-N channel layer 613 (e.g., GaN) above the III-N buffer layer 612, and may include a III-N barrier layer 614 (e.g., AlGaN, AlInN or AlGaInN) above the III-N channel layer 613. The bandgap of the III-N barrier layer 614 is greater than the bandgap of the III-N channel layer 613. The III-N channel layer 613 has a different composition from the III-N barrier layer 614, and the thickness and composition of the III-N barrier layer 614 are selected such that a two-dimensional electron gas (2DEG) channel 619 (shown by a dashed line in FIG. 6) is induced adjacent to the interface of layers 614 and 613 in the III-N channel layer 613.

[0051] Typically, a III-N high electron mobility transistor (HEMT) is formed from an epitaxial (i.e., epi) III-N material structure grown in a reactor by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). As shown in the device of FIG. 6, the III-N material structure may be grown in a group III polar (e.g., Ga polar) orientation (e.g., [0 0 0 1] (C-plane) orientation). Alternatively, the III-N HEMT may be formed on a III-N material structure grown in an N polar (i.e., N-plane) orientation (e.g., [0 0 0 -1] orientation (not shown), etc.). In an N polar device, the III-N barrier layer may be above the III-N buffer layer, and the III-N channel layer may be above the III-N barrier layer. The N polar III-N material has a polarization field in the opposite direction to the group III polar III-N material, thus enabling the implementation of III-N device structures that cannot be formed using group III polar structures.

[0052] An insulating layer 615 (e.g., a dielectric layer) is grown or deposited above the upper surface of the III-N material structure 618. The insulating layer 615 is, for example, aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), Si x N y , Al 1-x Si x N, Al 1-x Si x O, Al 1-x Si x ON or any other wide bandgap insulator, or may be formed from or include these. The insulating layer 115 is shown as a single layer, but alternatively may be formed of several layers and / or materials deposited during various processing steps to form a single composite insulating layer. The insulating layer 18 may be uniform throughout or may be formed from insulating materials of varying types.

[0053] The source electrode 634 and the drain electrode 636 are formed on the side opposite to the substrate of the D-mode transistor 623 such that the device 623 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between the source 634 and the drain 636). The source and drain electrodes 634, 636 may each be formed from a stack of a plurality of metal layers. Each metal stack may be, for example, a stack of Ti / Al / Ni / Au, Ti / Al, or other suitable metal layers.

[0054] The D-mode transistor 623 further includes a gate electrode 635. As shown in FIG. 6, the gate electrode 635 may be formed such that the insulating layer 615 is at least partially between the gate electrode and the III-N material structure 618. The gate electrode 435 may be formed from a suitable conductive material such as a metal stack (e.g., titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au)).

[0055] The low-voltage E-mode device 622 is electrically connected to the high-voltage D-mode III-N device 623 to form a cascode switch 600. Here, the drain electrode 653 of the E-mode transistor 622 is directly in contact with (e.g., attached to) the source electrode 634 of the III-N transistor 623 and is electrically connected. The drain electrode 653 of the E-mode transistor 622 may be connected to the source electrode 634 of the D-mode transistor 623 (e.g., by soldering, solder paste, conductive epoxy, conductive tape, or other suitable attachment methods that enable a high-quality mechanical, thermal, and electrical connection between the FET drain electrode 653 and the source electrode 634 of the D-mode transistor). The E-mode transistor 622 may be attached above the 2DEG channel 619 as shown in FIG. 6, or the device 622 may be attached partially or entirely in a region outside the active region of the device such that the FET 622 does not come above the 2DEG channel layer.

[0056] Returning to FIGS. 5A and 5B, module 500 includes a direct bond copper (DBC) substrate 510 (best shown in FIG. 5B) that can serve as the base substrate of the module. DBC substrate 510 includes an insulating (e.g., ceramic) substrate 515, to which an upper metal layer (e.g., copper) is patterned into at least a first portion 511 that functions as a high voltage plate, a second portion 512 that functions as an output plate, and a third portion 513 that functions as a ground plate. Each of the portions 511, 512, and 513 is electrically insulated from each other by grooves 514 formed through the upper metal layer. DBC substrate 510 may optionally include a backside metal layer 516 on the opposite side of insulating substrate 515 with respect to the upper metal layer (511 / 512 / 513). Optionally, ground plate 513 may be electrically connected to backside metal layer 516 by forming metal via holes 517 through insulating substrate 515. High-side switch 582 and low-side switch 583 are cascode switches shown in FIG. 6, respectively. High-side switch 582 is mounted directly on output plate 512, and low-side switch 583 is mounted directly on ground plate 513.

[0057] For high-side switch 582, the drain electrode 636 of the D-mode transistor is electrically connected to high voltage plate 511 via connector 541, and the source electrode 651 of the E-mode transistor is electrically connected to output plate 512 via wire connector 542. For low-side switch 583, the drain electrode 636' of the D-mode transistor is electrically connected to output plate 512 via connector 543, and the source electrode 651' of the E-mode transistor is electrically connected to ground plate 513 via wire connector 544. Connectors 541-544 may comprise a single wire bonding (not shown), multiple parallel wire bondings, a ribbon, a conductive metal clip, or other connectors including a conductive material (e.g., aluminum (Al), gold (Au), copper (Cu), or other suitable material).

[0058] Optionally, the electronic module 500 includes a package in which electronic components are placed, and the package includes a first input lead 572, a second input lead 573, a high voltage lead 591, a ground lead 593, and an output lead 592. The first input lead 572 is connected to the gate electrode 652 of the E-mode transistor of the high-side switch 582, the second input lead 573 is connected to the gate electrode 652' of the E-mode transistor of the low-side switch 583, the high voltage lead 591 is connected to the high voltage plate 511, the ground lead 593 is connected to the ground plate 513, and the output lead 592 is connected to the output plate 512.

[0059] To ensure proper operation of the half-bridge circuit formed by the electronic module 500 of FIGS. 5A and 5B, the high voltage node 591 should be maintained at AC ground. That is, by connecting the first terminal of the capacitor 575 to the high voltage plate 511 and the second terminal of the capacitor 575 to the ground plate 593, the node 591 can be capacitively coupled to the DC ground node 593. As shown in FIG. 5A, the capacitor 575 can be placed directly above a portion of the via 514. When either switch 582 or 583 is switched on or off, the capacitor 575 can be appropriately charged and discharged to provide the current necessary to substantially maintain the voltages on the high side and low side of the circuit. Further, the capacitor 575 may be a hybrid capacitor including capacitive components and resistive components. For example, the capacitor 575 may be configured as a single component including a series-connected capacitor and resistor. Due to the large di / dt required for high current operation, ringing and voltage spikes can occur during the turn-off of the high side switch or the low side switch. Typically, the ringing frequency can be observed within the range of 100 mHz. This ringing is effectively attenuated by a series-connected resistor and capacitor rather than just a decoupling capacitor. For an operating current around 30 A, the capacitance value may be greater than 0.1 nF, for example, it may be in the range from 0.1 nF to 100 nF, and the resistance value may be greater than 0.1 ohm, for example, it may be in the range from 0.1 ohm to 100 ohm. The designer may choose higher resistance and capacitance values to bias towards conditions of weaker attenuation.

[0060] FIGS. 7A, 7B, and 7C show three different modes for operating a half-bridge buck converter circuit similar to the half-bridge of FIG. 1A. The half-bridge circuit includes a high side switch 102 connected to the high voltage node 111 and a low side switch 103 connected to the ground node 113. An inductor 104 is between the node 112 (which is between the low side switch 103 and the high side switch 102) and the output node V of the circuitOUT is connected between them. The first capacitor 106 is connected between the high voltage node 111 and the DC ground 113. The second capacitor 107 is connected between the output node V of the circuit OUT and the DC ground 113. The low-side switch 103 and the high-side switch 102 are selected to have characteristics that improve the efficiency of the buck converter circuit. Specifically, the switches 102 and 103 should have a low on-resistance (R DS(ON) ) and low switching losses. The switches 102 and / or 103 may be formed, for example, with the cascode switch 200 of FIG. 2. Alternatively, the switches 102 and / or 103 may be implemented as the cascode switch 600 of FIG. 6 assembled within the half-bridge module 500 of FIG. 5A.

[0061] The buck converter half-bridge of FIGS. 7A - 7C can operate as follows. Referring to FIG. 7A, in the first operating mode, the gate of the high-side switch 102 is biased on (i.e., V GS 102 > V TH ), and the gate of the low-side switch 103 is biased off (i.e., V GS 103 < V TH ). The current 97 flows from the high voltage node 111 in the forward direction through the high-side switch 102 to the node 112. This current is blocked by the low-side switch 103 and flows through the inductor 104 as indicated by the current path 97. While the device is operating in the first operating mode, the gate-source voltage of the high-side switch 102 is lowered or switched off (i.e., V GS 102 < V TH ), and when the gates of both switches 102 and 103 are biased off, the half-bridge switches to the second operating mode shown in FIG. 7B. The current must continue to flow through the inductor 104.

[0062] Figures 7D and 7E show the circuit schematic of the cascode switch (such as the cascode switch 200 in Fig. 2), and also show various parasitic inductances and capacitances inherent in the cascode configuration. The parasitic gate-drain capacitance (C GD ) of the D-mode III-N transistor 223 is shown as capacitor 57. The built-in body diode of the E-mode FET 222 is shown by diode 237. The parasitic inductance of the source connection of the E-mode FET 222 is shown as inductor 54, and the parasitic inductance of the gate connection of the D-mode III-N transistor 223 is shown as inductor 53. When the circuits of Figs. 7D and 7E are implemented as the low-side switch 383 in a half-bridge module (similar to the module 300 in Fig. 3A), the inductor 54 represents the inductance of the wire (e.g., wire 348 in Fig. 3A) connecting from the source 451' of the E-mode transistor to the ground plate 313. To connect the gate electrode 435' of the D-mode transistor of the switch 383 to the source electrode 451' of the E-mode transistor of the switch 383, and to connect the gate electrode 435' of the D-mode transistor to the ground plate 313, an external gate wire connector 346 is used. As a result of this gate wire connector 346, a substantial inductance (represented by inductor 53 in Fig. 7D) occurs between the gate electrode 435 of the D-mode transistor and the ground plate 313. The parasitic inductances 53 and 54 can reduce the turn-on time and turn-off time of the module, increase the switching loss, and thereby degrade the performance of the circuit.

[0063] Figure 7D shows the detailed current path through the cascode configuration of the low-side switch 103 during the transition time T 1 between the first operating mode and the second operating mode shown in Figs. 7A and 7B. During the transition time T 1 , the voltage at node 112 (shown in Figs. 7A - 7B) drops until it becomes negative, and the current path I in Fig. 7D ACAs shown by, displacement current flows through the parasitic gate-drain capacitor 57 of the D-mode III-N transistor 223. When the voltage of node 112 becomes sufficiently negative, the gate of the low-side switch 102 is biased off (i.e., V GS < V TH ), but the built-in body diode 237 of the E-mode FET transistor 222 turns on, and the switch 103 changes from off to reverse conduction state. This is called the reverse conduction mode (i.e., free-wheeling diode mode). At the end of the transition time T 1 , the switch 103 transitions from off to reverse conduction, and the current rapidly transitions from the displacement current (shown in FIG. 7D) flowing through the gate-drain capacitor 57 of the D-mode transistor 223 to the reverse DC current (current path I in FIG. 7E) flowing through the built-in body diode 237 of the E-mode transistor 222 and the channel of the D-mode transistor 223 DC shown by.

[0064] When the operating current through the inductor 104 is high, the current path transition may cause voltage spikes and ringing across the gate of the D-mode transistor 223. This voltage spike injects charge into the gate dielectric of the D-mode transistor (e.g., insulating layer 415 or 615), leading to an increase in the channel on-resistance (R ON ) of the D-mode transistor, which in turn increases the on-resistance of the cascode switch 383. Since the current in the inductor 104 must be continuous, reverse conduction of the switch 103 occurs in the circuit of FIG. 7B even when the gate of the switch 103 is biased off.

[0065] Returning to FIG. 7C, after the gate of the high-side 102 switches off as shown in FIG. 7B, the low-side switch 103 switches on (i.e., V GS > V TH ), operating the buck converter in the third operating mode, and the current 98 is in the second mode and is in the reverse direction toIt continues to flow through the low-side switch 103, provided that the low-side switch 103 is biased on. By biasing the low-side switch on during the third operation mode, the reverse voltage drop across the E-mode transistor 222 is reduced compared to the second operation mode, enabling higher efficiency compared to the second operation mode. To prevent the high-voltage node 111 from accidentally shorting to the ground node 113, a sufficient dead time is used between the time when the high-side switch 102 is turned off and the time when the low-side switch 103 is turned on.

[0066] To determine the performance of the low-side switch 103 during reverse conduction mode, the design of the cascode switch and related modules can be an important factor. By implementing the device 600 as the low-side device 103 within the half-bridge module 500, and also by eliminating the need for an external gate wire connection (such as wire 346 in FIG. 3A) between the D-mode transistor of the switch 583 and the ground plane 513 within the module 500 (since the gate of the D-mode transistor is connected to the ground plane 513 through the via hole 638), the parasitic inductance within the half-bridge module (shown by the inductor 53 in FIG. 7D) is reduced. This reduces the voltage spikes and ringing that the gate of the D-mode transistor of the switch 583 experiences during the current path transition between the first and second operating modes. Surprisingly, it has been shown that when operating with a very high reverse DC current, the degradation (i.e., increase) of the channel on-resistance of the switch is substantially reduced compared to conventional modules with external gate wires. This result was unexpected. The contribution of the gate wire inductance to the module switching performance from the depletion mode transistor was considered negligible by the inventors because there is no DC current flowing through this path and the gate voltage of the depletion mode transistor of the low-side switch is typically pinned to ground. This degradation in on-resistance is generally referred to as current collapse or dispersion and is a major concern for the implementation of III-N devices in half-bridge circuits. When the cascode switch 600 is implemented as the low-side switch 583 in the half-bridge module 500, the switch 583 can operate with a reverse DC current greater than 50 A (and even 70 A) between the second and third operating modes while showing little increase in on-resistance. For example, the increase in on-resistance can be less than 5% compared to the first operating mode. Conventional modules with external gate wire connections can typically show an increase in on-resistance of more than 30% even when operating with a reverse DC current of 30 A or less. The low-side switch 583 can block a voltage greater than 600 V during the first operating mode.

[0067] In addition, the high-side switch 582 can operate in a reverse conduction mode during a specific switching procedure. Here, the gate connection between the D-mode III-N transistor of the cascode switch 582 and the output plate 512 is connected through the via hole 638, and the parasitic inductance of the electronic module is further reduced. As a result, the voltage spike and ringing received by the cascode switch 582 during the current path transition when switching to the reverse conduction mode are further reduced.

[0068] FIG. 8 is a top view of an integrated electronic module 800 forming a half-bridge circuit similar to the integrated electronic half-bridge module 500 of FIG. 5A, having an alternative DBC 810 layout that allows for a more compact arrangement of the high-voltage plate 811, output plate 812, and ground plate 813 compared to the module 500 of FIG. 5A. This reduces the electronic module size and footprint and reduces cost. Also, module 800 includes a high-side source sense node 896 and a low-side source sense node 897. Although not shown in FIG. 5A, module 500 may also include sense nodes 896 and 897. The high-side source sense node 896 is connected to the output plate 812, and the low-side source sense node 897 is connected to the ground plate 813. The first input lead 872, high-side source sense node 896, second input lead 873, and low-side source sense node 897 (collectively the gate nodes) extend from the first side of the module 800, and all the gate nodes are configured to extend from the same side of the module and be connected to an external gate driver. In some examples, the high-side gate node may be connected to a high-side gate driver, and the low-side gate node may be connected to a low-side gate driver. The high-voltage node 891, ground node 893, and output node 892 extend from the second side of the module 800, opposite the first side, with the high-voltage node 891 configured to be connected to a circuit high-voltage supply, the ground node 893 configured to be connected to a circuit ground, and the output node 892 configured to be connected to an inductive element or circuit load. The high-side switch 882 is arranged with a 90° rotation compared to the low-side switch 883 of the module 800, allowing for a more compact arrangement of the module components and also allowing for shorter wire bond connections to the DBC 810. In particular, in the high-side switch 882, the source electrode 634 and drain electrode 634 are arranged along a first axis, while in the low-side switch 883, the source electrode 634' and drain electrode 634' are arranged along a second axis orthogonal to the first axis.

[0069] FIG. 9 is a top view of an integrated electronic module 900 that forms a half-bridge circuit integrated in a surface-mounted power device (i.e., SMPD) type package. The half-bridge circuit configured within the electronic module 600 is similar to the module 500 of FIG. 5A, but includes an additional metal routing layer on the DBC 910 and a connector lead that houses a source sense pin and a gate connection ferrite bead. The electronic module 900 includes a high-side switch 582 and a low-side switch 583, which may be identical to the module 500 of FIG. 5A. The module 900 includes a DBC 910 that includes a high-voltage plate 911, an output plate 912, and a ground plate 913, each plate being separated by a groove 914 formed in the upper metal layer of the DBC 910. The DBC 910 can be constructed in a manner similar to the DBC 510 of FIGS. 5A and 5B, but results in an alternative upper metal layer configuration as a result of the separation pattern from the groove 914. The electronic module 900 further includes a high-voltage lead 991 connected to the high-voltage plate 911, an output lead 992 connected to the output plate 912, and a ground lead 993 connected to the ground plate 913. The electronic module 900 further includes a first input lead 961 (which may be a plurality of leads), a high-side source sense lead 962, a second input lead 963 (which may be a plurality of leads), and a low-side source sense lead 964. The module 900 includes a hybrid capacitor 575 connected between the high-voltage plate 911 and the ground plate 913, similar to the module 500 of FIG. 5A.

[0070] FIG. 9 further includes optional high-side ferrite beads 68 and optional low-side ferrite beads 69. The high-side ferrite beads 68 include a first terminal electrically coupled to the first input lead 961 and a second terminal electrically coupled to the first side of the high-side gate connector 65. The high-side gate connector 65 includes a second side connected to the gate electrode of the E-mode transistor of the cascode switch 582. The low-side ferrite beads 69 include a first terminal electrically coupled to the second input lead 963 and a second terminal electrically coupled to the first side of the low-side gate connector 67. The low-side gate connector 67 includes a second side connected to the gate electrode of the E-mode transistor of the cascode switch 583. The electronic module 900 further includes a source detection connector 66 having a first side electrically connected to the high-side source detection node 962 and a second side electrically connected to the output plate 912. The connector 66 bridges the ground plate 913 and is used to make the high-side source detection node 962 have the same potential as the source of the high-side switch 582. The connectors 65, 66, and 67 may comprise a single wire bonding (not shown), multiple parallel wire bondings, a ribbon, a conductive metal clip, or other connectors including a conductive material (e.g., aluminum (Al), gold (Au), copper (Cu), or other suitable materials).

[0071] As shown in FIG. 9, the high-side switch 582 is directly attached to the output plate 912. As a result, without using an external wire connector, the gate of the D-mode III-N transistor of the cascode switch 582 is directly electrically connected to the output plate 912 through the substrate of the cascode switch 582. Also, the low-side switch 583 is directly attached to the ground plate 913. As a result, without using an external wire connector, the gate of the D-mode III-N transistor of the cascode switch 583 is electrically connected to the ground plate 912 through the substrate of the switch 583. The hybrid capacitor 575 is connected to the input side of the module 900 between the first input lead 931 and the high-side switch 582. By integrating the cascode switches 582 and 583 in an SMPD type package, a simplified and efficient integration of the half-bridge circuit into an industry-standard power device package becomes possible.

[0072] FIG. 10 is a top view of an integrated electronic module 1000, similar to the electronic module 900 of FIG. 9, but module 1000 connects a hybrid capacitor 1075 between the ground plate 1013 and the high voltage plate 1011 on the output side of module 1000 as compared to the input side of the module shown in FIG. 9. Module 1000 includes a DBC 1010 including a high voltage plate 1011, an output plate 1012, and a ground plate 1013, and each plate is separated by a groove 1014 formed in the upper metal layer of the DBC 1010. The DBC 1010 can be constructed in a manner similar to the DBC 510 of FIGS. 5A and 5B, but results in an alternative upper metal layer configuration as a result of the separation pattern from the groove 1014. Here, the high-side switch 582 and the source sense lead 962 are both directly connected to the first output plate 1012, and the connector 66 of FIG. 6 is omitted. The connector 66' of module 1000 has a first side connected to the output plate 1012 and a second side connected to the output plate 1012'. The output node 992 directly contacts the second output plate 1012', whereby the output node 992 and the source of the cascode switch 582 are at the same potential.

[0073] FIG. 11 is a top view of an integrated electronic module 1100, similar to the electronic module 1000 of FIG. 10, but module 1100 includes a capacitor 1174 and a resistor 1175 as two separate components connected in series (different from module 1000 which uses a single hybrid component 1075) to connect to the high voltage plate 1111 and the ground plate 1113, thereby maintaining the high voltage plate 1111 at the AC ground of the DBC 1110. By using two separate components, it becomes possible for a circuit designer to select additional components to change the performance of the package. In addition, the relative order of the capacitor 1174 and the resistor 1175 is interchangeable.

[0074] FIG. 12 is a top view of an integrated electronic module 1200, similar to the electronic module 1000 of FIG. 10, but the module 1200 is implemented using a source ferrite bead 1266 (having a first terminal electrically coupled to the source voltage of the high-side switch 582 and a second terminal electrically coupled to the output lead 992). The source ferrite bead 1266 can be implemented such that the ferrite bead bridges the high-voltage plate 1011 in the same manner as the connector 66' of FIG. 10. Implementing the module 1200 with the source ferrite bead 1266 instead of using the connector 66' contributes to suppressing voltage ringing and other noises at the output node, thereby further improving the operation of the half-bridge module.

[0075] FIGS. 13A and 13B show side and top views, respectively, of an external rendering of a fully encapsulated SMPD type package that can be used for modules 900-1200. The encapsulated package includes a molding compound 1311 (plastic, epoxy, metal, or other suitable material for hermetically sealing and electrically encapsulating each component of the integrated electronic module).

[0076] The integrated electronic modules 900, 1000, 1100, and 1200 represent a surface mount power device (SMPD) package type, but alternative module packages such as quad flat no-lead (QFN) or loss-free package (LFPAK), or other suitable types of module packages capable of properly accommodating the high-side 582 and low-side switches 583 to form a half-bridge circuit, etc. can also be used. Each component of modules 900-1200 can be arranged or arrayed in a manner that best suits the needs of the designer and the package type.

[0077] FIG. 14 is a top view of the integrated electronic module 1400, which is similar to the electronic module 500 of FIG. 5A, but the module 1400 is implemented using two high-side switches (582 and 582a) connected in parallel and two low-side switches (583 and 583a) connected in parallel. The connector 41a connects the high-voltage plate 11 to the drain electrode 36a of each D-mode transistor of the high-side switch 582a. The connector 42a connects the source electrode 51a of the E-mode transistor of the high-side switch 582a to the output plate 12. The connector 43a connects the output plate 12 to the drain electrode 36a' of the D-mode transistor of the low-side switch 583a, and the connector 44a connects the source electrode 51a' of the E-mode transistor of the low-side switch 583a to the ground plate 13. The first input lead 572 is connected to the gate electrode of the E-mode transistor of each of the high-side switches 582 and 582a, and the second input lead 573 is connected to the gate electrode of the E-mode transistor of each of the low-side switches 583 and 583a. Here, the substrates of the first high-side switch 582 and the second high-side switch 582a are both in contact with and electrically connected to the same portion of the upper metal layer of the DBC 1410 forming the output plate 12. Also, the substrates of the first low-side switch 583 and the second low-side switch 583a are both in contact with and electrically connected to the same portion of the upper metal layer of the DBC 1410 forming the ground plate 13. By constructing the module 1400 by attaching a plurality of switches connected in parallel to the same portion of the upper metal layer, the operating performance of the module is improved and the overall rated power can be made much higher.

[0078] During operation of module 1400, when the first input lead 572 switches on or off, both switches 582 and 582a switch on or off simultaneously. Similarly, when the second input lead 573 switches on or off, both switches 583 and 583a switch on or off simultaneously. Typically, when paralleling a half-bridge circuit using multiple distributed components, external routing wires are used which can cause circuit alignment problems when switching at high speed. By integrating these switching transistors into the same electronic module, switching misalignment problems can be alleviated and overall circuit performance can be improved. Although FIG. 14 shows two high-side switches and two low-side switches, for example, three or four high-side switches and low-side switches may be connected in parallel. In theory, there is no limit to the number of switches that can be paralleled in this way.

[0079] Returning to FIG. 1B, a circuit schematic of the three-phase full-bridge circuit 120 is shown. Each of the three half-bridges 122, 124, and 126 within circuit 120 can be implemented using an integrated electronic module (e.g., electronic modules 300-1400 described herein).

[0080] FIG. 15 is a top view of an electronic module 1500 that includes an integrated three-phase full-bridge circuit (e.g., circuit 120 of FIG. 1B) within a single package. The first-phase half-bridge circuit includes a high-side switch 82 and a low-side switch 83. The second-phase half-bridge circuit includes a high-side switch 82' and a low-side switch 83'. The third-phase half-bridge circuit includes a high-side switch 82'' and a low-side switch 83''. All of the high-side switches and low-side switches can be implemented using the cascode switch 600 of FIG. 6. The module 1500 includes a DBC layer 1510, and the upper metal layer of the DBC 1510 is patterned into at least five portions separated by grooves 1514 formed through the upper metal layer of the DBC 1510. The first portion functions as a high-voltage plate 14, which is configured to be connected to a DC high voltage via a high-voltage lead 91. The second portion functions as an output plate 15, which is connected to the output node 92 of the first phase. The third portion functions as an output plate 16, which is connected to the output node 92' of the second phase. The fourth portion functions as an output plate 17, which is connected to the output node 92'' of the third phase. The fifth portion functions as a ground plate 18, which is configured to be connected to a DC ground via a ground lead 93.

[0081] The substrates of the high-side switches 82, 82' and 82'' are each in contact with and electrically connected to the output plates 15, 16 and 17, respectively. The substrates of the low-side switches 83, 83' and 83'' are in contact with and electrically connected to the ground plate 18, and all the low-side switches are in contact with and electrically connected to the same metal part of the DBC 1510. The substrates of the high-side switches 82, 82' and 82'' are electrically insulated from each other. The drain electrode 36 of the D-mode transistor node of the high-side switch 82 is connected to the high-voltage plate 14 by the connector 41, the drain electrode 36' of the D-mode transistor of the high-side switch 82' is connected to the high-voltage plate 14 by the connector 41', and the drain electrode 36'' of the D-mode transistor of the high-side switch 82'' is connected to the high-voltage plate 14 by the connector 41''. The source electrode 34 of the E-mode transistor node of the high-side switch 82 is connected to the output plate 15 by the connector 42, the source electrode 34' of the E-mode transistor of the high-side switch 82' is connected to the output plate 16 by the connector 42', and the source electrode 34'' of the E-mode transistor of the high-side switch 82'' is connected to the output plate 17 by the connector 42''. The drain electrode 56 of the D-mode transistor of the low-side switch 83 is connected to the first-phase output plate 15 by the connector 43, the drain electrode 56' of the D-mode transistor of the low-side switch 83' is connected to the second-phase output plate 16 by the connector 43', and the drain electrode 56'' of the D-mode transistor of the low-side switch 83'' is connected to the third-phase output plate 17 by the connector 43''. The source electrode 54 of the E-mode transistor node of the low-side switch 83 is connected to the ground plate 18 by the connector 44, the source electrode 54' of the E-mode transistor of the low-side switch 83' is connected to the ground plate 18 by the connector 44', and the source electrode 54'' of the E-mode transistor of the low-side switch 83'' is connected to the ground plate 18 by the connector 44''.

[0082] The gate driver operates module 1500 using three independent gate signals for each high-side switch and three independent gate signals for each low-side switch. Each independent high-side gate signal from the gate driver can be connected to gate input nodes 94, 94' and 94'', and each low-side gate signal from the gate driver can be connected to gate input nodes 95, 95' and 95''. By integrating the three-phase full-bridge circuit 120 of FIG. 1B into a single integrated electronic device module 1500, the switching efficiency can be greatly improved while reducing the circuit complexity at the same time. Although not shown for simplicity, module 1500 may include an integrated gate driver housed within the same package as components of module 1500. The gate driver can be configured in a manner similar to that described below with respect to FIG. 16.

[0083] FIG. 16 is a top view of an integrated electronic module 1600 forming a half-bridge circuit similar to the integrated electronic half-bridge module 500 of FIG. 5A. However, module 1600 also includes a gate driver 1620 integrated within the same module package as the high-side switch 582 and the low-side switch 583. Components with similar numbers include the same or similar features as those in module 500. Module 1600 includes a DBC 1610. The DBC 1610 includes a high-voltage plate 511, an output plate 512, and a ground plate 513, and optionally includes a driver plate 515, all of which are separated by grooves 516. The gate driver 1620 may be attached to the driver plate 515, or alternatively, the gate driver 1620 may be directly attached to the structural package base of the module (e.g., a copper or Ni lead frame (not shown)). The driver plate 515 may be configured in multiple parts to accommodate and attach a plurality of leads extending from or connected to the gate driver 1620. The gate driver 1620 has at least a first terminal 1622 (V INIt includes <582>. The gate driver 1620 includes a second terminal 1623 which is a high-side source current sensing node, and this is connected to the output plate 512 or, optionally, directly connected to the source electrode 651 of the E-mode transistor of the high-side switch 582 (not shown). The gate driver 1620 has a third terminal 1624 (V IN 583) connected to the gate electrode 652’ of the E-mode transistor of the low-side switch <583>. The gate driver 1620 includes a fourth terminal 1626 which is a low-side source current sensing node, and this is connected to the ground plate 513 or, optionally, directly connected to the source electrode 651’ of the E-mode transistor of the high-side switch <583> (not shown). Integrating the gate driver 1620 into the module 1600 increases the cost and complexity compared to the module 500, but the overall performance of the module 1600 may be better than that of the module 500 operating with an external gate driver. Additionally, the overall size of the electronic circuit components into which the module 1600 can be incorporated can be reduced, resulting in cost savings and other advantages. Although not shown, the gate driver 1620 may be two separate gate drivers, whereby the first gate driver is connected to the high-side switch and the second gate driver is connected to the low-side switch.

[0084] FIG. 17 is a top view of an integrated electronic module 1700 that forms a half-bridge circuit similar to the integrated electronic half-bridge module 1600 of FIG. 16. However, module 1700 includes a gate driver 1720 in which an E-mode transistor of the high-side switch 582 and an E-mode transistor of the low-side switch 583 are integrated. The high-side D-mode III-N transistor 1782 is attached to the output plate 512, and the low-side D-mode III-N transistor 1783 is attached to the ground plate 513. The gate driver 1720 includes at least a first terminal 1721 that connects the source of the integrated E-mode transistor of the high-side switch to the output plate 512. This connection couples the source of the E-mode transistor to the output terminal 592 and the conductive substrate of the high-side D-mode III-N transistor 1782. The gate driver 1722 includes a second terminal 1722 that connects the drain of the integrated E-mode transistor of the high-side switch to the source electrode 634 of the high-side D-mode III-N transistor 1782. The gate driver 1720 includes a third terminal 1724 that connects the source of the integrated E-mode transistor of the low-side switch to the ground plate 513. This connection couples the source of the E-mode transistor to the ground terminal 593 and the conductive substrate of the low-side D-mode III-N transistor 1783. The gate driver 1722 includes a fourth terminal 1725 that connects the drain of the integrated E-mode transistor of the low-side switch to the source electrode 634' of the low-side D-mode III-N transistor 1783. By integrating the E-mode transistors of the high-side switch and the low-side switch into the gate driver 1720, the complexity of module 1700 can be reduced compared to module 1600, and the overall assembly cost can be reduced. Although not shown, the gate driver 1720 may alternatively be two separate gate drivers, where the first gate driver is connected to the high-side switch and the second gate driver is connected to the low-side switch.

[0085] Some embodiments have been described. However, it is understood that various modifications can be made without departing from the spirit and scope of the technology and devices described herein. Accordingly, other implementations are also within the scope of the appended claims.

Claims

1. A base substrate including an insulating layer between a first metal layer and a second metal layer, wherein the first metal layer includes a first portion, a second portion, and a third portion, and a groove formed through the first metal layer electrically insulates the first portion, the second portion, and the third portion of the first metal layer from each other; a base substrate, A high-side switch including an enhancement-mode transistor and a depletion-mode transistor, wherein the depletion-mode transistor includes a III-N material structure on a conductive substrate; a high-side switch, A low-side switch, An electronic module comprising: A drain electrode of the depletion-mode transistor is electrically connected to the first portion of the first metal layer, A source electrode of the enhancement-mode transistor is electrically connected to the second portion of the first metal layer, A drain electrode of the enhancement-mode transistor is electrically connected to a source electrode of the depletion-mode transistor, A gate electrode of the depletion-mode transistor is electrically connected to the conductive substrate, The conductive substrate is electrically connected to the second portion of the first metal layer, An electronic module.

2. The low-side switch includes a second enhancement-mode transistor and a second depletion-mode transistor, The second depletion-mode transistor includes a second III-N material structure above a second conductive substrate, A drain electrode of the second depletion-mode transistor is electrically connected to the second portion of the first metal layer, A source electrode of the second enhancement-mode transistor is connected to the third portion of the first metal layer, A drain electrode of the second enhancement-mode transistor is electrically connected to a source electrode of the second depletion-mode transistor, A gate electrode of the second depletion-mode transistor is electrically connected to the second conductive substrate, The second conductive substrate is electrically connected to the third portion of the first metal layer, The electronic module according to Claim 1.

3. The electronic module according to Claim 2, wherein the high-side switch and the low-side switch form a half-bridge circuit.

4. The depletion-mode transistor, able to block at least 600 V while the high-side switch is biased off, able to conduct a current greater than 30 A while the high-side switch is biased on The electronic module according to claim 2, configured as such.

5. further comprising a capacitor, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, a second terminal of the capacitor is electrically connected to the third portion of the first metal layer, The electronic module according to claim 2.

6. The electronic module according to claim 5, wherein the capacitor extends orthogonally above the groove.

7. The electronic module according to claim 5, wherein the capacitor is a hybrid capacitor comprising a resistive component and a capacitive component in series.

8. The resistive component is greater than 0.1 ohm, and the capacitive component is greater than 0.1 nF. The electronic module according to claim 7.

9. The gate electrode, the source electrode, and the drain electrode are on the side of the III-N material structure opposite to the conductive substrate, the III-N material structure comprises a via hole formed therein, the gate electrode is electrically connected to the conductive substrate through the via hole, The electronic module according to claim 1.

10. further comprising a package, the base substrate, the high-side switch, and the low-side switch are placed in the package, The electronic module according to claim 1.

11. Further comprising a package, the base substrate, the high-side switch, and the low-side switch are placed in the package, further comprising a gate driver placed in the package, a first terminal of the gate driver is connected to the gate electrode of the enhancement-mode transistor, a second terminal of the gate driver is connected to the gate electrode of the second enhancement-mode transistor, The electronic module according to claim 2.

12. a second high-side switch connected in parallel with the high-side switch, a second low-side switch connected in parallel with the low-side switch, The electronic module according to claim 1, further comprising.

13. The electronic module according to claim 1, wherein the second portion of the first metal layer is connected to the output node of the electronic module.

14. During operation of the module, the first portion of the first metal layer is connected to a DC voltage supply, and the third portion of the first metal layer is connected to a DC ground The electronic module according to claim 13, configured as such.

15. A half-bridge circuit, the half-bridge circuit comprising: a high-side switch and a low-side switch each placed in a single electronic package, the package comprising a high-voltage terminal, an output terminal, and a ground terminal, the high-side switch and the low-side switch; the high-side switch comprising a first enhancement-mode transistor and a first depletion-mode III-N transistor arranged in a cascode configuration; the low-side switch comprising a second enhancement-mode transistor and a second depletion-mode III-N transistor arranged in a cascode configuration; comprising the drain electrode of the first depletion-mode III-N transistor is electrically connected to the high-voltage terminal, the conductive substrate of the first depletion-mode III-N transistor is electrically connected to the output terminal, the drain electrode of the second depletion-mode III-N transistor is electrically connected to the output terminal, and the conductive substrate of the second depletion-mode III-N transistor is electrically connected to the ground terminal. Half-bridge circuit.

16. the gate electrode of the first depletion-mode III-N transistor is electrically connected to the substrate of the first depletion-mode III-N transistor, the source electrode of the first enhancement-mode transistor is electrically connected to the output terminal, The circuit according to claim 15.

17. the gate electrode of the second depletion-mode III-N transistor is electrically connected to the substrate of the second depletion-mode III-N transistor, the source electrode of the second enhancement-mode transistor is electrically connected to the ground terminal, The circuit according to claim 16.

18. the package further comprises a DBC substrate comprising a first metal layer, the first metal layer includes a first portion, a second portion, and a third portion, The groove formed through the first metal layer electrically insulates the first portion, the second portion, and the third portion of the first metal layer from each other. The substrate of the first depletion-mode III-N transistor is in direct contact with the second portion of the first metal layer. The substrate of the second depletion-mode III-N transistor is in direct contact with the third portion of the first metal layer. The second portion is connected to the output terminal. The third portion is connected to the ground terminal. The circuit according to claim 17.

19. Further comprising a ferrite bead having a first terminal and a second terminal. The first terminal of the ferrite bead is connected to the second portion of the first metal layer, and the second terminal is connected to the output terminal. The circuit according to claim 18.

20. The substrate of the first depletion-mode III-N transistor and the substrate of the second depletion-mode III-N transistor are silicon-doped p-type with a hole concentration of 1×10 １９ holes / cm ３ greater than that of the circuit according to claim 15.

21. Further comprising a gate driver placed within the package. The first terminal of the gate driver is connected to the gate electrode of the first enhancement-mode transistor. The second terminal of the gate driver is connected to the gate electrode of the second enhancement-mode transistor. The circuit according to claim 15.

22. A half-bridge circuit, The half-bridge circuit includes a high-side switch and a low-side switch, each placed within a single electronic package. The high-side switch is connected to a high-voltage node. The low-side switch is connected to a ground node. An inductor is connected to the output terminal of the package configured between the high-side switch and the low-side switch. The low-side switch includes a low-voltage enhancement-mode transistor and a high-voltage III-N depletion-mode transistor arranged in a cascode configuration. The half-bridge circuit, In a first operating mode, while the high-side switch is biased on and the low-side switch is biased off, current passes through the high-side switch in a first direction and flows through the inductor. In a second operating mode, while the high-side switch is biased off and the low-side switch is biased off, current passes through the low-side switch in a second direction and flows through the inductor. In the third operation mode, while the high-side switch is biased off and the low-side switch is biased on, current flows through the low-side switch in a direction opposite to the second direction and through the inductor. configured as During the second operation mode, the low-side switch is configured to conduct a reverse DC current greater than 50 A. During the third operation mode, the relative increase in the on-resistance of the III-N depletion mode transistor with respect to the first operation mode is less than 5%. Half-bridge circuit.

23. The gate electrode of the III-N depletion mode transistor is connected to a conductive substrate. The conductive substrate is electrically connected to the ground terminal of the package. The half-bridge circuit according to claim 22.

24. During the first operation mode, the low-side switch blocks a voltage greater than 600 V. The half-bridge circuit according to claim 23.

25. The high-side switch includes a low-voltage enhancement mode transistor and a high-voltage III-N depletion mode transistor arranged in a cascode configuration. The half-bridge circuit according to claim 24.

26. During the second operation mode, the reverse DC current flows through the parasitic body diode of the enhancement mode transistor and through the device channel of the III-N depletion mode transistor. The half-bridge circuit according to claim 25.

27. During the third operation mode, the reverse DC current flows through the channel of the enhancement mode transistor and through the device channel of the III-N depletion mode transistor. The half-bridge circuit according to claim 26.

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