Solid-state imaging device

Abstract

This solid-state imaging device 100 is provided with: an N-type semiconductor layer 101; an element layer 102 which comprises a photoelectric conversion element and an active element; a wiring layer 103 which performs wiring to the active element; and an element isolation trench 135 which penetrates through the semiconductor layer 101. The element layer 102 comprises a P-type region 112 and an N-type region 113. A first hole accumulation layer 103a is formed on a surface of the semiconductor layer 101, said surface being on the reverse side from the element layer 102. A second hole accumulation layer 130b is formed on portions of the semiconductor layer 101 and the element layer 102, said portions being in contact with the element isolation trench 135. The P-type region 112 of the element layer 102 and the first hole accumulation layer 103a are connected to each other by means of the second hole accumulation layer 130b.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device.

Background Art

[0002] In recent years, many image sensors with significantly improved sensitivity in the infrared region have been proposed. Since silicon has low infrared absorption sensitivity, it is effective to increase the distance that infrared light penetrates the silicon substrate in order to improve the sensitivity. Therefore, many techniques for forming a thick silicon substrate have been proposed.

[0003] On the other hand, as a technique for improving the sensitivity, a back-illuminated image sensor has been proposed. This is an image sensor that allows light to enter from the surface opposite to the surface on which the active elements are formed. According to Patent Document 1 that discloses this, in order to suppress the dark current on the back surface side, a technique of forming a p-type layer on the surface of the back surface and fixing the potential through a deep P-type well from the surface side is disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the thickness of the silicon substrate is increased to improve the infrared sensitivity, it becomes difficult to extend the deep P-type well region to the back surface side. As a result, the potential of the p-type layer on the back surface side cannot be fixed, and the dark current increases.

[0006] In view of the above, the technique of the present disclosure aims to provide an imaging device capable of obtaining good image quality without dark current degradation even when the thickness of the silicon substrate of a back-illuminated image sensor is increased to improve the infrared sensitivity.

Means for Solving the Problems

[0007] The solid-state imaging device of the present disclosure is a solid-state imaging device having a pixel array composed of a plurality of unit pixels. Each unit pixel includes a photoelectric conversion element that generates signal charges by photoelectric conversion, and an active element that converts the signal charges into an electrical signal and outputs it. The solid-state imaging device includes an N-type semiconductor layer, an element layer laminated on the semiconductor layer and including the photoelectric conversion element and the active element, a wiring layer laminated on the element layer and performing wiring for the active element, and an element isolation groove penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole accumulation layer is formed on the surface of the semiconductor layer opposite to the element layer. A second hole accumulation layer is formed at a portion of the semiconductor layer and the element layer in contact with the element isolation groove. The P-type region of the element layer and the first hole accumulation layer are connected by the second hole accumulation layer.

Advantages of the Invention

[0008] According to the solid-state imaging device of the present disclosure, even if the thickness increases, an increase in dark current can be suppressed.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings.

[0011] (First Embodiment) FIG. 1 is a diagram schematically showing a cross section of a main part of an exemplary solid-state imaging device 100 according to a first embodiment of the present disclosure.

[0012] The solid-state imaging device 100 includes an N-type semiconductor layer 101, an element layer 102 laminated thereon and including a photoelectric conversion element and an active element, and a wiring layer 103 laminated further thereon and performing wiring for the active element and the like. In the solid-state imaging device 100, incident light enters from the side of the N-type semiconductor layer 101 opposite to the wiring layer 103 with respect to the element layer 102.

[0013] The N-type semiconductor layer 101 and the element layer 102 are formed using an N-type epitaxial layer formed on an N-type semiconductor substrate (not shown). By forming a P-type region, an N-type region, and an insulating layer in an upper region of the N-type epitaxial layer, the element layer 102 is formed. A region of the N-type epitaxial layer below the element layer 102 becomes the N-type semiconductor layer 101. Note that this is an example, and the method for forming the N-type semiconductor layer 101 and the element layer 102 is not particularly limited.

[0014] More specifically, the element layer 102 is provided by introducing impurities or the like for a P-type well region 110, an N-type well region 111, a P-type layer 112, a photodiode 113 which is an N-type region, a high-concentration N-type layer 115, and a high-concentration P-type layer 116. Further, a groove is formed so as to penetrate the N-type semiconductor layer 101 and remove a part of the element layer 102, and impurities are embedded in the groove, whereby a shallow trench isolation (STI) 114 which is an element isolation groove is provided.

[0015] The photodiode 113 performs photoelectric conversion on incident light and generates signal charges. An active element including the N-type well region 111 and the like converts the signal charges generated by the photodiode 113 into an electric signal and outputs the electric signal. A unit pixel is configured to include such a photodiode 113 and an active element. The unit pixels are arranged in a matrix to form a pixel array. In addition, circuits separated by a P-type well region and an N-type well region are formed in a peripheral portion of the pixel array.

[0016] On the element layer 102, a wiring layer 103 including an element insulating film 120 and a transfer gate 121 formed thereon is formed.

[0017] In addition, for the N-type semiconductor layer 101, a DTI 135 (Deep Trench Isolation), which is an element isolation groove reaching the P-type layer 112 of the element layer 102 from the surface on the side opposite to the element layer 102, is provided. The DTI 135 forms a groove 136 having a depth that penetrates the N-type semiconductor layer 101 and cuts a part of the element layer 102, and is formed by embedding a first insulating film 132 in the groove 136.

[0018] However, before the first insulating film 132 is embedded, a metal oxide film 131 made of hafnium oxide (HfO 2 ) or aluminum oxide (Al 2 O 3 ) is formed so as to cover the side walls and the bottom surface of the groove 136.

[0019] The metal oxide film 131 is formed so as to cover the inside of the groove 136 and the surface of the N-type semiconductor layer 101. Therefore, the first insulating film 132 embeds the inside of the groove 136 via the metal oxide film 131. Also, the first insulating film 132 is formed so as to cover the metal oxide film 131 even outside the groove 136. Further, a second insulating film 133 is formed so as to cover the insulating film 132.

[0020] Negative fixed charges are formed on the side of the metal oxide film 131 facing the N-type semiconductor layer 101 and the element layer 102. As a result, in the N-type semiconductor layer 101 and the element layer 102, holes (positive holes) are supplied from the GND terminal through the P-type well layer 110 to the portion in contact with the metal oxide film 131 and accumulated to form a hole accumulation layer 130 that has become P-type. More specifically, a first hole accumulation layer 130a is formed along the surface of the N-type semiconductor layer 101 on the side opposite to the element layer 102, and a second hole accumulation layer 130b is formed on the bottom surface and side wall portions of the groove 136.

[0021] Also, a via 140 (through-silicon via; TSV) that penetrates the N-type semiconductor layer 101 and the element layer 102 is formed. The via 140 is insulated from the N-type semiconductor layer 101 and the element layer 102 by a second insulating film 133. Further, a copper wiring 122 is connected to the via 140 on the side of the wiring layer 103, and an electrode pad 141 is connected to the via 140 on the side of the N-type semiconductor layer 101.

[0022] In the solid-state imaging device 100 of the present disclosure as described above, the P-type region (such as the P-type layer 112) in the element layer 102 and the first hole accumulation layer 130a, which is a P-type region on the side of the N-type semiconductor layer 101 opposite to the element layer 102, are electrically connected by a second hole accumulation layer 130b formed along the DTI 135. Therefore, even when the thickness of the N-type semiconductor layer 101 increases, holes are supplied through the second hole accumulation layer 130b formed on the sidewall portion of the DTI 135, so that an increase in dark current can be suppressed.

[0023] FIG. 2 shows a comparative example solid-state imaging device 100a in which the DTI 135 in the solid-state imaging device 100 is not formed. In the solid-state imaging device 100a, when the thickness T of the N-type semiconductor layer 101 is sufficiently small, a deep P-type well region can be formed by impurity implantation or the like from the element layer 102 side and extended to the surface (back surface) opposite to the element layer 102. In this case, it is possible to fix the potential of the P-type layer on the back surface side.

[0024] However, when the thickness T of the N-type semiconductor layer 101 is increased to improve the infrared sensitivity, it becomes difficult to form the P-type well region up to the back surface. As a result, the potential of the P-type layer on the back surface side cannot be fixed, and the dark current increases.

[0025] On the other hand, in the solid-state imaging device 100 of the present disclosure shown in FIG. 1, the DTI 135 is formed from the back side, and the hole accumulation layer 130 is formed in a portion in contact with the DTI 135. As a result, even when the N-type semiconductor layer 101 becomes thick, holes can be supplied to the back side through the hole accumulation layer 130. As a result, an increase in dark current can be suppressed, and the quality of the captured image can be improved.

[0026] (Second Embodiment) FIG. 3 shows a schematic cross-sectional view of the solid-state imaging device 100b according to the second embodiment. The solid-state imaging device 100b is the same as the solid-state imaging device 100 of FIG. 1 except that a via portion DTI 135a is formed around the via 140. The via portion DTI 135a has a configuration in which an insulating film is embedded in a groove via a metal oxide film 131, similar to the DTI 135 of the solid-state imaging device 100.

[0027] Further, FIG. 4 shows a schematic planar configuration A of the via 140 and the via portion DTI 135a in the solid-state imaging device 100b as a plan view. As shown here, the via portion DTI 135a is formed so as to surround the via 140.

[0028] The via 140 is formed as a TSV that penetrates the silicon substrate (N-type semiconductor layer 101) in order to form the electrode pad 141 on the side opposite to the element layer 102 in the N-type semiconductor layer 101. A p-n junction is formed on the side surface of the DTI 135, which causes leakage current to occur.

[0029] Therefore, in the solid-state imaging device 100b of the present embodiment, the via portion DTI 135a is formed so as to surround the via 140. As a result, the N-type semiconductor layer 101a around the via 140 is electrically separated, so that the occurrence of leakage current is suppressed.

[0030] Still, the planar configuration B of FIG. 4 shows a modified example of the layout of the via portion DTI135a. In the planar configuration A, the via portion DTI135a is rectangular and has a corner that bends at 90°. In contrast, in the planar configuration B, instead of bending at 90° at the rectangular corner, it has a shape (octagon) that bends twice at an obtuse angle (135° in this example). In this way, by adopting a configuration without a 90° bending portion, the dimensions of the via portion DTI135a can be stabilized, and the embedding characteristics of the first insulating film 132 and the like when forming the via portion DTI135a can be stabilized. Note that the shape of the via portion DTI135a in the plan view is not limited to the illustrated octagon, and other shapes may be used.

[0031] (Third Embodiment) FIG. 5 shows a schematic cross-sectional view of an exemplary solid-state imaging device 100c according to the third embodiment. Comparing the solid-state imaging device 100c with the solid-state imaging device 100 of FIG. 1, vias 140, copper wirings 122 connected thereto, and electrode pads 141 are not formed. Also, a peripheral portion DTI135b having the same structure as DTI135 is formed.

[0032] Further, FIG. 6 shows, as a plan view, a schematic planar configuration C of the peripheral portion DTI135b in the solid-state imaging device 100c and the internal circuit region 151 surrounded by it. In the internal circuit region 151, both an N-type well region and a P-type well region are provided, and a photoelectric conversion element, an active element, and the like are configured.

[0033] In FIG. 5, the left end of the solid-state imaging device 100c is a chip end 150 obtained by dicing (separating) the chip. At the chip end 150, p-n junctions are formed at two locations, between the P-well layer 110 and the N-type semiconductor layer 101, and between the N-type semiconductor layer 101 and the hole induction layer 130a, which also causes leakage current. Therefore, in the solid-state imaging device 100c, at the peripheral portion of the chip, a peripheral DTI 135b is formed along the chip end 150. The peripheral DTI 135b surrounds the inside without a break. As a result, the N-type semiconductor layer 101b near the chip end 150 is electrically separated, so an increase in leakage current can be suppressed.

[0034] As a modification, similar to the via portion DTI 135a shown in the planar configuration B of FIG. 4, the peripheral DTI 135b may also be configured not to have a portion that bends at 90° (a configuration that bends at an obtuse angle, for example, 135°). This is shown in the planar configuration D of FIG. 6. Thereby, the peripheral DTI 135b can be formed stably.

[0035] (Fourth Embodiment) FIG. 7 shows a schematic cross-sectional view of an exemplary solid-state imaging device 100d of the fourth embodiment. Comparing the solid-state imaging device 100d with the solid-state imaging device 100c of FIG. 5, the difference is that an end N-type well region 117 is provided in the element layer 102 near the chip end 150. The end N-type well region 117 reaches the N-type semiconductor layer 101. By doing so, the p-n junction formed at the chip end 150 (the diced surface) becomes only one location between the N-type semiconductor layer 101 and the hole induction layer 130a and decreases, so the generation of leakage current can be further suppressed.

[0036] FIG. 8 shows, as a plan view, an end N-type well region 117 formed near the chip end 150, a P-type well region 110 provided inside thereof, a peripheral DTI 135b provided in the P-type well region 110 along the chip end 150, and an internal circuit region 151 provided inside the peripheral DTI 135b. Further, as a modification, similar to the case of the planar configuration B in FIG. 4, the peripheral DTI 135b may be formed to bend at an obtuse angle (here, 135°). This is shown as the planar configuration F in FIG. 8.

[0037] Furthermore, the configuration of providing an N-type well region so as to reach the N-type semiconductor layer 101 with respect to the element layer 102 to reduce the p-n junction can be applied not only near the chip end 150. For example, an N-type well region as described above may be provided around the via 140 shown in FIG. 3 (illustration is omitted). Thereby, the p-n junction can be reduced around the via 140, and the leakage current can be suppressed.

[0038] (Fifth Embodiment) FIG. 9 shows a schematic plan view of an exemplary solid-state imaging device 100e according to the fifth embodiment. FIG. 9 shows the entire chip of the solid-state imaging device 100e.

[0039] In FIG. 9, a P-type well region 110, an N-type well region 111, and a via 140 are provided. Further, as described in the second embodiment (FIGS. 3 and 4), a via 140 and a via portion DTI 135a surrounding the same are provided. Thereby, the leakage current is reduced around the via 140. Further, as described in the third embodiment (FIGS. 5 and 6), a peripheral DTI 135b is provided along the chip end 150. Thereby, the leakage current is reduced near the chip end 150.

[0040] In the solid-state imaging device 100e, a pixel array 152 in which a plurality of unit pixels are arranged in a matrix is provided on the central side of the chip. An annular array portion DTI 135c is formed so as to surround the pixel array 152. The array portion DTI 135c has the same structure as the DTI 135 shown in FIG. 1.

[0041] Using the P-type well region 110 and the array part DTI135c, it is possible to electrically isolate the inside of the pixel array 152 from the peripheral part. As a result, it is possible to suppress the influence of the noise of the peripheral circuit on the pixel array 152 and the like.

[0042] (Sixth Embodiment) Next, as a sixth embodiment, a method for manufacturing a solid-state imaging device will be described. In particular, the manufacturing method of the DTI135 will be described in detail. FIGS. 10 to 17 are diagrams for explaining the manufacturing method of the solid-state imaging device of the present disclosure. In these figures, the solid-state imaging device is shown upside down compared to FIG. 1 and the like.

[0043] FIG. 10 shows a stage before forming the DTI135. To obtain this structure, first, an N-type epitaxial layer is formed on an N-type semiconductor substrate. For the upper region of the epitaxial layer, means such as impurity implantation are used to form a P-type well region 110, an N-type well region 111, a P-type layer 112, an N-type photodiode 113, and the like. Also, the STI114 is formed. Thereby, a pixel array 152 including a photoelectric conversion element and an active element is formed, and the epitaxial layer becomes the element layer 102. Among the N-type epitaxial layers, the region below the element layer 102 becomes the N-type semiconductor layer 101.

[0044] Subsequently, a wiring layer 103 in which a plurality of wirings 161 are embedded in an insulating layer 162 is formed on the element layer 102. Further, another wafer is attached as a support substrate 160 on the wiring layer 103. Next, the thickness of the N-type semiconductor substrate initially used is thinned and removed. If necessary, the N-type semiconductor layer 101 may also be thinned to a predetermined thickness. FIG. 10 shows this state with the support substrate 160 facing down.

[0045] Next, perform the process of FIG. 11. Here, a groove 136 for forming the DTI 135 is formed. The groove 136 is formed so as to penetrate the N-type semiconductor layer 101 and cut a part of the element layer 102. For example, a mask with an opening at a predetermined position may be created by lithography technology, and the groove 136 may be formed by etching to a required depth.

[0046] Next, perform the process of FIG. 12. Here, a metal oxide film 131 is formed so as to cover the bottom and side walls of the groove 136 and also cover the upper surface of the N-type semiconductor layer 101 (the surface opposite to the element layer 102). At this time, a space is left without completely filling the groove 136. Specifically, the metal oxide film 131 is 2 a film of HfO 2 or Al 3 oxide film, and is formed by a method such as CVD (Chemical Vapor Deposition).

[0047] When the metal oxide film 131 is formed, holes are induced and accumulated at the portions of the N-type semiconductor layer 101 and the element layer 102 that are in contact with the metal oxide film 131, and a P-type hole accumulation layer 130 is formed. Therefore, the metal oxide film 131 covers the inside of the groove 136 and the upper surface of the N-type semiconductor layer 101 via the hole accumulation layer 130.

[0048] Next, the process of FIG. 13 will be described. Here, a first insulating film 132 is formed so as to fill the space left in the groove 136 and also cover the metal oxide film 131 outside the groove 136. For example, an oxide film may be used as a material and formed by a method such as CVD. Thus, it means that the DTI 135 has been formed.

[0049] Next, the process of FIG. 14 will be described. Here, a through hole 140a for forming a via 140 is formed. The through hole 140a penetrates the N-type semiconductor layer 101 and the element layer 102, and partially removes the first insulating film 132 and the insulating layer 162 of the wiring layer 103 so as to reach the wiring 161. For this purpose, for example, etching or the like may be performed. The wiring 161 reached by the through hole 140a corresponds to the copper wiring 122 in FIG. 1.

[0050] Furthermore, a second insulating film 133 is formed so as to cover the first insulating film 132 outside the through hole 140a together with the tail covering the side wall and the bottom surface of the through hole 140a. Thereafter, at the bottom of the through hole 140a, a part of the second insulating film 133 is removed to expose the wiring 161.

[0051] Next, the process of FIG. 15 will be described. Here, in order to form a via 140, a copper layer 140b is formed so as to fill the through hole 140a. The copper layer 140b is formed so as to cover the second insulating film also outside the through hole 140a. For the formation of the copper layer 140b, for example, an electroplating method may be used.

[0052] Next, the process of FIG. 16 will be described. Here, the copper layer 140b in the portion outside the through hole 140a is removed. For this purpose, for example, a CMP method (Chemical Mechanical Polishing) may be used. As a result, a via 140 in which the through hole 140a is filled with the copper layer 140b via the second insulating film 133 is formed.

[0053] Next, the process of FIG. 17 will be described. Here, an electrode pad 141 connected to the via 140 is formed on the N-type semiconductor layer 101 side. The electrode pad 141 may be formed of, for example, aluminum.

[0054] Thus, the solid-state imaging device of the present disclosure is manufactured. Note that the materials, manufacturing methods, shapes, etc. described above are all examples, and the technology of the present disclosure is not limited thereto.

Industrial Applicability

[0055] According to the solid-state imaging device of the present disclosure, even when the semiconductor layer is thickened, an increase in dark current can be suppressed, so it is useful as a solid-state imaging device with improved infrared sensitivity and the like.

Explanation of symbols

[0056] 100 Solid-state imaging device 100a~100e Solid-state imaging device 101 N-type semiconductor layer 101a N-type semiconductor layer 101b N-type semiconductor layer 102 Element layer 103 Wiring layer 110 P-type well region 111 N-type well region 112 P-type layer 113 Photodiode 114 STI 115 High-concentration N-type layer 116 High-concentration P-type layer 117 End N-well region 120 Insulating film on element 121 Electrode 122 Copper wiring 130 Hole accumulation layer 130a First hole accumulation layer 130b Second hole accumulation layer 131 Metal oxide film 132 First insulating film 133 Second insulating film 135 DTI 135a Via part DTI 135b Peripheral part DTI 135c Array part DTI 136 Groove 140 Via 140a Through hole 140b Copper layer 141 Electrode pad 150 Chip end 151 Internal circuit region 152 Pixel array 160 Support substrate 161 Wiring 162 Insulating layer

Claims

1. A solid-state imaging device having a pixel array composed of a plurality of unit pixels, each of said unit pixels including a photoelectric conversion element that generates signal charges by photoelectric conversion, and an active element that converts said signal charges into an electrical signal and outputs the same, an N-type semiconductor layer, an element layer laminated on said semiconductor layer and including said photoelectric conversion element and said active element, a wiring layer laminated on said element layer and performing wiring for said active element, and an element isolation groove penetrating said semiconductor layer, said element layer including a P-type region and an N-type region, a first hole accumulation layer being formed on a surface of said semiconductor layer opposite to said element layer, a second hole accumulation layer being formed at a portion of said semiconductor layer and said element layer in contact with said element isolation groove, said P-type region of said element layer and said first hole accumulation layer being connected by said second hole accumulation layer, an electrode pad formed on a surface of said semiconductor layer opposite to said element layer, and a via penetrating said semiconductor layer and connecting said electrode pad and said wiring layer, the element layer around said via being a P-type region, said element isolation groove including a via portion element isolation groove formed so as to surround said via, and another element isolation groove in contact with said P-type region adjacent to said photoelectric conversion element, said via portion element isolation groove being formed beyond a p-n junction between said P-type region of said element layer and said semiconductor layer, characterized in that it is a solid-state imaging device.

2. In claim 1, On the surface of the semiconductor layer opposite to the element layer, an HfO formed via the first hole accumulation layer ２ film or Al ２ O ３ film and, On the surface of the element isolation groove, HfO formed via the second hole accumulation layer ２ film or Al ２ O ３ film, and further comprising a solid-state imaging device characterized by the above.

3. In claim 1, In a plan view, said via portion element isolation groove surrounds said via in a polygonal shape having an obtuse angle, characterized in that it is a solid-state imaging device.

4. A solid-state imaging device having a pixel array composed of a plurality of unit pixels, each of said unit pixels including a photoelectric conversion element that generates signal charges by photoelectric conversion, and an active element that converts said signal charges into an electrical signal and outputs the same, an N-type semiconductor layer, an element layer laminated on said semiconductor layer and including said photoelectric conversion element and said active element, a wiring layer laminated on said element layer and performing wiring for said active element, and an element isolation groove penetrating said semiconductor layer, said element layer including a P-type region and an N-type region, a first hole accumulation layer being formed on a surface of said semiconductor layer opposite to said element layer, a second hole accumulation layer being formed at a portion of said semiconductor layer and said element layer in contact with said element isolation groove, The P-type region of the element layer and the first hole accumulation layer are connected by the second hole accumulation layer. The solid-state imaging device is formed as a semiconductor chip. The element isolation groove includes a peripheral element isolation groove continuously formed along the outer peripheral end at the peripheral portion of the semiconductor chip, and another element isolation groove in contact with the P-type region adjacent to the photoelectric conversion element. At the peripheral portion of the semiconductor chip, the element layer is a P-type region. The solid-state imaging device is characterized in that the peripheral element isolation groove is formed beyond the p-n junction between the P-type region of the element layer and the semiconductor layer.

5. In claim 4, In a plan view, the solid-state imaging device is characterized in that the peripheral element isolation groove has a polygonal shape formed by obtuse angles.

6. A solid-state imaging device having a pixel array composed of a plurality of unit pixels, Each of the unit pixels includes a photoelectric conversion element that generates signal charges by photoelectric conversion, and an active element that converts the signal charges into an electrical signal and outputs the electrical signal. An N-type semiconductor layer, An element layer laminated on the semiconductor layer and including the photoelectric conversion element and the active element, A wiring layer laminated on the element layer and performing wiring for the active element, An element isolation groove penetrating the semiconductor layer, The element layer includes a P-type region and an N-type region. A first hole accumulation layer is formed on the surface of the semiconductor layer opposite to the element layer. A second hole accumulation layer is formed at a portion of the semiconductor layer and the element layer in contact with the element isolation groove. The P-type region of the element layer and the first hole accumulation layer are connected by the second hole accumulation layer. A P-type well region is formed in the element layer at the periphery of the pixel array. The element isolation groove is formed in the P-type well region and includes a pixel array portion element isolation groove surrounding the pixel array and another element isolation groove in contact with the P-type region adjacent to the photoelectric conversion element. The solid-state imaging device is characterized in that the pixel array portion element isolation groove is formed beyond the p-n junction between the P-type region of the element layer and the semiconductor layer.

7. In claim 6, In a plan view, the solid-state imaging device is characterized in that the pixel array portion element isolation groove surrounds the pixel array in a polygonal shape formed by obtuse angles.

8. In claim 4 or 6, On the surface of the semiconductor layer opposite to the element layer, an HfO₂ film or an Al₂O₃ film formed via the first hole accumulation layer, and A solid-state imaging device, further comprising an HfO₂ film or an Al₂O₃ film formed via the second hole accumulation layer on the surface of the element isolation groove.

Images