Double-stack semiconductor light-emitting device and method for manufacturing double-stack semiconductor light-emitting device

Abstract

Provided is a double-stack semiconductor light-emitting device having good output characteristics and capable of improving reverse voltage characteristics (reducing leakage current). 【Solution means】A double-stack semiconductor light-emitting device 100 including, in this order, a first n-type semiconductor layer 140, an undoped first active layer 144, a p-type pseudo tunnel junction layer 1471 having a p-type dopant, an n-type pseudo tunnel junction layer 1472 having an n-type dopant provided in contact with the p-type pseudo tunnel junction layer 1471, an undoped second active layer 149, and a second p-type semiconductor layer 150, wherein the maximum value of the impurity concentration of the n-type dopant included on the n-type pseudo tunnel junction layer 1472 side of the second active layer 149 is 1.0×10 16 atoms / cm 3 or less.

Description

Technical Field

[0001] The present invention relates to a double-stack semiconductor light-emitting device and a method for manufacturing the double-stack semiconductor light-emitting device.

Background Art

[0002] Conventionally, in order to increase the output of a semiconductor light-emitting device, a double-stack semiconductor light-emitting device that increases the output by fabricating two or more light-emitting layers and arranging them perpendicular to each other has been known. Such a double-stack semiconductor light-emitting device has a tunnel junction layer doped with a high concentration of dopant between each of two or more vertically arranged light-emitting layers.

[0003] For example, Patent Document 1 discloses an LED semiconductor in which a first active layer and a second active layer are arranged so as to overlap each other vertically, and a tunnel junction is formed between the first active layer and the second active layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the double-stack type LED semiconductor described in Patent Document 1 has hardly been put into practical use. As a result of investigations by the present inventors, in reality, even when two light-emitting layers are arranged, the light-emitting output is only about 1.3 to 1.45 times that in the case of a single light-emitting layer when the current is 100 mA. Therefore, in fact, it is more efficient to use a plurality of single-stack type LEDs each having one light-emitting layer than to use a double-stack type LED. In addition, further reduction of leakage current and increase of reverse voltage have also been required as element characteristics.

[0006] Therefore, an object of the present invention is to provide a double-stack type semiconductor light-emitting device having good output characteristics and capable of reducing leakage current and increasing reverse voltage, and a method for manufacturing the same.

Means for Solving the Problems

[0007] The inventors of the present invention have intensively studied ways to solve the above problems. The inventors of the present invention considered that the reason why the light emission output of the double-stack type LED can only be about 1.3 to 1.45 times as described above is that the dopants contained in the layer for forming the tunnel junction (the layer in which the dopant is highly doped) have an unintended adverse effect. As a result of measuring the diffusion behavior of the dopant, it was clarified that the dopant doped in the n-type tunnel junction layer diffused into the second active layer, causing a decrease in output. The inventors of the present invention usually focused on the n-type dopant concentration of the active layer on the side where the n-type tunnel layer is provided, and experimentally confirmed the conditions under which the output characteristics and reverse voltage characteristics can be improved. That is, the gist configuration of the present invention is as follows.

[0008] (1) A first n-type semiconductor layer, An undoped first active layer, A p-type pseudo tunnel junction layer having a p-type dopant, An n-type pseudo tunnel junction layer having an n-type dopant provided in contact with the p-type pseudo tunnel junction layer, An undoped second active layer, A second p-type semiconductor layer, are provided in this order, The maximum value of the impurity concentration of the n-type dopant contained on the n-type pseudo tunnel junction layer side of the second active layer is 1.0×10 16 atoms / cm 3 or less, characterized in that Double-stack type semiconductor light-emitting device.

[0009] (2) Between the n-type pseudo tunnel junction layer and the second active layer, the Si impurity concentration is 5.0×10 17 atoms / cm 3 or more and 5.0×1018 atoms / cm 3 having a second n-type semiconductor layer as follows, The double-stack semiconductor light-emitting device according to (1) above.

[0010] (3) The average impurity concentration of the n-type dopant contained in the first active layer and the second active layer is 5.0×10 15 atoms / cm 3 or less. The double-stack semiconductor light-emitting device according to (1) or (2) above.

[0011] (4) The n-type dopant doped in the n-type pseudo tunnel junction layer is Si. The double-stack semiconductor light-emitting device according to any one of (1) to (3) above.

[0012] (5) The p-type dopant doped in the p-type pseudo tunnel junction layer is C. The double-stack semiconductor light-emitting device according to any one of (1) to (4) above.

[0013] (6) The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer is 1.5×10 19 atoms / cm 3 or more. The double-stack semiconductor light-emitting device according to any one of (1) to (5) above.

[0014] (7) The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer is 1.0×10 19 atoms / cm 3 or more. The double-stack semiconductor light-emitting device according to any one of (1) to (6) above.

[0015] (8) The first active layer and the second active layer, and the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer contain AlGaInAs or InGaAsP. The double-stack type semiconductor light-emitting device according to any one of (1) to (7) above.

[0016] (9) When the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer are energized without passing through the first active layer and the second active layer, in the current-voltage curve, the point where the current becomes maximum is in the range of 0.02 V or more and 0.2 V or less. The double-stack type semiconductor light-emitting device according to any one of (1) to (8) above.

[0017] (10) When the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer are energized without passing through the first active layer and the second active layer, in the current-voltage curve, the maximum value of the current is 7 mA or less. The double-stack type semiconductor light-emitting device according to any one of (1) to (9) above.

[0018] (11) A step of forming a first n-type semiconductor layer on a substrate; A step of forming an undoped first active layer on the first n-type semiconductor layer; A step of forming a p-type pseudo tunnel junction layer having a p-type dopant on the first active layer; A step of directly forming an n-type pseudo tunnel junction layer having an n-type dopant on the p-type pseudo tunnel junction layer; A step of forming an undoped second active layer on the n-type pseudo tunnel junction layer; A step of forming a second p-type semiconductor layer on the second active layer; Comprising, The maximum value of the impurity concentration of the n-type dopant contained on the n-type pseudo tunnel junction layer side of the second active layer is 1.0×10 16 atoms / cm 3 or less. A method for manufacturing a double-stack type semiconductor light-emitting device.

[0019] (12) A support substrate, A bonding layer provided on the support substrate, An intermediate electrode layer in which a dielectric part and an electrode part provided on the bonding layer are in parallel, A second p-type semiconductor layer provided on the intermediate electrode layer, An undoped second active layer provided on the second p-type semiconductor layer, An n-type pseudo tunnel junction layer having an n-type dopant provided on the second active layer, A p-type pseudo tunnel layer having a p-type dopant provided in contact with the n-type pseudo tunnel junction layer, An undoped first active layer provided on the p-type pseudo tunnel layer, A first n-type semiconductor layer provided on the first active layer, An upper electrode provided on the first n-type semiconductor layer, and comprising The maximum value of the impurity concentration of the n-type dopant contained on the n-type pseudo tunnel junction layer side of the second active layer is 1.0×10 16 atoms / cm 3 or less A double stack type semiconductor light emitting device.

Advantages of the Invention

[0020] According to the present invention, it is possible to provide a double stack type semiconductor light emitting device having good output characteristics and capable of reducing leakage current and increasing reverse voltage, and a method for manufacturing the same.

Brief Description of the Drawings

[0021]

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Embodiments for Carrying Out the Invention

[0022] In this specification, a layer that electrically functions as a p-type is referred to as a p-type semiconductor layer (which may be abbreviated as "p-type layer"), and a layer that electrically functions as an n-type is referred to as an n-type semiconductor layer (which may be abbreviated as "n-type layer"). On the other hand, when specific impurities such as Si, Te, Zn, S, and C are not intentionally added, it is called "i-type" or "undoped". In this III-V compound semiconductor layer, unavoidable impurity incorporation during the manufacturing process may be allowed. In the present invention, it has at least an undoped first active layer and an undoped second active layer, and each active layer is formed as an undoped layer without flowing a dopant gas during formation, but there may be an influence of dopant diffusion from other layers (for example, a tunnel junction layer or a pseudo tunnel junction layer). In the present invention, although impurities are not intentionally added during layer growth, it is a case where an influence due to diffusion of impurities contained in other layers is observed during the manufacturing process, and if impurities with a concentration exceeding 1×10 16 / cm 3 are not observed, the active layer is treated as "undoped".

[0023] Generally, the "tunnel junction layer" refers to a layer having a current-voltage curve with a negative resistance region in which, as shown by the curve of Comparative Example 1 in FIG. 9, after showing a behavior in which the forward current increases as the forward voltage increases from 0 V, the forward current decreases as the forward voltage increases. The forward current flowing before the negative resistance region is called the tunnel current. In this specification, the "pseudo tunnel junction layer" refers to a layer having a negative resistance region in the current-voltage curve, but having a tunnel current close to zero (for example, 10 mA or less), as shown by the curves of Examples 1 to 3 in FIG. 9. Although it has a region showing negative resistance in terms of numerical values, at first glance, it has the same curve as the current-voltage curve of a normal pn junction diode except for having a negative resistance region. Generally, in an element using a tunnel junction structure, it has been considered that a large tunnel current needs to flow as in Comparative Example 1 in FIG. 9. Therefore, the inventors also initially thought that the behavior as in the examples of FIG. 9 could not be used as a tunnel junction layer because the tunnel current was weak. However, when actually used in the double-stack type semiconductor light-emitting element of the present invention, for some unknown reason, it was confirmed that energization occurred and a higher light emission output, a lower leakage current, and a higher reverse voltage than the tunnel junction layer as in Comparative Example 1 were obtained. For example, in the "pseudo tunnel junction layer", it is preferable that the starting point (the maximum point of the current) of the negative resistance region is in the range of 0.02 V or more and 0.2 V, and it is preferable that the maximum tunnel current (the maximum value of the current) at the maximum point of the current is 7 mA or less. And the p-type layer and the n-type layer in contact within the "pseudo tunnel junction layer" are respectively referred to as the "p-type pseudo tunnel junction layer" and the "n-type pseudo tunnel junction layer".

[0024] In this specification, the impurity concentrations of the n-type and p-type dopants were measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry, CAMECA IMS-4f manufactured by AMTEC). The analysis conditions were that the primary species was Cs+, the primary energy was 14.5 keV, and the secondary polarity was negative. The SIMS value of each layer is the average value excluding the end portion (width 5 nm) when the film thickness is thicker than 40 nm, and the maximum value (peak value) of the SIMS of the corresponding layer when the film thickness is 40 nm or less.

[0025] In this specification, the side of the second active layer on the n-type pseudo tunnel junction layer side refers to the region from the center in the thickness direction of the second active layer to the boundary with another layer in contact with the n-type pseudo tunnel junction layer side of the second active layer. For example, it is a barrier layer located at the end on the n-type pseudo tunnel junction layer side of the second active layer. In this region, the maximum value of the impurity concentration of the n-type dopant often appears at the boundary between the second active layer and another layer in contact with the n-type pseudo tunnel junction layer side of the second active layer.

[0026] Each semiconductor layer can be formed by epitaxial growth. For example, it can be formed by a known thin film growth method such as the metal organic chemical vapor deposition (MOCVD) method or the molecular beam epitaxy (MBE) method. For example, trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, arsine (AsH 3 ) or tertiarybutylarsine (TBAs) as an As source, phosphine (PH 3 ) or tertiarybutylphosphine (TBP) as a P source are used at a predetermined mixing ratio, and these source gases are vapor-grown while using a carrier gas, so that they can be formed with a desired thickness according to the growth time. When doping each layer into p-type or n-type, a gas of a dopant source according to desire may be further used. For example, when doping with Si, Si 2 H 6 gas or the like can be used, and when doping with C, CBr 4 gas or the like can be used.

[0027] (First Embodiment) Referring to FIG. 1, a double-stack type semiconductor light-emitting device and a method of manufacturing the double-stack type semiconductor light-emitting device according to the first embodiment will be described. In the double-stack type semiconductor light-emitting device 100, a plurality of active layers are stacked in the vertical direction, and between these active layers, a pseudo tunnel junction layer through which current flows in a direction opposite to the direction of the conductivity type (e.g., from p-type to n-type) before and after the active layer (e.g., from n-type to p-type) due to a pseudo tunnel effect is sandwiched, and it functions as a so-called double-stack type light-emitting diode. For example, in the case where there are two active layers which is the embodiment of the minimum configuration, the first active layer and the second active layer are arranged to overlap each other in the vertical direction. Then, the active layer closer to the p-type pseudo tunnel junction layer 1471 included in the pseudo tunnel junction layer 147 is defined as the first active layer 144, and the active layer closer to the n-type pseudo tunnel junction layer 1472 included in the pseudo tunnel junction layer 147 is defined as the second active layer 149. Note that the semiconductor light-emitting device is preferably a light-emitting diode (LED), and it is preferable that the first active layer and the second active layer emit incoherent light in each layer. Each active layer may be formed as a single quantum well structure (SQW) or a multiple quantum well structure (MQW), or a quantum wire structure or a quantum dot structure. Even when the number of active layers is three or more, each active layer is arranged to overlap each other in the vertical direction, and any two adjacent active layers among the plurality of active layers are regarded as the first active layer 144 and the second active layer 149, and if the first active layer 144, the pseudo tunnel junction layer 147, and the second active layer 149 satisfy the present invention, it is the double-stack type semiconductor light-emitting device 100 of the present invention.

[0028] The manufacturing method of the double-stack type semiconductor light-emitting device 100 according to the first embodiment includes at least a step of forming a first n-type semiconductor layer 140, a step of forming an undoped first active layer 144 on the first n-type semiconductor layer 140, a step of forming a p-type pseudo tunnel junction layer 1471 having a p-type dopant on the first active layer 144, a step of directly forming an n-type pseudo tunnel junction layer 1472 having an n-type dopant on the p-type pseudo tunnel junction layer 1471, a step of forming a second active layer 149 on the n-type pseudo tunnel junction layer 1472, and a step of forming a second p-type semiconductor layer 150 on the second active layer 149. All the semiconductor layers constituting the first n-type semiconductor layer 140 to the second p-type semiconductor layer 150 are collectively referred to as a semiconductor laminate 120. Also, the maximum value of the impurity concentration of the n-type dopant derived from the n-type pseudo tunnel junction layer 1472, which is included on the n-type pseudo tunnel junction layer 1472 side of the second active layer 149, is 1.0×10 16 atoms / cm 3 or less. The impurity concentration of this n-type dopant is more preferably 7.0×10 15 atoms / cm 3 or less, and even more preferably 5.0×10 15 atoms / cm 3 or less.

[0029] A first electron blocking layer 145 and / or a first p-type semiconductor layer 146 may be provided between the first active layer 144 and the p-type pseudo tunnel junction layer 1471. A second n-type semiconductor layer 148 may be provided between the n-type pseudo tunnel junction layer 1472 and the second active layer 149. And a second electron blocking layer 151 may be provided between the second active layer 149 and the second p-type semiconductor layer 150. Also, an undoped spacer layer may be provided between the undoped layer and the layer made p-type or n-type by doping. Hereinafter, the details of each step will be described.

[0030] First, prepare a growth substrate 105. As the growth substrate 105, substrates of compound semiconductors such as GaAs, InP, InAs, GaSb, and InSb can be used. From the perspective of cost, it is preferable to use a GaAs substrate. The growth substrate 105 preferably has the same conductivity type as the layer that is first grown thereon. For example, the growth substrate is preferably an S-doped n-type InP substrate, and the first n-type semiconductor layer 140 is preferably laminated on the (100) surface of the n-type InP substrate. Also, the thickness of the growth substrate 105 is preferably 200 μm or more and 900 μm or less.

[0031] <Formation step of the first n-type semiconductor layer> Form the first n-type semiconductor layer 140 on the growth substrate 105. The first n-type semiconductor layer 140 may be a single layer or may be composed of a plurality of different layers. In FIG. 1, as the layers constituting the first n-type semiconductor layer 140, an n-type contact layer 141 and a first n-type cladding layer 142 are shown. The n-type contact layer 141 can be, for example, an n-type InGaAs layer, and its thickness is preferably 2 nm or more and 200 nm or less, and more preferably 5 nm or more and 20 nm or less. The first n-type cladding layer can be, for example, an n-type InP layer, and its thickness is preferably 500 nm or more and 8000 nm or less, and more preferably 3150 nm or more and 3750 nm or less. Examples of the n-type dopant used for the n-type contact layer 141 and the first n-type cladding layer 142 include Si, S, etc. Also, a buffer layer may be provided between the growth substrate 105 and the n-type semiconductor layer 140.

[0032] Although not shown, a spacer layer may be provided between the first n-type semiconductor layer 140 and the undoped first active layer 144 formed thereon. When the spacer layer is in contact with a layer containing an n-type dopant, the thickness of the spacer layer is preferably 10 nm or more and 200 nm or less, and more preferably 70 nm or more and 130 nm or less. The spacer layer preferably has the same composition as the adjacent layer and is a layer not doped with a dopant. This spacer layer reduces the amount of impurity diffusion from the doped layer to the undoped layer, for example, reduces the amount of n-type dopant diffusing from the first n-type cladding layer 142 to the first active layer 144.

[0033] <Formation Step of the First Active Layer> An undoped first active layer 144 is formed on the first n-type semiconductor layer 140. The first active layer 144 preferably contains AlGaInAs or InGaAsP. In FIG. 1, a quantum well structure in which the well layer of the first active layer is the well layer 144w and the barrier layer is the barrier layer 144b is exemplarily shown, but the first active layer 144 may have a single-layer structure. The well layer 144w and the barrier layer 144b may be different layers, or a strain may be applied to the well layer 144w by adjusting the composition difference. Further, the first active layer 144 may be formed using, for example, InGaAlAs layers having different composition ratios. The first active layer 144 preferably has a multiple quantum well (MQW) structure as shown in FIG. 1 for improving the light output by suppressing crystal defects. This multiple quantum well structure can be formed by alternately repeating the above well layer 144w and barrier layer 144b. When using a multiple quantum well structure, the combination of the well layer 144w and the barrier layer 144b is preferably 3 or more and 40 or less. That is, including the first barrier layer, it is preferably 3.5 or more and 40.5 or less. Further, the film thickness of each well layer is preferably 5 nm or more and 40 nm or less, and the film thickness of each barrier layer is preferably 10 nm or more and 50 nm or less. Also, the first active layer 144 may have a wavelength range with an emission center wavelength of 1200 nm or more.

[0034] A first electron blocking layer 145 may be provided on the first active layer 144. The first electron blocking layer 145 may be undoped or p-type, but is preferably undoped. The first electron blocking layer may be a single layer or may be composed of a plurality of layers. The thickness of the first electron blocking layer 145 is preferably 2 nm or more and 200 nm or less, and more preferably 5 nm or more and 30 nm or less. This first electron blocking layer 145 is a layer that injects and confines carriers into the first active layer 144. Further, the first electron blocking layer 145 also has an effect of reducing the diffusion of p-type dopants from the pseudo tunnel junction layer 147 described later to the first active layer 144.

[0035] Although not shown, a spacer layer may be provided between the undoped first electron blocking layer 145 and the first p-type semiconductor layer 146 formed thereon. When the spacer layer is in contact with a layer containing a p-type dopant, the thickness thereof is preferably 40 nm or more and 400 nm or less, and more preferably 170 nm or more and 330 nm or less.

[0036] <Formation step of the first p-type semiconductor layer> It is preferable to provide a first p-type semiconductor layer 146 between the first active layer 144 and the p-type pseudo tunnel junction layer 1471. The first p-type semiconductor layer 146 may have, for example, a first p-type cladding layer. The composition of the first p-type cladding layer preferably has a smaller bandgap than the composition of the first electron blocking layer 145, and examples thereof include InGaAsP or InP. The p-type dopant concentration of the first p-type semiconductor layer 146 is 5.0×10 17 atoms / cm 3 or more and 5.0×10 18 atoms / cm 3 or less. The first p-type semiconductor layer 146 may include layers other than the first p-type cladding layer, and may have, for example, an InAlAs layer or an AlInGaAs layer in which the group V element is different from that of the first p-type cladding layer.

[0037] <Formation steps of the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer> On the first p-type semiconductor layer 146, a pseudo tunnel junction layer 147 is formed in which an n-type pseudo tunnel junction layer 1472 is directly laminated on a p-type pseudo tunnel junction layer 1471. The p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 are preferably made of AlGaInAs or InGaAsP. Examples of dopants that can be used for the p-type pseudo tunnel junction layer 1471 include Mg, Zn, C, Be, etc., but it is preferable to use C. By using C as the dopant for the p-type pseudo tunnel junction layer 1471, the dopant diffusion phenomenon to adjacent epitaxial layers during growth can be suppressed as compared with other dopants. Examples of dopants that can be used for the n-type pseudo tunnel junction layer 1472 include Si, Te, S, Ge, Sn, Se, etc., but it is preferable to use Si. By using Si as the dopant for the n-type pseudo tunnel junction layer 1472, the amount of dopant doped in the n-type pseudo tunnel junction layer 1472 diffusing into the second active layer 149 described later can be suppressed. The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer 1471 is preferably 19 atoms / cm 3 or more, more preferably 19 atoms / cm 3 or more, and even more preferably 19 atoms / cm 3 or more. Also, the impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is preferably 19 atoms / cm 3 or more, more preferably 19 atoms / cm 3 or more, and even more preferably 19 atoms / cm 3More preferably, the above conditions are satisfied. The thicknesses and impurity concentrations of the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 may be the same or different. Further, the impurity concentrations of the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 do not have to be uniform within the layers, and a concentration gradient may be present. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is more preferably 19 atoms / cm 3 or less.

[0038] Also, a p-type intermediate layer may be provided between the first p-type semiconductor layer 146 and the p-type pseudo tunnel junction layer 1471. The p-type intermediate layer is a layer made of a layer having a different group V element from the p-type pseudo tunnel junction layer 1471. For example, if the p-type pseudo tunnel junction layer 1471 is made of AlInGaAs, the p-type intermediate layer is made of InGaAsP. The p-type intermediate layer preferably has an impurity concentration higher than that of the first p-type cladding layer and an impurity concentration equal to or lower than that of the p-type pseudo tunnel junction layer 1471. Similarly, an n-type intermediate layer may be provided between the n-type pseudo tunnel junction layer 1472 and the second n-type semiconductor layer 148. The n-type intermediate layer is a layer made of a layer having a different group V element from the n-type pseudo tunnel junction layer 1472. For example, if the n-type pseudo tunnel junction layer 1472 is made of AlInGaAs, the n-type intermediate layer is made of InGaAsP. The n-type intermediate layer preferably has an impurity concentration higher than that of the second n-type cladding layer and an impurity concentration equal to or lower than that of the n-type pseudo tunnel junction layer 1472.

[0039] Generally, for the formation of the tunnel junction layer, the doping rate into the semiconductor needs to be extremely high so that the depletion layer formed at the junction surface between the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 becomes thin enough for quantum tunneling to occur. In the present embodiment, the thickness of the p-type pseudo tunnel junction layer 1471 is preferably 10 nm or more and 60 nm or less, more preferably 20 nm or more and 50 nm or less, and even more preferably 30 nm or more and 40 nm or less. Further, the thickness of the n-type pseudo tunnel junction layer 1472 is preferably 5 nm or more and 30 nm or less, more preferably 10 nm or more and 25 nm or less, and even more preferably 15 nm or more and 20 nm or less.

[0040] The inventors of the present invention particularly focused on the doping concentration of the Si dopant in the n-type pseudo tunnel junction layer 1472. By optimizing various growth conditions, it becomes possible to dope the n-type pseudo tunnel junction layer 1472 with a high concentration of Si. Since Si atoms have the property of being less likely to diffuse into the second active layer 149 compared to other dopants (for example, Te), the light emission efficiency of the second active layer 149 is improved, and the output characteristics of the double-stack type semiconductor light-emitting device 100 as a whole are also improved.

[0041] A Si-doped second n-type semiconductor layer 148 may be formed on the pseudo tunnel junction layer 147. The Si impurity concentration of the second n-type semiconductor layer 148 is 1.0×10 17 atoms / cm 3 or more and 5.0×10 18 atoms / cm 3 or less, preferably 3.0×10 17 atoms / cm 3 or more and 3.0×10 18 atoms / cm 3 or less, more preferably 5.0×10 17 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3The following are more preferable. The thickness of the second n-type semiconductor layer 148 is preferably 100 nm or more and 2000 nm or less, and more preferably 300 nm or more and 600 nm or less. Also, a layer other than the second n-type semiconductor layer 148 may be included between the second active layer 149 and the pseudo tunnel junction layer 147, which will be described later, and a spacer layer may be provided between the second n-type semiconductor layer 148 and the undoped second active layer 149.

[0042] The thickness of the spacer layer formed between the second n-type semiconductor layer 148 and the undoped second active layer 149 is preferably 10 nm or more and 200 nm or less, and more preferably 70 nm or more and 130 nm or less. This spacer layer reduces the amount of impurity diffusion from the doped layer to the undoped layer, for example, reduces the amount of Si diffusing from the second n-type semiconductor layer 148 to the second active layer 149.

[0043] <Step of forming the second active layer> An undoped second active layer 149 is formed on the 2n-type semiconductor layer 148. The second active layer 149 preferably contains AlGaInAs or InGaAsP. Here, for the double-stack type semiconductor light-emitting device 100 having the first active layer 144 and the second active layer 149, the emission center wavelength of the first active layer 144 and the emission center wavelength of the second active layer 149 may be the same wavelength or close wavelengths. When they are the same wavelength, the second active layer 149 preferably has the same configuration as the first active layer 144. For example, in FIG. 1, a quantum well structure composed of the barrier layer 144b and the well layer 144w of the first active layer 144 is illustrated using InGaAlAs layers with different composition ratios, but the barrier layer 149b and the well layer 149w of the second active layer 149 are also preferably of the same common configuration. In this case, the first active layer 144 and the second active layer 149 have the same emission wavelength, and the emission center wavelength of the combined emission spectrum obtained by combining the emission spectra emitted by each active layer has a wavelength range of 1200 nm or more. If there is no bias in the emission efficiency and power consumption between the active layers due to impurity diffusion into the second active layer 149 as described above, the combined emission intensity increases to a value nearly twice that in the case of a single active layer. Also, even when they are not the same wavelength, if the configurations of the materials used in the active layers are the same and the emission center wavelengths are close enough that a part of the two emission spectra overlaps, the same effects as those of the present invention are exhibited, and the combined emission intensity increases to a value nearly twice that in the case of a single active layer.

[0044] A second electron blocking layer 151 may be provided on the second active layer 149. The second electron blocking layer 151 may be undoped or p-type, but is preferably undoped. The second electron blocking layer 151 may be a single layer or may be composed of a plurality of layers. The thickness of the second electron blocking layer 151 is preferably 2 nm or more and 200 nm or less, and more preferably 5 nm or more and 30 nm or less. This second electron blocking layer 151 is a layer that injects and confines carriers into the second active layer 149. Further, the second electron blocking layer 151 also has an effect of reducing the diffusion of dopants from the second p-type cladding layer 152 described later into the second active layer 149. When the second electron blocking layer 151 is undoped, a spacer layer may be provided between the second electron blocking layer 151 and the second p-type semiconductor layer 150 thereon.

[0045] <Step of forming the second p-type semiconductor layer> A second p-type semiconductor layer 150 is formed on the second active layer 149. The second p-type semiconductor layer 150 may be a single layer or may be composed of a plurality of different layers. In FIG. 1, a p-type semiconductor layer 150 composed of a second p-type cladding layer 152 and a p-type contact layer 153 is shown.

[0046] The thickness of the second p-type cladding layer 152 is preferably 1000 nm or more and 8000 nm or less. If the second p-type cladding layer 152 is thicker than this, the influence of the light emission from the second active layer 149 being absorbed in the second p-type cladding layer 152 is large, and the external extraction of light decreases, which is not preferable. In addition, the current spreads to the ends of the LED chip, increasing surface recombination, and the ohmic resistance of the element increases, reducing the light emission efficiency, which is not preferable. On the other hand, if the second p-type cladding layer 152 is thinner than this, light emission occurs directly under the electrode, preventing light extraction, which is not preferable. Dopants that can be used here include Mg, Zn, C, Be, etc. The dopant concentration of the second p-type cladding layer 152 is 5.0×10 17 atoms / cm 3 or more and 3.0×10 18 atoms / cm 3 or less is preferable.

[0047] A p-type contact layer 153 may be provided on the second p-type cladding layer 152, and the thickness of the p-type contact layer 153 is preferably 30 nm or more and 200 nm or less. Further, the p-type contact layer 153 is preferably formed of a plurality of layers having different group V elements so that partial etching removal is possible by patterning, and a part of the p-type contact layer 153 excluding the p-type contact portion 163 for connecting to the upper electrode 191 may be etched and removed. The dopant concentration of the p-type contact layer 153 is higher than the dopant concentration of the second p-type cladding layer 152, and is 1.0×10 18 atoms / cm 3 or more and 8.0×10 19 atoms / cm 3 or less. Further, the dopant concentration may be inclined so that the dopant concentration on the surface side in contact with the electrode becomes high.

[0048] In the present embodiment, a back electrode 195 may be provided on the back surface of the growth substrate 105, and an upper electrode 191 may be provided on a part of the p-type contact layer 153. The upper electrode 191 may include a wiring portion and a pad portion of an ohmic electrode, and although not shown, the pad portion may have a bonding metal layer or solder. Known metal materials and forming methods can be used for the upper electrode 191 and the back electrode 195. As the metal material, Ti, Pt, Au, Ag, Al, Zn, Ni, etc. can be used.

[0049] The double-stack type semiconductor light-emitting device 100 obtained through the above-described process has good output characteristics, and it is possible to reduce the leakage current and increase the reverse voltage.

[0050] The double-stack type semiconductor light-emitting device 100 obtained through the manufacturing method of the above double-stack type semiconductor light-emitting device 100 will be described. An example of the double-stack type semiconductor light-emitting device 100 is shown using FIG. 1.

[0051] The double-stack type semiconductor light-emitting element 100 includes at least a first n-type semiconductor layer 140, an undoped first active layer 144 on the first n-type semiconductor layer 140, a p-type pseudo tunnel junction layer 1471 having a p-type dopant on the first active layer 144, an n-type pseudo tunnel junction layer 1472 having an n-type dopant in contact with the p-type pseudo tunnel junction layer 1471, an undoped second active layer 149 on the n-type pseudo tunnel junction layer 1472, and a second p-type semiconductor layer 150 on the second active layer 149. Further, the maximum value of the impurity concentration of the n-type dopant resulting from the n-type pseudo tunnel junction layer 1472 included in the second active layer 149 is 1.0×10 16 atoms / cm 3 or less, and more preferably 7.0×10 15 atoms / cm 3 or less, and even more preferably 5.0×10 15 atoms / cm 3 or less.

[0052] <First n-type semiconductor layer> The thickness of the first n-type semiconductor layer 140 is preferably 500 nm or more and 8000 nm or less, and more preferably 3150 nm or more and 3750 nm or less. The first n-type semiconductor layer 140 may include an n-type contact layer 141 and a first n-type cladding layer 142. Although not shown, a spacer layer may be provided between the first n-type semiconductor layer 140 and the first active layer 144. Examples of the dopant of the first n-type semiconductor layer 140 include S or Si.

[0053] <First active layer and second active layer> The impurity concentration of the n-type dopant included in the first active layer 144 and the second active layer 149 is preferably 1.0×10 16 atoms / cm 3 or less, and more preferably 7.0×10 15 atoms / cm 3 or less, and even more preferably 5.0×10 15 atoms / cm 3The following are more preferable. Also, in principle, the impurity concentration of the n-type dopant contained in the first active layer 144 and the second active layer 149 is 2.0×10 14 atoms / cm 3 or more. Further, the first active layer 144 and the second active layer 149 preferably contain AlGaInAs or InGaAsP, respectively. The first active layer 144 may have a wavelength range with an emission center wavelength of 1200 nm or more. Also, for the double-stack type semiconductor light-emitting device 100 having the first active layer 144 and the second active layer 149, the emission center wavelength of the first active layer 144 and the emission center wavelength of the second active layer 149 may be the same wavelength or close wavelengths.

[0054] A first electron blocking layer 145 may be provided on the first active layer 144. The first electron blocking layer 145 may be undoped or p-type, but is preferably undoped. This first electron blocking layer 145 is a layer that injects and confines carriers into the first active layer 144. Also, the first electron blocking layer 145 has the effect of reducing the diffusion of the p-type dopant from the pseudo tunnel junction layer 147 described later to the first active layer 144.

[0055] For example, a first p-type semiconductor layer 146 such as a first p-type clad layer may be provided on the first electron blocking layer 145. The composition of the first p-type clad layer preferably has a smaller bandgap than the composition of the first electron blocking layer 145, and examples include InGaAsP or InP. Although not shown, the above-described spacer layer may be provided between the undoped first electron blocking layer 145 and the first p-type semiconductor layer 146 formed thereon.

[0056] <p-Type Pseudo Tunnel Junction Layer and n-Type Pseudo Tunnel Junction Layer> Examples of the dopant that can be used for the p-type pseudo tunnel junction layer 1471 include Mg, Zn, C, Be, etc., and it is preferable to use C. The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer 1471 is 1.0×10 19 atoms / cm 3It is preferably the above, and the impurity concentration is 1.02×10 19 atoms / cm 3 It is more preferably the above, and 1.05×10 19 atoms / cm 3 It is even more preferably the above. Examples of the dopant that can be used for the n-type pseudo tunnel junction layer 1472 include Si, Te, S, Ge, Sn, Se, etc., but it is preferable to use Si. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is 1.0×10 19 atoms / cm 3 It is preferably the above, and 1.55×10 19 atoms / cm 3 It is more preferably the above, and 1.6×10 19 atoms / cm 3 It is even more preferably the above. The p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 preferably contain AlGaInAs or InGaAsP, respectively. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is more preferably 5×10 19 atoms / cm 3 It is even more preferably the following

[0057] <Second n-type semiconductor layer> It is preferable that a Si-doped second n-type semiconductor layer 148 is provided between the n-type pseudo tunnel junction layer 1472 and the second active layer 149. The Si impurity concentration of the second n-type semiconductor layer 148 is preferably 1.0×10 17 atoms / cm 3 or more and 5.0×10 18 atoms / cm 3 or less, more preferably 3.0×10 17 atoms / cm 3 or more and 3.0×10 18 atoms / cm 3 or less, even more preferably 5.0×10 17 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3The following are more preferable. The thickness of the second n-type semiconductor layer 148 is preferably 100 nm or more and 2000 nm or less, and more preferably 300 nm or more and 600 nm or less. The above-described spacer layer may be provided between the second n-type semiconductor layer 148 and the undoped second active layer 149.

[0058] <Second p-type semiconductor layer> The thickness of the second p-type semiconductor layer 150 is preferably 1000 nm or more and 8400 nm or less, and more preferably 2000 nm or more and 5000 nm or less. The second p-type semiconductor layer 150 may include a second p-type cladding layer 152 or a p-type contact layer 153. Examples of the dopant of the second p-type semiconductor layer 150 include Zn and C. A second electron blocking layer 151 may be provided between the second active layer 149 and the second p-type semiconductor layer 150. Further, although not shown, a spacer layer may be provided on the second electron blocking layer 151. A p-type contact portion 163 for connecting to the upper electrode 191 may be provided by removing a part of the p-type contact layer 153.

[0059] <Characteristics of the pseudo tunnel junction layer> In the current-voltage curve when the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 are energized without passing through the first active layer 144 and the second active layer 149, the voltage when the current becomes maximum is preferably 0.02 V or more and 0.2 V or less.

[0060] Further, in the current-voltage curve when the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 are energized without passing through the first active layer 144 and the second active layer 149, the maximum value of the current is preferably 7 mA or less.

[0061] As described in detail above, the double-stack type semiconductor light-emitting device 100 has good output characteristics, and it is possible to reduce the leakage current and increase the reverse voltage characteristics. In the double-stack type semiconductor light-emitting device 100 of FIG. 1, the first n-type semiconductor layer 140, the first active layer 144, the p-type pseudo tunnel junction layer 1471, the n-type pseudo tunnel junction layer 1472, the second active layer 149, and the second p-type semiconductor layer 150 are provided in this order from below the paper surface, but this is just an example, and this stacking order may be reversed.

[0062] (Second Embodiment) Referring to FIG. 2, a double-stack type semiconductor light-emitting device 200 according to a second embodiment of the present invention will be described. The double-stack type semiconductor light-emitting device 200 is a bonded type semiconductor light-emitting device obtained by bonding a support substrate to the side opposite to the growth substrate side of the semiconductor laminate and then removing the growth substrate. In principle, the same components as those of the double-stack type semiconductor light-emitting device 100 are given the same reference numerals in the lower two digits of the three-digit number, and redundant descriptions are omitted.

[0063] The double-stack type semiconductor light-emitting device 200 includes at least a support substrate 280, a bonding layer 270 provided on the support substrate 280, an intermediate electrode layer 260 in which a dielectric part 261 and an electrode part 265 provided on the bonding layer 270 are arranged in parallel, a second p-type semiconductor layer 250 provided on the intermediate electrode layer 260, an undoped second active layer 249 provided on the second p-type semiconductor layer 250, an n-type pseudo tunnel junction layer 2472 having an n-type dopant provided on the second active layer 249, a p-type pseudo tunnel junction layer 2471 having a p-type dopant provided in contact with the n-type pseudo tunnel junction layer 2472, an undoped first active layer 244 provided on the p-type pseudo tunnel junction layer 2471, a first n-type semiconductor layer 240 provided on the first active layer 244, and an upper electrode 291 provided on the first n-type semiconductor layer 240. Further, the maximum value of the impurity concentration of the n-type dopant derived from the n-type pseudo tunnel junction layer 2472, which is included on the n-type pseudo tunnel junction layer 2472 side of the second active layer 249, is 1.0×10 16 atoms / cm 3It is characterized by the following. Also, the impurity concentration of this n-type dopant is 7.0×10 15 atoms / cm 3 It is more preferably below, and 5.0×10 15 atoms / cm 3 It is even more preferably below. Also, in principle, the impurity concentration of the n-type dopant due to the n-type pseudo tunnel junction layer 2472 contained in the second active layer 249 is 2.0×10 14 atoms / cm 3 or more.

[0064] The double-stack type semiconductor light-emitting device 200 shown in FIG. 2 includes, in order from the side opposite to the support substrate 280, a first n-type semiconductor layer 240 (n-type contact layer 241 and first n-type clad layer 242), a first active layer 244, a first electron blocking layer 245, a first p-type semiconductor layer 246, a p-type pseudo tunnel junction layer 2471, an n-type pseudo tunnel junction layer 2472, a second n-type semiconductor layer 248, a second active layer 249, a second electron blocking layer 251, and a second p-type semiconductor layer 250 (second p-type clad layer 252 and p-type contact layer 253).

[0065] As the support substrate 280 different from the growth substrate, it is preferably cheaper than the growth substrate and has high thermal conductivity. For example, in addition to compound substrates such as Si, Ge, and GaAs, a metal substrate using a metal such as copper alloy, molybdenum, tungsten, or kovar that can suppress the thermal expansion coefficient, or a submount substrate with a metal attached to a ceramic substrate such as AlN can be used. It is also preferable to use an Si substrate as the support substrate 280 in terms of processability and cost.

[0066] Hereinafter, an example of an embodiment of the double-stack type semiconductor light-emitting device 200 and its manufacturing method will be described in more detail with reference to FIGS. 3 to 7. First, a growth substrate 205 is prepared. Then, referring to FIG. 3, a semiconductor laminate 220 is formed. At this time, an etching stop layer (not shown) may be formed on the growth substrate 205. The semiconductor laminate 220 is the same as the semiconductor laminate 120 described above.

[0067] <<Formation of Intermediate Electrode Layer>> An intermediate electrode layer 260 may be formed on the p-type contact layer 253, which includes a dielectric part 261 having a through-hole, an electrode part 265 provided in the through-hole, and a p-type contact part 263 that is a part of the p-type contact layer 253. The dielectric part 261 and the electrode part 265 (and the p-type contact part 263) may be arranged in parallel, and the electrode part 265 and the p-type contact part 263 may be arranged in series. The specific method for forming the intermediate electrode layer 260 is arbitrary. An example of a specific embodiment for forming the intermediate electrode layer 260 will be described below with reference to FIGS. 4 and 5. In the figures, two locations including the electrode part 265 and the p-type contact part 263 in the intermediate electrode layer 260 are simply illustrated, but this location may be one, or three or more. While avoiding directly below the upper electrode 291, it is preferably arranged in a dispersed island shape or stripe shape so that the current between it and the upper electrode 291 spreads evenly in the in-plane direction.

[0068] First, a mask is formed on the p-type contact layer 253. Using a sputtering method or the like, the electrode part 265 is formed on the p-type contact part 263 which is a part of the p-type contact layer 253. The resist is removed and the electrode part 265 other than on the p-type contact part 263 is removed. Then, a mask is formed on the p-type contact layer 253, and a part of the p-type contact layer 253 other than the region of the p-type contact part 263 where the electrode part 265 is formed is removed to form the p-type contact part 263 as a convex part. Next, the dielectric part 261 is formed on the semiconductor laminate 220. As the film formation method, a known method such as a plasma CVD method or a sputtering method can be applied. Then, a resist pattern on the intermediate electrode layer 260 is formed using a photomask on the dielectric part 261, and the dielectric part 261 on the electrode part 265 is removed by etching until the electrode part 265 is exposed. The thickness of the intermediate electrode layer 260 is preferably 500 nm or more and 1000 nm or less, and more preferably 600 nm or more and 800 nm or less.

[0069] <<Formation of Metal Reflective Layer>> As shown in FIG. 4, it is also preferable to form a metal reflective layer 271 on the intermediate electrode layer 260. The metal reflective layer 271 can include a plurality of metal layers. In addition to Au, metals such as Al, Pt, Ti, and Ag can be used for the metal constituting the metal reflective layer 271. Here, it is preferable that the metal reflective layer 271 has 50% by mass or more of Au in its composition. Further, in order to ensure bonding with the metal bonding layer 279 in subsequent processes, it is preferable that the outermost layer (the surface opposite to the semiconductor laminate 220) of the metal reflective layer 271 is an Au metal layer. The thickness of the metal reflective layer 271 is preferably 400 nm or more and 2200 nm or less, and more preferably 1500 nm or more and 2000 nm or less.

[0070] <<Bonding with the support substrate>> The semiconductor laminate 220 and the intermediate electrode layer 260 are bonded to the support substrate 280 via at least the metal bonding layer 279. By providing the metal reflective layer 271, the metal reflective layer 271 and the metal bonding layer 279 can be bonded. The metal bonding layer 279 and the metal reflective layer 271 are arranged opposite to each other and bonded together, and both can be bonded by performing thermocompression bonding at a temperature of about 250°C to 500°C.

[0071] <<Formation of the metal bonding layer>> The metal bonding layer 279 can be formed using metals such as Ti, Pt, and Au, metals that form eutectic alloys with Au (such as Sn), or solders, and it is preferable to stack these to form the metal bonding layer 279. The thickness of the metal bonding layer 279 is preferably 1000 nm or more and 2000 nm or less, and more preferably 1200 nm or more and 1800 nm or less. By making the outermost layer of the metal bonding layer 279 an Au metal and the outermost layer of the metal reflective layer 271 also an Au, bonding between the Au's by Au-Au diffusion can be performed. The metal reflective layer 271 and the metal bonding layer 279 are bonded together and referred to as the bonding layer 270.

[0072] The support substrate 280 may be a substrate different from the growth substrate 205, and submount substrates based on the semiconductor substrate, metal substrate, ceramic substrate, etc. described above can be used. Since the bonding method described above is used, the support substrate 280 may be lattice mismatched with each semiconductor layer formed in the present embodiment. Note that although the support substrate 280 may be insulating depending on the application, it is preferably a conductive substrate. It is preferable to use an Si substrate as the support substrate 280 in terms of processability and cost. By using an Si substrate, the thickness of the support substrate 280 can be made significantly smaller than before, and it is also suitable for mounting in combination with various semiconductor devices. Also, the Si substrate is advantageous in terms of heat dissipation compared to the InAs substrate.

[0073] [[Removal of the growth substrate]] After bonding the support substrate 280, the growth substrate 205 is removed. When the growth substrate 205 is a GaAs substrate, for example, the growth substrate 205 can be wet-etched using an ammonia hydrogen peroxide mixture. When the growth substrate 205 is an InP substrate, for example, it can be wet-etched using diluted hydrochloric acid.

[0074] As shown in FIG. 5, after removing the growth substrate 205, an ohmic electrode and a pad electrode may be formed as the upper electrode 291 on the upper surface (the surface opposite to the support substrate 280) of the semiconductor laminate 220. The ohmic electrode can be formed using a metal such as Au, Ge, Ni, Ti, a metal (such as Sn) that forms a eutectic alloy with Au, or solder. By using general means such as vapor deposition, the ohmic electrode can be formed by film formation. The thickness of the ohmic electrode is not limited, but it can be, for example, 300 nm or more and 1300 nm or less. It is preferable to perform heat treatment for ohmic contact after forming the ohmic electrode.

[0075] After forming the ohmic electrode, it is preferable to form a pad electrode on the ohmic electrode. The pad electrode can be formed using a metal such as Ti or Au, or a metal that forms a eutectic alloy with Au (such as Sn), or solder. By using general means such as vapor deposition, the pad electrode can be formed. And when the n-type contact layer 241 is a layer with low light transmittance for the emission wavelength, it is preferable to remove the n-type contact layer 241 other than the region where the upper electrode 291 is formed to expose the surface of the first n-type clad layer 242.

[0076] After forming the pad electrode, the upper surface of the semiconductor laminate 220 other than the upper electrode 291 and its periphery (for example, the surface of the first n-type clad layer 242) may be roughened. This is because the light extraction efficiency is improved by roughening. The roughening of the surface of the first n-type clad layer 242 can be performed by using general methods such as selective etching or wet etching using a mask. In a plan view, it is preferable that the upper electrode 291 and the electrode portion 265 are formed separately.

[0077] <<Mesa formation>> As shown in FIG. 6, a mesa shape may be formed in the semiconductor laminate 220 by removing a part of the semiconductor laminate 220 by a dry etching method. As the method of the dry etching method, reactive etching (RIE) is preferably used, and for example, inductively coupled plasma (ICP) can be used as the plasma source to be used. The dry etching is performed on a street region having a certain width along the planned chip division line when viewed from above. The width of the street region (street width) is a width necessary for performing chip division without adversely affecting the active layer or the like, and is, for example, 40 to 100 μm. The street region can be in a grid shape, and the pad electrode formed above or the electrode portion 265 of the intermediate electrode layer 260 is disposed in a region that is not the street region when viewed from above. A mask (for example, SiO 2 mask) having a thickness such that the etching rate during dry etching on the first n-type clad layer 242 is smaller than that of the semiconductor laminate 220 and does not disappear until the etching of the street region is completed is formed on the first n-type clad layer 242, and then dry etching of the street region is performed. This dry etching is performed until the intermediate electrode layer 260 is exposed outside the mesa shape. The angle θ formed by the intermediate electrode layer 260 and the second p-type semiconductor layer 250 is preferably 70° or more and 85° or less. Further, it is preferable that the two active layers have the same area of the first active layer and the second active layer when viewed from above and the side surfaces therebetween are perpendicular.

[0078] <Formation of protective film> As shown in FIG. 7, after mesa formation, it is preferable to form a protective film 230 using plasma CVD or the like. Examples of the protective film 230 used at this time include SiO 2 or SiN. The SiO 2 of the mask in the mesa formation step may be used as a part of the protective film 230. Further, it is preferable that the upper surface of the upper electrode 291 is not covered with the protective film 230. The thickness of the protective film 230 is preferably 50 nm or more and 500 nm or less.

[0079] Furthermore, a back surface electrode 295 may be formed on the back surface of the support substrate 280.

[0080] By the above manufacturing method, the double-stack type semiconductor light-emitting element 200 shown in FIG. 2 can be obtained.

Example

[0081] (Example 1) First, using the MOCVD method, on the (100) surface of an n-type InP growth substrate 205 (thickness: 600 μm, S-doped, dopant concentration: 2.0×10 18 / cm 3 ), an Si-doped n-type InP buffer layer (thickness: 120 nm, carrier concentration: 5.0×10 17 / cm 3 ) is formed, and on it, as the first n-type semiconductor layer 240, an Si-doped n-type In 0.532 Ga 0.468 As contact layer 241 (thickness: 24 nm, carrier concentration: 5.0×10 17 / cm 3 ), an Si-doped first n-type InP cladding layer 242 (thickness: 3.5 μm, carrier concentration: 5.0×10 17 / cm 3 ) are formed, and on it, an undoped InP spacer layer (thickness: 100 nm) is formed. Next, a first active layer 244 with a quantum well structure having an emission center wavelength of 1500 nm (total film thickness: 165 nm) is formed. The first active layer 244 is composed of an undoped In 0.419 Ga 0.297 Al 0.284 As barrier layer 244w (thickness: 10 nm) and an In 0.765 Ga 0.125 Al 0.110 As well layer 244b (thickness: 5 nm) stacked alternately 10 layers each in sequence, and then an In 0.419 Ga 0.297 Al 0.284 As barrier layer 244w is grown, making a total of 10.5 sets including the last barrier layer. On the first active layer 244, an undoped In 0.522 Al 0.478Formed a first electron block layer 245 (thickness: 20 nm) and an undoped InP spacer layer (thickness: 300 nm), and a Zn-doped first p-type InP semiconductor layer (thickness: 500 nm, carrier concentration: 7.0×10 17 / cm 3 ) as the first p-type semiconductor layer 246, a Zn-doped p-type Al 0.478 In 0.522 As layer (thickness: 200 nm, carrier concentration: 1.0×10 18 / cm 3 ), a Zn-doped p-type Al 0.122 In 0.529 Ga 0.349 As layer (thickness: 20 nm, carrier concentration: 1.0×10 18 / cm 3 ). On top of that, a Zn-doped p-type In 0.763 Ga 0.237 As 0.512 P 0.488 intermediate layer (thickness: 20 nm, carrier concentration: 1.0×10 18 / cm 3 ) was formed.

[0082] Furthermore, on a C-doped p-type Al 0.137 In 0.529 Ga 0.334 As pseudo tunnel junction layer 2471 (thickness: 36 nm, carrier concentration: 5.0×10 19 / cm 3 ), a Si-doped n-type Al 0.137 In 0.529 Ga 0.334 As pseudo tunnel junction layer 2472 (thickness 18 nm, carrier concentration: 1.5×10 19 / cm 3 ) was directly formed. The p-type pseudo tunnel junction layer 2471 was doped with C using CBr 4 as the doping gas. The n-type pseudo tunnel junction layer 2472 was doped with Si using Si 2 H 6 as the doping gas. Next, on the n-type pseudo tunnel junction layer 2472, a Si-doped n-type In 0.763 Ga 0.237 As 0.512 P 0.488An intermediate layer (thickness: 16 nm, carrier concentration: 1.5×10 19 / cm 3 ) was formed.

[0083] On the pseudo tunnel junction layer 247, via the n-type intermediate layer, a Si-doped second n-type InP semiconductor layer (thickness: 500 nm, carrier concentration: 1.5×10 18 / cm 3 ) was formed as the second n-type semiconductor layer 248, and an undoped InP spacer layer (thickness: 100 nm) was formed thereon. Next, a second active layer 249 having the same configuration as the first active layer 244 (total film thickness: 165 nm) was formed. Further, an undoped In 0.522 Al 0.478 As second electron blocking layer 251 (thickness: 20 nm) and an undoped InP spacer layer (thickness: 300 nm) were formed. Then, a Zn-doped second p-type InP cladding layer 252 (thickness: 2.4 μm, carrier concentration: 7.0×10 17 / cm 3 ) and a Zn-doped p-type InP layer (thickness: 240 nm, carrier concentration: 1.5×10 18 / cm 3 ), a Zn-doped p-type In 0.749 Ga 0.251 As 0.543 P 0.457 layer (thickness: 60 nm, carrier concentration: 5.0×10 18 / cm 3 ), and a Zn-doped p-type InGa 0.468 As (thickness: 120 nm, carrier concentration: 1.5×10 19 / cm 3 ) were formed to form a p-type contact layer 253.

[0084] The composition, thickness, dopant type, and carrier concentration of each layer are described in Table 1 below. Note that the carrier concentration is the designed impurity concentration during crystal growth. The measured value of the impurity concentration in the SIMS analysis described later is the impurity concentration in the present invention.

[0085]

Table 1

[0086] Next, except for the surface of the region to be the p-type contact portion 263 of the p-type InGaAs layer on the outermost surface of the p-type contact layer 253, the rest is covered with a photoresist. As the electrode portion 265, Ti (thickness: 10 nm) and Au (thickness: 530 nm) are deposited by vapor deposition, and the resist of the pattern other than the electrode portion 265 on the region to be the p-type contact portion 263 is removed together with the metal deposited thereon. After contact annealing, a photomask is formed on the electrode portion 265, leaving the p-type InGaAs layer in the range where the p-type contact portion 263 is desired, and removing the other p-type InGaAs layers by wet etching using a tartaric acid - hydrogen peroxide water mixture. By plasma CVD method, SiO 2 A dielectric portion 261 (thickness: 700 nm) made of is formed on the entire surface of the p-type contact layer 253. The dielectric portion 261 on the electrode portion 265 is removed by etching to form an intermediate electrode layer 260 in which the dielectric portion 261 and the electrode portion 265 (and the p-type InGaAs contact portion 263) are arranged in parallel. Next, a metal reflective layer 271 (Al (film thickness: 10 nm / Au (film thickness: 650 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 900 nm))) is formed on the intermediate electrode layer 260 by vapor deposition.

[0087] Thereafter, a metal bonding layer 279 (Ti (film thickness: 650 nm) / Pt (film thickness: 20 nm) / Au (film thickness: 900 nm)) is formed on the support substrate (Si substrate) 280 by vapor deposition. Then, the metal reflective layer 271 and the metal bonding layer 279 are arranged opposite to each other, and thermocompression bonding is performed at 300 °C to form a bonding layer 270. Next, the growth substrate 205 is removed by wet etching using a diluted hydrochloric acid solution to expose the n-type InGaAs contact layer 241.

[0088] An Au (thickness: 10 nm) / Ge (thickness: 30 nm) / Au (thickness: 60 nm) / Ni (thickness: 30 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm) was formed on the n-type InGaAs contact layer 241 by vapor deposition method to serve as the top ohmic electrode. A pad electrode (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was formed on the top ohmic electrode by vapor deposition method. For the formation of the electrode pattern, a lift-off method using a resist was employed. Thereafter, the n-type InGaAs contact layer 241 other than the region directly under the top ohmic electrode was removed by wet etching using a tartaric acid - hydrogen peroxide water mixture.

[0089] Next, a resist mask was formed by photolithography so as to cover the street region along the chip division planned line as well as the top ohmic electrode and the pad electrode, and upper surface roughening was performed by wet etching on the light extraction surface of the first n-type InP clad layer 242 outside the masked region.

[0090] Thereafter, SiO 2 was formed over the entire surface by plasma CVD method. After that, a SiO 2 mask in a form where the street region along the chip division planned line was exposed was formed by mask pattern formation with a resist and etching. The width of the street region exposed by the mask pattern is 55 μm. A mesa was formed by dry etching (ICP-RIE) to expose the outer peripheral portion of the intermediate electrode layer 260 in the street region and also to expose the side surface of the semiconductor laminate 220. The etching conditions were: dry etching, stage temperature of 200 °C, pressure of 0.2 Pa, bias power of 150 W, ICP power of 190 W, overetching rate of 5%, and the ratio of the gas species used was SiCl 4 :Ar = 4:8.

[0091] After mesa formation, after removing the above-mentioned SiO 2 mask existing on the upper electrode 291, SiO was formed over the entire surface (the remaining SiO 2On the upper surface of the mask, on the side surface of the exposed mesa portion, and in the street region (including these), SiN (thickness: 190 μm) was deposited as the protective film 230. Then, the SiN on the upper surface of the upper electrode 291 was removed by etching using a resist mask pattern, and then the resist was removed. Next, the back surface of the support substrate 280 was shaved by polishing or etching to make the thickness of the double-stack type semiconductor light-emitting element 200 150 μm. Next, a back surface electrode 295 (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the back surface of the support substrate 280 by vapor deposition, and heat treatment was performed at 300 °C for 60 seconds by RTA. Finally, the double-stack type semiconductor light-emitting element 200 according to Example 1 was fabricated by separating it into individual elements on a rectangle with a chip size of 1080 μm × 1080 μm using laser dicing.

[0092] (Example 2) A double-stack type semiconductor light-emitting element 200 according to Example 2 was obtained in the same manner as in Example 1, except that the n-type InGaAsP intermediate layer (n-InGaAsP layer) and the p-type InGaAsP intermediate layer (p-InGaAsP layer) were not provided.

[0093] (Example 3) A double-stack type semiconductor light-emitting element 200 according to Example 3 was obtained in the same manner as in Example 1, except that the flow rate of the dopant gas (Si 2 H 6 ) during the formation of the n-type pseudo tunnel junction layer 2472 was set to 3200 sccm.

[0094] (Comparative Example 1) When forming the p-type pseudo tunnel junction layer 2471, the growth temperature was set to 725 °C instead of 750 °C, and it was formed while changing the temperature from 725 °C to 630 °C during growth. Further, the dopant of the n-type pseudo tunnel junction layer 2472 was Te, and DETe (diethyl tellurium) was used as the dopant gas. It was formed while changing the flow rate to 10 sccm and the growth temperature from 725 °C to 630 °C. Except for these conditions, the double-stack type semiconductor light-emitting device 200 according to Comparative Example 1 was obtained in the same manner as in Example 1. Hereinafter, the layer located in the pseudo tunnel junction layer 247 of Comparative Example 1 is simply referred to as a tunnel junction layer.

[0095] (Comparative Example 2) After forming up to the first p-type semiconductor layer 246 in the same manner as in Example 1 on the growth substrate 205, a single-stack type semiconductor light-emitting device according to Comparative Example 2 was obtained in the same manner as in Example 1, except that a p-type contact layer 253 was formed without forming a pseudo tunnel junction layer 247 or a second active layer 249 or the like.

[0096] (Example 4) A double-stack type semiconductor light-emitting device 200 according to Example 4 was obtained in the same manner as in Example 1, except that the compositions of the first active layer 244 and the second active layer 249 were adjusted so that the emission center wavelength became 1300 nm.

[0097] (Comparative Example 3) A single-stack type semiconductor light-emitting device according to Comparative Example 3 was obtained in the same manner as in Comparative Example 2, except that the compositions of the first active layer 244 and the second active layer 249 were adjusted so that the emission center wavelength became 1300 nm.

[0098] [Test 1] In Test 1, the performance of the pseudo tunnel junction layer 247 of Examples 1 to 3 and the tunnel junction layer of Comparative Example 1 was evaluated. In order to evaluate the pure tunnel effect, the following test was conducted so that the pseudo tunnel junction layer 247 (or tunnel junction layer) could be energized without passing through the first active layer 244 and the second active layer 249.

[0099] Specifically, first, on a 2-inch p-type InP substrate, under the above-described conditions, a first p-type semiconductor layer 246 (p-InP, film thickness 500 nm), a pseudo tunnel junction layer 247 (or a tunnel junction layer), and a second n-type semiconductor layer 248 (n-InP, film thickness 500 nm) were formed, and further, an n-type contact layer 241 (n-InGaAs, film thickness 24 nm) and an InP cap layer were grown in this order (Fig. 8a). The upper InP cap layer was etched with an etching solution of hydrochloric acid - acetic acid to expose the n-type contact layer 241 (Fig. 8b). Next, except for the upper electrode pattern, it was covered with a photoresist, and after depositing the upper electrode, the resist was removed together with the metal film formed thereon to form the upper electrode (Fig. 8c). Next, the area directly under the upper electrode of the n-type contact layer 241 and the area outside its periphery were etched away, and a mesa formation mask covering the remaining n-type contact layer 24 and the upper electrode was formed (Fig. 8d), and mesa etching was performed by wet etching (etching solution: Br - MeOH) (Fig. 8e). After removing the mask, a back electrode was deposited on the back surface of the p-type InP substrate (Fig. 8f). The fabricated device was designated as the device 10 for performance confirmation.

[0100] The device for performance confirmation was placed on the stage of an LED tester (manufactured by Waishii Gaater, model number: LX4730A), and a probe was applied to the upper electrode and energized for 100 ms. Here, the shape of the upper electrode of the device 10 for performance confirmation was circular, with a diameter of 194.4 μm and an area of 29681 μm 2 . Further, the shape of the mesa was circular, with a diameter of 235.2 μm and an area of 43447 μm 2 . The results of the above energization for each example and Comparative Example 1 are shown in Fig. 9. Also, Table 2 shows the epitaxial structure, dopant, film thickness, and the above energization results of the p-type pseudo tunnel junction layer 2471 and the n-type pseudo tunnel junction layer 2472 in each example. And the epitaxial structure, dopant, film thickness, and the above energization results of the tunnel junction layer in Comparative Example 1 are also shown in Table 2 together. The SIMS impurity concentration [cm -3 shown in Table 2 is the impurity concentration (peak value) measured by SIMS in Test 2 described later, not the device 10 for performance confirmation.

[0101]

Table 2

[0102] As can be seen from FIG. 9 and Table 2, in Comparative Example 1, as shown by a general tunnel junction layer, the maximum tunnel current (the maximum value of the current) is as large as several tens of mA, and tunnel junction characteristics with negative resistance are obtained. On the other hand, in Examples 1 to 3, in the I-V curve, the starting point of the negative resistance region (the point where the current becomes maximum) is between 0.02 V and 0.2 V, and the maximum tunnel current (the maximum value of the current) is 7 mA or less, and a phenomenon different from the conventionally considered behavior was confirmed.

[0103] [Test 2] In Test 2, the output characteristics of the double-stack type semiconductor light-emitting elements 200 fabricated in Examples 1 to 4 and Comparative Example 1 and the single-stack type semiconductor light-emitting elements fabricated in Comparative Examples 2 to 3 were measured. Further, Examples 1 to 3 and Comparative Examples 1 to 2 were subjected to SIMS analysis to measure the impurity concentration. Table 3 shows the light emission output Po [mW] and the forward voltage Vf [V] when currents of 30 mA, 100 mA, and 1 A were passed through the double-stack type semiconductor light-emitting elements 200 fabricated in Examples 1 to 4 and Comparative Example 1 and the single-stack type semiconductor light-emitting elements fabricated in Comparative Examples 2 to 3, the leakage current Ir [A] when voltages of 5 V and 10 V were applied, and the reverse voltage Vr [V] when currents of 0.1 μA and 1 μA were passed through. FIG. 10 is a graph showing the current-light emission output characteristics of Examples 1 to 3 and Comparative Examples 1 to 2 (elements in the target wavelength band of 1500 nm band).

[0104]

Table 3

[0105] As can be seen from Table 3 and FIG. 10, when a current of 1 A is passed, the light emission output of Examples 1 to 3 in which the dopant of the n-type pseudo tunnel junction layer 2472 is Si is 1.8 to 1.9 times that of Comparative Example 2 of the single stack type, and when the current is 100 mA, it is 1.6 to 1.7 times. On the other hand, when a current of 1 A is passed, the light emission output of Comparative Example 1 in which the dopant of the n-type pseudo tunnel junction layer 2472 is Te is about 1.5 times that of Comparative Example 2 of the single stack type, and when the current is 100 mA, it is about 1.4 times. The greater the current passed, the greater the improvement effect of the light emission output of this example. This example also has the effect of suppressing the output decrease due to heat generation when a large current is passed. It is also considered that the pseudo tunnel junction layer 247 of the present invention can easily diffuse the current in the in-plane direction compared to a normal tunnel junction layer and suppress heat generation due to current concentration. Also, the leakage current Ir when a reverse voltage of 5 V is passed through Examples 1 to 3 is 1.0×10 -10 A, which is 1 / 65 of that of Comparative Example 1, 6.5×10 -9 A, and a significant reduction in the leakage current is also observed. The leakage current Ir when a reverse voltage of 10 V is passed through Examples 1 to 3 is also reduced compared to Comparative Example 1 and Comparative Example 2 of the single stack type. Also, the reverse voltage Vr when 0.1 μA or 1 μA is passed through Examples 1 to 3 is about 30 V, and a significant increase in the reverse voltage is also observed compared to Comparative Example 1 or Comparative Example 2 of the single stack type. The effects of the improvement in light emission output, reduction in leakage current, and increase in reverse voltage were similarly observed in the comparison between Example 4 with a different wavelength and Comparative Example 3 of the single stack type.

[0106] Figures 11 to 14 respectively show the results of SIMS analysis of Examples 1 to 3 and Comparative Example 1. In these figures, the horizontal axis range was set so that the entire areas of the second active layer 249 and the first active layer 244 were within the range, so as to understand the degree to which the n-type dopant diffuses. Also, the average values of the impurity concentrations of the second active layer 249, the first active layer 244, and the n-type InP layer, the maximum value (peak value) of the impurity concentration of the pseudo tunnel junction layer 247 (TJ), and the maximum value (peak value) of the impurity concentration of the n-type dopant on the TJ side of the second active layer 249, read from the results of these SIMS analyses, are shown in Table 4. Also, the average values of the impurity concentrations of the second active layer 249, the first active layer 244, and the n-type InP layer, the maximum value (peak value) of the impurity concentration of the tunnel junction layer (TJ), and the maximum value (peak value) of the impurity concentration of the n-type dopant on the TJ side of the second active layer 249 for Comparative Example 1 are also shown in Table 4 together.

[0107] Regarding the method of setting the boundary line between the second active layer 249 (i-InGaAlAs) and the spacer layer (i-InP) illustrated by a broken line in the SIMS profiles of FIGS. 11 to 14, the boundary line was set at the center of the variation in the difference at the location where the As profile drops steeply. Based on the As profile, the region from the center in the thickness direction of the second active layer 249 to the boundary with the other layer (spacer layer) in contact with the n-type pseudo tunnel junction layer 2472 side of the second active layer 249 was defined as the TJ side of the second active layer 249.

[0108] [Table 4]

[0109] The impurity concentration of Si mixed in the second active layer 249 of Examples 1 to 3 is 1.0×10 at the maximum value (peak value) on the n-type pseudo tunnel junction layer 2472 side 16 atoms / cm 3 or less, and the average over the entire second active layer 249 is 5.0×10 15 atoms / cm 3 or less. On the other hand, the impurity concentration of Te mixed in the second active layer 249 of Comparative Example 1 is 1.0×10 in most of the second active layer 24916 atoms / cm 3 exceeds. Further, in Comparative Example 1, the Te concentration in the barrier layer on the TJ side of the second active layer 249 is 3.3×10 17 atoms / cm 3 and there is a large peak. The peak value of the impurity concentration (Si) in the n-type pseudo tunnel junction layer 2472 of Examples 1 to 3 is 1.65 to 1.83×10 19 cm -3 and the peak value of the impurity concentration (Te) in the n-type tunnel junction layer of Comparative Example 1 is 1.48×10 19 cm -3 It is presumed that the reason why the peak value of the impurity concentration in the n-type tunnel junction layer of Comparative Example 1 is less than the peak value of the impurity concentration in the n-type pseudo tunnel junction layer 2472 of Examples 1 to 3 is the result of Te in Comparative Example 1 moving in the direction of the second active layer.

[0110] From the results of these SIMS analyses and the measurement results of the output characteristics shown in Table 3, when Te is used as the n-type dopant in the tunnel junction layer, it is considered that the impurity Te diffuses into the second active layer 249 and the output decreases. On the other hand, when Si is used as the n-type dopant, although it becomes a pseudo tunnel junction layer showing behavior different from that of a normal tunnel junction from the results of Test 1, since Si hardly diffuses into the second active layer 249, the output hardly decreases.

[0111] As described above, by satisfying the conditions of the present invention, it is possible to provide a double-stack type semiconductor light-emitting device having good output characteristics, capable of reducing leakage current and increasing reverse voltage. The pseudo tunnel junction layer according to the present invention clearly has different behavior from the conventionally considered tunnel junction layer.

Description of Reference Numerals

[0112] 100 Double-stack type semiconductor light-emitting device 105 Growth substrate 120 Semiconductor laminate 140 First n-type semiconductor layer 141 n-type contact layer 142 First n-type cladding layer 144 First active layer 144b Barrier layer of the first active layer 144w Well layer of the first active layer 145 First electron blocking layer 146 First p-type semiconductor layer 147 Pseudotunnel junction layer 1471 p-type pseudotunnel junction layer 1472 n-type pseudotunnel junction layer 148 Second n-type semiconductor layer 149 Second active layer 149b Barrier layer of the second active layer 149w Well layer of the second active layer 150 Second p-type semiconductor layer 151 Second electron blocking layer 152 Second p-type cladding layer 153 p-type contact layer 163 p-type contact portion 191 Upper electrode 195 Back electrode 200 Double-stack type semiconductor light-emitting element 205 Substrate for growth 220 Semiconductor laminate 240 First n-type semiconductor layer 241 n-type contact layer 242 First n-type cladding layer 244 First active layer 244b Barrier layer of the first active layer 244w Well layer of the first active layer 245 First electron blocking layer 246 First p-type semiconductor layer 247 Pseudotunnel junction layer 2471 p-type pseudotunnel junction layer 2472 n-type pseudotunnel junction layer 248 Second n-type semiconductor layer 249 Second active layer 249b Barrier layer of the second active layer 249w Well layer of the second active layer 250 Second p-type semiconductor layer 251 Second electron block layer 252 Second p-type clad layer 253 p-type contact layer 230 Protective film 260 Intermediate electrode layer 261 Dielectric part 263 p-type contact part 265 Electrode part 270 Bonding layer 271 Metal reflection layer 279 Metal bonding layer 280 Support substrate 291 Upper electrode 295 Back electrode

Claims

1. A first n-type semiconductor layer; an undoped first active layer; a p-type pseudo tunnel junction layer having a p-type dopant; an n-type pseudo tunnel junction layer having an n-type dopant provided in contact with the p-type pseudo tunnel junction layer; an undoped second active layer; A second p-type semiconductor layer; In this order, The maximum impurity concentration of the n-type dopant contained in the second active layer on the n-type pseudo tunnel junction layer side is 1.0×10 １６ atoms / cm ３ Characterized in that A double-stack type semiconductor light-emitting element.

2. Between the n-type pseudo tunnel junction layer and the second active layer, a Si impurity concentration of 5.0×10 １７ atoms / cm ３ Above 5.0 x 10 １８ atoms / cm ３ A second n-type semiconductor layer having the following structure: The double-stack type semiconductor light-emitting device according to claim 1 .

3. The average impurity concentration of the n-type dopant contained in the first active layer and the second active layer is 5.0×10 １５ atoms / cm ３ Below is the The double-stack type semiconductor light-emitting device according to claim 1 .

4. The n-type dopant doped into the n-type pseudo tunnel junction layer is Si. The double-stack type semiconductor light-emitting device according to claim 1 .

5. The p-type dopant doped into the p-type pseudo tunnel junction layer is C. The double-stack type semiconductor light-emitting device according to claim 1 .

6. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer is 1.5×10 １９ atoms / cm ３ That's all. The double-stack type semiconductor light-emitting device according to claim 1 .

7. The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer is 1.0×10 １９ atoms / cm ３ That's all. The double-stack type semiconductor light-emitting device according to claim 1 .

8. the first active layer, the second active layer, and the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer each contain AlGaInAs or InGaAsP; The double-stack type semiconductor light-emitting device according to claim 1 .

9. a current-voltage curve when a current is applied to the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer without passing through the first active layer and the second active layer has a point where the current is maximum in a range of 0.02 V or more and 0.2 V or less; The double-stack type semiconductor light-emitting device according to claim 1 .

10. a maximum current value is 7 mA or less in a current-voltage curve when a current is passed through the p-type pseudo tunnel junction layer and the n-type pseudo tunnel junction layer without passing through the first active layer and the second active layer; The double-stack type semiconductor light-emitting device according to claim 1 .

11. forming a first n-type semiconductor layer on a substrate; forming an undoped first active layer on the first n-type semiconductor layer; forming a p-type pseudo tunnel junction layer having a p-type dopant on the first active layer; forming an n-type pseudo tunnel junction layer having an n-type dopant directly on the p-type pseudo tunnel junction layer; forming an undoped second active layer on the n-type pseudo tunnel junction layer; forming a second p-type semiconductor layer on the second active layer; Equipped with The maximum impurity concentration of the n-type dopant contained in the second active layer on the n-type pseudo tunnel junction layer side is set to 1.0×10 １６ atoms / cm ３ To the following, A method for manufacturing a double-stack type semiconductor light-emitting device.

12. A support substrate; A bonding layer provided on the support substrate; an intermediate electrode layer provided on the bonding layer, the intermediate electrode layer having a dielectric portion and an electrode portion arranged in parallel; A second p-type semiconductor layer provided on the intermediate electrode layer; an undoped second active layer provided on the second p-type semiconductor layer; an n-type pseudo tunnel junction layer having an n-type dopant provided on the second active layer; a p-type pseudo tunnel layer having a p-type dopant provided on and in contact with the n-type pseudo tunnel junction layer; an undoped first active layer provided on the p-type pseudo tunnel layer; a first n-type semiconductor layer provided on the first active layer; an upper electrode provided on the first n-type semiconductor layer; Equipped with The maximum impurity concentration of the n-type dopant contained in the second active layer on the n-type pseudo tunnel junction layer side is 1.0×10 １６ atoms / cm ３ is less than or equal to A double-stack type semiconductor light-emitting element.

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