Semiconductor device, electronic component, and electronic apparatus

Abstract

Provided is a semiconductor device capable of efficiently reading weighting factors and efficiently performing multiply-accumulate operations. The semiconductor device comprises multiply-accumulate circuitry and a storage device. The multiply-accumulate circuitry is configured using transistors formed in a semiconductor substrate, and the memory cells of the storage device are configured using OS transistors that are provided so as to be layered above the semiconductor substrate. The semiconductor device comprises a plurality of multiply-accumulate units obtained by electrically connecting the multiply-accumulate circuitry to the memory cells of the storage device, wherein each multiply-accumulate unit reads weighting factors stored in memory cells, and can perform a multiply-accumulate operation.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device having a multiply-accumulate circuit and a memory device.

[0002] In this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics. For example, it refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. Further, in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, and an electronic device equipped with an integrated circuit are examples of semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Background Art

[0004] The multiply-accumulate operation is often used, for example, in calculations using neural networks. A neural network has a circuit configuration that mimics a neural network composed of neurons and synapses. A plurality of data are input to each neuron, and each data is multiplied by a "weight coefficient" representing the strength of the connection, and the results are added together. When the result of the multiply-accumulate operation thus obtained exceeds a threshold value, the neuron outputs a high-level signal, and this phenomenon is called "firing".

[0005] By using a neural network, which is an information processing system modeled after a neural network, it is expected that a computer with higher performance than that of a conventional Neumann-type computer can be realized. In recent years, various studies on constructing neural networks have been advanced.

[0006] A neural network is used, for example, in image recognition. In image recognition, a convolutional operation is performed to detect features of image data by multiplying and adding the parameters of a filter to the image data and repeating the same operation while sliding. The convolutional operation is performed multiple times. In the earlier convolutional operations, edges of the image are detected, and in the later convolutional operations, complex features such as the shape and pattern of the image are detected.

[0007] Patent Document 1 discloses an example in which machine learning using a neural network is performed using a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) to perform handwritten character recognition.

[0008] In recent years, transistors having an oxide semiconductor or a metal oxide in the channel formation region of a transistor (also referred to as an oxide semiconductor transistor or an OS (Oxide Semiconductor) transistor) have attracted attention. Since the drain current (also referred to as the off-current) when the transistor is in the off state is extremely small (see, for example, Non-Patent Documents 1 and 2), by using an OS transistor in a memory cell of a DRAM, the charge stored in the capacitance element can be held for a long time.

[0009] Patent Document 2 discloses an example of a semiconductor device having a plurality of memory cells using an OS transistor on a semiconductor substrate on which peripheral circuits such as a drive circuit and a control circuit are formed, and an example of applying an OS transistor to a memory cell of a DRAM (Dynamic Random Access Memory). For example, by configuring a peripheral circuit using an Si transistor formed on a single crystal silicon substrate and laminating and providing a memory cell using an OS transistor above it, the chip area can be reduced.

[0010] In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystals nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 3). Non-Patent Document 1 and Non-Patent Document 3 disclose techniques for fabricating transistors using oxide semiconductors having a CAAC structure.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0012]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0013] In image recognition, image data and filter parameters respectively correspond to a plurality of data input to neurons and weight coefficients in a neural network. Also, in the convolution operation in image recognition, a sum-of-products operation is performed.

[0014] The weight coefficients are generated, for example, by learning. The weight coefficients after learning are repeatedly used for a plurality of data input to neurons. Therefore, the weight coefficients are required to be processed with speed and efficiency in reading to a sum-of-products operation circuit rather than writing to a storage device.

[0015] One aspect of the present invention is to provide a semiconductor device having a sum-of-products operation circuit and a storage device, which can efficiently perform reading of weight coefficients and sum-of-products operations. Or, one aspect of the present invention is to provide a semiconductor device having a sum-of-products operation circuit and a storage device, which reduces the chip area.

[0016] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it suffices if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will be naturally clarified from the descriptions in the specification, claims, drawings, etc., and it is possible to extract these other problems from the descriptions in the specification, claims, drawings, etc.

Means for Solving the Problems

[0017] One embodiment of the present invention is a semiconductor device having a plurality of multiply-accumulate units. Each multiply-accumulate unit has a first circuit and a memory cell. The first circuit has a first transistor formed on a semiconductor substrate, and the memory cell has a second transistor including a metal oxide in a channel formation region. The second transistor is formed by being stacked above the first transistor, and the first circuit has a function of reading data stored in the memory cell and a function of performing a multiply-accumulate operation.

[0018] Also, one embodiment of the present invention is a semiconductor device having a word line driver circuit, a bit line driver circuit, and a multiply-accumulate block. The multiply-accumulate block has a plurality of multiply-accumulate units, and each multiply-accumulate unit has a first circuit and a memory cell. The first circuit has a first transistor formed on a semiconductor substrate, and the memory cell has a second transistor including a metal oxide in a channel formation region. The second transistor is formed by being stacked above the first transistor, and the word line driver circuit and the bit line driver circuit have a function of writing data to the memory cell, and the first circuit has a function of reading data stored in the memory cell and a function of performing a multiply-accumulate operation.

[0019] Also, one embodiment of the present invention is a semiconductor device having a word line driver circuit, a bit line driver circuit, and a multiply-accumulate block. The multiply-accumulate block has a plurality of multiply-accumulate units, and each multiply-accumulate unit has a first circuit and a memory cell. The word line driver circuit, the bit line driver circuit, and the first circuit each have a first transistor formed on a semiconductor substrate, and the memory cell has a second transistor including a metal oxide in a channel formation region. The second transistor is formed by being stacked above the first transistor, and the word line driver circuit and the bit line driver circuit have a function of writing data to the memory cell, and the first circuit has a function of reading data stored in the memory cell and a function of performing a multiply-accumulate operation.

[0020] Also, in the above embodiment, the metal oxide contains at least one of In or Zn.

Advantages of the Invention

[0021] According to one embodiment of the present invention, there is provided a semiconductor device having a multiplication and accumulation circuit and a storage device, which can efficiently perform reading of weight coefficients and multiplication and accumulation operations. Alternatively, according to one embodiment of the present invention, there is provided a semiconductor device having a multiplication and accumulation circuit and a storage device, which can reduce the chip area.

[0022] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will be naturally revealed from the descriptions in the specification, claims, drawings, etc., and it is possible to extract these other problems from the descriptions in the specification, claims, drawings, etc.

Brief Description of the Drawings

[0023] FIG. 1 is a schematic perspective view showing a configuration example of a semiconductor device. FIG. 2A is a schematic perspective view showing a configuration example of a multiplication and accumulation block. FIG. 2B is a schematic perspective view showing a configuration example of a multiplication and accumulation unit. FIG. 3 is a circuit diagram showing a configuration example of a multiplication and accumulation unit. FIG. 4A is a circuit diagram showing a configuration example of circuit 15. FIG. 4B is a timing chart. FIG. 5A is a diagram showing an image of data signal X and data signal W. FIG. 5B is a diagram showing an image of image data P. FIG. 5C is a diagram showing an image of filter F. FIG. 6 is a cross-sectional view showing a configuration example of a storage device. FIGS. 7A to 7C are cross-sectional views showing a structural example of a transistor. FIG. 8A is a top view showing a structural example of a transistor. FIGS. 8B and 8C are cross-sectional views showing a structural example of a transistor. FIG. 9A is a top view showing a structural example of a transistor. FIGS. 9B and 9C are cross-sectional views showing a structural example of a transistor. FIG. 10A is a top view showing an example of the structure of a transistor. FIGS. 10B and 10C are cross-sectional views showing an example of the structure of a transistor. FIG. 11A is a top view showing an example of the structure of a transistor. FIGS. 11B and 11C are cross-sectional views showing an example of the structure of a transistor. FIG. 12A is a top view showing an example of the structure of a transistor. FIGS. 12B and 12C are cross-sectional views showing an example of the structure of a transistor. FIG. 13A is a top view showing an example of the structure of a transistor. FIGS. 13B and 13C are cross-sectional views showing an example of the structure of a transistor. FIGS. 14A and 14B are cross-sectional views showing an example of the structure of a transistor. FIG. 15 is a cross-sectional view showing an example of the configuration of a memory device. FIGS. 16A and 16B are cross-sectional views showing an example of the structure of a transistor. FIG. 17A is a diagram for explaining the classification of the crystal structure of IGZO. FIG. 17B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film. FIG. 17C is a diagram for explaining the nanoelectron diffraction pattern of a CAAC-IGZO film. FIG. 18A is a top view of a semiconductor wafer. FIG. 18B is a top view of a chip. FIG. 19A is a flowchart for explaining an example of the manufacturing process of an electronic component. FIG. 19B is a perspective schematic diagram of an electronic component. FIGS. 20A and 20B are diagrams for explaining the configuration of an electronic device. FIGS. 21A and 21B are diagrams for explaining the configuration of an electronic device.

Embodiments for Carrying Out the Invention

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different forms, and it will be easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and scope. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0025] Moreover, the multiple embodiments described below can be combined as appropriate. Also, when multiple configuration examples are shown within one embodiment, the configuration examples can be combined with each other as appropriate.

[0026] Note that in the drawings attached to this specification, the components are classified by function and shown as independent blocks in a block diagram. However, in reality, it is difficult to completely separate the components by function, and one component may be related to multiple functions.

[0027] Also, in the drawings and the like, the size, layer thickness, area, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.

[0028] Also, in the drawings and the like, the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously may be given the same reference numerals, and the repeated description may be omitted.

[0029] Also, in this specification and the like, the term "film" and the term "layer" can be interchanged with each other. For example, in some cases, the term "conductive layer" can be changed to the term "conductive film". Or, for example, in some cases, the term "insulating film" can be changed to the term "insulating layer".

[0030] Also, in this specification and the like, terms indicating arrangements such as "above" and "below" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", those including other components between the gate insulating layer and the gate electrode are not excluded.

[0031] Also, in this specification and the like, ordinal numbers such as "first", "second", "third", etc. are attached to avoid confusion of the components and do not numerically limit them.

[0032] Also, in this specification and the like, when the same reference numeral is used for a plurality of elements, particularly when it is necessary to distinguish them, the reference numeral may be described with an identification symbol such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL is described as wiring GL[2].

[0033] Also, in this specification and the like, "electrically connected" includes the case where it is connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitance elements, and other elements having various functions. Also, even when expressed as "electrically connected", in an actual circuit, there may be a case where there is no physical connection part and only the wiring extends.

[0034] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa.

[0035] Also, in this specification and the like, the "terminal" in an electric circuit refers to a part where current or potential is input (or output), or a signal is received (or transmitted). Therefore, a part of a wiring or an electrode may function as a terminal.

[0036] Generally, a "capacitance element" has a configuration in which two electrodes face each other via an insulator (dielectric). Also, in this specification and the like, the "capacitance element" includes not only those having a configuration in which two electrodes face each other via an insulator, but also those having a configuration in which two wirings face each other via an insulator, or those in which two wirings are arranged via an insulator. Also, in this specification and the like, the "capacitance element" may be referred to as a "capacitor", a "capacitator", or a "capacitance".

[0037] In addition, in this specification and the like, the term "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage and potential difference can be used interchangeably.

[0038] In addition, in this specification and the like, a transistor is an element having at least three terminals including a source, a drain, and a gate. And it has a channel formation region between the source (source terminal, source region, or source electrode) and the drain (drain terminal, drain region, or drain electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0039] Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes in a circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

[0040] In addition, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state, unless otherwise specified, for an n-channel type transistor, is a state where the gate voltage Vgs with respect to the source is lower than the threshold voltage Vth, and for a p-channel type transistor, is a state where the gate voltage Vgs with respect to the source is higher than the threshold voltage Vth. That is, the off-current of an n-channel type transistor may refer to the drain current when the gate voltage Vgs with respect to the source is lower than the threshold voltage Vth.

[0041] In the description of the off-current, the drain and the source may be read as each other. That is, the off-current may refer to the source current when the transistor is in the off state. Also, in the same sense as the off-current, it may be referred to as the leakage current. Further, in this specification and the like, the off-current may refer to the current flowing between the source and the drain when the transistor is in the off state.

[0042] Also, in this specification and the like, the on-current may refer to the current flowing between the source and the drain when the transistor is in the on state (also referred to as the conducting state).

[0043] Also, in this specification and the like, the metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like.

[0044] For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the metal oxide has at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be called a metal oxide semiconductor. That is, a transistor having a metal oxide in the channel formation region can be called an "oxide semiconductor transistor" or an "OS transistor". Similarly, a "transistor using an oxide semiconductor" is also a transistor having a metal oxide in the channel formation region.

[0045] Also, in this specification and the like, a metal oxide having nitrogen may also be referred to as a metal oxide. Also, a metal oxide having nitrogen may be referred to as a metal oxynitride. Details of the metal oxide will be described later.

[0046] (Embodiment 1) In this embodiment, a configuration example and an operation example of a semiconductor device according to one aspect of the present invention will be described. The semiconductor device according to one aspect of the present invention includes a multiply-accumulate circuit and a storage device. Further, the semiconductor device according to one aspect of the present invention has a structure in which a layer having OS transistors is laminated above a layer having transistors formed on a semiconductor substrate. The OS transistor has a property that its off-current is extremely small.

[0047] <Perspective schematic view of a semiconductor device> FIG. 1 is a perspective schematic view showing a configuration example of a semiconductor device 100 according to one aspect of the present invention. The semiconductor device 100 shown in FIG. 1 has a layer 101 and a layer 102, and has a structure in which the layer 102 is laminated above the layer 101. Circuits that can function by utilizing semiconductor characteristics are provided in the layer 101 and the layer 102, respectively. In the drawings described in this specification and the like, the main signal flow is indicated by arrows or lines, and power supply lines and the like may be omitted.

[0048] The semiconductor device 100 includes a word line driver circuit 111, a bit line driver circuit 112, and a multiply-accumulate block 113. The word line driver circuit 111 and the bit line driver circuit 112 are provided in the layer 101, and the multiply-accumulate block 113 is provided across the layer 101 and the layer 102.

[0049] The word line driver circuit 111 and the bit line driver circuit 112 are configured using transistors formed on a semiconductor substrate SUB. The semiconductor substrate SUB is not particularly limited as long as it can form a channel region of a transistor. For example, a single crystal silicon substrate, a single crystal germanium substrate, a compound semiconductor substrate (such as a SiC substrate or a GaN substrate), an SOI (Silicon on Insulator) substrate, or the like can be used.

[0050] As the SOI substrate, for example, after implanting oxygen ions into a mirror-polished wafer and then performing high-temperature heating, a SIMOX (Separation by Implanted Oxygen) substrate formed by forming an oxide layer to a certain depth from the surface and eliminating defects generated in the surface layer, or a smart cut method of splitting a semiconductor substrate by utilizing the growth by heat treatment of microvoids formed by hydrogen ion implantation, an SOI substrate formed using the ELTRAN method (registered trademark: Epitaxial Layer Transfer), etc. can be used. Further, a transistor formed using a single crystal substrate has a single crystal semiconductor in the channel formation region.

[0051] The product-sum operation block 113 is configured using transistors formed on the semiconductor substrate SUB and OS transistors. Since the OS transistors can be formed using a technique such as a thin film method, they can be stacked and provided on the semiconductor substrate SUB. That is, in layer 101, a circuit is configured using transistors formed on the semiconductor substrate SUB, and in layer 102, a circuit is configured using OS transistors.

[0052] In this embodiment, an example using a single crystal silicon substrate for the semiconductor substrate SUB will be described. A transistor formed on the single crystal silicon substrate is called an Si transistor. A circuit configured using Si transistors can operate at high speed.

[0053] By configuring the product-sum operation block 113 using Si transistors and OS transistors, the chip area of the semiconductor device 100 can be reduced (the semiconductor device 100 can be miniaturized) compared to the case of configuring using only Si transistors. Further, since the OS transistors can be fabricated using the same manufacturing equipment as Si transistors, low-cost fabrication is possible.

[0054] Here, since the band gap of the oxide semiconductor is 2.5 eV or more, preferably 3.0 eV or more, the OS transistor has the property that the leakage current due to thermal excitation is small and the off-current is extremely small. Note that the off-current refers to the current flowing between the source and the drain when the transistor is in the off state.

[0055] The metal oxide used for the channel formation region of the OS transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). As such an oxide semiconductor, In-M-Zn oxide (element M is one or more selected from, for example, Al, Ga, Y, and Sn) is typical. By reducing impurities such as moisture and hydrogen that serve as electron donors (donors) and also reducing oxygen deficiency, the oxide semiconductor can be made into an i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be called a highly purified oxide semiconductor. Details of the OS transistor will be described in Embodiment 2 and Embodiment 3.

[0056] Also, as shown in FIG. 1, the word line driver circuit 111 provided in layer 101 and the portion provided in layer 102 of the sum-of-products operation block 113 are electrically connected by wiring WL. Similarly, the bit line driver circuit 112 provided in layer 101 and the portion provided in layer 102 of the sum-of-products operation block 113 are electrically connected by wiring BL.

[0057] In this embodiment, an example in which the word line driver circuit 111 and the bit line driver circuit 112 are configured using Si transistors has been described, but they may also be configured using OS transistors.

[0058] <Configuration example of sum-of-products operation block> FIG. 2A is a perspective schematic diagram showing a configuration example of the sum-of-products operation block 113. The sum-of-products operation block 113 has m×n sum-of-products operation units 10, wiring WL, and wiring BL (m and n are integers of 1 or more).

[0059] As shown in FIG. 2A, m product-sum operation units 10 are arranged in a matrix (also referred to as a matrix shape) with m units in a column and n units in a row. [1,1], [m,1], [1,n], and [m,n] shown in FIG. 2A indicate the addresses of the product-sum operation units 10. Each product-sum operation unit 10 is electrically connected to wiring WL and wiring BL.

[0060] Further, the product-sum operation unit 10 is provided across layer 101 and layer 102. The part provided in layer 102 of the product-sum operation unit 10 is called circuit MEM, and the part provided in layer 101 of the product-sum operation unit 10 is called circuit MAC.

[0061] FIG. 2B is a perspective schematic view showing a configuration example of the product-sum operation unit 10. In the product-sum operation unit 10, circuit MEM and circuit MAC are electrically connected by wiring WS and wiring WO.

[0062] FIG. 3 is a circuit diagram showing a configuration example of the product-sum operation unit 10. The product-sum operation unit 10 includes circuit MEM, circuit MAC, wiring REF, wiring PC, wiring RD, wiring DX, wiring DA, wiring DB, wiring CX, s pieces of wiring WS, and t pieces of wiring WO (s and t are integers of 1 or more).

[0063] Circuit MEM and circuit MAC are electrically connected via s pieces of wiring WS and t pieces of wiring WO. Also, as shown in FIG. 3, among the wiring WL and wiring BL included in the product-sum operation block 113, s pieces of wiring WL and t pieces of wiring BL are arranged in circuit MEM.

[0064] <Configuration Example of Circuit MEM> Circuit MEM includes t precharge circuits 12 and s×t memory cells 11. The s memory cells 11 in a column and the t memory cells 11 in a row are arranged in a matrix. [1,1], [s,1], [1,t], and [s,t] shown in FIG. 3 indicate the addresses of the memory cells 11.

[0065] In the drawings described in this specification and the like, when there are a plurality of components such as the precharge circuit 12 and the memory cell 11, the details of a circuit diagram or the like may be illustrated for one of them, and the details may be omitted for the others. For example, in FIG. 3, a circuit diagram is illustrated for the memory cell 11[1,1], and the circuit diagrams for the memory cells 11[s,1], 11[1,t], and 11[s,t] are omitted.

[0066] The memory cell 11 is electrically connected to the wiring WS and the wiring WO. When k is an integer from 1 to s and l is an integer from 1 to t, the memory cell 11[k,l] is electrically connected to the wiring WS[k] and the wiring WO[l] (k and l are not shown). Further, the memory cell 11[k,l] is electrically connected to the wiring WL[k] and the wiring BL[l].

[0067] Similarly, the precharge circuit 12 is electrically connected to the wiring WO, and the precharge circuit 12[l] is electrically connected to the wiring WO[l]. Further, the precharge circuit 12 is electrically connected to the wiring REF and the wiring PC.

[0068] The precharge circuit 12 has a transistor 25 and has a function of precharging the wiring WO. One of the source or drain of the transistor 25 is electrically connected to the wiring REF, the other of the source or drain of the transistor 25 is electrically connected to the wiring WO, and the gate of the transistor 25 is electrically connected to the wiring PC. That is, when a high-level potential is applied to the wiring PC, the transistor 25 is turned on, and the precharge circuit 12 has a function of precharging the wiring WO with the potential supplied to the wiring REF.

[0069] Memory cell 11 includes transistors 21 to 23 and capacitor 24. One of the source or drain of transistor 21 is electrically connected to wiring BL, the other of the source or drain of transistor 21 is electrically connected to the gate of transistor 22 and one electrode of capacitor 24, and the gate of transistor 21 is electrically connected to wiring WL. One of the source or drain of transistor 22 is electrically connected to one of the source or drain of transistor 23, and the other of the source or drain of transistor 23 is electrically connected to wiring WO.

[0070] Also, the other of the source or drain of transistor 22 is electrically connected to a reference potential, and the other electrode of capacitor 24 is electrically connected to, for example, the reference potential. Note that the connection portion between the other of the source or drain of transistor 21, the gate of transistor 22, and one electrode of capacitor 24 is referred to as node N1.

[0071] Memory cell 11 has a function of storing data by accumulating and holding charges. Memory cell 11 has a function of storing, for example, binary (high level or low level) data. In the present embodiment, the low level is represented using the aforementioned reference potential. Also, a potential representing the high level can be supplied to wiring REF.

[0072] In memory cell 11, data writing is performed using wiring BL and wiring WL. When writing data to memory cell 11, wiring BL functions as a bit line, wiring WL functions as a word line, and transistor 21 functions as a switch that makes the one electrode of capacitor 24 and wiring BL conductive or non-conductive. Data writing is performed by applying a high level potential to wiring WL, making the one electrode of capacitor 24 and wiring BL conductive, and writing the potential of wiring BL to node N1.

[0073] In memory cell 11, data is read using wiring WO, wiring WS, and precharge circuit 12. When reading data from memory cell 11, transistor 22 becomes conductive or non-conductive depending on the potential of node N1, and transistor 23 functions as a switch that makes either the source or drain of transistor 22 and wiring WO conductive or non-conductive.

[0074] To read data, after applying a high-level potential (the potential supplied to wiring REF) to wiring WO using precharge circuit 12, wiring WO is put in a floating state (electrically floating state), a high-level potential is applied to wiring WS, and either the source or drain of transistor 22 and wiring WO are made conductive. That is, when the potential of node N1 is high, transistor 22 is conductive and wiring WO becomes low level (reference potential). When the potential of node N1 is low, transistor 22 is non-conductive and wiring WO remains at a high level.

[0075] Here, transistors 21 to 23 and transistor 25 are transistors having a metal oxide in the channel formation region (OS transistors). For example, a metal oxide having any one of indium, element M (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), or zinc can be used in the channel formation region of transistor 21. In particular, a metal oxide composed of indium, gallium, and zinc is preferable.

[0076] Since the off-current of the OS transistor is extremely small, by using the OS transistor for transistor 21, memory cell 11 can hold the charge stored in capacitance 24 for a long time. Or, by using the OS transistor for transistor 21, even if the capacitance value of capacitance 24 of memory cell 11 is reduced, the charge stored in capacitance 24 can be held. Also, the off-current of the OS transistor hardly increases even in a high-temperature environment, and memory cell 11 can be made into a highly reliable memory cell.

[0077] Also, transistor 21 to transistor 23 and transistor 25 may have a back gate. For example, when transistor 21 has a back gate, the threshold voltage of transistor 21 can be increased or decreased by applying a predetermined potential to the back gate of transistor 21. Or, by electrically connecting the back gate of transistor 21 to the gate of transistor 21, the on-current of transistor 21 can be increased.

[0078] Also, capacitance 24 has a structure in which an insulator is sandwiched between conductors serving as electrodes. As the conductor constituting the electrode, in addition to metal, a semiconductor imparted with conductivity can be used.

[0079] <Configuration Example of Circuit MAC> Circuit MAC includes a decoder circuit 13, a register circuit 14, t circuits 15, a multiplication circuit 16, an addition circuit 17, a register circuit 18, and t wirings WT. Note that multiplication circuit 16 and addition circuit 17 constitute a multiply-accumulate circuit.

[0080] The circuit MAC can be configured, for example, with a CMOS (Complementary Metal Oxide Semiconductor) circuit using Si transistors. The CMOS circuit is configured, for example, using an n-channel transistor and a p-channel transistor formed on a single-crystalline silicon substrate, and is widely used as a circuit (also called a digital circuit or a logic circuit) that handles digital signals represented by a high level or a low level (which may be represented as High or Low, H or L, 1 or 0, etc.).

[0081] Note that signals having an information amount of a plurality of bits may be input to the wiring DX, the wiring DA, and the wiring CX. For example, the signal input to the wiring DX can be a signal having an information amount of 8 bits, 16 bits, 32 bits, or 64 bits.

[0082] The decoder circuit 13 is electrically connected to the wiring CX and s pieces of wiring WS, and has a function of decoding the signal input to the wiring CX and driving the s pieces of wiring WS. More specifically, the decoder circuit 13 selects one from the wiring WS[1] to the wiring WS[s] according to the signal input to the wiring CX, and applies a high-level potential to the selected wiring WS.

[0083] The register circuit 14 is electrically connected to the wiring DX, and has a function of temporarily holding the signal input to the wiring DX. The register circuit 14 holds the signal input to the wiring DX and outputs it to the multiplication circuit 16.

[0084] Regarding a configuration example of the circuit 15, a circuit diagram is shown in FIG. 4A. The circuit 15 includes inverters 41 to 43, transistors 44 to 47, a wiring VD, and a wiring VS.

[0085] One of the source or drain of transistor 44 is electrically connected to wiring VD, and the other of the source or drain of transistor 44 is electrically connected to one of the source or drain of transistor 45. The other of the source or drain of transistor 45 is electrically connected to one of the source or drain of transistor 46, the input terminal of inverter 42, and the output terminal of inverter 41. The other of the source or drain of transistor 46 is electrically connected to one of the source or drain of transistor 47, and the other of the source or drain of transistor 47 is electrically connected to wiring VS.

[0086] The gate of transistor 44 is electrically connected to the output terminal of inverter 43. The gate of transistor 45 is electrically connected to the gate of transistor 46 and wiring WO. The gate of transistor 47 is electrically connected to the input terminal of inverter 43 and wiring RD. Also, the output terminal of inverter 42 is electrically connected to the input terminal of inverter 41 and wiring WT.

[0087] A high power supply potential VDD is supplied to wiring VD, and a low power supply potential VSS is supplied to wiring VS. Note that the low power supply potential VSS may be used as a reference potential in semiconductor device 100.

[0088] In circuit 15, when a high level potential is applied to wiring RD, inverter 43 outputs a low level potential. Therefore, transistors 44 and 47 are turned on, and transistors 45 and 46 function as inverters. Also, inverters 41 and 42 form an inverter loop and have a memory function. Therefore, circuit 15 acquires the potential state (high level or low level) of wiring WO when a high level potential is applied to wiring RD, holds it by inverters 41 and 42, and has a function of outputting it to wiring WT.

[0089] The signal output to the wiring WT is multiplied by the signal output from the register circuit 14 in the multiplication circuit 16 and then output to the addition circuit 17. The addition circuit 17 adds the signal output from the multiplication circuit 16 and the signal input to the wiring DA, and outputs the result to the register circuit 18. The register circuit 18 temporarily holds the signal output from the addition circuit 17 and outputs it to the outside of the multiply-accumulate unit 10 via the wiring DB.

[0090] Note that since the decoder circuit, register circuit, multiplication circuit, and addition circuit are respectively known as decoder circuits, register circuits, multiplication circuits, and addition circuits each composed of CMOS circuits, their descriptions are omitted.

[0091] <Multiply-accumulate unit> Here, let the signal input to the wiring DX be the data signal X, the signal input to the wiring DA be the data signal A, and the signal output to the wiring DB be the data signal B. Also, let the signals output to the t wirings WT (wirings WT[1] to WT[t]) be the data signal W. Then, the multiply-accumulate unit 10 has the function of outputting the data signal B, and it can be said that the data signal B is the result of multiplying the data signal X by the data signal W and then adding the data signal A.

[0092] Also, since the circuit MEM has s×t memory cells 11, the circuit MEM has the function of storing the data signals W[1] to W[s] in the memory cells 11. The data signals W[1] to W[s] can be read out at time intervals by driving the wirings WS[1] to WS[s].

[0093] For example, regarding the case of reading the data signals W[1] to W[3] out to the wiring WT among the data signals W[1] to W[s], a timing chart is shown in FIG. 4B. FIG. 4B is a timing chart showing the potential states (high level or low level) of the wiring PC, the wirings WS[1] to WS[3], the wiring RD, the wiring WO, and the wiring WT at times T1 to T9.

[0094] As shown in FIG. 4B, at time T1, the wiring PC becomes high level, and the wiring WO is precharged at a high level potential. When the wiring WS[1] becomes high level at time T2, the wiring WO assumes a potential state corresponding to the data stored in the memory cells 11[1,1] to 11[1,t] (denoted as W[1] in FIG. 4B). When the wiring RD becomes high level at time T3, the potential state of the wiring WO is output to the wiring WT.

[0095] Also, at time T4, the wiring PC becomes high level, and the wiring WO is precharged at a high level potential. When the wiring WS[2] becomes high level at time T5, the wiring WO assumes a potential state corresponding to the data stored in the memory cells 11[2,1] to 11[2,t] (denoted as W[2] in FIG. 4B). When the wiring RD becomes high level at time T6, the potential state of the wiring WO is output to the wiring WT. Since the same applies from time T7 to time T9, the description is omitted.

[0096] Regarding the data signal X and the data signal A as well, by preparing a plurality of data signals X and a plurality of data signals A and inputting them into the sum-of-products operation unit 10 at time intervals, a plurality of sum-of-products operations can be performed.

[0097] For example, by preparing s data signals X (data signal X[1] to data signal X[s]) and s data signals A (data signal A[1] to data signal A[s]), multiplying each of the data signals X[1] to X[s] by the data signals W[1] to W[s] read from the memory cell 11, and adding the data signals A[1] to A[s], s data signals B (data signal B[1] to data signal B[s]) can be obtained. That is, when k is an integer from 1 to s, the data signal B[k] = data signal X[k] × data signal W[k] + data signal A[k].

[0098] Furthermore, by inputting the data signal B[k] into the data signal A[k + 1] and setting the data signal A[1] to 0, the data signal B = data signal X[1] × data signal W[1] + data signal X[2] × data signal W[2] + (omitted in the middle) + data signal X[s - 1] × data signal W[s - 1] + data signal X[s] × data signal W[s] can be obtained.

[0099] For example, when s = 9, the data signal X can be a 3-row × 3-column data signal, and the data signal W can be a 3-row × 3-column data signal. An image diagram of the data signal X and the data signal W in the case of s = 9 is shown in FIG. 5A. In this case, the data signal B = data signal X[1] × data signal W[1] + data signal X[2] × data signal W[2] + (omitted in the middle) + data signal X[8] × data signal W[8] + data signal X[9] × data signal W[9] can be used, for example, for a convolution operation on image data.

[0100] <Convolution operation> Next, an example of a convolution operation on image data is shown. The p-row q-column image data is represented by image data P(1, 1) to P(p, q) (p and q are integers greater than or equal to 2), and the u-row v-column filter is represented by filter F(1, 1) to F(u, v) (u and v are integers greater than or equal to 1, and u < p, v < q). The image data P(1, 1) to P(p, q) are image data corresponding to one pixel each, and the filters F(1, 1) to F(u, v) are the parameters constituting the filter respectively. An image diagram of the image data P is shown in FIG. 5B, and an image diagram of the filter F is shown in FIG. 5C.

[0101] For example, when p = q = 3 and u = v = 2, the following Y(1, 1) to Y(2, 2) are calculated. Y(1, 1) = P(1, 1) × F(1, 1) + P(1, 2) × F(1, 2) + P(2, 1) × F(2, 1) + P(2, 2) × F(2, 2) (a1) Y(1, 2) = P(1, 2) × F(1, 1) + P(1, 3) × F(1, 2) + P(2, 2) × F(2, 1) + P(2, 3) × F(2, 2) (a2) Y(2, 1) = P(2, 1) × F(1, 1) + P(2, 2) × F(1, 2) + P(3, 1) × F(2, 1) + P(3, 2) × F(2, 2) (a3) Y(2, 2) = P(2, 2) × F(1, 1) + P(2, 3) × F(1, 2) + P(3, 2) × F(2, 1) + P(3, 3) × F(2, 2) (a4)

[0102] When expressing formulas a1 to a4 in a general formula, Y(x, y) = Σa(ΣbP(a + x - 1, b + y - 1) × F(a, b)) (a5) Here, a is an integer from 1 to u, b is an integer from 1 to v, x is an integer from 1 to p - u + 1, and y is an integer from 1 to q - v + 1. For example, when calculating Y(1, 1), a sum-of-products operation is performed on the image data P in region 50 shown in FIG. 5B.

[0103] The convolution operation on the image data is performed by calculating Y(1, 1) to Y(u, v) using the sum-of-products operation. By performing the convolution operation on the image data, for example, edges of the image can be detected. Also, by performing the convolution operation multiple times, features of the image data such as the shape and pattern of the image can be detected, and such a convolution operation is used in image recognition.

[0104] The memory cell 11 of the sum-of-products operation unit 10 stores the parameters of the filter F, and by inputting the image data P to the data signal X, the sum-of-products operation unit 10 can perform the convolution operation. The parameters of the filter F used in the convolution operation are generated, for example, by learning, and the parameters of the filter F after learning are repeatedly used. In the sum-of-products operation unit 10, in terms of repeatedly using the parameters of the filter F by taking out the parameters of the filter F as the data signal W using the wiring WS and the wiring WO that each sum-of-products operation unit 10 has, the sum-of-products operation unit 10 is efficient.

[0105] Note that the convolution operation may be performed using a plurality of multiply-accumulate units 10. Since the image data P and the filter F are two-dimensional data, for example, for the filter F(1, 1) to F(u, v) of u rows and v columns, the filter F(1, 1) to F(1, v) is stored in the multiply-accumulate unit 10[1, 1], the filter F(2, 1) to F(2, v) is stored in the multiply-accumulate unit 10[2, 1], (omitted in the middle), and the filter F(u, 1) to F(u, v) can be stored in the multiply-accumulate unit 10[u, 1] (assuming m >= u). In this case, the multiply-accumulate operation for the image data P(1, 1) to P(1, v) is performed by the multiply-accumulate unit 10[1, 1], the multiply-accumulate operation for the image data P(2, 1) to P(2, v) is performed by the multiply-accumulate unit 10[2, 1], (omitted in the middle), and the multiply-accumulate operation for the image data P(u, 1) to P(u, v) can be performed by the multiply-accumulate unit 10[u, 1], and Y(1, 1) can be calculated by adding up the results.

[0106] Also, in this embodiment, an example of using the multiply-accumulate unit 10 for the convolution operation on image data is shown. However, the multiply-accumulate operation is frequently used in neural networks that mimic neural circuit networks composed of neurons and synapses, and the multiply-accumulate unit 10 can also be used in neural networks. When the multiply-accumulate unit 10 is used in a neural network, the parameters of the filter F correspond to weight coefficients, and the multiply-accumulate unit 10 can efficiently use the weight coefficients by storing the weight coefficients in the memory cell 11.

[0107] A semiconductor device 100 according to an aspect of the present invention has a layer having an OS transistor laminated above a layer having transistors formed on a semiconductor substrate, and a memory cell is configured using the OS transistor. Since the OS transistor has a very small off-current, the memory cell configured using the OS transistor can hold the stored data for a long time.

[0108] Also, a multiply-accumulate circuit is configured using transistors formed on a semiconductor substrate, and the multiply-accumulate circuit is electrically connected via a wiring WS and a wiring WO to a memory cell provided by being stacked upward. The semiconductor device 100 has a plurality of multiply-accumulate units 10 each combining a multiply-accumulate circuit and a memory cell. In each of the multiply-accumulate units 10, by reading out the parameters (or weight coefficients) of the filter F stored in the memory cell, a convolution operation (or a calculation using a neural network) can be efficiently performed. The semiconductor device 100 can be suitably used for a convolution operation in which the parameters of the filter F are repeatedly used (or a calculation of a neural network in which the weight coefficients are repeatedly used).

[0109] Since the memory cell is stacked and provided above the multiply-accumulate circuit in the semiconductor device 100, the semiconductor device 100 is small in size. Since the off-current of the OS transistor hardly increases even in a high-temperature environment, a highly reliable memory cell can be obtained with respect to the heat generation of the multiply-accumulate circuit. Further, since the OS transistor can be manufactured using the same manufacturing equipment as that of the Si transistor, the semiconductor device 100 can be manufactured at low cost.

[0110] Note that this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0111] (Embodiment 2) In this embodiment, a configuration example of a transistor that constitutes the semiconductor device 100 described in the above embodiment will be described. In this embodiment, a configuration example of a semiconductor device having a structure in which a layer having an OS transistor is stacked and provided above a layer having an Si transistor formed on a single-crystalline silicon substrate will be described.

[0112] <Configuration Example of Semiconductor Device> The semiconductor device shown in FIG. 6 includes a transistor 300, a transistor 500, and a capacitor element 600. FIG. 7A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 7B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 7C is a cross-sectional view of the transistor 300 in the channel width direction.

[0113] For example, the transistor 500 corresponds to the transistor 21 shown in the above embodiment. The transistor 500 has a second gate (also referred to as a bottom gate or a back gate) in addition to a first gate (also referred to as a top gate or simply a gate). Further, the transistor 300 corresponds to, for example, the transistor 47 included in the semiconductor device 100, and the capacitor element 600 corresponds to the capacitor 24.

[0114] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. Since the transistor 500 has characteristics such that the off-current is very small and the off-current is difficult to increase even in a high-temperature environment, in the above embodiment, by using this in the semiconductor device 100, the semiconductor device can be made a highly reliable semiconductor device.

[0115] As shown in FIG. 6, in the semiconductor device described in this embodiment, the transistor 500 is provided above the transistor 300, and the capacitor element 600 is provided above the transistor 300 and the transistor 500.

[0116] The transistor 300 is provided on a substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region.

[0117] As shown in FIG. 7C, in the transistor 300, the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. Thus, by making the transistor 300 a Fin type, the effective channel width is increased, thereby improving the on characteristics of the transistor 300. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

[0118] Note that the transistor 300 may be either a p-channel type or an n-channel type.

[0119] In the region where the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or the drain region, i.e., the low-resistance regions 314a and 314b, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is more preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs, GaAlAs, or the like, the transistor 300 may be a HEMT (High Electron Mobility Transistor).

[0120] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0121] As the conductor 316 that functions as a gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material that includes an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron can be used.

[0122] Note that since the work function is determined by the material of the conductor, the Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to use a laminated metal material such as tungsten or aluminum for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0123] Note that the transistor 300 shown in FIG. 6 is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and driving method.

[0124] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially laminated and provided covering the transistor 300.

[0125] As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0126] The insulator 322 may have a function as a planarization film that planarizes the step generated by the transistor 300 or the like provided below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0127] Also, for the insulator 324, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse into the region where the transistor 500 is provided from the substrate 311 or the transistor 300 or the like.

[0128] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by CVD method can be used. Here, when hydrogen diffuses into a semiconductor device having an oxide semiconductor such as transistor 500, the characteristics of the semiconductor device may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between transistor 500 and transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0129] The amount of hydrogen desorption can be analyzed using, for example, the temperature-programmed desorption gas analysis (TDS analysis) method. For example, the amount of hydrogen desorption of insulator 324 is such that in TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, per unit area of insulator 324, is 10×10 15 atoms / cm 2 Hereinafter, preferably 5×10 15 atoms / cm 2 or less is sufficient.

[0130] Note that insulator 326 preferably has a lower relative dielectric constant than insulator 324. For example, the relative dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of insulator 324. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0131] Also, capacitor element 600, or conductor 328 and conductor 330 etc. that are connected to transistor 500 are embedded in insulator 320, insulator 322, insulator 324, and insulator 326. Note that conductor 328 and conductor 330 have the function of a plug or a wiring. Also, conductors having the function of a plug or a wiring may be given the same reference numeral collectively for a plurality of structures. Also, in this specification etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0132] As materials for each plug and wiring (such as conductor 328 and conductor 330), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used alone or in a laminated manner. It is preferable to use high melting point materials such as tungsten and molybdenum that can achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0133] A wiring layer may be provided on insulator 326 and conductor 330. For example, in FIG. 6, insulator 350, insulator 352, and insulator 354 are laminated and provided in sequence. Also, conductor 356 is formed on insulator 350, insulator 352, and insulator 354. Conductor 356 has the function of a plug connected to transistor 300 or wiring. Note that conductor 356 can be provided using the same materials as conductor 328 and conductor 330.

[0134] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for insulator 350 in the same manner as insulator 324. Also, conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 350 having a barrier property against hydrogen. With this configuration, transistor 300 and transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0135] Note that, as a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Also, by laminating tantalum nitride having a barrier property against hydrogen and tungsten having high conductivity, the diffusion of hydrogen from transistor 300 can be suppressed while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0136] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 6, the insulator 360, the insulator 362, and the insulator 364 are sequentially stacked and provided. Further, the conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using the same materials as the conductor 328 and the conductor 330.

[0137] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 360 as in the case of the insulator 324. Further, the conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0138] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. 6, the insulator 370, the insulator 372, and the insulator 374 are sequentially stacked and provided. Further, the conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or a wiring. Note that the conductor 376 can be provided using the same materials as the conductor 328 and the conductor 330.

[0139] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 370. Further, conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 370 having a barrier property against hydrogen. With this configuration, transistor 300 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0140] A wiring layer may be provided on insulator 374 and conductor 376. For example, in FIG. 6, insulators 380, 382, and 384 are stacked and provided in this order. Further, conductor 386 is formed in insulators 380, 382, and 384. Conductor 386 has a function as a plug or wiring. Note that conductor 386 can be provided using the same materials as conductor 328 and conductor 330.

[0141] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 380. Further, conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 380 having a barrier property against hydrogen. With this configuration, transistor 300 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0142] In the above, the wiring layers including conductor 356, the wiring layer including conductor 366, the wiring layer including conductor 376, and the wiring layer including conductor 386 have been described, but the semiconductor device according to the present embodiment is not limited to this. The number of wiring layers similar to the wiring layer including conductor 356 may be three or less, or may be five or more.

[0143] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked and provided. Any one of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a material that is barrier against oxygen and hydrogen.

[0144] For example, for the insulator 510 and the insulator 514, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse from, for example, the substrate 311 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, the same material as that of the insulator 324 can be used.

[0145] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0146] Also, as a film having a barrier property against hydrogen, for example, for the insulator 510 and the insulator 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0147] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0148] Also, for example, the same material as that of the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by using a material with a relatively low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 512 and the insulator 516.

[0149] Also, conductors such as the conductor 518 and the conductor (conductor 503) constituting the transistor 500 are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 has a function as a plug connected to the capacitor element 600 or the transistor 300, or a wiring. The conductor 518 can be provided using the same material as that of the conductor 328 and the conductor 330.

[0150] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0151] A transistor 500 is provided above the insulator 516.

[0152] As shown in FIGS. 7A and 7B, the transistor 500 includes a conductor 503 disposed to be embedded in insulators 514 and 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed by overlapping between the conductors 542a and 542b, a conductor 560 disposed in the opening, an insulator 550 disposed between the oxide 530b, the conductors 542a and 542b, and the insulator 580, and the conductor 560, and an oxide 530c disposed between the oxide 530b, the conductors 542a and 542b, and the insulator 580, and the insulator 550.

[0153] Also, as shown in FIGS. 7A and 7B, it is preferable that an insulator 544 is disposed between the oxides 530a, 530b, the conductors 542a and 542b, and the insulator 580. Also, as shown in FIGS. 7A and 7B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 550 and a conductor 560b provided to be embedded inside the conductor 560a. Also, as shown in FIGS. 7A and 7B, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550.

[0154] Hereinafter, the oxides 530a, 530b, and 530c may be collectively referred to as the oxide 530. Also, the conductors 542a and 542b may be collectively referred to as the conductor 542.

[0155] Note that, in the transistor 500, a structure in which three layers of the oxide 530a, the oxide 530b, and the oxide 530c are laminated in the region where the channel is formed and in its vicinity is shown, but the present invention is not limited thereto. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a laminated structure of four or more layers may be provided. Also, in the transistor 500, the conductor 560 is shown as a two-layer laminated structure, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers. Further, the transistor 500 shown in FIGS. 6, 7A, and 7B is an example, and the present invention is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0156] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, so that the occupied area of the transistor 500 can be reduced. As a result, miniaturization and high integration of the semiconductor device can be achieved.

[0157] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductors 542a and 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be obtained.

[0158] The conductor 560 may function as a first gate electrode. Further, the conductor 503 may function as a second gate electrode. In that case, by changing the potential applied to the conductor 503 independently without linking it to the potential applied to the conductor 560, the Vth of the transistor 500 can be controlled. In particular, by applying a negative potential to the conductor 503, the Vth of the transistor 500 can be made greater than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0 V than when no negative potential is applied.

[0159] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Thereby, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, the structure of a transistor in which a channel formation region is electrically surrounded by the electric fields of a first gate electrode and a second gate electrode is called a surrounded channel (S-channel) structure.

[0160] Further, in this specification and the like, the S-channel structure has the feature that the side surface and periphery of the oxide 530 in contact with the conductors 542a and 542b that function as source and drain electrodes are of the same I-type as the channel formation region. Also, since the side surface and periphery of the oxide 530 in contact with the conductors 542a and 542b are in contact with the insulator 544, they can be of the I-type similar to the channel formation region. In this specification and the like, the I-type can be treated in the same manner as high-purity intrinsic described later. Also, the S-channel structure disclosed in this specification and the like is different from the Fin-type structure and the planar-type structure. By adopting the S-channel structure, the resistance to the short-channel effect can be enhanced, in other words, a transistor in which the short-channel effect is less likely to occur can be obtained.

[0161] Also, the conductor 503 has the same configuration as the conductor 518, and a conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b is further formed inside.

[0162] The insulator 520, the insulator 522, the insulator 524, and the insulator 550 have a function as a gate insulating film.

[0163] Here, it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition for the insulator 524 in contact with the oxide 530. That is, it is preferable that an excess oxygen region is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved.

[0164] Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material in which some oxygen is desorbed by heating. The oxide that desorbs oxygen by heating means that in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0165] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0166] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, so that the oxygen in the oxide 530 does not diffuse to the insulator 520 side. Further, the conductor 503 can be prevented from reacting with the oxygen in the insulator 524 and the oxide 530.

[0167] The insulator 522 is preferably a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0168] In particular, it is advisable to use an insulator containing one or both of the oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (difficult for the above-mentioned oxygen to permeate). As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0169] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above-mentioned insulator and used.

[0170] Also, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0171] Note that the insulator 520, the insulator 522, and the insulator 524 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0172] For the transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Also, an In-Ga oxide or an In-Zn oxide may be used as the oxide 530.

[0173] Note that the formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. The metal oxide that functions as an oxide semiconductor will be described in other embodiments.

[0174] Also, for the transistor 500, it is preferable to use a metal oxide having a low carrier density. When reducing the carrier density of the metal oxide, the impurity concentration in the metal oxide may be lowered and the density of defect levels may be lowered. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high purity intrinsic or substantially high purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0175] In particular, hydrogen contained in the metal oxide may react with oxygen bonded to the metal atom to form water, thereby forming oxygen vacancies in the metal oxide. If the channel formation region in the metal oxide contains oxygen vacancies, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors, and electrons as carriers may be generated. Also, a part of hydrogen may bond with oxygen bonded to the metal atom to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics.

[0176] Defects in which hydrogen enters the oxygen vacancies can function as donors of the metal oxide. However, it is difficult to quantitatively evaluate such defects. Therefore, in the metal oxide, it may be evaluated by carrier density instead of donor density. Thus, in this specification and the like, as a parameter of the metal oxide, carrier density assuming a state where no electric field is applied may be used instead of donor density. That is, the "carrier density" described in this specification and the like may be paraphrased as "donor density" in some cases.

[0177] Therefore, when using the metal oxide for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using a metal oxide with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0178] In addition, when a metal oxide is used for the oxide 530, the carrier density of the metal oxide in the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 even more preferably less than 1×10 16 cm -3 even more preferably less than 1×10 13 cm -3 even more preferably less than 1×10 12 cm -3 even more preferably less than that. Note that the lower limit value of the carrier density of the metal oxide in the channel formation region is not particularly limited, but for example, it can be 1×10 -9 cm -3

[0179] In addition, when a metal oxide is used for the oxide 530, oxygen in the oxide 530 may diffuse into the conductor 542 (conductor 542a and conductor 542b), and the conductor 542 may be oxidized. When the conductor 542 is oxidized, there is a high probability that the conductivity of the conductor 542 will decrease. Note that the diffusion of oxygen in the oxide 530 into the conductor 542 can be rephrased as the conductor 542 absorbing oxygen in the oxide 530.

[0180] In addition, when oxygen in the oxide 530 diffuses into the conductor 542 (conductor 542a and conductor 542b), a heterolayer may be formed between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b. Since the heterolayer contains more oxygen than the conductor 542, it is presumed that the heterolayer has insulating properties. At this time, the three-layer structure of the conductor 542, the heterolayer, and the oxide 530b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly composed of a MIS structure.

[0181] ​Note that the different layers are not limited to being formed between the conductor 542 and the oxide 530b. For example, the different layers may be formed between the conductor 542 and the oxide 530c, or may be formed between the conductor 542 and the oxide 530b and between the conductor 542 and the oxide 530c.

[0182] Also, as the metal oxide that functions as the channel formation region in the oxide 530, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0183] In addition, the semiconductor materials that can be used for the oxide 530 are not limited to the above-mentioned metal oxides. As the oxide 530, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use semiconductor materials such as single-element semiconductors like silicon, compound semiconductors like gallium arsenide, and layer-like substances that function as semiconductors (also referred to as atomic layer substances, two-dimensional materials, etc.). In particular, it is suitable to use a layer-like substance that functions as a semiconductor as the semiconductor material.

[0184] Here, in this specification and the like, the layer-like substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer-like substance has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0185] Examples of the layer material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, a chalcogen is a general term for elements belonging to Group 16 and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0186] As the oxide 530, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 530 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0187] By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b. Also, by having the oxide 530c on the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b.

[0188] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a. Further, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0189] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinities of the oxide 530a and the oxide 530c are smaller than the electron affinity of the oxide 530b.

[0190] Here, at the junction of the oxide 530a, the oxide 530b, and the oxide 530c, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is continuously joined. To achieve this, it is advisable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c.

[0191] Specifically, by having the oxide 530a, the oxide 530b, and the oxide 530c have a common element other than oxygen (as the main component), a mixed layer with a low defect level density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a and the oxide 530c.

[0192] At this time, the main path of carriers becomes the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the defect level density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0193] On the oxide 530b, conductors 542 (conductor 542a and conductor 542b) that function as a source electrode and a drain electrode are provided. As the conductor 542, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0194] Also, as shown in FIG. 7A, regions 543 (regions 543a and 543b) may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542 and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0195] By providing the conductor 542 so as to be in contact with the oxide 530, the oxygen concentration in region 543 may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542 and the components of the oxide 530 may be formed in region 543. In such a case, the carrier density in region 543 increases, and region 543 becomes a low-resistance region.

[0196] The insulator 544 is provided so as to cover the conductor 542 and suppresses the oxidation of the conductor 542. At this time, the insulator 544 may cover the side surface of the oxide 530 and be provided so as to be in contact with the insulator 524.

[0197] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0198] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing one or both of aluminum or hafnium oxides. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in a later process. Note that when the conductor 542 is made of a material having oxidation resistance or the conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0199] The insulator 550 functions as a gate insulating film. The insulator 550 is preferably disposed in contact with the inner side (upper surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that releases oxygen upon heating. For example, in TDS analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less.

[0200] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0201] By providing an insulator that releases oxygen upon heating as the insulator 550 in contact with the upper surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 through the oxide 530c to the channel formation region of the oxide 530b. Also, similar to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0202] In addition, in order to efficiently supply the excess oxygen in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0203] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 7A and 7B, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0204] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0205] In addition, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. In addition, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0206] The insulator 580 is provided on the conductor 542 via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later process.

[0207] Further, by providing the insulator 580 that releases oxygen by heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0208] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. Thereby, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0209] When miniaturizing the semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 may have a high aspect ratio shape. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a high aspect ratio shape, it can be formed without collapsing the conductor 560 during the process.

[0210] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0211] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0212] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0213] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0214] Also, the conductors 540a and 540b are disposed in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductors 546 and 548 described later.

[0215] An insulator 582 is provided on an insulator 581. It is preferable to use a material that is barrier - resistant to oxygen and hydrogen for the insulator 582. Therefore, the same material as that of the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0216] In particular, aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the intrusion of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0217] An insulator 586 is provided on the insulator 582. The same material as that of the insulator 320 can be used for the insulator 586. Also, by using a material with a relatively low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, etc. can be used as the insulator 586.

[0218] Conductors 546 and 548, etc. are embedded in the insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0219] The conductors 546 and 548 have functions as plugs connected to the capacitor element 600, the transistor 500, or the transistor 300, or as wirings. The conductors 546 and 548 can be provided using the same materials as the conductors 328 and 330.

[0220] Subsequently, a capacitive element 600 is provided above the transistor 500. The capacitive element 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0221] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug connected to the transistor 500 or a wiring. The conductor 610 functions as an electrode of the capacitive element 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0222] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the above-described elements can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0223] In FIG. 6, the conductor 612 and the conductor 610 are shown as a single-layer structure, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, between a conductor having barrier properties and a conductor having high conductivity, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed.

[0224] A conductor 620 is provided so as to overlap with a conductor 610 via an insulator 630. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. When forming simultaneously with other structures such as conductors, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

[0225] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. Further, the insulator 650 may function as a planarization film that covers the uneven shape thereunder.

[0226] By using this structure, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor having an oxide semiconductor with a large on-current can be provided. Alternatively, a transistor having an oxide semiconductor with a small off-current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0227] <Structural example of transistor> Note that the transistor 500 of the semiconductor device described in this embodiment is not limited to the above structure. Structural examples that can be used for the transistor 500 will be described below.

[0228] <Structural example 1 of transistor> A structural example of a transistor 510A will be described with reference to FIGS. 8A, 8B, and 8C. FIG. 8A is a top view of the transistor 510A. FIG. 8B is a cross-sectional view of a portion indicated by a one-dot chain line L1-L2 in FIG. 8A. FIG. 8C is a cross-sectional view of a portion indicated by a one-dot chain line W1-W2 in FIG. 8A. Note that in the top view of FIG. 8A, some elements are omitted for clarity of the drawing.

[0229] In FIGS. 8A, 8B, and 8C, transistor 510A, and insulators 511, 512, 514, 516, 580, 582, and 584 that function as interlayer films are shown. Also shown are conductors 546 (conductor 546a and conductor 546b) that are electrically connected to transistor 510A and function as contact plugs, and conductor 503 that functions as wiring.

[0230] Transistor 510A includes conductors 560 (conductor 560a and conductor 560b) that function as a first gate electrode, conductors 505 (conductor 505a and conductor 505b) that function as a second gate electrode, insulator 550 that functions as a first gate insulating film, insulators 521, 522, and 524 that function as a second gate insulating film, oxides 530 (oxide 530a, oxide 530b, and oxide 530c) having a region where a channel is formed, conductor 542a that functions as one of a source or a drain, conductor 542b that functions as the other of the source or the drain, and insulator 574.

[0231] Also, in transistor 510A shown in FIG. 8, oxide 530c, insulator 550, and conductor 560 are disposed via insulator 574 within an opening provided in insulator 580. Also, oxide 530c, insulator 550, and conductor 560 are disposed between conductor 542a and conductor 542b.

[0232] Insulators 511 and 512 function as interlayer films.

[0233] As the interlayer film, insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used alone or in a stacked layer. Or, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators and used.

[0234] For example, the insulator 511 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, it is preferable to use an insulating material for the insulator 511 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Or, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Also, for example, aluminum oxide, silicon nitride, etc. may be used as the insulator 511. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side rather than through the insulator 511.

[0235] For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0236] The conductor 503 is formed to be embedded in the insulator 512. Here, the height of the upper surface of the conductor 503 and the height of the upper surface of the insulator 512 can be made approximately the same. Although the conductor 503 is shown as a single-layer structure, the present invention is not limited to this. For example, the conductor 503 may have a multi-layer film structure of two or more layers. In addition, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503.

[0237] In the transistor 510A, the conductor 560 may function as a first gate electrode. Also, the conductor 505 may function as a second gate electrode. In that case, by changing the potential applied to the conductor 505 independently without linking it to the potential applied to the conductor 560, the threshold voltage of the transistor 510A can be controlled. In particular, by applying a negative potential to the conductor 505, the threshold voltage of the transistor 510A can be made greater than 0V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 505 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0238] Also, for example, by providing the conductor 505 and the conductor 560 in a superimposed manner, when a potential is applied to the conductor 560 and the conductor 505, the electric field generated from the conductor 560 and the electric field generated from the conductor 505 can be connected to cover the channel formation region formed in the oxide 530.

[0239] That is, the channel formation region can be electrically surrounded by the electric field of the conductor 560 having the function of the first gate electrode and the electric field of the conductor 505 having the function of the second gate electrode. That is, it has a surrounded channel (S-channel) structure similar to the transistor 500 described above.

[0240] The insulators 514 and 516 function as interlayer films, similar to the insulator 511 or the insulator 512. For example, the insulator 514 preferably functions as a barrier film that suppresses the intrusion of impurities such as water or hydrogen from the substrate side into the transistor 510A. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side through the insulator 514. Also, for example, the insulator 516 preferably has a lower dielectric constant than the insulator 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0241] The conductor 505 that functions as the second gate has a conductor 505a formed in contact with the inner walls of the openings of the insulators 514 and 516, and a conductor 505b further formed inside. Here, the heights of the upper surfaces of the conductor 505a and the conductor 505b can be made approximately the same as the height of the upper surface of the insulator 516. Note that in the transistor 510A, a configuration in which the conductor 505a and the conductor 505b are laminated is shown, but the present invention is not limited to this. For example, the conductor 505 may be provided in a single-layer or a laminated structure of three or more layers.

[0242] Here, for the conductor 505a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that in this specification and the like, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0243] For example, when the conductor 505a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 505b and the decrease in conductivity.

[0244] Also, when the conductor 505 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 505b. In that case, the conductor 503 does not necessarily have to be provided. Although the conductor 505b is illustrated as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the above-mentioned conductive material.

[0245] The insulators 521, 522, and 524 have a function as a second gate insulating film.

[0246] Also, the insulator 522 preferably has a barrier property. Since the insulator 522 has a barrier property, it functions as a layer that suppresses the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 510A into the transistor 510A.

[0247] For the insulator 522, it is preferable to use, for example, a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0248] Also, the insulator 521 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 521 with a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0249] Note that in FIG. 8, a three-layer stacked structure is shown as the second gate insulating film, but a stacked structure of two layers or less or four layers or more may be used. In that case, it is not limited to a stacked structure made of the same material, and a stacked structure made of different materials may also be used.

[0250] The oxide 530 having a region that functions as a channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. By having the oxide 530a under the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a into the oxide 530b can be suppressed. Also, by having the oxide 530c on the oxide 530b, diffusion of impurities from a structure formed above the oxide 530c into the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor which is one of the metal oxides described above can be used.

[0251] Note that the oxide 530c is preferably provided in an opening provided in the insulator 580 via the insulator 574. When the insulator 574 has a barrier property, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.

[0252] One side of the conductor 542 functions as a source electrode and the other side functions as a drain electrode.

[0253] As the conductor 542a and the conductor 542b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy mainly composed of this can be used. In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and high oxidation resistance.

[0254] In addition, although a single-layer structure was shown in FIG. 8, a laminated structure of two or more layers may also be used. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may also be used.

[0255] In addition, there is a three-layer structure in which a titanium film or a titanium nitride film is provided, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film is provided, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon, and the like. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0256] Also, a barrier layer may be provided on the conductor 542. It is preferable to use a material having barrier properties against oxygen or hydrogen for the barrier layer. With this configuration, oxidation of the conductor 542 can be suppressed when forming the insulator 574.

[0257] For the barrier layer, for example, a metal oxide can be used. In particular, it is preferable to use an insulating film having barrier properties against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Also, silicon nitride formed by CVD may be used.

[0258] By having a barrier layer, the range of material selection for the conductor 542 can be widened. For example, for the conductor 542, a material having low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used. Also, for example, a conductor that is easy to film or process can be used.

[0259] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably provided in an opening provided in the insulator 580 via the oxide 530c and the insulator 574.

[0260] As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. In that case, the insulator 550 may have a laminated structure, similar to the second gate insulating film. By forming an insulator that functions as a gate insulating film into a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a laminated structure that is thermally stable and has a high relative permittivity can be formed.

[0261] The conductor 560 that functions as a first gate electrode has a conductor 560a and a conductor 560b on the conductor 560a. For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms, similar to the conductor 505a. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0262] Since the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0263] As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, an oxide semiconductor that can be used as the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0264] The conductor 560b preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560 functions as a wiring, it is preferable to use a conductor with high conductivity for the conductor 560b. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductor 560b may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material may be used.

[0265] An insulator 574 is disposed between the insulator 580 and the transistor 510A. The insulator 574 is preferably made of an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can also be used.

[0266] By having the insulator 574, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 to the oxide 530b through the oxide 530c and the insulator 550. Further, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen contained in the insulator 580.

[0267] The insulator 580, the insulator 582, and the insulator 584 function as interlayer films.

[0268] Similar to the insulator 514, the insulator 582 preferably functions as a barrier insulating film that suppresses the entry of impurities such as water or hydrogen from the outside into the transistor 510A.

[0269] Also, similar to the insulator 516, the insulator 580 and the insulator 584 preferably have a lower dielectric constant than the insulator 582. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0270] Further, the transistor 510A may be electrically connected to other structures via plugs and wirings such as the conductor 546 embedded in the insulator 580, the insulator 582, and the insulator 584.

[0271] Also, as the material of the conductor 546, similar to the conductor 505, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used alone or in a stacked manner. For example, it is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity. Alternatively, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0272] For example, as the conductor 546, by using a laminated structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity, the diffusion of impurities from the outside can be suppressed while maintaining the conductivity as a wiring.

[0273] By having the above structure, a transistor having an oxide semiconductor with a large on-current can be provided. Alternatively, a transistor having an oxide semiconductor with a small off-current can be provided. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved.

[0274] <Structural Example 2 of Transistor> A structural example of the transistor 510B will be described with reference to FIGS. 9A, 9B, and 9C. FIG. 9A is a top view of the transistor 510B. FIG. 9B is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 9A. FIG. 9C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. 9A. In the top view of FIG. 9A, some elements are omitted for clarity of the figure.

[0275] Transistor 510B is a modified example of transistor 510A. Therefore, to avoid repeating the description, mainly the differences from transistor 510A will be described.

[0276] Transistor 510B has a region where the conductor 542 (conductor 542a and conductor 542b), the oxide 530c, the insulator 550, and the conductor 560 overlap. By adopting such a structure, a transistor with a high on-current can be provided. Also, a transistor with high controllability can be provided.

[0277] The conductor 560 that functions as the first gate electrode has the conductor 560a and the conductor 560b on the conductor 560a. Similar to the conductor 505a, it is preferable to use a conductive material for the conductor 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0278] Since the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, the oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0279] Also, it is preferable to provide an insulator 574 so as to cover the upper surface and side surfaces of the conductor 560, the side surfaces of the insulator 550, and the side surfaces of the oxide 530c. The insulator 574 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Also, among others, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0280] By providing the insulator 574, oxidation of the conductor 560 can be suppressed. Also, by having the insulator 574, diffusion of impurities such as water and hydrogen that the insulator 580 has into the transistor 510B can be suppressed.

[0281] Also, an insulator 576 (insulator 576a and insulator 576b) having a barrier property may be disposed between the conductor 546 and the insulator 580. By providing the insulator 576, reaction of oxygen in the insulator 580 with the conductor 546 and oxidation of the conductor 546 can be suppressed.

[0282] Also, by providing the insulator 576 having a barrier property, the range of material selection for the conductor used for the plug or wiring can be widened. For example, by using a metal material that has a property of absorbing oxygen while having high conductivity for the conductor 546, a semiconductor device with low power consumption can be provided. Specifically, materials with low oxidation resistance but high conductivity such as tungsten and aluminum can be used. Also, for example, a conductor that is easy to form a film or process can be used.

[0283] <Structural Example 3 of Transistor> A structural example of the transistor 510C will be described with reference to FIGS. 10A, 10B, and 10C. FIG. 10A is a top view of the transistor 510C. FIG. 10B is a cross-sectional view of the portion indicated by the dashed line L1 - L2 in FIG. 10A. FIG. 10C is a cross-sectional view of the portion indicated by the dashed line W1 - W2 in FIG. 10A. In the top view of FIG. 10A, some elements are omitted for clarity of the figure.

[0284] The transistor 510C is a modified example of the transistor 510A. Therefore, to avoid repetition of the explanation, mainly the differences from the transistor 510A will be described.

[0285] The transistor 510C shown in FIG. 10 has a conductor 547a disposed between a conductor 542a and an oxide 530b, and a conductor 547b disposed between a conductor 542b and the oxide 530b. Here, the conductor 542a (conductor 542b) extends beyond the upper surface of the conductor 547a (conductor 547b) and the side surface on the conductor 560 side, and has a region in contact with the upper surface of the oxide 530b. Here, as the conductor 547, a conductor that can be used for the conductor 542 may be used. Further, the film thickness of the conductor 547 is preferably at least thicker than that of the conductor 542.

[0286] By having the configuration as described above, the transistor 510C shown in FIG. 10 can bring the conductor 542 closer to the conductor 560 than the transistor 510A. Alternatively, the ends of the conductor 542a and the conductor 542b can overlap with the conductor 560. Thereby, the substantial channel length of the transistor 510C can be shortened, and the on-current and frequency characteristics can be improved.

[0287] Also, the conductor 547a (conductor 547b) is preferably provided so as to overlap with the conductor 542a (conductor 542b). With such a configuration, in the etching for forming an opening for embedding the conductor 546a (conductor 546b), the conductor 547a (conductor 547b) can function as a stopper, and over-etching of the oxide 530b can be prevented.

[0288] Also, the transistor 510C shown in FIG. 10 may be configured such that an insulator 545 is disposed in contact with the insulator 544. As the insulator 544, it is preferably a barrier insulating film that suppresses impurities such as water or hydrogen and excess oxygen from entering the transistor 510C from the insulator 580 side. As the insulator 545, an insulator that can be used for the insulator 544 can be used. Further, as the insulator 544, for example, a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon oxynitride may be used.

[0289] Further, unlike the transistor 510A shown in FIG. 8, the transistor 510C shown in FIG. 10 may have a single-layer structure for the conductor 505. In this case, an insulating film that becomes the insulator 516 may be formed on the patterned conductor 505, and the upper portion of the insulating film may be removed using, for example, the CMP method until the upper surface of the conductor 505 is exposed. Here, it is preferable to improve the flatness of the upper surface of the conductor 505. For example, the average surface roughness (Ra) of the upper surface of the conductor 505 may be set to 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. Thereby, the flatness of the insulating layer formed on the conductor 505 can be improved, and the crystallinity of the oxide 530b and the oxide 530c can be enhanced.

[0290] <Structural Example 4 of Transistor> A structural example of the transistor 510D will be described with reference to FIGS. 11A, 11B, and 11C. FIG. 11A is a top view of the transistor 510D. FIG. 11B is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 11A. FIG. 11C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. 11A. Note that, in the top view of FIG. 11A, some elements are omitted for clarity of the drawing.

[0291] The transistor 510D is a modified example of the above-described transistor. Therefore, to avoid redundant explanations, mainly the differences from the above-described transistor will be explained.

[0292] In FIGS. 11A to 11C, the conductor 505 having the function of the second gate also functions as a wiring without providing the conductor 503. Further, an insulator 550 is provided on the oxide 530c, and a metal oxide 552 is provided on the insulator 550. Further, a conductor 560 is provided on the metal oxide 552, and an insulator 570 is provided on the conductor 560. Further, an insulator 571 is provided on the insulator 570.

[0293] The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing a metal oxide 552 that suppresses oxygen diffusion between the insulator 550 and the conductor 560, the diffusion of oxygen into the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 by oxygen can be suppressed.

[0294] Note that the metal oxide 552 may have a function as part of the first gate. For example, an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552. In that case, by forming the conductor 560 by sputtering, the electrical resistance value of the metal oxide 552 can be reduced to form a conductive layer. This can be called an OC (Oxide Conductor) electrode.

[0295] In addition, the metal oxide 552 may function as part of the gate insulating film. Therefore, when silicon oxide, silicon oxynitride, etc. are used for the insulator 550, it is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant, as the metal oxide 552. By adopting such a stacked structure, a stacked structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, it is possible to thin the equivalent oxide film thickness (EOT) of the insulating layer that functions as the gate insulating film.

[0296] In the transistor 510D, the metal oxide 552 is shown as a single layer, but it may have a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulating film may be stacked and provided.

[0297] By having the metal oxide 552, when functioning as a gate electrode, it is possible to improve the on-current of the transistor 510D without weakening the influence of the electric field from the conductor 560. Or, when functioning as a gate insulating film, by maintaining the distance between the conductor 560 and the oxide 530 based on the physical thickness of the insulator 550 and the metal oxide 552, the leakage current between the conductor 560 and the oxide 530 can be suppressed. Therefore, by providing a laminated structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the electric field strength applied from the conductor 560 to the oxide 530 can be easily adjusted as appropriate.

[0298] Specifically, as the metal oxide 552, it can be used by reducing the resistance of the oxide semiconductor that can be used for the oxide 530. Or, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0299] In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulating layers containing one or both of aluminum and hafnium oxides. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in the heat treatment in the subsequent process. Note that the metal oxide 552 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0300] The insulator 570 may be made of an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Thereby, oxidation of the conductor 560 by oxygen from above the insulator 570 can be suppressed. In addition, it is possible to suppress impurities such as water or hydrogen from above the insulator 570 from mixing into the oxide 530 through the conductor 560 and the insulator 550.

[0301] The insulator 571 functions as a hard mask. By providing the insulator 571, when processing the conductor 560, the side surface of the conductor 560 can be made substantially perpendicular, specifically, the angle between the side surface of the conductor 560 and the substrate surface can be set to 75 degrees or more and 100 degrees or less, preferably 80 degrees or more and 95 degrees or less.

[0302] Note that, by using an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen for the insulator 571, it may also function as a barrier layer. In that case, the insulator 570 may not be provided.

[0303] By selectively removing a part of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c using the insulator 571 as a hard mask, these side surfaces can be made substantially coincident, and a part of the surface of the oxide 530b can be exposed.

[0304] Further, the transistor 510D has a region 531a and a region 531b on a part of the exposed surface of the oxide 530b. One of the region 531a or the region 531b functions as a source region, and the other functions as a drain region.

[0305] The formation of region 531a and region 531b can be achieved, for example, by introducing impurity elements such as phosphorus or boron into the exposed surface of oxide 530b using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment. Note that in this embodiment and the like, the "impurity element" refers to an element other than the main component element.

[0306] Alternatively, after partially exposing the surface of oxide 530b, a metal film is formed, and then heat treatment is performed to diffuse the elements contained in the metal film into oxide 530b to form region 531a and region 531b.

[0307] In the region where the impurity elements of oxide 530b are introduced, the electrical resistivity decreases. Therefore, region 531a and region 531b may be referred to as "impurity regions" or "low-resistance regions".

[0308] By using insulator 571 and / or conductor 560 as a mask, region 531a and region 531b can be formed self-alignedly. Therefore, region 531a and / or region 531b do not overlap with conductor 560, and the parasitic capacitance can be reduced. Also, no offset region is formed between the channel formation region and the source / drain region (region 531a or region 531b). By forming region 531a and region 531b self-alignedly, an increase in on-current, a reduction in threshold voltage, an improvement in operating frequency, etc. can be realized.

[0309] In addition, in order to further reduce the off-current, an offset region may be provided between the channel formation region and the source / drain regions. The offset region is a region with a high electrical resistivity and is a region where the introduction of the above-described impurity elements is not performed. The formation of the offset region can be realized by introducing the above-described impurity elements after the formation of the insulator 575. In this case, the insulator 575 also functions as a mask in the same manner as the insulator 571 or the like. Therefore, impurity elements are not introduced into the region overlapping with the insulator 575 of the oxide 530b, and the electrical resistivity of the region can be kept high.

[0310] Further, the transistor 510D has an insulator 575 on the side surfaces of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c. The insulator 575 is preferably an insulator with a low relative permittivity. For example, it is preferably silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or a resin. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide with pores for the insulator 575 because an excess oxygen region can be easily formed in the insulator 575 in a later process. Further, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Also, the insulator 575 preferably has a function of diffusing oxygen.

[0311] Further, the transistor 510D has an insulator 574 on the insulator 575 and the oxide 530. The insulator 574 is preferably formed by a sputtering method. By using the sputtering method, an insulator with few impurities such as water or hydrogen can be formed. For example, aluminum oxide may be used as the insulator 574.

[0312] Note that the oxide film formed by the sputtering method may extract hydrogen from the film-forming structure. Therefore, by the insulator 574 absorbing hydrogen and water from the oxide 530 and the insulator 575, the hydrogen concentration of the oxide 530 and the insulator 575 can be reduced.

[0313] <Structure Example 5 of Transistor> The structure example of the transistor 510E will be described with reference to FIGS. 12A to 12C. FIG. 12A is a top view of the transistor 510E. FIG. 12B is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 12A. FIG. 12C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. 12A. In the top view of FIG. 12A, some elements are omitted for clarity of the drawing.

[0314] The transistor 510E is a modified example of the above transistor. Therefore, to prevent repetition of the description, mainly the differences from the above transistor will be described.

[0315] In FIGS. 12A to 12C, without providing the conductor 542, the region 531a and the region 531b are provided on a part of the exposed surface of the oxide 530b. One of the region 531a or the region 531b functions as a source region, and the other functions as a drain region. Also, an insulator 573 is provided between the oxide 530b and the insulator 574.

[0316] The region 531 (the region 531a and the region 531b) shown in FIG. 12 is a region in which the following elements are added to the oxide 530b. The region 531 can be formed, for example, by using a dummy gate.

[0317] Specifically, a dummy gate may be provided on the oxide 530b, and the dummy gate may be used as a mask to add an element for reducing the resistance of the oxide 530b. That is, the element is added to the region where the oxide 530 does not overlap with the dummy gate, and the region 531 is formed. As a method for adding the element, an ion implantation method in which an ionized source gas is mass-separated and added, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used.

[0318] Typical examples of the element for reducing the resistance of the oxide 530 include boron or phosphorus. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gases, etc. may be used. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. The concentration of the element may be measured using secondary ion mass spectrometry (SIMS) or the like.

[0319] In particular, boron and phosphorus are preferable because the equipment of a manufacturing line such as low-temperature polysilicon can be used. Existing equipment can be diverted, and capital investment can be suppressed.

[0320] Subsequently, an insulating film that becomes the insulator 573 and an insulating film that becomes the insulator 574 may be formed on the oxide 530b and the dummy gate. By laminating and providing the insulating film that becomes the insulator 573 and the insulating film that becomes the insulator 574, a region where the region 531 overlaps with the oxide 530c and the insulator 550 can be provided.

[0321] Specifically, after providing an insulating film that becomes insulator 580 on an insulating film that becomes insulator 574, by performing CMP (Chemical Mechanical Polishing) treatment on the insulating film that becomes insulator 580, a part of the insulating film that becomes insulator 580 is removed to expose the dummy gate. Subsequently, when removing the dummy gate, a part of insulator 573 in contact with the dummy gate may also be removed. Therefore, insulator 574 and insulator 573 are exposed on the side surface of the opening provided in insulator 580, and a part of region 531 provided in oxide 530b is exposed on the bottom surface of the opening. Next, after sequentially forming an oxide film that becomes oxide 530c, an insulating film that becomes insulator 550, and a conductive film that becomes conductor 560 in the opening, by removing a part of the oxide film that becomes oxide 530c, the insulating film that becomes insulator 550, and the conductive film that becomes conductor 560 by CMP treatment or the like until insulator 580 is exposed, the transistor shown in FIG. 12 can be formed.

[0322] Note that insulator 573 and insulator 574 are not essential components. They may be appropriately designed according to the required transistor characteristics.

[0323] The transistor shown in FIG. 12 can utilize an existing device, and furthermore, since conductor 542 is not provided, cost reduction can be achieved.

[0324] <Structural Example 6 of Transistor> A structural example of transistor 510F will be described with reference to FIGS. 13A to 13C. FIG. 13A is a top view of transistor 510F. FIG. 13B is a cross-sectional view of the portion indicated by the dashed line L1 - L2 in FIG. 13A. FIG. 13C is a cross-sectional view of the portion indicated by the dashed line W1 - W2 in FIG. 13A. In the top view of FIG. 13A, some elements are omitted for clarity of the drawing.

[0325] Transistor 510F is a modified example of transistor 510A. Therefore, to avoid repetition of the description, mainly the differences from the above transistor will be described.

[0326] In the transistor 510A, a part of the insulator 574 is provided in an opening provided in the insulator 580 and is provided so as to cover the side surface of the conductor 560. On the other hand, in the transistor 510F, an opening is formed by removing a part of the insulator 580 and the insulator 574.

[0327] Further, a barrier insulator 576 (insulator 576a and insulator 576b) may be disposed between the conductor 546 and the insulator 580. By providing the insulator 576, it is possible to suppress the reaction between the oxygen of the insulator 580 and the conductor 546 and the oxidation of the conductor 546.

[0328] When an oxide semiconductor is used as the oxide 530, it preferably has a stacked structure of a plurality of oxide layers having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M in the constituent elements is preferably larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a. Further, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0329] Oxide 530a, oxide 530b, and oxide 530c preferably have crystallinity, and in particular, it is preferable to use CAAC-OS. Oxides having crystallinity such as CAAC-OS have few impurities and defects (such as oxygen deficiencies) and have a dense structure with high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from oxide 530b by the source electrode or the drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 530b can be reduced, so transistor 510F is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0330] Note that one or both of oxide 530a and oxide 530c may be omitted. Oxide 530 may be a single layer of oxide 530b. When oxide 530 is a laminate of oxide 530a, oxide 530b, and oxide 530c, it is preferable that the energy of the lower end of the conduction band of oxide 530a and oxide 530c is higher than the energy of the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b. In this case, it is preferable to use a metal oxide that can be used for oxide 530a for oxide 530c. Specifically, in the metal oxide used for oxide 530c, it is preferable that the atomic ratio of element M in the constituent elements is larger than the atomic ratio of element M in the constituent elements in the metal oxide used for oxide 530b. Also, in the metal oxide used for oxide 530c, it is preferable that the atomic ratio of element M to In is larger than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Further, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is larger than the atomic ratio of In to element M in the metal oxide used for oxide 530c.

[0331] Here, the energy level of the conduction band minimum changes gradually at the junction of the oxide 530a, the oxide 530b, and the oxide 530c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

[0332] Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element other than oxygen (as a main component), so that a mixed layer with a low defect level density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like. The oxide 530c may also have a laminated structure. For example, a laminated structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a laminated structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide can be used. In other words, a laminated structure of an In-Ga-Zn oxide and an oxide not containing In may be used as the oxide 530c.

[0333] Specifically, as the oxide 530a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. As the oxide 530b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 3:1:2 may be used. As the oxide 530c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Specific examples of the case where the oxide 530c has a laminated structure include a laminated structure of In:Ga:Zn = 4:2:3 and Ga:Zn = 2:1, a laminated structure of In:Ga:Zn = 4:2:3 and Ga:Zn = 2:5, a laminated structure of In:Ga:Zn = 4:2:3 and gallium oxide, etc.

[0334] At this time, the main path of carriers becomes the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 510F can obtain a high on-current and high frequency characteristics. When the oxide 530c has a laminated structure, in addition to the effect of reducing the density of defect energy levels at the interface between the oxide 530b and the oxide 530c described above, it is expected to suppress the diffusion of the constituent elements of the oxide 530c to the insulator 550 side. More specifically, since the oxide 530c has a laminated structure and an oxide containing no In is positioned above the laminated structure, In that may diffuse to the insulator 550 side can be suppressed. Since the insulator 550 functions as a gate insulator, if In diffuses, the characteristics of the transistor deteriorate. Therefore, by forming the oxide 530c into a laminated structure, it is possible to provide a highly reliable semiconductor device.

[0335] The oxide 530 preferably uses a metal oxide that functions as an oxide semiconductor. For example, as the metal oxide that forms the channel region of the oxide 530, those having a bandgap of 2 eV or more, preferably 2.5 eV or more are preferably used. By using a metal oxide with a large bandgap in this way, the off-current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0336] <Example 7 of the structure of the transistor> The structural example of the transistor 510G will be described with reference to FIGS. 14A and 14B. The transistor 510G is a modified example of the transistor 500. Therefore, in order to avoid repetition of the description, mainly the differences from the above transistor will be described. Note that the configuration shown in FIGS. 14A and 14B can also be applied to other transistors included in the semiconductor device of one embodiment of the present invention, such as the transistor 300.

[0337] FIG. 14A is a cross-sectional view of the transistor 510G in the channel length direction, and FIG. 14B is a cross-sectional view of the transistor 510G in the channel width direction. The transistor 510G shown in FIGS. 14A and 14B is different from the transistor 500 shown in FIGS. 7A and 7B in that it has the insulators 402 and 404. Also, the insulator 551 is provided in contact with the side surface of the conductor 540a, and the insulator 551 is provided in contact with the side surface of the conductor 540b, which is different from the transistor 500 shown in FIGS. 7A and 7B. Furthermore, it is different from the transistor 500 shown in FIGS. 7A and 7B in that it does not have the insulator 520.

[0338] In the transistor 510G shown in FIGS. 14A and 14B, the insulator 402 is provided on the insulator 512. Also, the insulator 404 is provided on the insulator 574 and on the insulator 402.

[0339] In the transistor 510G shown in FIGS. 14A and 14B, the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 has a structure covering these. That is, the insulator 404 is in contact with the upper surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the upper surface of the insulator 402, respectively. Thereby, the oxide 530 etc. are isolated from the outside by the insulator 404 and the insulator 402.

[0340] The insulators 402 and 404 preferably have a high function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.) or water molecules. For example, as the insulators 402 and 404, it is preferable to use silicon nitride or silicon oxynitride, which are materials having a high hydrogen barrier property. Thereby, since the diffusion of hydrogen or the like into the oxide 530 can be suppressed, the deterioration of the characteristics of the transistor 510G can be suppressed. Therefore, the reliability of the semiconductor device according to one embodiment of the present invention can be enhanced.

[0341] The insulator 551 is provided in contact with the insulators 581, 404, 574, 580, and 544. The insulator 551 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulator 551, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which is a material having a high hydrogen barrier property. In particular, since silicon nitride is a material having a high hydrogen barrier property, it is suitable to be used as the insulator 551. By using a material having a high hydrogen barrier property as the insulator 551, the diffusion of impurities such as water or hydrogen from the insulator 580 etc. through the conductors 540a and 540b into the oxide 530 can be suppressed. Also, the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b can be suppressed. As described above, the reliability of the semiconductor device according to one embodiment of the present invention can be enhanced.

[0342] FIG. 15 is a cross-sectional view showing a configuration example of a semiconductor device when the transistor 500 and the transistor 300 are configured as shown in FIGS. 14A and 14B. An insulator 551 is provided on a side surface of the conductor 546.

[0343] FIGS. 16A and 16B are modified examples of the transistors shown in FIGS. 14A and 14B. FIG. 16A is a cross-sectional view in a channel length direction of the transistor, and FIG. 16B is a cross-sectional view in a channel width direction of the transistor. The transistors shown in FIGS. 16A and 16B are different from the transistors shown in FIGS. 14A and 14B in that the oxide 530c has a two-layer structure of an oxide 530c1 and an oxide 530c2.

[0344] The oxide 530c1 is in contact with an upper surface of the insulator 524, side surfaces of the oxides 530a and 530b, upper and side surfaces of the conductors 542a and 542b, side surfaces of the insulator 544, and side surfaces of the insulator 580. The oxide 530c2 is in contact with the insulator 550.

[0345] As the oxide 530c1, for example, an In-Zn oxide can be used. Also, as the oxide 530c2, the same materials as those that can be used for the oxide 530c when the oxide 530c has a single-layer structure can be used. For example, as the oxide 530c2, a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4, an atomic ratio of Ga:Zn = 2:1, or an atomic ratio of Ga:Zn = 2:5 can be used.

[0346] By forming the oxide 530c into a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased as compared with the case where the oxide 530c has a single-layer structure. Therefore, the transistor can be, for example, a power MOS transistor. Note that the oxide 530c included in the transistors shown in FIGS. 7A and 7B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0347] The transistors shown in FIGS. 16A and 16B can be applied to, for example, transistor 500, transistor 300, or both of them.

[0348] Note that this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0349] (Embodiment 3) In this embodiment, an oxide semiconductor which is a kind of metal oxide will be described.

[0350] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that it contains one or more selected from aluminum, gallium, yttrium, tin, etc. Further, it may contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0351] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 17A. FIG. 17A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0352] As shown in Fig. 17A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Further, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, "Crystal" includes single crystal and poly crystal.

[0353] Note that the structure within the thick frame shown in Fig. 17A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable "Amorphous" and is completely different from "Crystal".

[0354] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, Fig. 17B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 17B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 17B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 17B is 500 nm.

[0355] In FIG. 17B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [a.u.]. As shown in FIG. 17B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating clear crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak showing c-axis orientation is detected near 2θ = 31°. As shown in FIG. 17B, the peak near 2θ = 31° is asymmetric about the axis of the angle at which the peak intensity was detected.

[0356] Also, the crystal structure of the film or the substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 17C. FIG. 17C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 17C is near In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0357] As shown in FIG. 17C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots showing c-axis orientation are observed.

[0358] <<Structure of Oxide Semiconductor>> Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 17A. For example, the oxide semiconductor can be divided into a single-crystal oxide semiconductor and other non-single-crystal oxide semiconductors. Examples of the non-single-crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. The non-single-crystal oxide semiconductor also includes polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0359] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0360] [CAAC-OS] [CAAC-OS] has a plurality of crystal regions, and the plurality of crystal regions are oxide semiconductors in which the c-axis is oriented in a specific direction. Here, the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Further, the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Furthermore, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0361] Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be about several tens of nm.

[0362] Also, in In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0363] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0364] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0365] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0366] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and there is a high possibility of causing a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to the capture of carriers. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0367] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0368] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nano-crystals. Also, nc-OS has no regularity in the crystal orientation among different nano-crystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nano-crystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nano-crystals (for example, 1 nm or more and 30 nm or less) is performed on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0369] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0370] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0371] [CAC-OS] The CAC-OS is, for example, a constitution of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0372] Furthermore, the CAC-OS is a structure in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0373] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0374] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0375] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0376] For example, in the CAC-OS in In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0377] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0378] Oxide semiconductors have various structures, each with different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0379] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0380] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0381] For a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 less, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be decreased and the density of defect levels may be decreased. In this specification and the like, the case where the impurity concentration is low and the density of defect levels is low is referred to as highly pure intrinsic or substantially highly pure intrinsic. In some cases, an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0382] In addition, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low.

[0383] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0384] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0385] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0386] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0387] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0388] In the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as the semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0389] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 less than, more preferably less than 5×10 18 atoms / cm 3 less than, even more preferably less than 1×10 18 atoms / cm 3 less than.

[0390] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0391] Note that the configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments, etc.

[0392] (Embodiment 4) In this embodiment, application examples of the semiconductor device described above will be described.

[0393] [Semiconductor Wafer, Chip] FIG. 18A shows a top view of a substrate 711 before dicing processing. As the substrate 711, for example, a semiconductor substrate (also referred to as a semiconductor wafer) can be used. A plurality of circuit regions 712 are provided on the substrate 711. In the circuit region 712, a semiconductor device according to one embodiment of the present invention, a CPU, an RF tag, an image sensor, or the like can be provided.

[0394] The plurality of circuit regions 712 are each surrounded by a separation region 713. A separation line (also called a dicing line) 714 is set at a position overlapping the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. An enlarged view of the chip 715 is shown in FIG. 18B.

[0395] Also, a conductive layer or a semiconductor layer may be provided in the separation region 713. By providing a conductive layer or a semiconductor layer in the separation region 713, ESD that may occur during the dicing process can be mitigated, and a decrease in the yield of the dicing process can be prevented. In general, the dicing process is performed while flowing pure water with a reduced resistivity by dissolving carbon dioxide gas or the like to the cutting part for the purpose of cooling the substrate, removing chips, preventing charging, etc. By providing a conductive layer or a semiconductor layer in the separation region 713, the amount of use of the pure water can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Also, the productivity of the semiconductor device can be increased.

[0396] As the semiconductor layer provided in the separation region 713, it is preferable to use a material having a bandgap of 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less. By using such a material, the accumulated charge can be slowly discharged, so that a rapid movement of charge due to ESD can be suppressed, and electrostatic breakdown can be made less likely to occur.

[0397] 〔Electronic Component〕 An example of applying the chip 715 to an electronic component will be described with reference to FIGS. 19A and 19B. Note that an electronic component is also referred to as a semiconductor package or an IC package. There are a plurality of standards and names for electronic components depending on the terminal extraction direction and the shape of the terminals.

[0398] In the assembly process (post-process), the electronic component is completed by combining the semiconductor device shown in the above embodiment and components other than the semiconductor device.

[0399] The post-process will be described using the flowchart shown in FIG. 19A. After the element substrate having the semiconductor device shown in the above embodiment is completed in the pre-process, a "back grinding process" of grinding the back surface of the element substrate (the surface on which no semiconductor device or the like is formed) is performed (step S721). By thinning the element substrate by grinding, warpage of the element substrate and the like can be reduced, and miniaturization of the electronic component can be achieved.

[0400] Next, a "dicing process" of separating the element substrate into a plurality of chips (chip 715) is performed (step S722). Then, a "die bonding process" of individually picking up the separated chips and bonding them onto the lead frame is performed (step S723). For the bonding between the chip and the lead frame in the die bonding process, an appropriate method suitable for the product, such as bonding with resin or bonding with tape, is selected. Note that the chip may be bonded onto an interposer substrate instead of the lead frame.

[0401] Next, a "wire bonding process" of electrically connecting the leads of the lead frame and the electrodes on the chip with a thin metal wire (wire) is performed (step S724). Silver wire or gold wire can be used for the thin metal wire. Also, ball bonding or wedge bonding can be used for wire bonding.

[0402] The wire-bonded chip is subjected to a "sealing process (molding process)" of being sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, and the circuit part built in the chip and the wire connecting the chip and the lead can be protected from mechanical external force, and deterioration of characteristics (reduction in reliability) due to moisture and dust can be reduced.

[0403] Next, a "lead plating process" for plating the leads of the lead frame is performed (step S726). The plating process can prevent the leads from rusting and enable more reliable soldering when the leads are later mounted on a printed circuit board. Next, a "shaping process" for cutting and shaping the leads is performed (step S727).

[0404] Next, a "marking process" for performing printing processing (marking) on the surface of the package is performed (step S728). Then, through an "inspection process" (step S729) for examining the quality of the external shape and the presence or absence of malfunction, etc., the electronic component is completed.

[0405] In addition, a perspective schematic diagram of the completed electronic component is shown in Fig. 19B. Fig. 19B shows a perspective schematic diagram of a QFP (Quad Flat Package) as an example of the electronic component. The electronic component 750 shown in Fig. 19B shows leads 755 and a semiconductor device 753. As the semiconductor device 753, the semiconductor devices shown in the above embodiments can be used.

[0406] The electronic component 750 shown in Fig. 19B is mounted on a printed circuit board 752, for example. A plurality of such electronic components 750 are combined, and each is electrically connected on the printed circuit board 752, thereby completing a board (mounted board 754) on which the electronic components are mounted. The completed mounted board 754 is used in an electronic device or the like.

[0407] 〔Electronic Device〕 Next, an example of an electronic device including the semiconductor device 100 or the above-described electronic component according to one embodiment of the present invention will be described with reference to Figs. 20A, 20B, 21A, and 21B.

[0408] Fig. 20A shows an example of a camera. The camera 1820 includes a housing 1821, a display unit 1822, operation buttons 1823, a shutter button 1824, etc. In addition, a detachable lens 1826 is attached to the camera 1820.

[0409] Here, the camera 1820 is configured such that the lens 1826 can be removed from the housing 1821 and replaced, but the lens 1826 and the housing 1821 may be integrated.

[0410] The camera 1820 can capture a still image or a moving image by pressing the shutter button 1824. Further, the display unit 1822 has a function as a touch sensor, and it is also possible to capture an image by touching the display unit 1822.

[0411] Note that the camera 1820 can be separately equipped with a strobe device, a viewfinder, etc. Or, these may be incorporated in the housing 1821.

[0412] FIG. 20B is an enlarged view of the display unit 1822. The display unit 1822 can display a still image, a moving image captured by the camera 1820, or an image currently being captured by the camera 1820 through the lens 1826, etc.

[0413] In the display unit 1822 shown in FIG. 20B, a rabbit 1828 and a woman 1829 are displayed. The semiconductor device 100 mounted on the camera 1820 performs image recognition and displays a frame for distinguishing the recognized objects around the rabbit 1828 and the woman 1829 (the frame is shown by a dotted line in the figure), and can display an indication of what the object is (shown as "Rabbit" and "Woman" respectively in the figure).

[0414] FIG. 21A is an example of an information terminal. The information terminal 1840 has a display unit 1841, etc. A touch sensor is arranged on the display unit 1841, and the display unit 1841 also has a function as an input unit.

[0415] The semiconductor device 100 mounted on the information terminal 1840 can recognize the characters input to the display unit 1841 and display the recognition result. FIG. 21A shows an example in which the user inputs the alphabet "a" with a finger, the semiconductor device 100 recognizes the input character, and the recognition result is displayed at the upper left of the display unit 1841. Note that the input of characters in the display unit 1841 can be performed not only with a finger but also using a stylus or the like.

[0416] FIG. 21B shows an example of a robot. The robot 1860 includes an arithmetic unit 1870, an illuminance sensor 1861, a microphone 1862, an upper camera 1863, a speaker 1864, a display 1865, a lower camera 1866, an obstacle sensor 1867, a moving mechanism 1868, and the like. The arithmetic unit 1870 is equipped with the semiconductor device 100.

[0417] The microphone 1862 has a function of detecting the user's voice and ambient sound. The speaker 1864 has a function of emitting sound. The robot 1860 can communicate with the user using the microphone 1862 and the speaker 1864.

[0418] The display 1865 has a function of displaying various information. The robot 1860 can display the information desired by the user on the display 1865. The display 1865 may be equipped with a touch sensor. The display 1865 may also be a removable information terminal or the like, and by installing it at a fixed position of the robot 1860, charging and data transfer can be enabled.

[0419] The upper camera 1863 and the lower camera 1866 have a function of imaging the surroundings of the robot 1860. The obstacle sensor 1867 can detect the presence or absence of obstacles in the traveling direction when the robot 1860 moves using the moving mechanism 1868.

[0420] The semiconductor device 100 mounted on the arithmetic unit 1870 can analyze the images captured by the upper camera 1863 and the lower camera 1866, and determine the presence or absence of obstacles such as walls, furniture, steps, or falling objects.

[0421] In addition, the semiconductor device 100 mounted on the arithmetic unit 1870 can recognize the user of the robot 1860 from the images captured by the upper camera 1863 and the lower camera 1866, and move in the direction of the user of the robot 1860. Or, it can follow the user as the user of the robot 1860 moves.

[0422] By mounting the semiconductor device 100 described in the above embodiment on the electronic devices shown in FIGS. 20A, 21A, and 21B, image recognition can be efficiently performed.

[0423] Note that this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

Description of Reference Numerals

[0424] A: Data signal, B: Data signal, BL: Wiring, CX: Wiring, DA: Wiring, DB: Wiring, DX: Wiring, F: Filter, MAC: Circuit, MEM: Circuit, N1: Node, P: Image data, PC: Wiring, RD: Wiring, REF: Wiring, SUB: Semiconductor substrate, VD: Wiring, VDD: High power supply potential, VS: Wiring, VSS: Low power supply potential, W: Data signal, WL: Wiring, WO: Wiring, WS: Wiring, WT: Wiring, X: Data signal, 10: Multiplication and addition unit, 11: Memory cell, 12: Precharge circuit, 13: Decoder circuit, 14: Register circuit, 15: Circuit, 16: Multiplication circuit, 17: Addition circuit, 18: Register circuit, 21: Transistor, 22: Transistor, 23: Transistor, 24: Capacitor, 25: Transistor, 41: Inverter, 42: Inverter, 43: Inverter, 44: Transistor, 45: Transistor, 46: Transistor, 47: Transistor, 50: Region, 100: Semiconductor device, 101: Layer, 102: Layer, 111: Word line driver circuit, 112: Bit line driver circuit, 113: Multiplication and addition block, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 402: Insulator, 404: Insulator, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 505: Conductor, 505a: Conductor, 505b: Conductor, 510: Insulator, 510A: Transistor, 510B: Transistor, 510C: Transistor, 510D: Transistor, 510E: Transistor, 510F: Transistor, 510G: Transistor, 511: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 521: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530c: Oxide, 530c1: Oxide, 530c2: Oxide, 531: Region,531a: Region, 531b: Region, 540a: Conductor, 540b: Conductor, 542: Conductor, 542a: Conductor, 542b: Conductor, 543: Region, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 546a: Conductor, 546b: Conductor, 547: Conductor, 547a: Conductor, 547b: Conductor, 548: Conductor, 550: Insulator, 551: Insulator, 552: Metal Oxide, 560: Conductor, 560a: Conductor, 560b: Conductor, 570: Insulator, 571: Insulator, 573: Insulator, 574: Insulator, 575: Insulator, 576: Insulator, 576a: Insulator, 576b: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 584: Insulator, 586: Insulator, 600: Capacitor Element, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 650: Insulator, 711: Substrate, 712: Circuit Region, 713: Separation Region, 714: Separation Line, 715: Chip, 750: Electronic Component, 752: Printed Circuit Board, 753: Semiconductor Device, 754: Mounting Substrate, 755: Lead, 1820: Camera, 1821: Housing, 1822: Display Unit, 1823: Operation Button, 1824: Shutter Button, 1826: Lens, 1829: Female, 1840: Information Terminal, 1841: Display Unit, 1860: Robot, 1861: Illuminance Sensor, 1862: Microphone, 1863: Upper Camera, 1864: Speaker, 1865: Display, 1866: Lower Camera, 1867: Obstacle Sensor, 1868: Moving Mechanism, 1870: Arithmetic Unit,

Claims

1. having a plurality of multiply-accumulate units, each of the plurality of multiply-accumulate units having a first circuit and a second circuit stacked on the first circuit, the second circuit having a plurality of memory cells arranged in a matrix, the first circuit having a plurality of circuits corresponding to each column of the plurality of memory cells and a function of performing a multiply-accumulate operation, each of the plurality of circuits having a function of reading data stored in the memory cells of the corresponding column, each of the plurality of circuits for reading the data having a p-channel first transistor, a p-channel second transistor, an n-channel third transistor, and an n-channel fourth transistor each having a channel formation region in a semiconductor substrate, and a first inverter to a third inverter, each of the plurality of memory cells having a fifth transistor including a metal oxide in a channel formation region, one of the source or drain of the first transistor being electrically connected to a first wiring, the other of the source or drain of the first transistor being electrically connected to one of the source or drain of the second transistor, the other of the source or drain of the second transistor being electrically connected to the output terminal of the first inverter and the input terminal of the second inverter, one of the source or drain of the third transistor being electrically connected to the output terminal of the first inverter and the input terminal of the second inverter, the other of the source or drain of the third transistor being electrically connected to one of the source or drain of the fourth transistor, the other of the source or drain of the fourth transistor being electrically connected to a second wiring, the input terminal of the first inverter being electrically connected to a third wiring, the output terminal of the second inverter being electrically connected to the third wiring, The input terminal of the third inverter is electrically connected to a fourth wiring. The output terminal of the third inverter is electrically connected to the gate of the first transistor. The gates of the second transistor and the third transistor are electrically connected to one of the plurality of memory cells via a fifth wiring. The gate of the fourth transistor is electrically connected to the fourth wiring. The plurality of multiplier-accumulator units are arranged in a matrix, a semiconductor device.

2. A word line driver circuit, A bit line driver circuit, And a multiplier-accumulator block, The multiplier-accumulator block includes a plurality of multiplier-accumulator units. Each of the plurality of multiplier-accumulator units includes a first circuit and a second circuit stacked on the first circuit. The second circuit includes a plurality of memory cells arranged in a matrix. The first circuit includes a plurality of circuits corresponding to each column of the plurality of memory cells and a function of performing a multiplier-accumulator operation. The word line driver circuit and the bit line driver circuit have a function of writing data to the plurality of memory cells. Each of the plurality of circuits has a function of reading the data stored in the memory cells of the corresponding column. Each of the plurality of circuits for reading the data includes a p-channel first transistor having a channel formation region in a semiconductor substrate, a p-channel second transistor, an n-channel third transistor, and an n-channel fourth transistor, and a first inverter to a third inverter. Each of the plurality of memory cells includes a fifth transistor including a metal oxide in a channel formation region. One of the source or drain of the first transistor is electrically connected to a first wiring. The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the second transistor is electrically connected to the output terminal of the first inverter and the input terminal of the second inverter. One of the source or drain of the third transistor is electrically connected to the output terminal of the first inverter and the input terminal of the second inverter. The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The other of the source or drain of the fourth transistor is electrically connected to the second wiring. The input terminal of the first inverter is electrically connected to the third wiring. The output terminal of the second inverter is electrically connected to the third wiring. The input terminal of the third inverter is electrically connected to the fourth wiring. The output terminal of the third inverter is electrically connected to the gate of the first transistor. The gates of the second transistor and the third transistor are electrically connected to one of the plurality of memory cells via a fifth wiring. The gate of the fourth transistor is electrically connected to the fourth wiring. The plurality of sum-of-products units are arranged in a matrix, semiconductor device.

3. In claim 1 or claim 2, The metal oxide contains at least one of In or Zn, semiconductor device.

4. An electronic component having the semiconductor device according to any one of claims 1 to 3.

5. An electronic device having the semiconductor device according to any one of claims 1 to 3.

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