Resistive switching memory cell

Abstract

A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode, a first resistor structure in contact with the first electrode, a dielectric layer in contact with the first resistor structure, and a second resistor structure in contact with the dielectric layer. The second resistor structure includes a resistive material layer and a high work function metal core. The ReRAM device also includes a second electrode in contact with the second resistor structure.

Description

Technical Field

[0001] The present disclosure generally relates to manufacturing methods for semiconductor-based electronic devices and the resulting structures. More specifically, the present disclosure relates to integrated access transistors for neuromorphic computing and resistive random access memory (ReRAM) cell structures having a high-density layout, where the ReRAM cells have a reduced programming voltage.

Background Art

[0002] ReRAM structures can be utilized as a type of non-volatile (NV) random access memory (RAM) in computing resources. ReRAM devices with a simple metal-insulator-metal structure exhibit promising characteristics in terms of scalability, low-power operation, and multi-value data storage capabilities, and may be suitable for next-generation memory applications. ReRAM generally operates by controlling the change in the resistance value of a dielectric solid material, which may be referred to as a memristor. ReRAM can be considered a promising technology for electronic synapse devices (or memristors) for neuromorphic computing and high-density high-speed non-volatile memory applications. In neuromorphic computing applications, resistive memory devices can be used as connections (synapses) between pre-neurons and post-neurons, and the connection weights can be expressed in the form of the resistance of the device. Multiple pre-neurons and post-neurons can be connected via a crossbar array of ReRAMs, which may enable the realization of a fully connected neural network.

[0003] Oxygen vacancies in the metal oxide layer of ReRAM devices are components of the filaments through which current flows. Therefore, it may be desirable to form ReRAM cells without damaging the surroundings of the ReRAM cells. Also, in order to prevent the intrusion of oxygen in subsequent processes, it may be desirable to form ReRAM cells with robust encapsulation.

Summary of the Invention

[0004] Embodiments of the present disclosure relate to resistive random access memory (ReRAM) devices. A ReRAM device includes a first electrode, a first resistive structure in contact with the first electrode, a dielectric layer in contact with the first resistive structure, and a second resistive structure in contact with the dielectric layer. The second resistive structure includes a resistive material layer and a high work function metal core. The ReRAM device also includes a second electrode in contact with the second resistive structure.

[0005] Other embodiments relate to a method of manufacturing a resistive random access memory (ReRAM) device. The method includes forming a first electrode, forming a first resistive structure in contact with the first electrode, forming a dielectric layer in contact with the first resistive structure, and forming a second resistive structure in contact with the dielectric layer, where the second resistive structure includes a resistive material layer and a high work function metal core. The method also includes forming a second electrode in contact with the second resistive structure.

[0006] The above summary is not intended to describe every illustrated embodiment or every implementation of the present disclosure.

[0007] The drawings included in this application are incorporated herein and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the description, explain the principles of the present disclosure. The drawings merely illustrate particular embodiments and do not limit the present disclosure.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0009] The present disclosure generally relates to a manufacturing method for semiconductor-based electronic devices and the resulting structures. More specifically, the present disclosure relates to a resistive random access memory (ReRAM) cell structure having integrated access transistors and a high-density layout, which can be used in neuromorphic computing applications, and a method for manufacturing such ReRAM devices.

[0010] The flowcharts and cross-sectional views in the figures show a method for manufacturing a ReRAM device according to various embodiments. In some alternative embodiments, the manufacturing steps may be performed in an order different from that shown in the figures, and certain additional manufacturing steps may be performed between the steps shown in the figures. Further, any of the layer structures depicted in the figures may include a plurality of sublayers.

[0011] Various embodiments of the present disclosure are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the present disclosure. In the following description and drawings, note that various connection and positional relationships (e.g., above, below, adjacent, etc.) are defined between elements. These connections or positional relationships or both may be direct or indirect, and the present disclosure is not intended to be limited in this regard. Thus, the coupling of entities can refer to either direct or indirect coupling, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, a reference herein to forming layer "A" on layer "B" includes a situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant properties and functionalities of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).

[0012] The following definitions and abbreviations are for use in the interpretation of the claims and the specification. As used herein, the terms "comprises", "comprising", "includes", "including", "has", "having", "contains", or "containing", or other variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, product, or apparatus consisting of a list of elements is not necessarily limited to only those elements, but may include other elements not explicitly listed or elements inherent to such composition, mixture, process, method, product, or apparatus.

[0013] For the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the structures and methods described as oriented in the drawing figures. The terms "overlying", "atop", "on top", "positioned on", or "positioned atop" mean that a first element, such as a first structure, is present over a second element, such as a second structure, and that intervening elements, such as interface structures, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconductor layer at the interface of the two elements. It should be noted that the term "selective to", such as "a first element selective to a second element", means that the first element can be etched and the second element can function as an etch stop.

[0014] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Further, the various operations and process steps described herein can be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, since the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing details of well-known processes.

[0015] Generally, the various processes for forming microchips mounted on ICs can be broadly classified into four categories: deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring materials onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process of removing materials from a wafer. Examples include etching processes (either wet or dry), chemical mechanical polishing (CMP), etc. Semiconductor doping is the process of doping sources and drains of transistors, etc., by methods such as diffusion, ion implantation, or both, to change electrical properties. After these doping processes, furnace annealing or rapid thermal annealing (RTA) is performed. Annealing serves to activate the implanted dopants. Films of conductors (such as polysilicon, aluminum, copper, etc.) and insulators (such as silicon dioxide, silicon nitride, etc.) are used to connect and separate transistors and their components. By selectively doping various regions of a semiconductor substrate, the conductivity of the substrate can be changed by applying a voltage. By creating the structures of such various components, millions of transistors can be fabricated, wired, and a complex circuit of modern microelectronic devices can be formed. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate and then transferring that pattern to the substrate. In semiconductor lithography, a pattern is formed by a photosensitive polymer called photoresist. To create the complex structures that make up transistors and the many wires that connect millions of transistors in a circuit, the pattern transfer steps of lithography and etching are repeated many times. Each pattern printed on the wafer is aligned with previously formed patterns, and gradually conductors, insulators, and selectively doped regions are built up to form the final device.

[0016] Next, turning to an overview of technologies specifically related to aspects of the present disclosure, in neuromorphic computing applications, resistive memory devices (e.g., ReRAM devices) can be used as connections (synapses) between pre-neurons and post-neurons, and the connection weights can be represented in the form of device resistance.

[0017] By connecting multiple pre-neurons and post-neurons with a crossbar array of RRAM, a fully connected neural network can be naturally represented.

[0018] A junction with a resistive switching material can be formed on the lower electrode to create a crossbar array of RRAM. The upper electrode is formed on the junction with the resistive switching material to form a crossbar array of RRAM.

[0019] HfO x 、TaO x 、TiO x Non-volatile resistive switching metal oxides such as are integrated into nanocrossbar arrays and nanocrosspoints defined by lithography techniques. This enables the rapid fabrication of a high-density prototype test structure for a passive memory core with two-terminal devices. The electrical characteristics of this structure and the integrated materials are evaluated to understand the general characteristics of nanocrossbar arrays using resistive switching metal oxides and to define the requirements for an external CMOS control system.

[0020] Integrating a non-volatile and resistive switching material with two stable states, such as HfO2, as a two-terminal memory device can efficiently create ReRAM bit patterns. These cells can be integrated into a crossbar array. The switching material present at each junction of the crosspoint is an addressable cell of ReRAM. Since the array is composed of passive elements, an active external circuit needs to be added for operations such as addressing the cells, setting the state, resetting, and reading the stored information.

[0021] An artificial neural network (ANN) can be formed from the crossbar array of resistive processing units (RPUs), and can provide local data storage and local data processing without requiring additional processing elements beyond the RPUs. Trainable resistive cross-point devices are called RPUs.

[0022] Neurons are integrated in a CMOS circuit with crossbar array devices and store matrices. Input neurons, together with hidden neuron layers and output neurons, form a neural network. Input signals can be transferred forward and backward through the network and can also be used to update the weights of the matrices.

[0023] A crossbar array (cross-point array or cross-wire array) is a high-density, low-cost circuit architecture used in the formation of various electronic circuits and devices such as ANN architectures, neuromorphic microchips, and ultra-high-density non-volatile memories. The basic configuration of a crossbar array includes conductive row wirings and conductive column wirings formed to intersect the conductive row wirings. The intersections of the two sets of wires are separated by so-called cross-point devices formed of thin-film materials. Cross-point devices effectively function as weighted connections between neurons in an ANN. To achieve synaptic plasticity with high energy efficiency, nanoscale two-terminal devices such as memristors having, for example, conduction state switching characteristics are often used as cross-point devices. The conduction state (e.g., resistance) of the memristor material can be changed by controlling the voltage applied between individual wires of the row and column wires.

[0024] A resistive processing unit (RPU) can further enhance the capabilities of neuromorphic computing. It is a new class of device (RPU) that can be used as a processing unit to accelerate various algorithms including the training of neural networks.

[0025] In one embodiment, the ReRAM device includes a metal oxide layer disposed between an upper electrode and a lower electrode (i.e., a metal-insulator-metal structure). Oxygen vacancies in the metal oxide layer enable the electroforming of a current-conducting filament (CF) therein. In many ReRAM devices, the formation and rupture of the CF formed between these two electrodes repeat the resistance switching between the high resistance state (HRS) and the low resistance state (LRS), which is the mechanism for storing information. Regarding the CF, when a metal oxide is sandwiched between two electrodes, when a sufficient positive voltage is applied to the upper electrode, a CF is formed between the two electrodes, resulting in a low resistance state. On the other hand, when a sufficient negative voltage is applied to the lower electrode, the CF is destroyed, resulting in a high resistance state. In a specific embodiment of the oxide-based ReRAM device, the formation of the CF is triggered by field-assisted oxygen ion migration, which, as described above, results in a change in the electron conductivity (or resistivity) of the switching device. In the case of an oxide-based ReRAM device, electroforming of the CF is required.

[0026] The process of forming the conductive filament may depend on a certain randomness, and the position of the created filament may not always be well controlled. Therefore, as the ReRAM cell is scaled down, a higher formation voltage is required, and the device variation may increase. In certain ReRAM devices, Si implantation may be used after the post-pillar reactive ion etching (RIE) process, which may significantly reduce the CF formation voltage in some cases.

[0027] Here, referring to the drawings in which like numerals represent the same or similar elements, and first referring to FIG. 1, this figure is a cross-sectional view of a ReRAM device at an intermediate stage of a manufacturing process according to a particular embodiment. As shown in FIG. 1, the ReRAM device 100 includes a substrate 102. The semiconductor substrate 102 may include any semiconductor material having semiconductor properties. The semiconductor material providing the semiconductor substrate 102 may include, for example, silicon (Si), germanium (Ge), silicon germanium alloy (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors. Shallow trench isolation (STI) regions 104 are formed in the substrate 102, and they function to separate certain transistors from other transistors. A source region 106 and a drain region 108 are formed, and they are doped regions of the silicon substrate 102. A gate electrode 116 is formed on the substrate 102 in a region between the source region 106 and the drain region 108. Dielectric spacers 118 are formed around the gate electrode 116. The dielectric spacers 118 may be composed of SiN or any other suitable type of dielectric material. A first interlayer dielectric (ILD) layer 110 is formed on the substrate 102 over the STI regions 104, the source region 106, the drain region 108, and the dielectric spacers 118. Although not shown in FIG. 1, vias are first formed in the first ILD layer 110 to accommodate the formation of a lower electrode including a via liner layer 112 and a via core 114. The via liner layer 112 may include TaN or TiN, or any other suitable material. The via core 114 may include, for example, W. After the formation of the lower electrode, the ReRAM device 100 may undergo chemical mechanical polishing (CMP) to planarize the upper surface of the device. Next, a first SiN layer 120 is formed on the upper surface of the first ILD layer 110 and the upper surface of the via core 114.

[0028] Next, referring to FIG. 2, this figure is a cross-sectional view of the ReRAM device 100 of FIG. 1 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 2, a via opening 122 is formed in the first SiN layer 120. The via opening 122 may be formed by a RIE process or by any other suitable material removal process.

[0029] Next, referring to FIG. 3, this figure is a cross-sectional view of the ReRAM device of FIG. 2 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 3, a liner layer 124 is formed to partially fill the via opening 122. The liner layer 124 may be composed of TiN or any other suitable material. The material of the liner layer 124 may be the same as or different from the material of the via liner layer 112 described above with respect to FIG. 1. Since the liner layer 124 is formed to only partially fill the via opening 122, there is space left so that the high WF metal layer 125 can be formed. The high WF metal layer 125 (or high work function (WF) metal core) may be considered to be embedded (or formed) in the liner layer 124 (or resistive material layer). That is, a particular method of manufacturing a ReRAM device may include filling a part of the via (or via opening 122) with a high-resistance material layer (or liner layer 124), and then filling the remaining part of the via opening 122 at the center of the first resistive structure (i.e., the combination of the liner layer 124 and the high WF metal layer 125) with a high work function metal core (or high WF metal layer 125). The high WF metal layer 125 may be composed of, for example, Ru or any other suitable high WF metal material such as Ir or Pt (e.g., >4.9 eV). After the formation of the high WF metal layer 125, the ReRAM device 100 may undergo a CMP process to planarize the structure. As shown in FIG. 3, the width of the high WF metal layer 125 is less than the width of the via core 114. As will be described in more detail herein, the structure and material of the high WF metal layer 125 (e.g., the narrow width) enhance the electric field near the lower electrode via core 114 during electroforming and facilitate CF formation near the center of the device. Therefore, the problems associated with the randomness of the CF formation described above can be reduced or eliminated.

[0030] Next, referring to FIG. 4, this figure is a cross-sectional view of the ReRAM device 100 of FIG. 3 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 4, first, a metal oxide layer 128 is formed over the entire ReRAM device 100. The metal oxide layer 128 may be composed of HfO2, or any other suitable metal oxide material or combination of metal oxide materials. The upper electrode 130 is formed over the entire surface of the metal oxide layer 128. The upper electrode 130 may be composed of TiN or any other suitable material. The material of the upper electrode 130 may be the same as or different from the material of the via liner layer 112 or the liner layer 124 or both. Next, a hard mask 132 is deposited over the entire surface of the upper electrode 130. The hard mask 132 may be composed of SiN, or any other suitable material. The deposition of the material of the hard mask 132 may include any deposition process such as, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0031] Next, referring to FIG. 5, this figure is a cross-sectional view of the ReRAM device 100 of FIG. 4 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 5, the hard mask 132 layer, the upper electrode 130, and the metal oxide layer 128 are etched to pattern these layers into ReRAM pillars. In a particular example, to facilitate manufacturing integration, the widths of the patterned hard mask 132 layer, the upper electrode 130, and the metal oxide layer 128 may be slightly larger than the width of the lower electrode structure to prevent accidental etching of the liner layer 124.

[0032] Next, referring to FIG. 6, this figure is a cross-sectional view of the ReRAM device of FIG. 5 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 6, additional material (e.g., SiN) is added to extend the hard mask 132 and form a encapsulation layer over the entire surface of the ReRAM device 100. The hard mask 132 may be composed of, for example, SiN, or any other suitable material. Next, the second ILD layer 136 may be deposited over the entire surface of the hard mask 132. Although the hard mask 132 is shown as a single layer, it should be understood that a separate encapsulation layer (i.e., a material other than the material of the hard mask 132) may be formed on the hard mask 132. In certain embodiments, following the formation of the second ILD layer 136, the ReRAM device 100 may undergo a CMP process to planarize the surface of the device.

[0033] Next, referring to FIG. 7, this figure is a cross-sectional view of the ReRAM device of FIG. 6 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 7, contact vias 138 are formed by etching through the second ILD layer 136 and the hard mask 132. The contact vias 138 can correspond to the formation of the upper electrode.

[0034] Next, referring to FIG. 8, this figure is a cross-sectional view of the ReRAM device of FIG. 7 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 8, the upper electrode includes an upper electrode via liner layer 146 and an upper electrode via core 148. The upper electrode via liner layer 146 may include TaN or TiN, or any other suitable material. The upper electrode via core 148 may include, for example, W. After the formation of the upper electrode, the ReRAM device 100 may undergo chemical mechanical polishing (CMP) to planarize the upper surface of the device.

[0035] Next, referring to FIG. 9, this figure is a cross-sectional view of the ReRAM device of FIG. 8 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 9, a second SiN layer 150 is deposited over the entire surface of the ReRAM device 100. Then, by etching through the second SiN layer 150, the second ILD layer 136, the hard mask 132, and the first SiN layer 120 to expose the via core 114, the peripheral contact via 152 is formed.

[0036] Next, referring to FIG. 10, this figure is a cross-sectional view of the ReRAM device of FIG. 9 in a subsequent stage of the manufacturing process according to an embodiment. As shown in FIG. 10, after the formation of the peripheral contact via 152, a peripheral contact via liner layer 154 is deposited. The peripheral contact via liner layer 154 may include TaN or TiN, or any other suitable material. The peripheral contact via core 156 may include, for example, W. After the formation of the peripheral contact, additional material is added to the second SiN layer 150 so as to cover the upper surface of the peripheral contact via core 156. Next, in a specific example, the ReRAM device 100 may undergo chemical mechanical polishing (CMP) to planarize the upper surface of the device.

[0037] By making the width of the high work function metal core layer narrower than that of the lower electrode, the formation position of the conductive filament (CF) can be made to correspond to that position, and randomness regarding the formation position of the CF can be eliminated. Also, by localizing (concentrating) the conductive filament, it is possible to reduce the amount of voltage required to change the resistance state from the high resistance state to the low resistance state.

[0038] In the above-described embodiment, the high work function metal core layer has been described as being formed on the lower electrode (i.e., the electrode closest to the underlying substrate). However, it should be understood that in other embodiments, the high WF metal core layer may be formed on the upper electrode, or may be formed on both the upper electrode and the lower electrode.

[0039] The descriptions of the various embodiments are presented for purposes of illustration and are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are chosen in order to best explain the principles of an embodiment, the practical application or technical improvement of technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A first electrode, A first resistance structure in contact with the first electrode, A dielectric layer in contact with the first resistance structure, A second resistance structure in contact with the dielectric layer, the second resistance structure including a resistive material layer and a high work function metal core having a work function greater than 4.9 eV embedded in the resistive material layer, A second electrode in contact with the second resistance structure, and a resistive change type random access memory (ReRAM) device including the same.

2. The ReRAM device according to claim 1, wherein the high work function metal core includes at least one selected from the group consisting of Ru, Ir, and Pt.

3. The ReRAM device according to claim 1, wherein the high work function metal core has a width smaller than the width of the first electrode and the width of the second electrode.

4. The ReRAM device according to claim 3, wherein the high work function metal core is disposed at the center of the second resistance structure.

5. The ReRAM device according to claim 1, wherein the dielectric layer includes a metal oxide material.

6. The metal oxide material is HfO ２ as described in claim 5, the ReRAM device.

7. The ReRAM device according to claim 1, further including a capping layer formed on the first electrode and an interlayer insulating layer formed on the capping layer.

8. The ReRAM device according to claim 1, wherein the first electrode and the second electrode each include a liner layer and a via core formed on the liner layer.

9. Forming a first electrode, Forming a first resistance structure in contact with the first electrode, Forming a dielectric layer that contacts the first resistance structure; Forming a second resistance structure that contacts the dielectric layer; Forming a second electrode that contacts the second resistance structure, including: The first resistance structure includes a resistance material layer and a high work function metal core embedded in the resistance material layer and having a work function greater than 4.9 eV. A method for manufacturing a resistive random access memory (ReRAM) device.

10. The method for manufacturing a ReRAM device according to claim 9, wherein the high work function metal core includes at least one selected from the group consisting of Ru, Ir, and Pt.

11. The method for manufacturing a ReRAM device according to claim 9, wherein the high work function metal core has a width smaller than the width of the first electrode and the width of the second electrode.

12. Forming the first resistance structure includes: Forming a SiN layer on the first electrode; Etching a via in the SiN layer; Filling a part of the via with the resistance material layer; The method for manufacturing a ReRAM device according to claim 11, further including filling the remaining part of the via with the high work function metal core at the center of the first resistance structure.

13. The method for manufacturing a ReRAM device according to claim 9, wherein the dielectric layer includes a metal oxide material.

14. The metal oxide material is HfO ２ The method for manufacturing a ReRAM device according to claim 13, which is.

15. The method for manufacturing a ReRAM device according to claim 9, further including forming a capping layer on the second resistance structure and forming an interlayer insulating layer on the capping layer.

16. The manufacturing method of the ReRAM device according to claim 9, wherein the first electrode and the second electrode each include a liner layer and a via core formed on the liner layer.

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